arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j721e.dtsi"
   9
  10 / {
  11         memory@80000000 {
  12                 device_type = "memory";
  13                 /* 4G RAM */
  14                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  15                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  16         };
  17
  18         reserved_memory: reserved-memory {
  19                 #address-cells = <2>;
  20                 #size-cells = <2>;
  21                 ranges;
  22
  23                 secure_ddr: optee@9e800000 {
  24                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  25                         alignment = <0x1000>;
  26                         no-map;
  27                 };
  28
  29                 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x00 0xa6000000 0x00 0x100000>;
  32                         no-map;
  33                 };
  34
  35                 c66_0_memory_region: c66-memory@a6100000 {
  36                         compatible = "shared-dma-pool";
  37                         reg = <0x00 0xa6100000 0x00 0xf00000>;
  38                         no-map;
  39                 };
  40
  41                 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
  42                         compatible = "shared-dma-pool";
  43                         reg = <0x00 0xa7000000 0x00 0x100000>;
  44                         no-map;
  45                 };
  46
  47                 c66_1_memory_region: c66-memory@a7100000 {
  48                         compatible = "shared-dma-pool";
  49                         reg = <0x00 0xa7100000 0x00 0xf00000>;
  50                         no-map;
  51                 };
  52
  53                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
  54                         compatible = "shared-dma-pool";
  55                         reg = <0x00 0xa8000000 0x00 0x100000>;
  56                         no-map;
  57                 };
  58
  59                 c71_0_memory_region: c71-memory@a8100000 {
  60                         compatible = "shared-dma-pool";
  61                         reg = <0x00 0xa8100000 0x00 0xf00000>;
  62                         no-map;
  63                 };
  64
  65                 rtos_ipc_memory_region: ipc-memories@aa000000 {
  66                         reg = <0x00 0xaa000000 0x00 0x01c00000>;
  67                         alignment = <0x1000>;
  68                         no-map;
  69                 };
  70         };
  71 };
  72
  73 &wkup_pmx0 {
  74         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  75                 pinctrl-single,pins = <
  76                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
  77                         J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
  78                 >;
  79         };
  80
  81         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
  82                 pinctrl-single,pins = <
  83                         J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
  84                         J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
  85                         J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
  86                         J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
  87                         J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
  88                         J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
  89                         J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
  90                         J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
  91                         J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
  92                         J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
  93                         J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
  94                 >;
  95         };
  96 };
  97
  98 &ospi0 {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 101
 102         flash@0{
 103                 compatible = "jedec,spi-nor";
 104                 reg = <0x0>;
 105                 spi-tx-bus-width = <1>;
 106                 spi-rx-bus-width = <8>;
 107                 spi-max-frequency = <40000000>;
 108                 cdns,tshsl-ns = <60>;
 109                 cdns,tsd2d-ns = <60>;
 110                 cdns,tchsh-ns = <60>;
 111                 cdns,tslch-ns = <60>;
 112                 cdns,read-delay = <0>;
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115         };
 116 };
 117
 118 &mailbox0_cluster0 {
 119         interrupts = <436>;
 120
 121         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 122                 ti,mbox-rx = <0 0 0>;
 123                 ti,mbox-tx = <1 0 0>;
 124         };
 125
 126         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 127                 ti,mbox-rx = <2 0 0>;
 128                 ti,mbox-tx = <3 0 0>;
 129         };
 130 };
 131
 132 &mailbox0_cluster1 {
 133         interrupts = <432>;
 134
 135         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 136                 ti,mbox-rx = <0 0 0>;
 137                 ti,mbox-tx = <1 0 0>;
 138         };
 139
 140         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 141                 ti,mbox-rx = <2 0 0>;
 142                 ti,mbox-tx = <3 0 0>;
 143         };
 144 };
 145
 146 &mailbox0_cluster2 {
 147         interrupts = <428>;
 148
 149         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 150                 ti,mbox-rx = <0 0 0>;
 151                 ti,mbox-tx = <1 0 0>;
 152         };
 153
 154         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 155                 ti,mbox-rx = <2 0 0>;
 156                 ti,mbox-tx = <3 0 0>;
 157         };
 158 };
 159
 160 &mailbox0_cluster3 {
 161         interrupts = <424>;
 162
 163         mbox_c66_0: mbox-c66-0 {
 164                 ti,mbox-rx = <0 0 0>;
 165                 ti,mbox-tx = <1 0 0>;
 166         };
 167
 168         mbox_c66_1: mbox-c66-1 {
 169                 ti,mbox-rx = <2 0 0>;
 170                 ti,mbox-tx = <3 0 0>;
 171         };
 172 };
 173
 174 &mailbox0_cluster4 {
 175         interrupts = <420>;
 176
 177         mbox_c71_0: mbox-c71-0 {
 178                 ti,mbox-rx = <0 0 0>;
 179                 ti,mbox-tx = <1 0 0>;
 180         };
 181 };
 182
 183 &mailbox0_cluster5 {
 184         status = "disabled";
 185 };
 186
 187 &mailbox0_cluster6 {
 188         status = "disabled";
 189 };
 190
 191 &mailbox0_cluster7 {
 192         status = "disabled";
 193 };
 194
 195 &mailbox0_cluster8 {
 196         status = "disabled";
 197 };
 198
 199 &mailbox0_cluster9 {
 200         status = "disabled";
 201 };
 202
 203 &mailbox0_cluster10 {
 204         status = "disabled";
 205 };
 206
 207 &mailbox0_cluster11 {
 208         status = "disabled";
 209 };
 210
 211 &c66_0 {
 212         mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
 213         memory-region = <&c66_0_dma_memory_region>,
 214                         <&c66_0_memory_region>;
 215 };
 216
 217 &c66_1 {
 218         mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
 219         memory-region = <&c66_1_dma_memory_region>,
 220                         <&c66_1_memory_region>;
 221 };
 222
 223 &c71_0 {
 224         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 225         memory-region = <&c71_0_dma_memory_region>,
 226                         <&c71_0_memory_region>;
 227 };