1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-j721e.dtsi"
12 device_type = "memory";
14 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
15 <0x00000008 0x80000000 0x00000000 0x80000000>;
18 reserved_memory: reserved-memory {
23 secure_ddr: optee@9e800000 {
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30 compatible = "shared-dma-pool";
31 reg = <0x00 0xa0000000 0x00 0x100000>;
35 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
36 compatible = "shared-dma-pool";
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
41 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
42 compatible = "shared-dma-pool";
43 reg = <0x00 0xa1000000 0x00 0x100000>;
47 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
48 compatible = "shared-dma-pool";
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
53 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
54 compatible = "shared-dma-pool";
55 reg = <0x00 0xa2000000 0x00 0x100000>;
59 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
60 compatible = "shared-dma-pool";
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
65 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
66 compatible = "shared-dma-pool";
67 reg = <0x00 0xa3000000 0x00 0x100000>;
71 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
72 compatible = "shared-dma-pool";
73 reg = <0x00 0xa3100000 0x00 0xf00000>;
77 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
78 compatible = "shared-dma-pool";
79 reg = <0x00 0xa4000000 0x00 0x100000>;
83 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
84 compatible = "shared-dma-pool";
85 reg = <0x00 0xa4100000 0x00 0xf00000>;
89 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
90 compatible = "shared-dma-pool";
91 reg = <0x00 0xa5000000 0x00 0x100000>;
95 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
96 compatible = "shared-dma-pool";
97 reg = <0x00 0xa5100000 0x00 0xf00000>;
101 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
102 compatible = "shared-dma-pool";
103 reg = <0x00 0xa6000000 0x00 0x100000>;
107 c66_0_memory_region: c66-memory@a6100000 {
108 compatible = "shared-dma-pool";
109 reg = <0x00 0xa6100000 0x00 0xf00000>;
113 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
114 compatible = "shared-dma-pool";
115 reg = <0x00 0xa7000000 0x00 0x100000>;
119 c66_1_memory_region: c66-memory@a7100000 {
120 compatible = "shared-dma-pool";
121 reg = <0x00 0xa7100000 0x00 0xf00000>;
125 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
126 compatible = "shared-dma-pool";
127 reg = <0x00 0xa8000000 0x00 0x100000>;
131 c71_0_memory_region: c71-memory@a8100000 {
132 compatible = "shared-dma-pool";
133 reg = <0x00 0xa8100000 0x00 0xf00000>;
137 rtos_ipc_memory_region: ipc-memories@aa000000 {
138 reg = <0x00 0xaa000000 0x00 0x01c00000>;
139 alignment = <0x1000>;
146 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
147 pinctrl-single,pins = <
148 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
149 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
153 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
154 pinctrl-single,pins = <
155 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
156 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
157 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
158 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
159 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
160 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
161 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
162 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
163 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
164 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
165 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
171 pinctrl-names = "default";
172 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
175 compatible = "jedec,spi-nor";
177 spi-tx-bus-width = <8>;
178 spi-rx-bus-width = <8>;
179 spi-max-frequency = <25000000>;
180 cdns,tshsl-ns = <60>;
181 cdns,tsd2d-ns = <60>;
182 cdns,tchsh-ns = <60>;
183 cdns,tslch-ns = <60>;
184 cdns,read-delay = <0>;
185 #address-cells = <1>;
193 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
194 ti,mbox-rx = <0 0 0>;
195 ti,mbox-tx = <1 0 0>;
198 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
199 ti,mbox-rx = <2 0 0>;
200 ti,mbox-tx = <3 0 0>;
207 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
208 ti,mbox-rx = <0 0 0>;
209 ti,mbox-tx = <1 0 0>;
212 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
213 ti,mbox-rx = <2 0 0>;
214 ti,mbox-tx = <3 0 0>;
221 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
222 ti,mbox-rx = <0 0 0>;
223 ti,mbox-tx = <1 0 0>;
226 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
227 ti,mbox-rx = <2 0 0>;
228 ti,mbox-tx = <3 0 0>;
235 mbox_c66_0: mbox-c66-0 {
236 ti,mbox-rx = <0 0 0>;
237 ti,mbox-tx = <1 0 0>;
240 mbox_c66_1: mbox-c66-1 {
241 ti,mbox-rx = <2 0 0>;
242 ti,mbox-tx = <3 0 0>;
249 mbox_c71_0: mbox-c71-0 {
250 ti,mbox-rx = <0 0 0>;
251 ti,mbox-tx = <1 0 0>;
275 &mailbox0_cluster10 {
279 &mailbox0_cluster11 {
284 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
285 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
286 <&mcu_r5fss0_core0_memory_region>;
290 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
291 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
292 <&mcu_r5fss0_core1_memory_region>;
296 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
297 memory-region = <&main_r5fss0_core0_dma_memory_region>,
298 <&main_r5fss0_core0_memory_region>;
302 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
303 memory-region = <&main_r5fss0_core1_dma_memory_region>,
304 <&main_r5fss0_core1_memory_region>;
308 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
309 memory-region = <&main_r5fss1_core0_dma_memory_region>,
310 <&main_r5fss1_core0_memory_region>;
314 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
315 memory-region = <&main_r5fss1_core1_dma_memory_region>,
316 <&main_r5fss1_core1_memory_region>;
320 mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
321 memory-region = <&c66_0_dma_memory_region>,
322 <&c66_0_memory_region>;
326 mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
327 memory-region = <&c66_1_dma_memory_region>,
328 <&c66_1_memory_region>;
332 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
333 memory-region = <&c71_0_dma_memory_region>,
334 <&c71_0_memory_region>;