arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy.h>
   8 #include <dt-bindings/mux/mux.h>
   9 #include <dt-bindings/mux/mux-j721e-wiz.h>
  10
  11 &cbass_main {
  12         msmc_ram: sram@70000000 {
  13                 compatible = "mmio-sram";
  14                 reg = <0x0 0x70000000 0x0 0x800000>;
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x0 0x0 0x70000000 0x800000>;
  18
  19                 atf-sram@0 {
  20                         reg = <0x0 0x20000>;
  21                 };
  22         };
  23
  24         scm_conf: scm-conf@100000 {
  25                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  26                 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges = <0x0 0x0 0x00100000 0x1c000>;
  30
  31                 serdes_ln_ctrl: serdes-ln-ctrl@4080 {
  32                         compatible = "mmio-mux";
  33                         reg = <0x00004080 0x50>;
  34                         #mux-control-cells = <1>;
  35                         mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
  36                                         <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
  37                                         <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
  38                                         <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
  39                                         <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
  40                                         /* SERDES4 lane0/1/2/3 select */
  41                         idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
  42                                       <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
  43                                       <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
  44                                       <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
  45                                       <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
  46                 };
  47
  48                 usb_serdes_mux: mux-controller@4000 {
  49                         compatible = "mmio-mux";
  50                         #mux-control-cells = <1>;
  51                         mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
  52                                         <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
  53             };
  54         };
  55
  56         gic500: interrupt-controller@1800000 {
  57                 compatible = "arm,gic-v3";
  58                 #address-cells = <2>;
  59                 #size-cells = <2>;
  60                 ranges;
  61                 #interrupt-cells = <3>;
  62                 interrupt-controller;
  63                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  64                       <0x00 0x01900000 0x00 0x100000>;  /* GICR */
  65
  66                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  67                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  68
  69                 gic_its: msi-controller@1820000 {
  70                         compatible = "arm,gic-v3-its";
  71                         reg = <0x00 0x01820000 0x00 0x10000>;
  72                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  73                         msi-controller;
  74                         #msi-cells = <1>;
  75                 };
  76         };
  77
  78         main_gpio_intr: interrupt-controller0 {
  79                 compatible = "ti,sci-intr";
  80                 ti,intr-trigger-type = <1>;
  81                 interrupt-controller;
  82                 interrupt-parent = <&gic500>;
  83                 #interrupt-cells = <2>;
  84                 ti,sci = <&dmsc>;
  85                 ti,sci-dst-id = <14>;
  86                 ti,sci-rm-range-girq = <0x1>;
  87         };
  88
  89         main_navss {
  90                 compatible = "simple-mfd";
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93                 ranges;
  94                 dma-coherent;
  95                 dma-ranges;
  96
  97                 ti,sci-dev-id = <199>;
  98
  99                 main_navss_intr: interrupt-controller1 {
 100                         compatible = "ti,sci-intr";
 101                         ti,intr-trigger-type = <4>;
 102                         interrupt-controller;
 103                         interrupt-parent = <&gic500>;
 104                         #interrupt-cells = <2>;
 105                         ti,sci = <&dmsc>;
 106                         ti,sci-dst-id = <14>;
 107                         ti,sci-rm-range-girq = <0>, <2>;
 108                 };
 109
 110                 main_udmass_inta: interrupt-controller@33d00000 {
 111                         compatible = "ti,sci-inta";
 112                         reg = <0x0 0x33d00000 0x0 0x100000>;
 113                         interrupt-controller;
 114                         interrupt-parent = <&main_navss_intr>;
 115                         msi-controller;
 116                         ti,sci = <&dmsc>;
 117                         ti,sci-dev-id = <209>;
 118                         ti,sci-rm-range-vint = <0xa>;
 119                         ti,sci-rm-range-global-event = <0xd>;
 120                 };
 121
 122                 secure_proxy_main: mailbox@32c00000 {
 123                         compatible = "ti,am654-secure-proxy";
 124                         #mbox-cells = <1>;
 125                         reg-names = "target_data", "rt", "scfg";
 126                         reg = <0x00 0x32c00000 0x00 0x100000>,
 127                               <0x00 0x32400000 0x00 0x100000>,
 128                               <0x00 0x32800000 0x00 0x100000>;
 129                         interrupt-names = "rx_011";
 130                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 131                 };
 132
 133                 smmu0: iommu@36600000 {
 134                         compatible = "arm,smmu-v3";
 135                         reg = <0x0 0x36600000 0x0 0x100000>;
 136                         interrupt-parent = <&gic500>;
 137                         interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
 138                                      <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
 139                         interrupt-names = "eventq", "gerror";
 140                         #iommu-cells = <1>;
 141                 };
 142
 143                 hwspinlock: spinlock@30e00000 {
 144                         compatible = "ti,am654-hwspinlock";
 145                         reg = <0x00 0x30e00000 0x00 0x1000>;
 146                         #hwlock-cells = <1>;
 147                 };
 148
 149                 mailbox0_cluster0: mailbox@31f80000 {
 150                         compatible = "ti,am654-mailbox";
 151                         reg = <0x00 0x31f80000 0x00 0x200>;
 152                         #mbox-cells = <1>;
 153                         ti,mbox-num-users = <4>;
 154                         ti,mbox-num-fifos = <16>;
 155                         interrupt-parent = <&main_navss_intr>;
 156                 };
 157
 158                 mailbox0_cluster1: mailbox@31f81000 {
 159                         compatible = "ti,am654-mailbox";
 160                         reg = <0x00 0x31f81000 0x00 0x200>;
 161                         #mbox-cells = <1>;
 162                         ti,mbox-num-users = <4>;
 163                         ti,mbox-num-fifos = <16>;
 164                         interrupt-parent = <&main_navss_intr>;
 165                 };
 166
 167                 mailbox0_cluster2: mailbox@31f82000 {
 168                         compatible = "ti,am654-mailbox";
 169                         reg = <0x00 0x31f82000 0x00 0x200>;
 170                         #mbox-cells = <1>;
 171                         ti,mbox-num-users = <4>;
 172                         ti,mbox-num-fifos = <16>;
 173                         interrupt-parent = <&main_navss_intr>;
 174                 };
 175
 176                 mailbox0_cluster3: mailbox@31f83000 {
 177                         compatible = "ti,am654-mailbox";
 178                         reg = <0x00 0x31f83000 0x00 0x200>;
 179                         #mbox-cells = <1>;
 180                         ti,mbox-num-users = <4>;
 181                         ti,mbox-num-fifos = <16>;
 182                         interrupt-parent = <&main_navss_intr>;
 183                 };
 184
 185                 mailbox0_cluster4: mailbox@31f84000 {
 186                         compatible = "ti,am654-mailbox";
 187                         reg = <0x00 0x31f84000 0x00 0x200>;
 188                         #mbox-cells = <1>;
 189                         ti,mbox-num-users = <4>;
 190                         ti,mbox-num-fifos = <16>;
 191                         interrupt-parent = <&main_navss_intr>;
 192                 };
 193
 194                 mailbox0_cluster5: mailbox@31f85000 {
 195                         compatible = "ti,am654-mailbox";
 196                         reg = <0x00 0x31f85000 0x00 0x200>;
 197                         #mbox-cells = <1>;
 198                         ti,mbox-num-users = <4>;
 199                         ti,mbox-num-fifos = <16>;
 200                         interrupt-parent = <&main_navss_intr>;
 201                 };
 202
 203                 mailbox0_cluster6: mailbox@31f86000 {
 204                         compatible = "ti,am654-mailbox";
 205                         reg = <0x00 0x31f86000 0x00 0x200>;
 206                         #mbox-cells = <1>;
 207                         ti,mbox-num-users = <4>;
 208                         ti,mbox-num-fifos = <16>;
 209                         interrupt-parent = <&main_navss_intr>;
 210                 };
 211
 212                 mailbox0_cluster7: mailbox@31f87000 {
 213                         compatible = "ti,am654-mailbox";
 214                         reg = <0x00 0x31f87000 0x00 0x200>;
 215                         #mbox-cells = <1>;
 216                         ti,mbox-num-users = <4>;
 217                         ti,mbox-num-fifos = <16>;
 218                         interrupt-parent = <&main_navss_intr>;
 219                 };
 220
 221                 mailbox0_cluster8: mailbox@31f88000 {
 222                         compatible = "ti,am654-mailbox";
 223                         reg = <0x00 0x31f88000 0x00 0x200>;
 224                         #mbox-cells = <1>;
 225                         ti,mbox-num-users = <4>;
 226                         ti,mbox-num-fifos = <16>;
 227                         interrupt-parent = <&main_navss_intr>;
 228                 };
 229
 230                 mailbox0_cluster9: mailbox@31f89000 {
 231                         compatible = "ti,am654-mailbox";
 232                         reg = <0x00 0x31f89000 0x00 0x200>;
 233                         #mbox-cells = <1>;
 234                         ti,mbox-num-users = <4>;
 235                         ti,mbox-num-fifos = <16>;
 236                         interrupt-parent = <&main_navss_intr>;
 237                 };
 238
 239                 mailbox0_cluster10: mailbox@31f8a000 {
 240                         compatible = "ti,am654-mailbox";
 241                         reg = <0x00 0x31f8a000 0x00 0x200>;
 242                         #mbox-cells = <1>;
 243                         ti,mbox-num-users = <4>;
 244                         ti,mbox-num-fifos = <16>;
 245                         interrupt-parent = <&main_navss_intr>;
 246                 };
 247
 248                 mailbox0_cluster11: mailbox@31f8b000 {
 249                         compatible = "ti,am654-mailbox";
 250                         reg = <0x00 0x31f8b000 0x00 0x200>;
 251                         #mbox-cells = <1>;
 252                         ti,mbox-num-users = <4>;
 253                         ti,mbox-num-fifos = <16>;
 254                         interrupt-parent = <&main_navss_intr>;
 255                 };
 256
 257                 main_ringacc: ringacc@3c000000 {
 258                         compatible = "ti,am654-navss-ringacc";
 259                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 260                                 <0x0 0x38000000 0x0 0x400000>,
 261                                 <0x0 0x31120000 0x0 0x100>,
 262                                 <0x0 0x33000000 0x0 0x40000>;
 263                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 264                         ti,num-rings = <1024>;
 265                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 266                         ti,sci = <&dmsc>;
 267                         ti,sci-dev-id = <211>;
 268                         msi-parent = <&main_udmass_inta>;
 269                 };
 270
 271                 main_udmap: dma-controller@31150000 {
 272                         compatible = "ti,j721e-navss-main-udmap";
 273                         reg =   <0x0 0x31150000 0x0 0x100>,
 274                                 <0x0 0x34000000 0x0 0x100000>,
 275                                 <0x0 0x35000000 0x0 0x100000>;
 276                         reg-names = "gcfg", "rchanrt", "tchanrt";
 277                         msi-parent = <&main_udmass_inta>;
 278                         #dma-cells = <1>;
 279
 280                         ti,sci = <&dmsc>;
 281                         ti,sci-dev-id = <212>;
 282                         ti,ringacc = <&main_ringacc>;
 283
 284                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 285                                                 <0x0f>, /* TX_HCHAN */
 286                                                 <0x10>; /* TX_UHCHAN */
 287                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 288                                                 <0x0b>, /* RX_HCHAN */
 289                                                 <0x0c>; /* RX_UHCHAN */
 290                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 291                 };
 292
 293                 cpts@310d0000 {
 294                         compatible = "ti,j721e-cpts";
 295                         reg = <0x0 0x310d0000 0x0 0x400>;
 296                         reg-names = "cpts";
 297                         clocks = <&k3_clks 201 1>;
 298                         clock-names = "cpts";
 299                         interrupts-extended = <&main_navss_intr 201 0>;
 300                         interrupt-names = "cpts";
 301                         ti,cpts-periodic-outputs = <6>;
 302                         ti,cpts-ext-ts-inputs = <8>;
 303                 };
 304         };
 305
 306         main_pmx0: pinmux@11c000 {
 307                 compatible = "pinctrl-single";
 308                 /* Proxy 0 addressing */
 309                 reg = <0x0 0x11c000 0x0 0x2b4>;
 310                 #pinctrl-cells = <1>;
 311                 pinctrl-single,register-width = <32>;
 312                 pinctrl-single,function-mask = <0xffffffff>;
 313         };
 314
 315         dummy_cmn_refclk: dummy-cmn-refclk {
 316                 #clock-cells = <0>;
 317                 compatible = "fixed-clock";
 318                 clock-frequency = <100000000>;
 319         };
 320
 321         dummy_cmn_refclk1: dummy-cmn-refclk1 {
 322                 #clock-cells = <0>;
 323                 compatible = "fixed-clock";
 324                 clock-frequency = <100000000>;
 325         };
 326
 327         serdes_wiz0: wiz@5000000 {
 328                 compatible = "ti,j721e-wiz-16g";
 329                 #address-cells = <1>;
 330                 #size-cells = <1>;
 331                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 332                 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
 333                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 334                 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
 335                 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
 336                 num-lanes = <2>;
 337                 #reset-cells = <1>;
 338                 ranges = <0x5000000 0x0 0x5000000 0x10000>;
 339
 340                 wiz0_pll0_refclk: pll0-refclk {
 341                         clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
 342                         #clock-cells = <0>;
 343                         assigned-clocks = <&wiz0_pll0_refclk>;
 344                         assigned-clock-parents = <&k3_clks 292 11>;
 345                 };
 346
 347                 wiz0_pll1_refclk: pll1-refclk {
 348                         clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
 349                         #clock-cells = <0>;
 350                         assigned-clocks = <&wiz0_pll1_refclk>;
 351                         assigned-clock-parents = <&k3_clks 292 0>;
 352                 };
 353
 354                 wiz0_refclk_dig: refclk-dig {
 355                         clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 356                         #clock-cells = <0>;
 357                         assigned-clocks = <&wiz0_refclk_dig>;
 358                         assigned-clock-parents = <&k3_clks 292 11>;
 359                 };
 360
 361                 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
 362                         clocks = <&wiz0_refclk_dig>;
 363                         #clock-cells = <0>;
 364                 };
 365
 366                 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 367                         clocks = <&wiz0_pll1_refclk>;
 368                         #clock-cells = <0>;
 369                 };
 370
 371                 serdes0: serdes@5000000 {
 372                         compatible = "ti,sierra-phy-t0";
 373                         reg-names = "serdes";
 374                         reg = <0x5000000 0x10000>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         resets = <&serdes_wiz0 0>;
 378                         reset-names = "sierra_reset";
 379                         clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
 380                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 381                 };
 382         };
 383
 384         serdes_wiz1: wiz@5010000 {
 385                 compatible = "ti,j721e-wiz-16g";
 386                 #address-cells = <1>;
 387                 #size-cells = <1>;
 388                 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
 389                 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
 390                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 391                 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
 392                 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
 393                 num-lanes = <2>;
 394                 #reset-cells = <1>;
 395                 ranges = <0x5010000 0x0 0x5010000 0x10000>;
 396
 397                 wiz1_pll0_refclk: pll0-refclk {
 398                         clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
 399                         #clock-cells = <0>;
 400                         assigned-clocks = <&wiz1_pll0_refclk>;
 401                         assigned-clock-parents = <&k3_clks 293 13>;
 402                 };
 403
 404                 wiz1_pll1_refclk: pll1-refclk {
 405                         clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
 406                         #clock-cells = <0>;
 407                         assigned-clocks = <&wiz1_pll1_refclk>;
 408                         assigned-clock-parents = <&k3_clks 293 0>;
 409                 };
 410
 411                 wiz1_refclk_dig: refclk-dig {
 412                         clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 413                         #clock-cells = <0>;
 414                         assigned-clocks = <&wiz1_refclk_dig>;
 415                         assigned-clock-parents = <&k3_clks 293 13>;
 416                 };
 417
 418                 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
 419                         clocks = <&wiz1_refclk_dig>;
 420                         #clock-cells = <0>;
 421                 };
 422
 423                 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 424                         clocks = <&wiz1_pll1_refclk>;
 425                         #clock-cells = <0>;
 426                 };
 427
 428                 serdes1: serdes@5010000 {
 429                         compatible = "ti,sierra-phy-t0";
 430                         reg-names = "serdes";
 431                         reg = <0x5010000 0x10000>;
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         resets = <&serdes_wiz1 0>;
 435                         reset-names = "sierra_reset";
 436                         clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
 437                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 438                 };
 439         };
 440
 441         serdes_wiz2: wiz@5020000 {
 442                 compatible = "ti,j721e-wiz-16g";
 443                 #address-cells = <1>;
 444                 #size-cells = <1>;
 445                 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
 446                 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
 447                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 448                 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
 449                 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
 450                 num-lanes = <2>;
 451                 #reset-cells = <1>;
 452                 ranges = <0x5020000 0x0 0x5020000 0x10000>;
 453
 454                 wiz2_pll0_refclk: pll0-refclk {
 455                         clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
 456                         #clock-cells = <0>;
 457                         assigned-clocks = <&wiz2_pll0_refclk>;
 458                         assigned-clock-parents = <&k3_clks 294 11>;
 459                 };
 460
 461                 wiz2_pll1_refclk: pll1-refclk {
 462                         clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
 463                         #clock-cells = <0>;
 464                         assigned-clocks = <&wiz2_pll1_refclk>;
 465                         assigned-clock-parents = <&k3_clks 294 0>;
 466                 };
 467
 468                 wiz2_refclk_dig: refclk-dig {
 469                         clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 470                         #clock-cells = <0>;
 471                         assigned-clocks = <&wiz2_refclk_dig>;
 472                         assigned-clock-parents = <&k3_clks 294 11>;
 473                 };
 474
 475                 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
 476                         clocks = <&wiz2_refclk_dig>;
 477                         #clock-cells = <0>;
 478                 };
 479
 480                 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 481                         clocks = <&wiz2_pll1_refclk>;
 482                         #clock-cells = <0>;
 483                 };
 484
 485                 serdes2: serdes@5020000 {
 486                         compatible = "ti,sierra-phy-t0";
 487                         reg-names = "serdes";
 488                         reg = <0x5020000 0x10000>;
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         resets = <&serdes_wiz2 0>;
 492                         reset-names = "sierra_reset";
 493                         clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
 494                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 495                 };
 496         };
 497
 498         serdes_wiz3: wiz@5030000 {
 499                 compatible = "ti,j721e-wiz-16g";
 500                 #address-cells = <1>;
 501                 #size-cells = <1>;
 502                 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
 503                 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
 504                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 505                 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
 506                 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
 507                 num-lanes = <2>;
 508                 #reset-cells = <1>;
 509                 ranges = <0x5030000 0x0 0x5030000 0x10000>;
 510
 511                 wiz3_pll0_refclk: pll0-refclk {
 512                         clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
 513                         #clock-cells = <0>;
 514                         assigned-clocks = <&wiz3_pll0_refclk>;
 515                         assigned-clock-parents = <&k3_clks 295 9>;
 516                 };
 517
 518                 wiz3_pll1_refclk: pll1-refclk {
 519                         clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
 520                         #clock-cells = <0>;
 521                         assigned-clocks = <&wiz3_pll1_refclk>;
 522                         assigned-clock-parents = <&k3_clks 295 0>;
 523                 };
 524
 525                 wiz3_refclk_dig: refclk-dig {
 526                         clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
 527                         #clock-cells = <0>;
 528                         assigned-clocks = <&wiz3_refclk_dig>;
 529                         assigned-clock-parents = <&k3_clks 295 9>;
 530                 };
 531
 532                 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
 533                         clocks = <&wiz3_refclk_dig>;
 534                         #clock-cells = <0>;
 535                 };
 536
 537                 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
 538                         clocks = <&wiz3_pll1_refclk>;
 539                         #clock-cells = <0>;
 540                 };
 541
 542                 serdes3: serdes@5030000 {
 543                         compatible = "ti,sierra-phy-t0";
 544                         reg-names = "serdes";
 545                         reg = <0x5030000 0x10000>;
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         resets = <&serdes_wiz3 0>;
 549                         reset-names = "sierra_reset";
 550                         clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
 551                         clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
 552                 };
 553         };
 554
 555         main_uart0: serial@2800000 {
 556                 compatible = "ti,j721e-uart", "ti,am654-uart";
 557                 reg = <0x00 0x02800000 0x00 0x100>;
 558                 reg-shift = <2>;
 559                 reg-io-width = <4>;
 560                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 561                 clock-frequency = <48000000>;
 562                 current-speed = <115200>;
 563                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 564                 clocks = <&k3_clks 146 0>;
 565                 clock-names = "fclk";
 566         };
 567
 568         main_uart1: serial@2810000 {
 569                 compatible = "ti,j721e-uart", "ti,am654-uart";
 570                 reg = <0x00 0x02810000 0x00 0x100>;
 571                 reg-shift = <2>;
 572                 reg-io-width = <4>;
 573                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 574                 clock-frequency = <48000000>;
 575                 current-speed = <115200>;
 576                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 577                 clocks = <&k3_clks 278 0>;
 578                 clock-names = "fclk";
 579         };
 580
 581         main_uart2: serial@2820000 {
 582                 compatible = "ti,j721e-uart", "ti,am654-uart";
 583                 reg = <0x00 0x02820000 0x00 0x100>;
 584                 reg-shift = <2>;
 585                 reg-io-width = <4>;
 586                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 587                 clock-frequency = <48000000>;
 588                 current-speed = <115200>;
 589                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 590                 clocks = <&k3_clks 279 0>;
 591                 clock-names = "fclk";
 592         };
 593
 594         main_uart3: serial@2830000 {
 595                 compatible = "ti,j721e-uart", "ti,am654-uart";
 596                 reg = <0x00 0x02830000 0x00 0x100>;
 597                 reg-shift = <2>;
 598                 reg-io-width = <4>;
 599                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 600                 clock-frequency = <48000000>;
 601                 current-speed = <115200>;
 602                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 603                 clocks = <&k3_clks 280 0>;
 604                 clock-names = "fclk";
 605         };
 606
 607         main_uart4: serial@2840000 {
 608                 compatible = "ti,j721e-uart", "ti,am654-uart";
 609                 reg = <0x00 0x02840000 0x00 0x100>;
 610                 reg-shift = <2>;
 611                 reg-io-width = <4>;
 612                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 613                 clock-frequency = <48000000>;
 614                 current-speed = <115200>;
 615                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 616                 clocks = <&k3_clks 281 0>;
 617                 clock-names = "fclk";
 618         };
 619
 620         main_uart5: serial@2850000 {
 621                 compatible = "ti,j721e-uart", "ti,am654-uart";
 622                 reg = <0x00 0x02850000 0x00 0x100>;
 623                 reg-shift = <2>;
 624                 reg-io-width = <4>;
 625                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 626                 clock-frequency = <48000000>;
 627                 current-speed = <115200>;
 628                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 629                 clocks = <&k3_clks 282 0>;
 630                 clock-names = "fclk";
 631         };
 632
 633         main_uart6: serial@2860000 {
 634                 compatible = "ti,j721e-uart", "ti,am654-uart";
 635                 reg = <0x00 0x02860000 0x00 0x100>;
 636                 reg-shift = <2>;
 637                 reg-io-width = <4>;
 638                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 639                 clock-frequency = <48000000>;
 640                 current-speed = <115200>;
 641                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 642                 clocks = <&k3_clks 283 0>;
 643                 clock-names = "fclk";
 644         };
 645
 646         main_uart7: serial@2870000 {
 647                 compatible = "ti,j721e-uart", "ti,am654-uart";
 648                 reg = <0x00 0x02870000 0x00 0x100>;
 649                 reg-shift = <2>;
 650                 reg-io-width = <4>;
 651                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 652                 clock-frequency = <48000000>;
 653                 current-speed = <115200>;
 654                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 655                 clocks = <&k3_clks 284 0>;
 656                 clock-names = "fclk";
 657         };
 658
 659         main_uart8: serial@2880000 {
 660                 compatible = "ti,j721e-uart", "ti,am654-uart";
 661                 reg = <0x00 0x02880000 0x00 0x100>;
 662                 reg-shift = <2>;
 663                 reg-io-width = <4>;
 664                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 665                 clock-frequency = <48000000>;
 666                 current-speed = <115200>;
 667                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 668                 clocks = <&k3_clks 285 0>;
 669                 clock-names = "fclk";
 670         };
 671
 672         main_uart9: serial@2890000 {
 673                 compatible = "ti,j721e-uart", "ti,am654-uart";
 674                 reg = <0x00 0x02890000 0x00 0x100>;
 675                 reg-shift = <2>;
 676                 reg-io-width = <4>;
 677                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 678                 clock-frequency = <48000000>;
 679                 current-speed = <115200>;
 680                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 681                 clocks = <&k3_clks 286 0>;
 682                 clock-names = "fclk";
 683         };
 684
 685         main_gpio0: gpio@600000 {
 686                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 687                 reg = <0x0 0x00600000 0x0 0x100>;
 688                 gpio-controller;
 689                 #gpio-cells = <2>;
 690                 interrupt-parent = <&main_gpio_intr>;
 691                 interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
 692                              <105 4>, <105 5>, <105 6>, <105 7>;
 693                 interrupt-controller;
 694                 #interrupt-cells = <2>;
 695                 ti,ngpio = <128>;
 696                 ti,davinci-gpio-unbanked = <0>;
 697                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 698                 clocks = <&k3_clks 105 0>;
 699                 clock-names = "gpio";
 700         };
 701
 702         main_gpio1: gpio@601000 {
 703                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 704                 reg = <0x0 0x00601000 0x0 0x100>;
 705                 gpio-controller;
 706                 #gpio-cells = <2>;
 707                 interrupt-parent = <&main_gpio_intr>;
 708                 interrupts = <106 0>, <106 1>, <106 2>;
 709                 interrupt-controller;
 710                 #interrupt-cells = <2>;
 711                 ti,ngpio = <36>;
 712                 ti,davinci-gpio-unbanked = <0>;
 713                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 714                 clocks = <&k3_clks 106 0>;
 715                 clock-names = "gpio";
 716         };
 717
 718         main_gpio2: gpio@610000 {
 719                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 720                 reg = <0x0 0x00610000 0x0 0x100>;
 721                 gpio-controller;
 722                 #gpio-cells = <2>;
 723                 interrupt-parent = <&main_gpio_intr>;
 724                 interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
 725                              <107 4>, <107 5>, <107 6>, <107 7>;
 726                 interrupt-controller;
 727                 #interrupt-cells = <2>;
 728                 ti,ngpio = <128>;
 729                 ti,davinci-gpio-unbanked = <0>;
 730                 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 731                 clocks = <&k3_clks 107 0>;
 732                 clock-names = "gpio";
 733         };
 734
 735         main_gpio3: gpio@611000 {
 736                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 737                 reg = <0x0 0x00611000 0x0 0x100>;
 738                 gpio-controller;
 739                 #gpio-cells = <2>;
 740                 interrupt-parent = <&main_gpio_intr>;
 741                 interrupts = <108 0>, <108 1>, <108 2>;
 742                 interrupt-controller;
 743                 #interrupt-cells = <2>;
 744                 ti,ngpio = <36>;
 745                 ti,davinci-gpio-unbanked = <0>;
 746                 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
 747                 clocks = <&k3_clks 108 0>;
 748                 clock-names = "gpio";
 749         };
 750
 751         main_gpio4: gpio@620000 {
 752                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 753                 reg = <0x0 0x00620000 0x0 0x100>;
 754                 gpio-controller;
 755                 #gpio-cells = <2>;
 756                 interrupt-parent = <&main_gpio_intr>;
 757                 interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
 758                              <109 4>, <109 5>, <109 6>, <109 7>;
 759                 interrupt-controller;
 760                 #interrupt-cells = <2>;
 761                 ti,ngpio = <128>;
 762                 ti,davinci-gpio-unbanked = <0>;
 763                 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 764                 clocks = <&k3_clks 109 0>;
 765                 clock-names = "gpio";
 766         };
 767
 768         main_gpio5: gpio@621000 {
 769                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 770                 reg = <0x0 0x00621000 0x0 0x100>;
 771                 gpio-controller;
 772                 #gpio-cells = <2>;
 773                 interrupt-parent = <&main_gpio_intr>;
 774                 interrupts = <110 0>, <110 1>, <110 2>;
 775                 interrupt-controller;
 776                 #interrupt-cells = <2>;
 777                 ti,ngpio = <36>;
 778                 ti,davinci-gpio-unbanked = <0>;
 779                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 780                 clocks = <&k3_clks 110 0>;
 781                 clock-names = "gpio";
 782         };
 783
 784         main_gpio6: gpio@630000 {
 785                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 786                 reg = <0x0 0x00630000 0x0 0x100>;
 787                 gpio-controller;
 788                 #gpio-cells = <2>;
 789                 interrupt-parent = <&main_gpio_intr>;
 790                 interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
 791                              <111 4>, <111 5>, <111 6>, <111 7>;
 792                 interrupt-controller;
 793                 #interrupt-cells = <2>;
 794                 ti,ngpio = <128>;
 795                 ti,davinci-gpio-unbanked = <0>;
 796                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 797                 clocks = <&k3_clks 111 0>;
 798                 clock-names = "gpio";
 799         };
 800
 801         main_gpio7: gpio@631000 {
 802                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 803                 reg = <0x0 0x00631000 0x0 0x100>;
 804                 gpio-controller;
 805                 #gpio-cells = <2>;
 806                 interrupt-parent = <&main_gpio_intr>;
 807                 interrupts = <112 0>, <112 1>, <112 2>;
 808                 interrupt-controller;
 809                 #interrupt-cells = <2>;
 810                 ti,ngpio = <36>;
 811                 ti,davinci-gpio-unbanked = <0>;
 812                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 813                 clocks = <&k3_clks 112 0>;
 814                 clock-names = "gpio";
 815         };
 816
 817         main_sdhci0: sdhci@4f80000 {
 818                 compatible = "ti,j721e-sdhci-8bit";
 819                 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
 820                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 821                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 822                 clock-names = "clk_xin", "clk_ahb";
 823                 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
 824                 assigned-clocks = <&k3_clks 91 1>;
 825                 assigned-clock-parents = <&k3_clks 91 2>;
 826                 bus-width = <8>;
 827                 mmc-hs400-1_8v;
 828                 mmc-ddr-1_8v;
 829                 ti,otap-del-sel = <0x2>;
 830                 ti,trm-icp = <0x8>;
 831                 ti,strobe-sel = <0x77>;
 832                 dma-coherent;
 833         };
 834
 835         main_sdhci1: sdhci@4fb0000 {
 836                 compatible = "ti,j721e-sdhci-4bit";
 837                 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
 838                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 839                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 840                 clock-names = "clk_xin", "clk_ahb";
 841                 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
 842                 assigned-clocks = <&k3_clks 92 0>;
 843                 assigned-clock-parents = <&k3_clks 92 1>;
 844                 ti,otap-del-sel = <0x2>;
 845                 ti,trm-icp = <0x8>;
 846                 ti,clkbuf-sel = <0x7>;
 847                 dma-coherent;
 848                 no-1-8-v;
 849         };
 850
 851         main_sdhci2: sdhci@4f98000 {
 852                 compatible = "ti,j721e-sdhci-4bit";
 853                 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
 854                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 855                 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
 856                 clock-names = "clk_xin", "clk_ahb";
 857                 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
 858                 assigned-clocks = <&k3_clks 93 0>;
 859                 assigned-clock-parents = <&k3_clks 93 1>;
 860                 ti,otap-del-sel = <0x2>;
 861                 ti,trm-icp = <0x8>;
 862                 ti,clkbuf-sel = <0x7>;
 863                 dma-coherent;
 864                 no-1-8-v;
 865         };
 866
 867         usbss0: cdns_usb@4104000 {
 868                 compatible = "ti,j721e-usb";
 869                 reg = <0x00 0x4104000 0x00 0x100>;
 870                 dma-coherent;
 871                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 872                 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
 873                 clock-names = "ref", "lpm";
 874                 assigned-clocks = <&k3_clks 288 15>;    /* USB2_REFCLK */
 875                 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
 876                 #address-cells = <2>;
 877                 #size-cells = <2>;
 878                 ranges;
 879
 880                 usb0: usb@6000000 {
 881                         compatible = "cdns,usb3";
 882                         reg = <0x00 0x6000000 0x00 0x10000>,
 883                               <0x00 0x6010000 0x00 0x10000>,
 884                               <0x00 0x6020000 0x00 0x10000>;
 885                         reg-names = "otg", "xhci", "dev";
 886                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
 887                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 888                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 889                         interrupt-names = "host",
 890                                           "peripheral",
 891                                           "otg";
 892                         maximum-speed = "super-speed";
 893                         dr_mode = "otg";
 894                 };
 895         };
 896
 897         usbss1: cdns_usb@4114000 {
 898                 compatible = "ti,j721e-usb";
 899                 reg = <0x00 0x4114000 0x00 0x100>;
 900                 dma-coherent;
 901                 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
 902                 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
 903                 clock-names = "ref", "lpm";
 904                 assigned-clocks = <&k3_clks 289 15>;    /* USB2_REFCLK */
 905                 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
 906                 #address-cells = <2>;
 907                 #size-cells = <2>;
 908                 ranges;
 909
 910                 usb1: usb@6400000 {
 911                         compatible = "cdns,usb3";
 912                         reg = <0x00 0x6400000 0x00 0x10000>,
 913                               <0x00 0x6410000 0x00 0x10000>,
 914                               <0x00 0x6420000 0x00 0x10000>;
 915                         reg-names = "otg", "xhci", "dev";
 916                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 917                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 918                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 919                         interrupt-names = "host",
 920                                           "peripheral",
 921                                           "otg";
 922                         maximum-speed = "super-speed";
 923                         dr_mode = "otg";
 924                 };
 925         };
 926
 927         main_i2c0: i2c@2000000 {
 928                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 929                 reg = <0x0 0x2000000 0x0 0x100>;
 930                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 931                 #address-cells = <1>;
 932                 #size-cells = <0>;
 933                 clock-names = "fck";
 934                 clocks = <&k3_clks 187 0>;
 935                 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
 936         };
 937
 938         main_i2c1: i2c@2010000 {
 939                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 940                 reg = <0x0 0x2010000 0x0 0x100>;
 941                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 942                 #address-cells = <1>;
 943                 #size-cells = <0>;
 944                 clock-names = "fck";
 945                 clocks = <&k3_clks 188 0>;
 946                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 947         };
 948
 949         main_i2c2: i2c@2020000 {
 950                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 951                 reg = <0x0 0x2020000 0x0 0x100>;
 952                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 953                 #address-cells = <1>;
 954                 #size-cells = <0>;
 955                 clock-names = "fck";
 956                 clocks = <&k3_clks 189 0>;
 957                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 958         };
 959
 960         main_i2c3: i2c@2030000 {
 961                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 962                 reg = <0x0 0x2030000 0x0 0x100>;
 963                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 964                 #address-cells = <1>;
 965                 #size-cells = <0>;
 966                 clock-names = "fck";
 967                 clocks = <&k3_clks 190 0>;
 968                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 969         };
 970
 971         main_i2c4: i2c@2040000 {
 972                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 973                 reg = <0x0 0x2040000 0x0 0x100>;
 974                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 975                 #address-cells = <1>;
 976                 #size-cells = <0>;
 977                 clock-names = "fck";
 978                 clocks = <&k3_clks 191 0>;
 979                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 980         };
 981
 982         main_i2c5: i2c@2050000 {
 983                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 984                 reg = <0x0 0x2050000 0x0 0x100>;
 985                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 986                 #address-cells = <1>;
 987                 #size-cells = <0>;
 988                 clock-names = "fck";
 989                 clocks = <&k3_clks 192 0>;
 990                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 991         };
 992
 993         main_i2c6: i2c@2060000 {
 994                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 995                 reg = <0x0 0x2060000 0x0 0x100>;
 996                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 997                 #address-cells = <1>;
 998                 #size-cells = <0>;
 999                 clock-names = "fck";
1000                 clocks = <&k3_clks 193 0>;
1001                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1002         };
1003
1004         ufs_wrapper: ufs-wrapper@4e80000 {
1005                 compatible = "ti,j721e-ufs";
1006                 reg = <0x0 0x4e80000 0x0 0x100>;
1007                 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1008                 clocks = <&k3_clks 277 1>;
1009                 assigned-clocks = <&k3_clks 277 1>;
1010                 assigned-clock-parents = <&k3_clks 277 4>;
1011                 ranges;
1012                 #address-cells = <2>;
1013                 #size-cells = <2>;
1014
1015                 ufs@4e84000 {
1016                         compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1017                         reg = <0x0 0x4e84000 0x0 0x10000>;
1018                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1019                         freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1020                         clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1021                         clock-names = "core_clk", "phy_clk", "ref_clk";
1022                         dma-coherent;
1023                 };
1024         };
1025
1026         dss: dss@04a00000 {
1027                 compatible = "ti,j721e-dss";
1028                 reg =
1029                         <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1030                         <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1031                         <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1032                         <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1033
1034                         <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1035                         <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1036                         <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1037                         <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1038
1039                         <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1040                         <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1041                         <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1042                         <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1043
1044                         <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1045                         <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1046                         <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1047                         <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1048                         <0x00 0x04af0000 0x00 0x10000>; /* wb */
1049
1050                 reg-names = "common_m", "common_s0",
1051                         "common_s1", "common_s2",
1052                         "vidl1", "vidl2","vid1","vid2",
1053                         "ovr1", "ovr2", "ovr3", "ovr4",
1054                         "vp1", "vp2", "vp3", "vp4",
1055                         "wb";
1056
1057                 clocks =        <&k3_clks 152 0>,
1058                                 <&k3_clks 152 1>,
1059                                 <&k3_clks 152 4>,
1060                                 <&k3_clks 152 9>,
1061                                 <&k3_clks 152 13>;
1062                 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1063
1064                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1065
1066                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1067                              <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1068                              <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1069                              <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1070                 interrupt-names = "common_m",
1071                                   "common_s0",
1072                                   "common_s1",
1073                                   "common_s2";
1074
1075                 status = "disabled";
1076
1077                 dss_ports: ports {
1078                         #address-cells = <1>;
1079                         #size-cells = <0>;
1080                 };
1081         };
1082
1083         mcasp0: mcasp@2b00000 {
1084                 compatible = "ti,am33xx-mcasp-audio";
1085                 reg = <0x0 0x02b00000 0x0 0x2000>,
1086                         <0x0 0x02b08000 0x0 0x1000>;
1087                 reg-names = "mpu","dat";
1088                 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1089                                 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1090                 interrupt-names = "tx", "rx";
1091
1092                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1093                 dma-names = "tx", "rx";
1094
1095                 clocks = <&k3_clks 174 1>;
1096                 clock-names = "fck";
1097                 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1098
1099                 status = "disabled";
1100         };
1101
1102         mcasp1: mcasp@2b10000 {
1103                 compatible = "ti,am33xx-mcasp-audio";
1104                 reg = <0x0 0x02b10000 0x0 0x2000>,
1105                         <0x0 0x02b18000 0x0 0x1000>;
1106                 reg-names = "mpu","dat";
1107                 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1108                                 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1109                 interrupt-names = "tx", "rx";
1110
1111                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1112                 dma-names = "tx", "rx";
1113
1114                 clocks = <&k3_clks 175 1>;
1115                 clock-names = "fck";
1116                 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1117
1118                 status = "disabled";
1119         };
1120
1121         mcasp2: mcasp@2b20000 {
1122                 compatible = "ti,am33xx-mcasp-audio";
1123                 reg = <0x0 0x02b20000 0x0 0x2000>,
1124                         <0x0 0x02b28000 0x0 0x1000>;
1125                 reg-names = "mpu","dat";
1126                 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1127                                 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1128                 interrupt-names = "tx", "rx";
1129
1130                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1131                 dma-names = "tx", "rx";
1132
1133                 clocks = <&k3_clks 176 1>;
1134                 clock-names = "fck";
1135                 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1136
1137                 status = "disabled";
1138         };
1139
1140         mcasp3: mcasp@2b30000 {
1141                 compatible = "ti,am33xx-mcasp-audio";
1142                 reg = <0x0 0x02b30000 0x0 0x2000>,
1143                         <0x0 0x02b38000 0x0 0x1000>;
1144                 reg-names = "mpu","dat";
1145                 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1146                                 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1147                 interrupt-names = "tx", "rx";
1148
1149                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1150                 dma-names = "tx", "rx";
1151
1152                 clocks = <&k3_clks 177 1>;
1153                 clock-names = "fck";
1154                 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1155
1156                 status = "disabled";
1157         };
1158
1159         mcasp4: mcasp@2b40000 {
1160                 compatible = "ti,am33xx-mcasp-audio";
1161                 reg = <0x0 0x02b40000 0x0 0x2000>,
1162                         <0x0 0x02b48000 0x0 0x1000>;
1163                 reg-names = "mpu","dat";
1164                 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1165                                 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1166                 interrupt-names = "tx", "rx";
1167
1168                 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1169                 dma-names = "tx", "rx";
1170
1171                 clocks = <&k3_clks 178 1>;
1172                 clock-names = "fck";
1173                 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1174
1175                 status = "disabled";
1176         };
1177
1178         mcasp5: mcasp@2b50000 {
1179                 compatible = "ti,am33xx-mcasp-audio";
1180                 reg = <0x0 0x02b50000 0x0 0x2000>,
1181                         <0x0 0x02b58000 0x0 0x1000>;
1182                 reg-names = "mpu","dat";
1183                 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1184                                 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1185                 interrupt-names = "tx", "rx";
1186
1187                 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1188                 dma-names = "tx", "rx";
1189
1190                 clocks = <&k3_clks 179 1>;
1191                 clock-names = "fck";
1192                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1193
1194                 status = "disabled";
1195         };
1196
1197         mcasp6: mcasp@2b60000 {
1198                 compatible = "ti,am33xx-mcasp-audio";
1199                 reg = <0x0 0x02b60000 0x0 0x2000>,
1200                         <0x0 0x02b68000 0x0 0x1000>;
1201                 reg-names = "mpu","dat";
1202                 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1203                                 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1204                 interrupt-names = "tx", "rx";
1205
1206                 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1207                 dma-names = "tx", "rx";
1208
1209                 clocks = <&k3_clks 180 1>;
1210                 clock-names = "fck";
1211                 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1212
1213                 status = "disabled";
1214         };
1215
1216         mcasp7: mcasp@2b70000 {
1217                 compatible = "ti,am33xx-mcasp-audio";
1218                 reg = <0x0 0x02b70000 0x0 0x2000>,
1219                         <0x0 0x02b78000 0x0 0x1000>;
1220                 reg-names = "mpu","dat";
1221                 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1222                                 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1223                 interrupt-names = "tx", "rx";
1224
1225                 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1226                 dma-names = "tx", "rx";
1227
1228                 clocks = <&k3_clks 181 1>;
1229                 clock-names = "fck";
1230                 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1231
1232                 status = "disabled";
1233         };
1234
1235         mcasp8: mcasp@2b80000 {
1236                 compatible = "ti,am33xx-mcasp-audio";
1237                 reg = <0x0 0x02b80000 0x0 0x2000>,
1238                         <0x0 0x02b88000 0x0 0x1000>;
1239                 reg-names = "mpu","dat";
1240                 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1241                                 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1242                 interrupt-names = "tx", "rx";
1243
1244                 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1245                 dma-names = "tx", "rx";
1246
1247                 clocks = <&k3_clks 182 1>;
1248                 clock-names = "fck";
1249                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1250
1251                 status = "disabled";
1252         };
1253
1254         mcasp9: mcasp@2b90000 {
1255                 compatible = "ti,am33xx-mcasp-audio";
1256                 reg = <0x0 0x02b90000 0x0 0x2000>,
1257                         <0x0 0x02b98000 0x0 0x1000>;
1258                 reg-names = "mpu","dat";
1259                 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1260                                 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1261                 interrupt-names = "tx", "rx";
1262
1263                 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1264                 dma-names = "tx", "rx";
1265
1266                 clocks = <&k3_clks 183 1>;
1267                 clock-names = "fck";
1268                 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1269
1270                 status = "disabled";
1271         };
1272
1273         mcasp10: mcasp@2ba0000 {
1274                 compatible = "ti,am33xx-mcasp-audio";
1275                 reg = <0x0 0x02ba0000 0x0 0x2000>,
1276                         <0x0 0x02ba8000 0x0 0x1000>;
1277                 reg-names = "mpu","dat";
1278                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1279                                 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1280                 interrupt-names = "tx", "rx";
1281
1282                 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1283                 dma-names = "tx", "rx";
1284
1285                 clocks = <&k3_clks 184 1>;
1286                 clock-names = "fck";
1287                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1288
1289                 status = "disabled";
1290         };
1291
1292         mcasp11: mcasp@2bb0000 {
1293                 compatible = "ti,am33xx-mcasp-audio";
1294                 reg = <0x0 0x02bb0000 0x0 0x2000>,
1295                         <0x0 0x02bb8000 0x0 0x1000>;
1296                 reg-names = "mpu","dat";
1297                 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1298                                 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1299                 interrupt-names = "tx", "rx";
1300
1301                 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1302                 dma-names = "tx", "rx";
1303
1304                 clocks = <&k3_clks 185 1>;
1305                 clock-names = "fck";
1306                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1307
1308                 status = "disabled";
1309         };
1310
1311         watchdog0: watchdog@2200000 {
1312                 compatible = "ti,j7-rti-wdt";
1313                 reg = <0x0 0x2200000 0x0 0x100>;
1314                 clocks = <&k3_clks 252 1>;
1315                 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1316                 assigned-clocks = <&k3_clks 252 1>;
1317                 assigned-clock-parents = <&k3_clks 252 5>;
1318         };
1319
1320         watchdog1: watchdog@2210000 {
1321                 compatible = "ti,j7-rti-wdt";
1322                 reg = <0x0 0x2210000 0x0 0x100>;
1323                 clocks = <&k3_clks 253 1>;
1324                 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1325                 assigned-clocks = <&k3_clks 253 1>;
1326                 assigned-clock-parents = <&k3_clks 253 5>;
1327         };
1328 };