arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         dmsc: dmsc@44083000 {
  10                 compatible = "ti,k2g-sci";
  11                 ti,host-id = <12>;
  12
  13                 mbox-names = "rx", "tx";
  14
  15                 mboxes= <&secure_proxy_main 11>,
  16                         <&secure_proxy_main 13>;
  17
  18                 reg-names = "debug_messages";
  19                 reg = <0x00 0x44083000 0x00 0x1000>;
  20
  21                 k3_pds: power-controller {
  22                         compatible = "ti,sci-pm-domain";
  23                         #power-domain-cells = <2>;
  24                 };
  25
  26                 k3_clks: clocks {
  27                         compatible = "ti,k2g-sci-clk";
  28                         #clock-cells = <2>;
  29                 };
  30
  31                 k3_reset: reset-controller {
  32                         compatible = "ti,sci-reset";
  33                         #reset-cells = <2>;
  34                 };
  35         };
  36
  37         mcu_conf: syscon@40f00000 {
  38                 compatible = "syscon", "simple-mfd";
  39                 reg = <0x00 0x40f00000 0x00 0x20000>;
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 ranges = <0x00 0x00 0x40f00000 0x20000>;
  43
  44                 phy_gmii_sel: phy@4040 {
  45                         compatible = "ti,am654-phy-gmii-sel";
  46                         reg = <0x4040 0x4>;
  47                         #phy-cells = <1>;
  48                 };
  49         };
  50
  51         chipid@43000014 {
  52                 compatible = "ti,am654-chipid";
  53                 reg = <0x00 0x43000014 0x00 0x4>;
  54         };
  55
  56         wkup_pmx0: pinctrl@4301c000 {
  57                 compatible = "pinctrl-single";
  58                 /* Proxy 0 addressing */
  59                 reg = <0x00 0x4301c000 0x00 0x178>;
  60                 #pinctrl-cells = <1>;
  61                 pinctrl-single,register-width = <32>;
  62                 pinctrl-single,function-mask = <0xffffffff>;
  63         };
  64
  65         mcu_ram: sram@41c00000 {
  66                 compatible = "mmio-sram";
  67                 reg = <0x00 0x41c00000 0x00 0x100000>;
  68                 ranges = <0x00 0x00 0x41c00000 0x100000>;
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71         };
  72
  73         wkup_uart0: serial@42300000 {
  74                 compatible = "ti,j721e-uart", "ti,am654-uart";
  75                 reg = <0x00 0x42300000 0x00 0x100>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <4>;
  78                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  79                 clock-frequency = <48000000>;
  80                 current-speed = <115200>;
  81                 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  82                 clocks = <&k3_clks 287 2>;
  83                 clock-names = "fclk";
  84         };
  85
  86         mcu_uart0: serial@40a00000 {
  87                 compatible = "ti,j721e-uart", "ti,am654-uart";
  88                 reg = <0x00 0x40a00000 0x00 0x100>;
  89                 reg-shift = <2>;
  90                 reg-io-width = <4>;
  91                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  92                 clock-frequency = <96000000>;
  93                 current-speed = <115200>;
  94                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  95                 clocks = <&k3_clks 149 2>;
  96                 clock-names = "fclk";
  97         };
  98
  99         wkup_gpio_intr: interrupt-controller2 {
 100                 compatible = "ti,sci-intr";
 101                 ti,intr-trigger-type = <1>;
 102                 interrupt-controller;
 103                 interrupt-parent = <&gic500>;
 104                 #interrupt-cells = <1>;
 105                 ti,sci = <&dmsc>;
 106                 ti,sci-dev-id = <137>;
 107                 ti,interrupt-ranges = <16 960 16>;
 108         };
 109
 110         mcu_navss: bus@28380000 {
 111                 compatible = "simple-mfd";
 112                 #address-cells = <2>;
 113                 #size-cells = <2>;
 114                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 115                 dma-coherent;
 116                 dma-ranges;
 117                 ti,sci-dev-id = <232>;
 118
 119                 mcu_ringacc: ringacc@2b800000 {
 120                         compatible = "ti,am654-navss-ringacc";
 121                         reg =   <0x00 0x2b800000 0x00 0x400000>,
 122                                 <0x00 0x2b000000 0x00 0x400000>,
 123                                 <0x00 0x28590000 0x00 0x100>,
 124                                 <0x00 0x2a500000 0x00 0x40000>;
 125                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 126                         ti,num-rings = <286>;
 127                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 128                         ti,sci = <&dmsc>;
 129                         ti,sci-dev-id = <235>;
 130                         msi-parent = <&main_udmass_inta>;
 131                 };
 132
 133                 mcu_udmap: dma-controller@285c0000 {
 134                         compatible = "ti,j721e-navss-mcu-udmap";
 135                         reg =   <0x00 0x285c0000 0x00 0x100>,
 136                                 <0x00 0x2a800000 0x00 0x40000>,
 137                                 <0x00 0x2aa00000 0x00 0x40000>;
 138                         reg-names = "gcfg", "rchanrt", "tchanrt";
 139                         msi-parent = <&main_udmass_inta>;
 140                         #dma-cells = <1>;
 141
 142                         ti,sci = <&dmsc>;
 143                         ti,sci-dev-id = <236>;
 144                         ti,ringacc = <&mcu_ringacc>;
 145
 146                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 147                                                 <0x0f>; /* TX_HCHAN */
 148                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 149                                                 <0x0b>; /* RX_HCHAN */
 150                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 151                 };
 152         };
 153
 154         mcu_cpsw: ethernet@46000000 {
 155                 compatible = "ti,j721e-cpsw-nuss";
 156                 #address-cells = <2>;
 157                 #size-cells = <2>;
 158                 reg = <0x00 0x46000000 0x00 0x200000>;
 159                 reg-names = "cpsw_nuss";
 160                 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
 161                 dma-coherent;
 162                 clocks = <&k3_clks 18 21>;
 163                 clock-names = "fck";
 164                 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
 165
 166                 dmas = <&mcu_udmap 0xf000>,
 167                        <&mcu_udmap 0xf001>,
 168                        <&mcu_udmap 0xf002>,
 169                        <&mcu_udmap 0xf003>,
 170                        <&mcu_udmap 0xf004>,
 171                        <&mcu_udmap 0xf005>,
 172                        <&mcu_udmap 0xf006>,
 173                        <&mcu_udmap 0xf007>,
 174                        <&mcu_udmap 0x7000>;
 175                 dma-names = "tx0", "tx1", "tx2", "tx3",
 176                             "tx4", "tx5", "tx6", "tx7",
 177                             "rx";
 178
 179                 ethernet-ports {
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182
 183                         cpsw_port1: port@1 {
 184                                 reg = <1>;
 185                                 ti,mac-only;
 186                                 label = "port1";
 187                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 188                                 phys = <&phy_gmii_sel 1>;
 189                         };
 190                 };
 191
 192                 davinci_mdio: mdio@f00 {
 193                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 194                         reg = <0x00 0xf00 0x00 0x100>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         clocks = <&k3_clks 18 21>;
 198                         clock-names = "fck";
 199                         bus_freq = <1000000>;
 200                 };
 201
 202                 cpts@3d000 {
 203                         compatible = "ti,am65-cpts";
 204                         reg = <0x00 0x3d000 0x00 0x400>;
 205                         clocks = <&k3_clks 18 2>;
 206                         clock-names = "cpts";
 207                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 208                         interrupt-names = "cpts";
 209                         ti,cpts-ext-ts-inputs = <4>;
 210                         ti,cpts-periodic-outputs = <2>;
 211                 };
 212         };
 213
 214         mcu_i2c0: i2c@40b00000 {
 215                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 216                 reg = <0x00 0x40b00000 0x00 0x100>;
 217                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 clock-names = "fck";
 221                 clocks = <&k3_clks 194 1>;
 222                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 223         };
 224
 225         mcu_i2c1: i2c@40b10000 {
 226                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 227                 reg = <0x00 0x40b10000 0x00 0x100>;
 228                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 clock-names = "fck";
 232                 clocks = <&k3_clks 195 1>;
 233                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
 234         };
 235
 236         wkup_i2c0: i2c@42120000 {
 237                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 238                 reg = <0x00 0x42120000 0x00 0x100>;
 239                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242                 clock-names = "fck";
 243                 clocks = <&k3_clks 197 1>;
 244                 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
 245         };
 246
 247         fss: syscon@47000000 {
 248                 compatible = "syscon", "simple-mfd";
 249                 reg = <0x00 0x47000000 0x00 0x100>;
 250                 #address-cells = <2>;
 251                 #size-cells = <2>;
 252                 ranges;
 253
 254                 hbmc_mux: hbmc-mux {
 255                         compatible = "mmio-mux";
 256                         #mux-control-cells = <1>;
 257                         mux-reg-masks = <0x4 0x2>; /* HBMC select */
 258                 };
 259
 260                 hbmc: hyperbus@47034000 {
 261                         compatible = "ti,am654-hbmc";
 262                         reg = <0x00 0x47034000 0x00 0x100>,
 263                                 <0x05 0x00000000 0x01 0x0000000>;
 264                         power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 265                         clocks = <&k3_clks 102 0>;
 266                         assigned-clocks = <&k3_clks 102 5>;
 267                         assigned-clock-rates = <333333333>;
 268                         #address-cells = <2>;
 269                         #size-cells = <1>;
 270                         mux-controls = <&hbmc_mux 0>;
 271                 };
 272         };
 273
 274         tscadc0: tscadc@40200000 {
 275                 compatible = "ti,am3359-tscadc";
 276                 reg = <0x00 0x40200000 0x00 0x1000>;
 277                 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 278                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 279                 clocks = <&k3_clks 0 1>;
 280                 assigned-clocks = <&k3_clks 0 3>;
 281                 assigned-clock-rates = <60000000>;
 282                 clock-names = "adc_tsc_fck";
 283                 dmas = <&main_udmap 0x7400>,
 284                         <&main_udmap 0x7401>;
 285                 dma-names = "fifo0", "fifo1";
 286
 287                 adc {
 288                         #io-channel-cells = <1>;
 289                         compatible = "ti,am3359-adc";
 290                 };
 291         };
 292 };