1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for AM6 SoC Family
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/k3.h>
12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 model = "Texas Instruments K3 AM654 SoC";
16 compatible = "ti,am654";
17 interrupt-parent = <&gic500>;
22 serial0 = &wkup_uart0;
24 serial2 = &main_uart0;
25 serial3 = &main_uart1;
26 serial4 = &main_uart2;
33 ethernet0 = &cpsw_port1;
40 compatible = "linaro,optee-tz";
45 compatible = "arm,psci-1.0";
50 a53_timer0: timer-cl0-cpu0 {
51 compatible = "arm,armv8-timer";
52 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
53 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
54 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
55 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
59 compatible = "arm,armv8-pmuv3";
60 /* Recommendation from GIC500 TRM Table A.3 */
61 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
64 cbass_main: bus@100000 {
65 compatible = "simple-bus";
68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
79 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
80 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
81 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
82 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
83 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
84 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
85 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
86 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
87 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
88 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
89 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
91 cbass_mcu: bus@28380000 {
92 compatible = "simple-bus";
95 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
96 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
97 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
98 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
99 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
100 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
101 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
102 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
103 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
104 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
105 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
106 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
107 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
109 cbass_wakeup: bus@42040000 {
110 compatible = "simple-bus";
111 #address-cells = <1>;
113 /* WKUP Basic peripherals */
114 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
120 /* Now include the peripherals for each bus segments */
121 #include "k3-am65-main.dtsi"
122 #include "k3-am65-mcu.dtsi"
123 #include "k3-am65-wakeup.dtsi"