arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family MCU Domain peripherals
   4  *
   5  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu {
   9         mcu_conf: scm-conf@40f00000 {
  10                 compatible = "syscon", "simple-mfd";
  11                 reg = <0x0 0x40f00000 0x0 0x20000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x40f00000 0x20000>;
  15
  16                 phy_gmii_sel: phy@4040 {
  17                         compatible = "ti,am654-phy-gmii-sel";
  18                         reg = <0x4040 0x4>;
  19                         #phy-cells = <1>;
  20                 };
  21         };
  22
  23         mcu_uart0: serial@40a00000 {
  24                 compatible = "ti,am654-uart";
  25                         reg = <0x00 0x40a00000 0x00 0x100>;
  26                         interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
  27                         clock-frequency = <96000000>;
  28                         current-speed = <115200>;
  29                         power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  30         };
  31
  32         mcu_ram: sram@41c00000 {
  33                 compatible = "mmio-sram";
  34                 reg = <0x00 0x41c00000 0x00 0x80000>;
  35                 ranges = <0x0 0x00 0x41c00000 0x80000>;
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38         };
  39
  40         mcu_i2c0: i2c@40b00000 {
  41                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
  42                 reg = <0x0 0x40b00000 0x0 0x100>;
  43                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 clock-names = "fck";
  47                 clocks = <&k3_clks 114 1>;
  48                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
  49         };
  50
  51         mcu_spi0: spi@40300000 {
  52                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  53                 reg = <0x0 0x40300000 0x0 0x400>;
  54                 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
  55                 clocks = <&k3_clks 142 1>;
  56                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59         };
  60
  61         mcu_spi1: spi@40310000 {
  62                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  63                 reg = <0x0 0x40310000 0x0 0x400>;
  64                 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
  65                 clocks = <&k3_clks 143 1>;
  66                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69         };
  70
  71         mcu_spi2: spi@40320000 {
  72                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  73                 reg = <0x0 0x40320000 0x0 0x400>;
  74                 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
  75                 clocks = <&k3_clks 144 1>;
  76                 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79         };
  80
  81         tscadc0: tscadc@40200000 {
  82                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
  83                 reg = <0x0 0x40200000 0x0 0x1000>;
  84                 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
  85                 clocks = <&k3_clks 0 2>;
  86                 assigned-clocks = <&k3_clks 0 2>;
  87                 assigned-clock-rates = <60000000>;
  88                 clock-names = "fck";
  89                 dmas = <&mcu_udmap 0x7100>,
  90                         <&mcu_udmap 0x7101 >;
  91                 dma-names = "fifo0", "fifo1";
  92
  93                 adc {
  94                         #io-channel-cells = <1>;
  95                         compatible = "ti,am654-adc", "ti,am3359-adc";
  96                 };
  97         };
  98
  99         tscadc1: tscadc@40210000 {
 100                 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
 101                 reg = <0x0 0x40210000 0x0 0x1000>;
 102                 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
 103                 clocks = <&k3_clks 1 2>;
 104                 assigned-clocks = <&k3_clks 1 2>;
 105                 assigned-clock-rates = <60000000>;
 106                 clock-names = "fck";
 107                 dmas = <&mcu_udmap 0x7102>,
 108                         <&mcu_udmap 0x7103>;
 109                 dma-names = "fifo0", "fifo1";
 110
 111                 adc {
 112                         #io-channel-cells = <1>;
 113                         compatible = "ti,am654-adc", "ti,am3359-adc";
 114                 };
 115         };
 116
 117         mcu_navss: bus@28380000 {
 118                 compatible = "simple-mfd";
 119                 #address-cells = <2>;
 120                 #size-cells = <2>;
 121                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 122                 dma-coherent;
 123                 dma-ranges;
 124
 125                 ti,sci-dev-id = <119>;
 126
 127                 mcu_ringacc: ringacc@2b800000 {
 128                         compatible = "ti,am654-navss-ringacc";
 129                         reg =   <0x0 0x2b800000 0x0 0x400000>,
 130                                 <0x0 0x2b000000 0x0 0x400000>,
 131                                 <0x0 0x28590000 0x0 0x100>,
 132                                 <0x0 0x2a500000 0x0 0x40000>;
 133                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 134                         ti,num-rings = <286>;
 135                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 136                         ti,sci = <&dmsc>;
 137                         ti,sci-dev-id = <195>;
 138                         msi-parent = <&inta_main_udmass>;
 139                 };
 140
 141                 mcu_udmap: dma-controller@285c0000 {
 142                         compatible = "ti,am654-navss-mcu-udmap";
 143                         reg =   <0x0 0x285c0000 0x0 0x100>,
 144                                 <0x0 0x2a800000 0x0 0x40000>,
 145                                 <0x0 0x2aa00000 0x0 0x40000>;
 146                         reg-names = "gcfg", "rchanrt", "tchanrt";
 147                         msi-parent = <&inta_main_udmass>;
 148                         #dma-cells = <1>;
 149
 150                         ti,sci = <&dmsc>;
 151                         ti,sci-dev-id = <194>;
 152                         ti,ringacc = <&mcu_ringacc>;
 153
 154                         ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
 155                                                 <0xd>; /* TX_CHAN */
 156                         ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
 157                                                 <0xa>; /* RX_CHAN */
 158                         ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
 159                 };
 160         };
 161
 162         m_can0: mcan@40528000 {
 163                 compatible = "bosch,m_can";
 164                 reg = <0x0 0x40528000 0x0 0x400>,
 165                       <0x0 0x40500000 0x0 0x4400>;
 166                 reg-names = "m_can", "message_ram";
 167                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 168                 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
 169                 clock-names = "hclk", "cclk";
 170                 interrupt-parent = <&gic500>;
 171                 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
 173                 interrupt-names = "int0", "int1";
 174                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 175         };
 176
 177         m_can1: mcan@40568000 {
 178                 compatible = "bosch,m_can";
 179                 reg = <0x0 0x40568000 0x0 0x400>,
 180                       <0x0 0x40540000 0x0 0x4400>;
 181                 reg-names = "m_can", "message_ram";
 182                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 183                 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
 184                 clock-names = "hclk", "cclk";
 185                 interrupt-parent = <&gic500>;
 186                 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
 188                 interrupt-names = "int0", "int1";
 189                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 190         };
 191
 192         fss: fss@47000000 {
 193                 compatible = "simple-bus";
 194                 #address-cells = <2>;
 195                 #size-cells = <2>;
 196                 ranges;
 197
 198                 ospi0: spi@47040000 {
 199                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 200                         reg = <0x0 0x47040000 0x0 0x100>,
 201                                 <0x5 0x00000000 0x1 0x0000000>;
 202                         interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
 203                         cdns,fifo-depth = <256>;
 204                         cdns,fifo-width = <4>;
 205                         cdns,trigger-address = <0x0>;
 206                         clocks = <&k3_clks 248 0>;
 207                         assigned-clocks = <&k3_clks 248 0>;
 208                         assigned-clock-parents = <&k3_clks 248 2>;
 209                         assigned-clock-rates = <166666666>;
 210                         power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                 };
 214
 215                 ospi1: spi@47050000 {
 216                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 217                         reg = <0x0 0x47050000 0x0 0x100>,
 218                                 <0x7 0x00000000 0x1 0x00000000>;
 219                         interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
 220                         cdns,fifo-depth = <256>;
 221                         cdns,fifo-width = <4>;
 222                         cdns,trigger-address = <0x0>;
 223                         clocks = <&k3_clks 249 6>;
 224                         power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                 };
 228         };
 229
 230         mcu_cpsw: ethernet@46000000 {
 231                 compatible = "ti,am654-cpsw-nuss";
 232                 #address-cells = <2>;
 233                 #size-cells = <2>;
 234                 reg = <0x0 0x46000000 0x0 0x200000>;
 235                 reg-names = "cpsw_nuss";
 236                 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 237                 dma-coherent;
 238                 clocks = <&k3_clks 5 10>;
 239                 clock-names = "fck";
 240                 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
 241
 242                 dmas = <&mcu_udmap 0xf000>,
 243                        <&mcu_udmap 0xf001>,
 244                        <&mcu_udmap 0xf002>,
 245                        <&mcu_udmap 0xf003>,
 246                        <&mcu_udmap 0xf004>,
 247                        <&mcu_udmap 0xf005>,
 248                        <&mcu_udmap 0xf006>,
 249                        <&mcu_udmap 0xf007>,
 250                        <&mcu_udmap 0x7000>;
 251                 dma-names = "tx0", "tx1", "tx2", "tx3",
 252                             "tx4", "tx5", "tx6", "tx7",
 253                             "rx";
 254
 255                 ethernet-ports {
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258
 259                         cpsw_port1: port@1 {
 260                                 reg = <1>;
 261                                 ti,mac-only;
 262                                 label = "port1";
 263                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 264                                 phys = <&phy_gmii_sel 1>;
 265                         };
 266                 };
 267
 268                 davinci_mdio: mdio@f00 {
 269                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 270                         reg = <0x0 0xf00 0x0 0x100>;
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         clocks = <&k3_clks 5 10>;
 274                         clock-names = "fck";
 275                         bus_freq = <1000000>;
 276                 };
 277
 278                 cpts@3d000 {
 279                         compatible = "ti,am65-cpts";
 280                         reg = <0x0 0x3d000 0x0 0x400>;
 281                         clocks = <&mcu_cpsw_cpts_mux>;
 282                         clock-names = "cpts";
 283                         interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
 284                         interrupt-names = "cpts";
 285                         ti,cpts-ext-ts-inputs = <4>;
 286                         ti,cpts-periodic-outputs = <2>;
 287
 288                         mcu_cpsw_cpts_mux: refclk-mux {
 289                                 #clock-cells = <0>;
 290                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 291                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 292                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 293                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 294                                 assigned-clocks = <&mcu_cpsw_cpts_mux>;
 295                                 assigned-clock-parents = <&k3_clks 118 5>;
 296                         };
 297                 };
 298         };
 299
 300         mcu_r5fss0: r5fss@41000000 {
 301                 compatible = "ti,am654-r5fss";
 302                 ti,cluster-mode = <1>;
 303                 #address-cells = <1>;
 304                 #size-cells = <1>;
 305                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 306                          <0x41400000 0x00 0x41400000 0x20000>;
 307                 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
 308
 309                 mcu_r5fss0_core0: r5f@41000000 {
 310                         compatible = "ti,am654-r5f";
 311                         reg = <0x41000000 0x00008000>,
 312                               <0x41010000 0x00008000>;
 313                         reg-names = "atcm", "btcm";
 314                         ti,sci = <&dmsc>;
 315                         ti,sci-dev-id = <159>;
 316                         ti,sci-proc-ids = <0x01 0xff>;
 317                         resets = <&k3_reset 159 1>;
 318                         firmware-name = "am65x-mcu-r5f0_0-fw";
 319                         ti,atcm-enable = <1>;
 320                         ti,btcm-enable = <1>;
 321                         ti,loczrama = <1>;
 322                 };
 323
 324                 mcu_r5fss0_core1: r5f@41400000 {
 325                         compatible = "ti,am654-r5f";
 326                         reg = <0x41400000 0x00008000>,
 327                               <0x41410000 0x00008000>;
 328                         reg-names = "atcm", "btcm";
 329                         ti,sci = <&dmsc>;
 330                         ti,sci-dev-id = <245>;
 331                         ti,sci-proc-ids = <0x02 0xff>;
 332                         resets = <&k3_reset 245 1>;
 333                         firmware-name = "am65x-mcu-r5f0_1-fw";
 334                         ti,atcm-enable = <1>;
 335                         ti,btcm-enable = <1>;
 336                         ti,loczrama = <1>;
 337                 };
 338         };
 339
 340         mcu_rti1: watchdog@40610000 {
 341                 compatible = "ti,j7-rti-wdt";
 342                 reg = <0x0 0x40610000 0x0 0x100>;
 343                 clocks = <&k3_clks 135 0>;
 344                 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
 345                 assigned-clocks = <&k3_clks 135 0>;
 346                 assigned-clock-parents = <&k3_clks 135 4>;
 347         };
 348 };