1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
10 msmc_ram: sram@70000000 {
11 compatible = "mmio-sram";
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
30 gic500: interrupt-controller@1800000 {
31 compatible = "arm,gic-v3";
35 #interrupt-cells = <3>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>; /* GICR */
41 * virtual CPU interface maintenance interrupt
43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
45 gic_its: msi-controller@1820000 {
46 compatible = "arm,gic-v3-its";
47 reg = <0x00 0x01820000 0x00 0x10000>;
48 socionext,synquacer-pre-its = <0x1000000 0x400000>;
54 serdes0: serdes@900000 {
55 compatible = "ti,phy-am654-serdes";
56 reg = <0x0 0x900000 0x0 0x2000>;
59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
60 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
64 ti,serdes-clk = <&serdes0_clk>;
66 mux-controls = <&serdes_mux 0>;
69 serdes1: serdes@910000 {
70 compatible = "ti,phy-am654-serdes";
71 reg = <0x0 0x910000 0x0 0x2000>;
74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
75 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
79 ti,serdes-clk = <&serdes1_clk>;
81 mux-controls = <&serdes_mux 1>;
84 main_uart0: serial@2800000 {
85 compatible = "ti,am654-uart";
86 reg = <0x00 0x02800000 0x00 0x100>;
89 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
90 clock-frequency = <48000000>;
91 current-speed = <115200>;
92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
95 main_uart1: serial@2810000 {
96 compatible = "ti,am654-uart";
97 reg = <0x00 0x02810000 0x00 0x100>;
100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
101 clock-frequency = <48000000>;
102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
105 main_uart2: serial@2820000 {
106 compatible = "ti,am654-uart";
107 reg = <0x00 0x02820000 0x00 0x100>;
110 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
111 clock-frequency = <48000000>;
112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
115 main_pmx0: pinmux@11c000 {
116 compatible = "pinctrl-single";
117 reg = <0x0 0x11c000 0x0 0x2e4>;
118 #pinctrl-cells = <1>;
119 pinctrl-single,register-width = <32>;
120 pinctrl-single,function-mask = <0xffffffff>;
123 main_pmx1: pinmux@11c2e8 {
124 compatible = "pinctrl-single";
125 reg = <0x0 0x11c2e8 0x0 0x24>;
126 #pinctrl-cells = <1>;
127 pinctrl-single,register-width = <32>;
128 pinctrl-single,function-mask = <0xffffffff>;
131 main_i2c0: i2c@2000000 {
132 compatible = "ti,am654-i2c", "ti,omap4-i2c";
133 reg = <0x0 0x2000000 0x0 0x100>;
134 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
135 #address-cells = <1>;
138 clocks = <&k3_clks 110 1>;
139 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
142 main_i2c1: i2c@2010000 {
143 compatible = "ti,am654-i2c", "ti,omap4-i2c";
144 reg = <0x0 0x2010000 0x0 0x100>;
145 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
146 #address-cells = <1>;
149 clocks = <&k3_clks 111 1>;
150 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
153 main_i2c2: i2c@2020000 {
154 compatible = "ti,am654-i2c", "ti,omap4-i2c";
155 reg = <0x0 0x2020000 0x0 0x100>;
156 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
157 #address-cells = <1>;
160 clocks = <&k3_clks 112 1>;
161 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
164 main_i2c3: i2c@2030000 {
165 compatible = "ti,am654-i2c", "ti,omap4-i2c";
166 reg = <0x0 0x2030000 0x0 0x100>;
167 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
168 #address-cells = <1>;
171 clocks = <&k3_clks 113 1>;
172 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
176 compatible = "ti,am654-ecap", "ti,am3352-ecap";
178 reg = <0x0 0x03100000 0x0 0x60>;
179 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
180 clocks = <&k3_clks 39 0>;
184 main_spi0: spi@2100000 {
185 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
186 reg = <0x0 0x2100000 0x0 0x400>;
187 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&k3_clks 137 1>;
189 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
190 #address-cells = <1>;
192 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
193 dma-names = "tx0", "rx0";
196 main_spi1: spi@2110000 {
197 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
198 reg = <0x0 0x2110000 0x0 0x400>;
199 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&k3_clks 138 1>;
201 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
202 #address-cells = <1>;
204 assigned-clocks = <&k3_clks 137 1>;
205 assigned-clock-rates = <48000000>;
208 main_spi2: spi@2120000 {
209 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
210 reg = <0x0 0x2120000 0x0 0x400>;
211 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&k3_clks 139 1>;
213 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
214 #address-cells = <1>;
218 main_spi3: spi@2130000 {
219 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
220 reg = <0x0 0x2130000 0x0 0x400>;
221 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&k3_clks 140 1>;
223 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
224 #address-cells = <1>;
228 main_spi4: spi@2140000 {
229 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
230 reg = <0x0 0x2140000 0x0 0x400>;
231 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&k3_clks 141 1>;
233 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
234 #address-cells = <1>;
238 sdhci0: sdhci@4f80000 {
239 compatible = "ti,am654-sdhci-5.1";
240 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
241 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
242 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
243 clock-names = "clk_ahb", "clk_xin";
244 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
247 ti,otap-del-sel-legacy = <0x0>;
248 ti,otap-del-sel-mmc-hs = <0x0>;
249 ti,otap-del-sel-sd-hs = <0x0>;
250 ti,otap-del-sel-sdr12 = <0x0>;
251 ti,otap-del-sel-sdr25 = <0x0>;
252 ti,otap-del-sel-sdr50 = <0x8>;
253 ti,otap-del-sel-sdr104 = <0x7>;
254 ti,otap-del-sel-ddr50 = <0x5>;
255 ti,otap-del-sel-ddr52 = <0x5>;
256 ti,otap-del-sel-hs200 = <0x5>;
257 ti,otap-del-sel-hs400 = <0x0>;
262 sdhci1: sdhci@4fa0000 {
263 compatible = "ti,am654-sdhci-5.1";
264 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
265 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
266 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
267 clock-names = "clk_ahb", "clk_xin";
268 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
269 ti,otap-del-sel-legacy = <0x0>;
270 ti,otap-del-sel-mmc-hs = <0x0>;
271 ti,otap-del-sel-sd-hs = <0x0>;
272 ti,otap-del-sel-sdr12 = <0x0>;
273 ti,otap-del-sel-sdr25 = <0x0>;
274 ti,otap-del-sel-sdr50 = <0x8>;
275 ti,otap-del-sel-sdr104 = <0x7>;
276 ti,otap-del-sel-ddr50 = <0x4>;
277 ti,otap-del-sel-ddr52 = <0x4>;
278 ti,otap-del-sel-hs200 = <0x7>;
279 ti,clkbuf-sel = <0x7>;
280 ti,otap-del-sel = <0x2>;
286 scm_conf: scm_conf@100000 {
287 compatible = "syscon", "simple-mfd";
288 reg = <0 0x00100000 0 0x1c000>;
289 #address-cells = <1>;
291 ranges = <0x0 0x0 0x00100000 0x1c000>;
293 pcie0_mode: pcie-mode@4060 {
294 compatible = "syscon";
295 reg = <0x00004060 0x4>;
298 pcie1_mode: pcie-mode@4070 {
299 compatible = "syscon";
300 reg = <0x00004070 0x4>;
303 pcie_devid: pcie-devid@210 {
304 compatible = "syscon";
305 reg = <0x00000210 0x4>;
308 serdes0_clk: serdes_clk@4080 {
309 compatible = "syscon";
310 reg = <0x00004080 0x4>;
313 serdes1_clk: serdes_clk@4090 {
314 compatible = "syscon";
315 reg = <0x00004090 0x4>;
318 serdes_mux: mux-controller {
319 compatible = "mmio-mux";
320 #mux-control-cells = <1>;
321 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
322 <0x4090 0x3>; /* SERDES1 lane select */
325 dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
326 compatible = "syscon";
327 reg = <0x0000041E0 0x14>;
330 ehrpwm_tbclk: syscon@4140 {
331 compatible = "ti,am654-ehrpwm-tbclk", "syscon";
337 dwc3_0: dwc3@4000000 {
338 compatible = "ti,am654-dwc3";
339 reg = <0x0 0x4000000 0x0 0x4000>;
340 #address-cells = <1>;
342 ranges = <0x0 0x0 0x4000000 0x20000>;
343 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
345 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
346 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
347 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
348 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
349 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
352 compatible = "snps,dwc3";
353 reg = <0x10000 0x10000>;
354 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-names = "peripheral",
360 maximum-speed = "high-speed";
363 phy-names = "usb2-phy";
364 snps,dis_u3_susphy_quirk;
368 usb0_phy: phy@4100000 {
369 compatible = "ti,am654-usb2", "ti,omap-usb2";
370 reg = <0x0 0x4100000 0x0 0x54>;
371 syscon-phy-power = <&scm_conf 0x4000>;
372 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
373 clock-names = "wkupclk", "refclk";
377 dwc3_1: dwc3@4020000 {
378 compatible = "ti,am654-dwc3";
379 reg = <0x0 0x4020000 0x0 0x4000>;
380 #address-cells = <1>;
382 ranges = <0x0 0x0 0x4020000 0x20000>;
383 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
385 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
386 clocks = <&k3_clks 152 2>;
387 assigned-clocks = <&k3_clks 152 2>;
388 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
391 compatible = "snps,dwc3";
392 reg = <0x10000 0x10000>;
393 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "peripheral",
399 maximum-speed = "high-speed";
402 phy-names = "usb2-phy";
406 usb1_phy: phy@4110000 {
407 compatible = "ti,am654-usb2", "ti,omap-usb2";
408 reg = <0x0 0x4110000 0x0 0x54>;
409 syscon-phy-power = <&scm_conf 0x4020>;
410 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
411 clock-names = "wkupclk", "refclk";
415 intr_main_gpio: interrupt-controller0 {
416 compatible = "ti,sci-intr";
417 ti,intr-trigger-type = <1>;
418 interrupt-controller;
419 interrupt-parent = <&gic500>;
420 #interrupt-cells = <2>;
422 ti,sci-dst-id = <56>;
423 ti,sci-rm-range-girq = <0x1>;
427 compatible = "simple-mfd";
428 #address-cells = <2>;
434 ti,sci-dev-id = <118>;
436 intr_main_navss: interrupt-controller1 {
437 compatible = "ti,sci-intr";
438 ti,intr-trigger-type = <4>;
439 interrupt-controller;
440 interrupt-parent = <&gic500>;
441 #interrupt-cells = <2>;
443 ti,sci-dst-id = <56>;
444 ti,sci-rm-range-girq = <0x0>, <0x2>;
447 inta_main_udmass: interrupt-controller@33d00000 {
448 compatible = "ti,sci-inta";
449 reg = <0x0 0x33d00000 0x0 0x100000>;
450 interrupt-controller;
451 interrupt-parent = <&intr_main_navss>;
454 ti,sci-dev-id = <179>;
455 ti,sci-rm-range-vint = <0x0>;
456 ti,sci-rm-range-global-event = <0x1>;
459 secure_proxy_main: mailbox@32c00000 {
460 compatible = "ti,am654-secure-proxy";
462 reg-names = "target_data", "rt", "scfg";
463 reg = <0x00 0x32c00000 0x00 0x100000>,
464 <0x00 0x32400000 0x00 0x100000>,
465 <0x00 0x32800000 0x00 0x100000>;
466 interrupt-names = "rx_011";
467 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
470 hwspinlock: spinlock@30e00000 {
471 compatible = "ti,am654-hwspinlock";
472 reg = <0x00 0x30e00000 0x00 0x1000>;
476 mailbox0_cluster0: mailbox@31f80000 {
477 compatible = "ti,am654-mailbox";
478 reg = <0x00 0x31f80000 0x00 0x200>;
480 ti,mbox-num-users = <4>;
481 ti,mbox-num-fifos = <16>;
482 interrupt-parent = <&intr_main_navss>;
485 mailbox0_cluster1: mailbox@31f81000 {
486 compatible = "ti,am654-mailbox";
487 reg = <0x00 0x31f81000 0x00 0x200>;
489 ti,mbox-num-users = <4>;
490 ti,mbox-num-fifos = <16>;
491 interrupt-parent = <&intr_main_navss>;
494 mailbox0_cluster2: mailbox@31f82000 {
495 compatible = "ti,am654-mailbox";
496 reg = <0x00 0x31f82000 0x00 0x200>;
498 ti,mbox-num-users = <4>;
499 ti,mbox-num-fifos = <16>;
500 interrupt-parent = <&intr_main_navss>;
503 mailbox0_cluster3: mailbox@31f83000 {
504 compatible = "ti,am654-mailbox";
505 reg = <0x00 0x31f83000 0x00 0x200>;
507 ti,mbox-num-users = <4>;
508 ti,mbox-num-fifos = <16>;
509 interrupt-parent = <&intr_main_navss>;
512 mailbox0_cluster4: mailbox@31f84000 {
513 compatible = "ti,am654-mailbox";
514 reg = <0x00 0x31f84000 0x00 0x200>;
516 ti,mbox-num-users = <4>;
517 ti,mbox-num-fifos = <16>;
518 interrupt-parent = <&intr_main_navss>;
521 mailbox0_cluster5: mailbox@31f85000 {
522 compatible = "ti,am654-mailbox";
523 reg = <0x00 0x31f85000 0x00 0x200>;
525 ti,mbox-num-users = <4>;
526 ti,mbox-num-fifos = <16>;
527 interrupt-parent = <&intr_main_navss>;
530 mailbox0_cluster6: mailbox@31f86000 {
531 compatible = "ti,am654-mailbox";
532 reg = <0x00 0x31f86000 0x00 0x200>;
534 ti,mbox-num-users = <4>;
535 ti,mbox-num-fifos = <16>;
536 interrupt-parent = <&intr_main_navss>;
539 mailbox0_cluster7: mailbox@31f87000 {
540 compatible = "ti,am654-mailbox";
541 reg = <0x00 0x31f87000 0x00 0x200>;
543 ti,mbox-num-users = <4>;
544 ti,mbox-num-fifos = <16>;
545 interrupt-parent = <&intr_main_navss>;
548 mailbox0_cluster8: mailbox@31f88000 {
549 compatible = "ti,am654-mailbox";
550 reg = <0x00 0x31f88000 0x00 0x200>;
552 ti,mbox-num-users = <4>;
553 ti,mbox-num-fifos = <16>;
554 interrupt-parent = <&intr_main_navss>;
557 mailbox0_cluster9: mailbox@31f89000 {
558 compatible = "ti,am654-mailbox";
559 reg = <0x00 0x31f89000 0x00 0x200>;
561 ti,mbox-num-users = <4>;
562 ti,mbox-num-fifos = <16>;
563 interrupt-parent = <&intr_main_navss>;
566 mailbox0_cluster10: mailbox@31f8a000 {
567 compatible = "ti,am654-mailbox";
568 reg = <0x00 0x31f8a000 0x00 0x200>;
570 ti,mbox-num-users = <4>;
571 ti,mbox-num-fifos = <16>;
572 interrupt-parent = <&intr_main_navss>;
575 mailbox0_cluster11: mailbox@31f8b000 {
576 compatible = "ti,am654-mailbox";
577 reg = <0x00 0x31f8b000 0x00 0x200>;
579 ti,mbox-num-users = <4>;
580 ti,mbox-num-fifos = <16>;
581 interrupt-parent = <&intr_main_navss>;
584 ringacc: ringacc@3c000000 {
585 compatible = "ti,am654-navss-ringacc";
586 reg = <0x0 0x3c000000 0x0 0x400000>,
587 <0x0 0x38000000 0x0 0x400000>,
588 <0x0 0x31120000 0x0 0x100>,
589 <0x0 0x33000000 0x0 0x40000>;
590 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
591 ti,num-rings = <818>;
592 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
593 ti,dma-ring-reset-quirk;
595 ti,sci-dev-id = <187>;
596 msi-parent = <&inta_main_udmass>;
599 main_udmap: dma-controller@31150000 {
600 compatible = "ti,am654-navss-main-udmap";
601 reg = <0x0 0x31150000 0x0 0x100>,
602 <0x0 0x34000000 0x0 0x100000>,
603 <0x0 0x35000000 0x0 0x100000>;
604 reg-names = "gcfg", "rchanrt", "tchanrt";
605 msi-parent = <&inta_main_udmass>;
609 ti,sci-dev-id = <188>;
610 ti,ringacc = <&ringacc>;
612 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
614 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
616 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
620 compatible = "ti,am65-cpts";
621 reg = <0x0 0x310d0000 0x0 0x400>;
623 clocks = <&main_cpts_mux>;
624 clock-names = "cpts";
625 interrupts-extended = <&intr_main_navss 163 0>;
626 interrupt-names = "cpts";
627 ti,cpts-periodic-outputs = <6>;
628 ti,cpts-ext-ts-inputs = <8>;
630 main_cpts_mux: refclk-mux {
632 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
633 <&k3_clks 118 6>, <&k3_clks 118 3>,
634 <&k3_clks 118 8>, <&k3_clks 118 14>,
635 <&k3_clks 120 3>, <&k3_clks 121 3>;
636 assigned-clocks = <&main_cpts_mux>;
637 assigned-clock-parents = <&k3_clks 118 5>;
642 main_gpio0: main_gpio0@600000 {
643 compatible = "ti,am654-gpio", "ti,keystone-gpio";
644 reg = <0x0 0x600000 0x0 0x100>;
647 interrupt-parent = <&intr_main_gpio>;
648 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
650 interrupt-controller;
651 #interrupt-cells = <2>;
653 ti,davinci-gpio-unbanked = <0>;
654 clocks = <&k3_clks 57 0>;
655 clock-names = "gpio";
658 main_gpio1: main_gpio1@601000 {
659 compatible = "ti,am654-gpio", "ti,keystone-gpio";
660 reg = <0x0 0x601000 0x0 0x100>;
663 interrupt-parent = <&intr_main_gpio>;
664 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
666 interrupt-controller;
667 #interrupt-cells = <2>;
669 ti,davinci-gpio-unbanked = <0>;
670 clocks = <&k3_clks 58 0>;
671 clock-names = "gpio";
674 pcie0_rc: pcie@5500000 {
675 compatible = "ti,am654-pcie-rc";
676 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
677 reg-names = "app", "dbics", "config", "atu";
678 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
679 #address-cells = <3>;
681 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
682 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
683 ti,syscon-pcie-id = <&pcie_devid>;
684 ti,syscon-pcie-mode = <&pcie0_mode>;
685 bus-range = <0x0 0xff>;
687 max-link-speed = <3>;
689 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
690 msi-map = <0x0 &gic_its 0x0 0x10000>;
693 pcie0_ep: pcie-ep@5500000 {
694 compatible = "ti,am654-pcie-ep";
695 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
696 reg-names = "app", "dbics", "addr_space", "atu";
697 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
698 ti,syscon-pcie-mode = <&pcie0_mode>;
699 num-ib-windows = <16>;
700 num-ob-windows = <16>;
701 max-link-speed = <3>;
703 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
706 pcie1_rc: pcie@5600000 {
707 compatible = "ti,am654-pcie-rc";
708 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
709 reg-names = "app", "dbics", "config", "atu";
710 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
711 #address-cells = <3>;
713 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
714 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
715 ti,syscon-pcie-id = <&pcie_devid>;
716 ti,syscon-pcie-mode = <&pcie1_mode>;
717 bus-range = <0x0 0xff>;
719 max-link-speed = <3>;
721 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
722 msi-map = <0x0 &gic_its 0x10000 0x10000>;
725 pcie1_ep: pcie-ep@5600000 {
726 compatible = "ti,am654-pcie-ep";
727 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
728 reg-names = "app", "dbics", "addr_space", "atu";
729 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
730 ti,syscon-pcie-mode = <&pcie1_mode>;
731 num-ib-windows = <16>;
732 num-ob-windows = <16>;
733 max-link-speed = <3>;
735 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
738 mcasp0: mcasp@2b00000 {
739 compatible = "ti,am33xx-mcasp-audio";
740 reg = <0x0 0x02b00000 0x0 0x2000>,
741 <0x0 0x02b08000 0x0 0x1000>;
742 reg-names = "mpu","dat";
743 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "tx", "rx";
747 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
748 dma-names = "tx", "rx";
750 clocks = <&k3_clks 104 0>;
752 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
757 mcasp1: mcasp@2b10000 {
758 compatible = "ti,am33xx-mcasp-audio";
759 reg = <0x0 0x02b10000 0x0 0x2000>,
760 <0x0 0x02b18000 0x0 0x1000>;
761 reg-names = "mpu","dat";
762 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
764 interrupt-names = "tx", "rx";
766 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
767 dma-names = "tx", "rx";
769 clocks = <&k3_clks 105 0>;
771 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
776 mcasp2: mcasp@2b20000 {
777 compatible = "ti,am33xx-mcasp-audio";
778 reg = <0x0 0x02b20000 0x0 0x2000>,
779 <0x0 0x02b28000 0x0 0x1000>;
780 reg-names = "mpu","dat";
781 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
783 interrupt-names = "tx", "rx";
785 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
786 dma-names = "tx", "rx";
788 clocks = <&k3_clks 106 0>;
790 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
796 compatible = "ti,am654-cal";
797 reg = <0x0 0x06f03000 0x0 0x400>,
798 <0x0 0x06f03800 0x0 0x40>;
799 reg-names = "cal_top",
801 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
802 ti,camerrx-control = <&scm_conf 0x40c0>;
804 clocks = <&k3_clks 2 0>;
805 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
808 #address-cells = <1>;
818 compatible = "ti,am65x-dss";
819 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
820 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
821 <0x0 0x04a06000 0x0 0x1000>, /* vid */
822 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
823 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
824 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
825 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
826 reg-names = "common", "vidl1", "vid",
827 "ovr1", "ovr2", "vp1", "vp2";
829 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
831 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
833 clocks = <&k3_clks 67 1>,
836 clock-names = "fck", "vp1", "vp2";
839 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
840 * DIV1. See "Figure 12-3365. DSS Integration"
841 * in AM65x TRM for details.
843 assigned-clocks = <&k3_clks 67 2>;
844 assigned-clock-parents = <&k3_clks 67 5>;
846 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
851 #address-cells = <1>;
856 ehrpwm0: pwm@3000000 {
857 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
859 reg = <0x0 0x3000000 0x0 0x100>;
860 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
861 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
862 clock-names = "tbclk", "fck";
865 ehrpwm1: pwm@3010000 {
866 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
868 reg = <0x0 0x3010000 0x0 0x100>;
869 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
870 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
871 clock-names = "tbclk", "fck";
874 ehrpwm2: pwm@3020000 {
875 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
877 reg = <0x0 0x3020000 0x0 0x100>;
878 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
879 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
880 clock-names = "tbclk", "fck";
883 ehrpwm3: pwm@3030000 {
884 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
886 reg = <0x0 0x3030000 0x0 0x100>;
887 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
888 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
889 clock-names = "tbclk", "fck";
892 ehrpwm4: pwm@3040000 {
893 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
895 reg = <0x0 0x3040000 0x0 0x100>;
896 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
897 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
898 clock-names = "tbclk", "fck";
901 ehrpwm5: pwm@3050000 {
902 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
904 reg = <0x0 0x3050000 0x0 0x100>;
905 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
906 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
907 clock-names = "tbclk", "fck";