arch/arm64/boot/dts/ti/k3-am65-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy-am654-serdes.h>
   8
   9 &cbass_main {
  10         msmc_ram: sram@70000000 {
  11                 compatible = "mmio-sram";
  12                 reg = <0x0 0x70000000 0x0 0x200000>;
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x0 0x0 0x70000000 0x200000>;
  16
  17                 atf-sram@0 {
  18                         reg = <0x0 0x20000>;
  19                 };
  20
  21                 sysfw-sram@f0000 {
  22                         reg = <0xf0000 0x10000>;
  23                 };
  24
  25                 l3cache-sram@100000 {
  26                         reg = <0x100000 0x100000>;
  27                 };
  28         };
  29
  30         gic500: interrupt-controller@1800000 {
  31                 compatible = "arm,gic-v3";
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  38                       <0x00 0x01880000 0x00 0x90000>;   /* GICR */
  39                 /*
  40                  * vcpumntirq:
  41                  * virtual CPU interface maintenance interrupt
  42                  */
  43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  44
  45                 gic_its: msi-controller@1820000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x00 0x01820000 0x00 0x10000>;
  48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };
  52         };
  53
  54         serdes0: serdes@900000 {
  55                 compatible = "ti,phy-am654-serdes";
  56                 reg = <0x0 0x900000 0x0 0x2000>;
  57                 reg-names = "serdes";
  58                 #phy-cells = <2>;
  59                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
  60                 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
  61                 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
  62                 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
  63                 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
  64                 ti,serdes-clk = <&serdes0_clk>;
  65                 #clock-cells = <1>;
  66                 mux-controls = <&serdes_mux 0>;
  67         };
  68
  69         serdes1: serdes@910000 {
  70                 compatible = "ti,phy-am654-serdes";
  71                 reg = <0x0 0x910000 0x0 0x2000>;
  72                 reg-names = "serdes";
  73                 #phy-cells = <2>;
  74                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  75                 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
  76                 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
  77                 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
  78                 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
  79                 ti,serdes-clk = <&serdes1_clk>;
  80                 #clock-cells = <1>;
  81                 mux-controls = <&serdes_mux 1>;
  82         };
  83
  84         main_uart0: serial@2800000 {
  85                 compatible = "ti,am654-uart";
  86                 reg = <0x00 0x02800000 0x00 0x100>;
  87                 reg-shift = <2>;
  88                 reg-io-width = <4>;
  89                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  90                 clock-frequency = <48000000>;
  91                 current-speed = <115200>;
  92                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  93         };
  94
  95         main_uart1: serial@2810000 {
  96                 compatible = "ti,am654-uart";
  97                 reg = <0x00 0x02810000 0x00 0x100>;
  98                 reg-shift = <2>;
  99                 reg-io-width = <4>;
 100                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 101                 clock-frequency = <48000000>;
 102                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
 103         };
 104
 105         main_uart2: serial@2820000 {
 106                 compatible = "ti,am654-uart";
 107                 reg = <0x00 0x02820000 0x00 0x100>;
 108                 reg-shift = <2>;
 109                 reg-io-width = <4>;
 110                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 111                 clock-frequency = <48000000>;
 112                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 113         };
 114
 115         main_pmx0: pinmux@11c000 {
 116                 compatible = "pinctrl-single";
 117                 reg = <0x0 0x11c000 0x0 0x2e4>;
 118                 #pinctrl-cells = <1>;
 119                 pinctrl-single,register-width = <32>;
 120                 pinctrl-single,function-mask = <0xffffffff>;
 121         };
 122
 123         main_pmx1: pinmux@11c2e8 {
 124                 compatible = "pinctrl-single";
 125                 reg = <0x0 0x11c2e8 0x0 0x24>;
 126                 #pinctrl-cells = <1>;
 127                 pinctrl-single,register-width = <32>;
 128                 pinctrl-single,function-mask = <0xffffffff>;
 129         };
 130
 131         main_i2c0: i2c@2000000 {
 132                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 133                 reg = <0x0 0x2000000 0x0 0x100>;
 134                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 clock-names = "fck";
 138                 clocks = <&k3_clks 110 1>;
 139                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 140         };
 141
 142         main_i2c1: i2c@2010000 {
 143                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 144                 reg = <0x0 0x2010000 0x0 0x100>;
 145                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 clock-names = "fck";
 149                 clocks = <&k3_clks 111 1>;
 150                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 151         };
 152
 153         main_i2c2: i2c@2020000 {
 154                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 155                 reg = <0x0 0x2020000 0x0 0x100>;
 156                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 clock-names = "fck";
 160                 clocks = <&k3_clks 112 1>;
 161                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 162         };
 163
 164         main_i2c3: i2c@2030000 {
 165                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 166                 reg = <0x0 0x2030000 0x0 0x100>;
 167                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 clock-names = "fck";
 171                 clocks = <&k3_clks 113 1>;
 172                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 173         };
 174
 175         ecap0: pwm@3100000 {
 176                 compatible = "ti,am654-ecap", "ti,am3352-ecap";
 177                 #pwm-cells = <3>;
 178                 reg = <0x0 0x03100000 0x0 0x60>;
 179                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 180                 clocks = <&k3_clks 39 0>;
 181                 clock-names = "fck";
 182         };
 183
 184         main_spi0: spi@2100000 {
 185                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 186                 reg = <0x0 0x2100000 0x0 0x400>;
 187                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&k3_clks 137 1>;
 189                 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
 193                 dma-names = "tx0", "rx0";
 194         };
 195
 196         main_spi1: spi@2110000 {
 197                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 198                 reg = <0x0 0x2110000 0x0 0x400>;
 199                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&k3_clks 138 1>;
 201                 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 assigned-clocks = <&k3_clks 137 1>;
 205                 assigned-clock-rates = <48000000>;
 206         };
 207
 208         main_spi2: spi@2120000 {
 209                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 210                 reg = <0x0 0x2120000 0x0 0x400>;
 211                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&k3_clks 139 1>;
 213                 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216         };
 217
 218         main_spi3: spi@2130000 {
 219                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 220                 reg = <0x0 0x2130000 0x0 0x400>;
 221                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&k3_clks 140 1>;
 223                 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226         };
 227
 228         main_spi4: spi@2140000 {
 229                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 230                 reg = <0x0 0x2140000 0x0 0x400>;
 231                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&k3_clks 141 1>;
 233                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236         };
 237
 238         sdhci0: sdhci@4f80000 {
 239                 compatible = "ti,am654-sdhci-5.1";
 240                 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 241                 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
 242                 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 243                 clock-names = "clk_ahb", "clk_xin";
 244                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 245                 mmc-ddr-1_8v;
 246                 mmc-hs200-1_8v;
 247                 ti,otap-del-sel-legacy = <0x0>;
 248                 ti,otap-del-sel-mmc-hs = <0x0>;
 249                 ti,otap-del-sel-sd-hs = <0x0>;
 250                 ti,otap-del-sel-sdr12 = <0x0>;
 251                 ti,otap-del-sel-sdr25 = <0x0>;
 252                 ti,otap-del-sel-sdr50 = <0x8>;
 253                 ti,otap-del-sel-sdr104 = <0x7>;
 254                 ti,otap-del-sel-ddr50 = <0x5>;
 255                 ti,otap-del-sel-ddr52 = <0x5>;
 256                 ti,otap-del-sel-hs200 = <0x5>;
 257                 ti,otap-del-sel-hs400 = <0x0>;
 258                 ti,trm-icp = <0x8>;
 259                 dma-coherent;
 260         };
 261
 262         sdhci1: sdhci@4fa0000 {
 263                 compatible = "ti,am654-sdhci-5.1";
 264                 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
 265                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
 266                 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
 267                 clock-names = "clk_ahb", "clk_xin";
 268                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 269                 ti,otap-del-sel-legacy = <0x0>;
 270                 ti,otap-del-sel-mmc-hs = <0x0>;
 271                 ti,otap-del-sel-sd-hs = <0x0>;
 272                 ti,otap-del-sel-sdr12 = <0x0>;
 273                 ti,otap-del-sel-sdr25 = <0x0>;
 274                 ti,otap-del-sel-sdr50 = <0x8>;
 275                 ti,otap-del-sel-sdr104 = <0x7>;
 276                 ti,otap-del-sel-ddr50 = <0x4>;
 277                 ti,otap-del-sel-ddr52 = <0x4>;
 278                 ti,otap-del-sel-hs200 = <0x7>;
 279                 ti,clkbuf-sel = <0x7>;
 280                 ti,otap-del-sel = <0x2>;
 281                 ti,trm-icp = <0x8>;
 282                 dma-coherent;
 283                 no-1-8-v;
 284         };
 285
 286         scm_conf: scm_conf@100000 {
 287                 compatible = "syscon", "simple-mfd";
 288                 reg = <0 0x00100000 0 0x1c000>;
 289                 #address-cells = <1>;
 290                 #size-cells = <1>;
 291                 ranges = <0x0 0x0 0x00100000 0x1c000>;
 292
 293                 pcie0_mode: pcie-mode@4060 {
 294                         compatible = "syscon";
 295                         reg = <0x00004060 0x4>;
 296                 };
 297
 298                 pcie1_mode: pcie-mode@4070 {
 299                         compatible = "syscon";
 300                         reg = <0x00004070 0x4>;
 301                 };
 302
 303                 pcie_devid: pcie-devid@210 {
 304                         compatible = "syscon";
 305                         reg = <0x00000210 0x4>;
 306                 };
 307
 308                 serdes0_clk: serdes_clk@4080 {
 309                         compatible = "syscon";
 310                         reg = <0x00004080 0x4>;
 311                 };
 312
 313                 serdes1_clk: serdes_clk@4090 {
 314                         compatible = "syscon";
 315                         reg = <0x00004090 0x4>;
 316                 };
 317
 318                 serdes_mux: mux-controller {
 319                         compatible = "mmio-mux";
 320                         #mux-control-cells = <1>;
 321                         mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
 322                                         <0x4090 0x3>; /* SERDES1 lane select */
 323                 };
 324
 325                 dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
 326                         compatible = "syscon";
 327                         reg = <0x0000041E0 0x14>;
 328                 };
 329
 330                 ehrpwm_tbclk: syscon@4140 {
 331                         compatible = "ti,am654-ehrpwm-tbclk", "syscon";
 332                         reg = <0x4140 0x18>;
 333                         #clock-cells = <1>;
 334                 };
 335         };
 336
 337         dwc3_0: dwc3@4000000 {
 338                 compatible = "ti,am654-dwc3";
 339                 reg = <0x0 0x4000000 0x0 0x4000>;
 340                 #address-cells = <1>;
 341                 #size-cells = <1>;
 342                 ranges = <0x0 0x0 0x4000000 0x20000>;
 343                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 344                 dma-coherent;
 345                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
 346                 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 347                 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 348                 assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 349                                          <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
 350
 351                 usb0: usb@10000 {
 352                         compatible = "snps,dwc3";
 353                         reg = <0x10000 0x10000>;
 354                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 356                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 357                         interrupt-names = "peripheral",
 358                                           "host",
 359                                           "otg";
 360                         maximum-speed = "high-speed";
 361                         dr_mode = "otg";
 362                         phys = <&usb0_phy>;
 363                         phy-names = "usb2-phy";
 364                         snps,dis_u3_susphy_quirk;
 365                 };
 366         };
 367
 368         usb0_phy: phy@4100000 {
 369                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 370                 reg = <0x0 0x4100000 0x0 0x54>;
 371                 syscon-phy-power = <&scm_conf 0x4000>;
 372                 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
 373                 clock-names = "wkupclk", "refclk";
 374                 #phy-cells = <0>;
 375         };
 376
 377         dwc3_1: dwc3@4020000 {
 378                 compatible = "ti,am654-dwc3";
 379                 reg = <0x0 0x4020000 0x0 0x4000>;
 380                 #address-cells = <1>;
 381                 #size-cells = <1>;
 382                 ranges = <0x0 0x0 0x4020000 0x20000>;
 383                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 384                 dma-coherent;
 385                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 386                 clocks = <&k3_clks 152 2>;
 387                 assigned-clocks = <&k3_clks 152 2>;
 388                 assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 389
 390                 usb1: usb@10000 {
 391                         compatible = "snps,dwc3";
 392                         reg = <0x10000 0x10000>;
 393                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 394                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 395                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 396                         interrupt-names = "peripheral",
 397                                           "host",
 398                                           "otg";
 399                         maximum-speed = "high-speed";
 400                         dr_mode = "otg";
 401                         phys = <&usb1_phy>;
 402                         phy-names = "usb2-phy";
 403                 };
 404         };
 405
 406         usb1_phy: phy@4110000 {
 407                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 408                 reg = <0x0 0x4110000 0x0 0x54>;
 409                 syscon-phy-power = <&scm_conf 0x4020>;
 410                 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
 411                 clock-names = "wkupclk", "refclk";
 412                 #phy-cells = <0>;
 413         };
 414
 415         intr_main_gpio: interrupt-controller0 {
 416                 compatible = "ti,sci-intr";
 417                 ti,intr-trigger-type = <1>;
 418                 interrupt-controller;
 419                 interrupt-parent = <&gic500>;
 420                 #interrupt-cells = <1>;
 421                 ti,sci = <&dmsc>;
 422                 ti,sci-dev-id = <100>;
 423                 ti,interrupt-ranges = <0 392 32>;
 424         };
 425
 426         main_navss {
 427                 compatible = "simple-mfd";
 428                 #address-cells = <2>;
 429                 #size-cells = <2>;
 430                 ranges;
 431                 dma-coherent;
 432                 dma-ranges;
 433
 434                 ti,sci-dev-id = <118>;
 435
 436                 intr_main_navss: interrupt-controller1 {
 437                         compatible = "ti,sci-intr";
 438                         ti,intr-trigger-type = <4>;
 439                         interrupt-controller;
 440                         interrupt-parent = <&gic500>;
 441                         #interrupt-cells = <1>;
 442                         ti,sci = <&dmsc>;
 443                         ti,sci-dev-id = <182>;
 444                         ti,interrupt-ranges = <0 64 64>,
 445                                               <64 448 64>;
 446                 };
 447
 448                 inta_main_udmass: interrupt-controller@33d00000 {
 449                         compatible = "ti,sci-inta";
 450                         reg = <0x0 0x33d00000 0x0 0x100000>;
 451                         interrupt-controller;
 452                         interrupt-parent = <&intr_main_navss>;
 453                         msi-controller;
 454                         ti,sci = <&dmsc>;
 455                         ti,sci-dev-id = <179>;
 456                         ti,interrupt-ranges = <0 0 256>;
 457                 };
 458
 459                 secure_proxy_main: mailbox@32c00000 {
 460                         compatible = "ti,am654-secure-proxy";
 461                         #mbox-cells = <1>;
 462                         reg-names = "target_data", "rt", "scfg";
 463                         reg = <0x00 0x32c00000 0x00 0x100000>,
 464                               <0x00 0x32400000 0x00 0x100000>,
 465                               <0x00 0x32800000 0x00 0x100000>;
 466                         interrupt-names = "rx_011";
 467                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 468                 };
 469
 470                 hwspinlock: spinlock@30e00000 {
 471                         compatible = "ti,am654-hwspinlock";
 472                         reg = <0x00 0x30e00000 0x00 0x1000>;
 473                         #hwlock-cells = <1>;
 474                 };
 475
 476                 mailbox0_cluster0: mailbox@31f80000 {
 477                         compatible = "ti,am654-mailbox";
 478                         reg = <0x00 0x31f80000 0x00 0x200>;
 479                         #mbox-cells = <1>;
 480                         ti,mbox-num-users = <4>;
 481                         ti,mbox-num-fifos = <16>;
 482                         interrupt-parent = <&intr_main_navss>;
 483                 };
 484
 485                 mailbox0_cluster1: mailbox@31f81000 {
 486                         compatible = "ti,am654-mailbox";
 487                         reg = <0x00 0x31f81000 0x00 0x200>;
 488                         #mbox-cells = <1>;
 489                         ti,mbox-num-users = <4>;
 490                         ti,mbox-num-fifos = <16>;
 491                         interrupt-parent = <&intr_main_navss>;
 492                 };
 493
 494                 mailbox0_cluster2: mailbox@31f82000 {
 495                         compatible = "ti,am654-mailbox";
 496                         reg = <0x00 0x31f82000 0x00 0x200>;
 497                         #mbox-cells = <1>;
 498                         ti,mbox-num-users = <4>;
 499                         ti,mbox-num-fifos = <16>;
 500                         interrupt-parent = <&intr_main_navss>;
 501                 };
 502
 503                 mailbox0_cluster3: mailbox@31f83000 {
 504                         compatible = "ti,am654-mailbox";
 505                         reg = <0x00 0x31f83000 0x00 0x200>;
 506                         #mbox-cells = <1>;
 507                         ti,mbox-num-users = <4>;
 508                         ti,mbox-num-fifos = <16>;
 509                         interrupt-parent = <&intr_main_navss>;
 510                 };
 511
 512                 mailbox0_cluster4: mailbox@31f84000 {
 513                         compatible = "ti,am654-mailbox";
 514                         reg = <0x00 0x31f84000 0x00 0x200>;
 515                         #mbox-cells = <1>;
 516                         ti,mbox-num-users = <4>;
 517                         ti,mbox-num-fifos = <16>;
 518                         interrupt-parent = <&intr_main_navss>;
 519                 };
 520
 521                 mailbox0_cluster5: mailbox@31f85000 {
 522                         compatible = "ti,am654-mailbox";
 523                         reg = <0x00 0x31f85000 0x00 0x200>;
 524                         #mbox-cells = <1>;
 525                         ti,mbox-num-users = <4>;
 526                         ti,mbox-num-fifos = <16>;
 527                         interrupt-parent = <&intr_main_navss>;
 528                 };
 529
 530                 mailbox0_cluster6: mailbox@31f86000 {
 531                         compatible = "ti,am654-mailbox";
 532                         reg = <0x00 0x31f86000 0x00 0x200>;
 533                         #mbox-cells = <1>;
 534                         ti,mbox-num-users = <4>;
 535                         ti,mbox-num-fifos = <16>;
 536                         interrupt-parent = <&intr_main_navss>;
 537                 };
 538
 539                 mailbox0_cluster7: mailbox@31f87000 {
 540                         compatible = "ti,am654-mailbox";
 541                         reg = <0x00 0x31f87000 0x00 0x200>;
 542                         #mbox-cells = <1>;
 543                         ti,mbox-num-users = <4>;
 544                         ti,mbox-num-fifos = <16>;
 545                         interrupt-parent = <&intr_main_navss>;
 546                 };
 547
 548                 mailbox0_cluster8: mailbox@31f88000 {
 549                         compatible = "ti,am654-mailbox";
 550                         reg = <0x00 0x31f88000 0x00 0x200>;
 551                         #mbox-cells = <1>;
 552                         ti,mbox-num-users = <4>;
 553                         ti,mbox-num-fifos = <16>;
 554                         interrupt-parent = <&intr_main_navss>;
 555                 };
 556
 557                 mailbox0_cluster9: mailbox@31f89000 {
 558                         compatible = "ti,am654-mailbox";
 559                         reg = <0x00 0x31f89000 0x00 0x200>;
 560                         #mbox-cells = <1>;
 561                         ti,mbox-num-users = <4>;
 562                         ti,mbox-num-fifos = <16>;
 563                         interrupt-parent = <&intr_main_navss>;
 564                 };
 565
 566                 mailbox0_cluster10: mailbox@31f8a000 {
 567                         compatible = "ti,am654-mailbox";
 568                         reg = <0x00 0x31f8a000 0x00 0x200>;
 569                         #mbox-cells = <1>;
 570                         ti,mbox-num-users = <4>;
 571                         ti,mbox-num-fifos = <16>;
 572                         interrupt-parent = <&intr_main_navss>;
 573                 };
 574
 575                 mailbox0_cluster11: mailbox@31f8b000 {
 576                         compatible = "ti,am654-mailbox";
 577                         reg = <0x00 0x31f8b000 0x00 0x200>;
 578                         #mbox-cells = <1>;
 579                         ti,mbox-num-users = <4>;
 580                         ti,mbox-num-fifos = <16>;
 581                         interrupt-parent = <&intr_main_navss>;
 582                 };
 583
 584                 ringacc: ringacc@3c000000 {
 585                         compatible = "ti,am654-navss-ringacc";
 586                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 587                                 <0x0 0x38000000 0x0 0x400000>,
 588                                 <0x0 0x31120000 0x0 0x100>,
 589                                 <0x0 0x33000000 0x0 0x40000>;
 590                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 591                         ti,num-rings = <818>;
 592                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 593                         ti,dma-ring-reset-quirk;
 594                         ti,sci = <&dmsc>;
 595                         ti,sci-dev-id = <187>;
 596                         msi-parent = <&inta_main_udmass>;
 597                 };
 598
 599                 main_udmap: dma-controller@31150000 {
 600                         compatible = "ti,am654-navss-main-udmap";
 601                         reg =   <0x0 0x31150000 0x0 0x100>,
 602                                 <0x0 0x34000000 0x0 0x100000>,
 603                                 <0x0 0x35000000 0x0 0x100000>;
 604                         reg-names = "gcfg", "rchanrt", "tchanrt";
 605                         msi-parent = <&inta_main_udmass>;
 606                         #dma-cells = <1>;
 607
 608                         ti,sci = <&dmsc>;
 609                         ti,sci-dev-id = <188>;
 610                         ti,ringacc = <&ringacc>;
 611
 612                         ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
 613                                                 <0xd>; /* TX_CHAN */
 614                         ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
 615                                                 <0xa>; /* RX_CHAN */
 616                         ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
 617                 };
 618
 619                 cpts@310d0000 {
 620                         compatible = "ti,am65-cpts";
 621                         reg = <0x0 0x310d0000 0x0 0x400>;
 622                         reg-names = "cpts";
 623                         clocks = <&main_cpts_mux>;
 624                         clock-names = "cpts";
 625                         interrupts-extended = <&intr_main_navss 391>;
 626                         interrupt-names = "cpts";
 627                         ti,cpts-periodic-outputs = <6>;
 628                         ti,cpts-ext-ts-inputs = <8>;
 629
 630                         main_cpts_mux: refclk-mux {
 631                                 #clock-cells = <0>;
 632                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 633                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 634                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 635                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 636                                 assigned-clocks = <&main_cpts_mux>;
 637                                 assigned-clock-parents = <&k3_clks 118 5>;
 638                         };
 639                 };
 640         };
 641
 642         main_gpio0:  main_gpio0@600000 {
 643                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 644                 reg = <0x0 0x600000 0x0 0x100>;
 645                 gpio-controller;
 646                 #gpio-cells = <2>;
 647                 interrupt-parent = <&intr_main_gpio>;
 648                 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
 649                 interrupt-controller;
 650                 #interrupt-cells = <2>;
 651                 ti,ngpio = <96>;
 652                 ti,davinci-gpio-unbanked = <0>;
 653                 clocks = <&k3_clks 57 0>;
 654                 clock-names = "gpio";
 655         };
 656
 657         main_gpio1:  main_gpio1@601000 {
 658                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 659                 reg = <0x0 0x601000 0x0 0x100>;
 660                 gpio-controller;
 661                 #gpio-cells = <2>;
 662                 interrupt-parent = <&intr_main_gpio>;
 663                 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
 664                 interrupt-controller;
 665                 #interrupt-cells = <2>;
 666                 ti,ngpio = <90>;
 667                 ti,davinci-gpio-unbanked = <0>;
 668                 clocks = <&k3_clks 58 0>;
 669                 clock-names = "gpio";
 670         };
 671
 672         pcie0_rc: pcie@5500000 {
 673                 compatible = "ti,am654-pcie-rc";
 674                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
 675                 reg-names = "app", "dbics", "config", "atu";
 676                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 677                 #address-cells = <3>;
 678                 #size-cells = <2>;
 679                 ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
 680                           0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
 681                 ti,syscon-pcie-id = <&pcie_devid>;
 682                 ti,syscon-pcie-mode = <&pcie0_mode>;
 683                 bus-range = <0x0 0xff>;
 684                 num-viewport = <16>;
 685                 max-link-speed = <3>;
 686                 dma-coherent;
 687                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 688                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 689         };
 690
 691         pcie0_ep: pcie-ep@5500000 {
 692                 compatible = "ti,am654-pcie-ep";
 693                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
 694                 reg-names = "app", "dbics", "addr_space", "atu";
 695                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 696                 ti,syscon-pcie-mode = <&pcie0_mode>;
 697                 num-ib-windows = <16>;
 698                 num-ob-windows = <16>;
 699                 max-link-speed = <3>;
 700                 dma-coherent;
 701                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 702         };
 703
 704         pcie1_rc: pcie@5600000 {
 705                 compatible = "ti,am654-pcie-rc";
 706                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
 707                 reg-names = "app", "dbics", "config", "atu";
 708                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 709                 #address-cells = <3>;
 710                 #size-cells = <2>;
 711                 ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
 712                           0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
 713                 ti,syscon-pcie-id = <&pcie_devid>;
 714                 ti,syscon-pcie-mode = <&pcie1_mode>;
 715                 bus-range = <0x0 0xff>;
 716                 num-viewport = <16>;
 717                 max-link-speed = <3>;
 718                 dma-coherent;
 719                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 720                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 721         };
 722
 723         pcie1_ep: pcie-ep@5600000 {
 724                 compatible = "ti,am654-pcie-ep";
 725                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
 726                 reg-names = "app", "dbics", "addr_space", "atu";
 727                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 728                 ti,syscon-pcie-mode = <&pcie1_mode>;
 729                 num-ib-windows = <16>;
 730                 num-ob-windows = <16>;
 731                 max-link-speed = <3>;
 732                 dma-coherent;
 733                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 734         };
 735
 736         mcasp0: mcasp@2b00000 {
 737                 compatible = "ti,am33xx-mcasp-audio";
 738                 reg = <0x0 0x02b00000 0x0 0x2000>,
 739                         <0x0 0x02b08000 0x0 0x1000>;
 740                 reg-names = "mpu","dat";
 741                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 742                                 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 743                 interrupt-names = "tx", "rx";
 744
 745                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
 746                 dma-names = "tx", "rx";
 747
 748                 clocks = <&k3_clks 104 0>;
 749                 clock-names = "fck";
 750                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 751
 752                 status = "disabled";
 753         };
 754
 755         mcasp1: mcasp@2b10000 {
 756                 compatible = "ti,am33xx-mcasp-audio";
 757                 reg = <0x0 0x02b10000 0x0 0x2000>,
 758                         <0x0 0x02b18000 0x0 0x1000>;
 759                 reg-names = "mpu","dat";
 760                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 761                                 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 762                 interrupt-names = "tx", "rx";
 763
 764                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
 765                 dma-names = "tx", "rx";
 766
 767                 clocks = <&k3_clks 105 0>;
 768                 clock-names = "fck";
 769                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 770
 771                 status = "disabled";
 772         };
 773
 774         mcasp2: mcasp@2b20000 {
 775                 compatible = "ti,am33xx-mcasp-audio";
 776                 reg = <0x0 0x02b20000 0x0 0x2000>,
 777                         <0x0 0x02b28000 0x0 0x1000>;
 778                 reg-names = "mpu","dat";
 779                 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 780                                 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 781                 interrupt-names = "tx", "rx";
 782
 783                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
 784                 dma-names = "tx", "rx";
 785
 786                 clocks = <&k3_clks 106 0>;
 787                 clock-names = "fck";
 788                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 789
 790                 status = "disabled";
 791         };
 792
 793         cal: cal@6f03000 {
 794                 compatible = "ti,am654-cal";
 795                 reg = <0x0 0x06f03000 0x0 0x400>,
 796                       <0x0 0x06f03800 0x0 0x40>;
 797                 reg-names = "cal_top",
 798                             "cal_rx_core0";
 799                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 800                 ti,camerrx-control = <&scm_conf 0x40c0>;
 801                 clock-names = "fck";
 802                 clocks = <&k3_clks 2 0>;
 803                 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
 804
 805                 ports {
 806                         #address-cells = <1>;
 807                         #size-cells = <0>;
 808
 809                         csi2_0: port@0 {
 810                                 reg = <0>;
 811                         };
 812                 };
 813         };
 814
 815         dss: dss@04a00000 {
 816                 compatible = "ti,am65x-dss";
 817                 reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
 818                         <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
 819                         <0x0 0x04a06000 0x0 0x1000>, /* vid */
 820                         <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
 821                         <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
 822                         <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
 823                         <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
 824                 reg-names = "common", "vidl1", "vid",
 825                         "ovr1", "ovr2", "vp1", "vp2";
 826
 827                 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
 828
 829                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 830
 831                 clocks =        <&k3_clks 67 1>,
 832                                 <&k3_clks 216 1>,
 833                                 <&k3_clks 67 2>;
 834                 clock-names = "fck", "vp1", "vp2";
 835
 836                 /*
 837                  * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
 838                  * DIV1. See "Figure 12-3365. DSS Integration"
 839                  * in AM65x TRM for details.
 840                  */
 841                 assigned-clocks = <&k3_clks 67 2>;
 842                 assigned-clock-parents = <&k3_clks 67 5>;
 843
 844                 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
 845
 846                 status = "disabled";
 847
 848                 dss_ports: ports {
 849                         #address-cells = <1>;
 850                         #size-cells = <0>;
 851                 };
 852         };
 853
 854         ehrpwm0: pwm@3000000 {
 855                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 856                 #pwm-cells = <3>;
 857                 reg = <0x0 0x3000000 0x0 0x100>;
 858                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 859                 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
 860                 clock-names = "tbclk", "fck";
 861         };
 862
 863         ehrpwm1: pwm@3010000 {
 864                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 865                 #pwm-cells = <3>;
 866                 reg = <0x0 0x3010000 0x0 0x100>;
 867                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 868                 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
 869                 clock-names = "tbclk", "fck";
 870         };
 871
 872         ehrpwm2: pwm@3020000 {
 873                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 874                 #pwm-cells = <3>;
 875                 reg = <0x0 0x3020000 0x0 0x100>;
 876                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 877                 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
 878                 clock-names = "tbclk", "fck";
 879         };
 880
 881         ehrpwm3: pwm@3030000 {
 882                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 883                 #pwm-cells = <3>;
 884                 reg = <0x0 0x3030000 0x0 0x100>;
 885                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 886                 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
 887                 clock-names = "tbclk", "fck";
 888         };
 889
 890         ehrpwm4: pwm@3040000 {
 891                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 892                 #pwm-cells = <3>;
 893                 reg = <0x0 0x3040000 0x0 0x100>;
 894                 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
 895                 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
 896                 clock-names = "tbclk", "fck";
 897         };
 898
 899         ehrpwm5: pwm@3050000 {
 900                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 901                 #pwm-cells = <3>;
 902                 reg = <0x0 0x3050000 0x0 0x100>;
 903                 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
 904                 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
 905                 clock-names = "tbclk", "fck";
 906         };
 907 };