arch/arm64/boot/dts/ti/k3-am642-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/leds/common.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/net/ti-dp83867.h>
  11 #include "k3-am642.dtsi"
  12
  13 / {
  14         compatible =  "ti,am642-evm", "ti,am642";
  15         model = "Texas Instruments AM642 EVM";
  16
  17         chosen {
  18                 stdout-path = "serial2:115200n8";
  19                 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
  20         };
  21
  22         memory@80000000 {
  23                 device_type = "memory";
  24                 /* 2G RAM */
  25                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
  26
  27         };
  28
  29         reserved-memory {
  30                 #address-cells = <2>;
  31                 #size-cells = <2>;
  32                 ranges;
  33
  34                 secure_ddr: optee@9e800000 {
  35                         reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
  36                         alignment = <0x1000>;
  37                         no-map;
  38                 };
  39         };
  40
  41         evm_12v0: fixedregulator-evm12v0 {
  42                 /* main DC jack */
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "evm_12v0";
  45                 regulator-min-microvolt = <12000000>;
  46                 regulator-max-microvolt = <12000000>;
  47                 regulator-always-on;
  48                 regulator-boot-on;
  49         };
  50
  51         vsys_5v0: fixedregulator-vsys5v0 {
  52                 /* output of LM5140 */
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "vsys_5v0";
  55                 regulator-min-microvolt = <5000000>;
  56                 regulator-max-microvolt = <5000000>;
  57                 vin-supply = <&evm_12v0>;
  58                 regulator-always-on;
  59                 regulator-boot-on;
  60         };
  61
  62         vsys_3v3: fixedregulator-vsys3v3 {
  63                 /* output of LM5140 */
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "vsys_3v3";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 vin-supply = <&evm_12v0>;
  69                 regulator-always-on;
  70                 regulator-boot-on;
  71         };
  72
  73         vdd_mmc1: fixed-regulator-sd {
  74                 /* TPS2051BD */
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "vdd_mmc1";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 regulator-boot-on;
  80                 enable-active-high;
  81                 vin-supply = <&vsys_3v3>;
  82                 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
  83         };
  84
  85         vddb: fixedregulator-vddb {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "vddb_3v3_display";
  88                 regulator-min-microvolt = <3300000>;
  89                 regulator-max-microvolt = <3300000>;
  90                 vin-supply = <&vsys_3v3>;
  91                 regulator-always-on;
  92                 regulator-boot-on;
  93         };
  94
  95         leds {
  96                 compatible = "gpio-leds";
  97
  98                 led-0 {
  99                         label = "am64-evm:red:heartbeat";
 100                         gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
 101                         linux,default-trigger = "heartbeat";
 102                         function = LED_FUNCTION_HEARTBEAT;
 103                         default-state = "off";
 104                 };
 105         };
 106
 107         mdio_mux: mux-controller {
 108                 compatible = "gpio-mux";
 109                 #mux-control-cells = <0>;
 110
 111                 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
 112         };
 113
 114         mdio-mux-1 {
 115                 compatible = "mdio-mux-multiplexer";
 116                 mux-controls = <&mdio_mux>;
 117                 mdio-parent-bus = <&cpsw3g_mdio>;
 118                 #address-cells = <1>;
 119                 #size-cells = <0>;
 120
 121                 mdio@1 {
 122                         reg = <0x1>;
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125
 126                         cpsw3g_phy3: ethernet-phy@3 {
 127                                 reg = <3>;
 128                         };
 129                 };
 130         };
 131 };
 132
 133 &main_pmx0 {
 134         main_mmc1_pins_default: main-mmc1-pins-default {
 135                 pinctrl-single,pins = <
 136                         AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
 137                         AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
 138                         AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
 139                         AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
 140                         AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
 141                         AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
 142                         AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
 143                         AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
 144                         AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
 145                 >;
 146         };
 147
 148         main_uart0_pins_default: main-uart0-pins-default {
 149                 pinctrl-single,pins = <
 150                         AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
 151                         AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
 152                         AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
 153                         AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
 154                 >;
 155         };
 156
 157         main_spi0_pins_default: main-spi0-pins-default {
 158                 pinctrl-single,pins = <
 159                         AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
 160                         AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
 161                         AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
 162                         AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
 163                 >;
 164         };
 165
 166         main_i2c1_pins_default: main-i2c1-pins-default {
 167                 pinctrl-single,pins = <
 168                         AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
 169                         AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
 170                 >;
 171         };
 172
 173         mdio1_pins_default: mdio1-pins-default {
 174                 pinctrl-single,pins = <
 175                         AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
 176                         AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
 177                 >;
 178         };
 179
 180         rgmii1_pins_default: rgmii1-pins-default {
 181                 pinctrl-single,pins = <
 182                         AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
 183                         AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
 184                         AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
 185                         AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
 186                         AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
 187                         AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
 188                         AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
 189                         AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
 190                         AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
 191                         AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
 192                         AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
 193                         AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
 194                 >;
 195         };
 196
 197        rgmii2_pins_default: rgmii2-pins-default {
 198                 pinctrl-single,pins = <
 199                         AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
 200                         AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
 201                         AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
 202                         AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
 203                         AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
 204                         AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
 205                         AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
 206                         AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
 207                         AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
 208                         AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
 209                         AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
 210                         AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
 211                 >;
 212         };
 213
 214         main_usb0_pins_default: main-usb0-pins-default {
 215                 pinctrl-single,pins = <
 216                         AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
 217                 >;
 218         };
 219
 220         ospi0_pins_default: ospi0-pins-default {
 221                 pinctrl-single,pins = <
 222                         AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
 223                         AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
 224                         AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
 225                         AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
 226                         AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
 227                         AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
 228                         AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
 229                         AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
 230                         AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
 231                         AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
 232                         AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
 233                 >;
 234         };
 235 };
 236
 237 &main_uart0 {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&main_uart0_pins_default>;
 240 };
 241
 242 /* main_uart1 is reserved for firmware usage */
 243 &main_uart1 {
 244         status = "reserved";
 245 };
 246
 247 &main_uart2 {
 248         status = "disabled";
 249 };
 250
 251 &main_uart3 {
 252         status = "disabled";
 253 };
 254
 255 &main_uart4 {
 256         status = "disabled";
 257 };
 258
 259 &main_uart5 {
 260         status = "disabled";
 261 };
 262
 263 &main_uart6 {
 264         status = "disabled";
 265 };
 266
 267 &mcu_uart0 {
 268         status = "disabled";
 269 };
 270
 271 &mcu_uart1 {
 272         status = "disabled";
 273 };
 274
 275 &main_i2c1 {
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&main_i2c1_pins_default>;
 278         clock-frequency = <400000>;
 279
 280         exp1: gpio@22 {
 281                 compatible = "ti,tca6424";
 282                 reg = <0x22>;
 283                 gpio-controller;
 284                 #gpio-cells = <2>;
 285                 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
 286                                   "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
 287                                   "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
 288                                   "MMC1_SD_EN", "FSI_FET_SEL",
 289                                   "MCAN0_STB_3V3", "MCAN1_STB_3V3",
 290                                   "CPSW_FET_SEL", "CPSW_FET2_SEL",
 291                                   "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
 292                                   "GPIO_OLED_RESETn", "VPP_LDO_EN",
 293                                   "TEST_LED1", "TP92", "TP90", "TP88",
 294                                   "TP87", "TP86", "TP89", "TP91";
 295         };
 296
 297         /* osd9616p0899-10 */
 298         display@3c {
 299                 compatible = "solomon,ssd1306fb-i2c";
 300                 reg = <0x3c>;
 301                 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
 302                 vbat-supply = <&vddb>;
 303                 solomon,height = <16>;
 304                 solomon,width = <96>;
 305                 solomon,com-seq;
 306                 solomon,com-invdir;
 307                 solomon,page-offset = <0>;
 308                 solomon,prechargep1 = <2>;
 309                 solomon,prechargep2 = <13>;
 310         };
 311 };
 312
 313 /* mcu_gpio0 is reserved for mcu firmware usage */
 314 &mcu_gpio0 {
 315         status = "reserved";
 316 };
 317
 318 &mcu_i2c0 {
 319         status = "disabled";
 320 };
 321
 322 &mcu_i2c1 {
 323         status = "disabled";
 324 };
 325
 326 &mcu_spi0 {
 327         status = "disabled";
 328 };
 329
 330 &mcu_spi1 {
 331         status = "disabled";
 332 };
 333
 334 &main_spi0 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&main_spi0_pins_default>;
 337         ti,pindir-d0-out-d1-in = <1>;
 338         eeprom@0 {
 339                 compatible = "microchip,93lc46b";
 340                 reg = <0>;
 341                 spi-max-frequency = <1000000>;
 342                 spi-cs-high;
 343                 data-size = <16>;
 344         };
 345 };
 346
 347 &sdhci0 {
 348         /* emmc */
 349         bus-width = <8>;
 350         non-removable;
 351         ti,driver-strength-ohm = <50>;
 352         disable-wp;
 353 };
 354
 355 &sdhci1 {
 356         /* SD/MMC */
 357         vmmc-supply = <&vdd_mmc1>;
 358         pinctrl-names = "default";
 359         bus-width = <4>;
 360         pinctrl-0 = <&main_mmc1_pins_default>;
 361         ti,driver-strength-ohm = <50>;
 362         disable-wp;
 363 };
 364
 365 &usbss0 {
 366         ti,vbus-divider;
 367         ti,usb2-only;
 368 };
 369
 370 &usb0 {
 371         dr_mode = "otg";
 372         maximum-speed = "high-speed";
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&main_usb0_pins_default>;
 375 };
 376
 377 &cpsw3g {
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&mdio1_pins_default
 380                      &rgmii1_pins_default
 381                      &rgmii2_pins_default>;
 382 };
 383
 384 &cpsw_port1 {
 385         phy-mode = "rgmii-rxid";
 386         phy-handle = <&cpsw3g_phy0>;
 387 };
 388
 389 &cpsw_port2 {
 390         phy-mode = "rgmii-rxid";
 391         phy-handle = <&cpsw3g_phy3>;
 392 };
 393
 394 &cpsw3g_mdio {
 395         cpsw3g_phy0: ethernet-phy@0 {
 396                 reg = <0>;
 397                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 398                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 399         };
 400 };
 401
 402 &tscadc0 {
 403         /* ADC is reserved for R5 usage */
 404         status = "reserved";
 405 };
 406
 407 &ospi0 {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&ospi0_pins_default>;
 410
 411         flash@0{
 412                 compatible = "jedec,spi-nor";
 413                 reg = <0x0>;
 414                 spi-tx-bus-width = <8>;
 415                 spi-rx-bus-width = <8>;
 416                 spi-max-frequency = <25000000>;
 417                 cdns,tshsl-ns = <60>;
 418                 cdns,tsd2d-ns = <60>;
 419                 cdns,tchsh-ns = <60>;
 420                 cdns,tslch-ns = <60>;
 421                 cdns,read-delay = <4>;
 422                 #address-cells = <1>;
 423                 #size-cells = <1>;
 424         };
 425 };
 426
 427 &mailbox0_cluster2 {
 428         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 429                 ti,mbox-rx = <0 0 2>;
 430                 ti,mbox-tx = <1 0 2>;
 431         };
 432
 433         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 434                 ti,mbox-rx = <2 0 2>;
 435                 ti,mbox-tx = <3 0 2>;
 436         };
 437 };
 438
 439 &mailbox0_cluster3 {
 440         status = "disabled";
 441 };
 442
 443 &mailbox0_cluster4 {
 444         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 445                 ti,mbox-rx = <0 0 2>;
 446                 ti,mbox-tx = <1 0 2>;
 447         };
 448
 449         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 450                 ti,mbox-rx = <2 0 2>;
 451                 ti,mbox-tx = <3 0 2>;
 452         };
 453 };
 454
 455 &mailbox0_cluster5 {
 456         status = "disabled";
 457 };
 458
 459 &mailbox0_cluster6 {
 460         mbox_m4_0: mbox-m4-0 {
 461                 ti,mbox-rx = <0 0 2>;
 462                 ti,mbox-tx = <1 0 2>;
 463         };
 464 };
 465
 466 &mailbox0_cluster7 {
 467         status = "disabled";
 468 };