1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
5 // Copyright (C) 2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 /memreserve/ 0x80000000 0x02000000;
14 compatible = "socionext,uniphier-ld11";
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a53";
38 clocks = <&sys_clk 33>;
39 enable-method = "psci";
40 operating-points-v2 = <&cluster0_opp>;
45 compatible = "arm,cortex-a53";
47 clocks = <&sys_clk 33>;
48 enable-method = "psci";
49 operating-points-v2 = <&cluster0_opp>;
53 cluster0_opp: opp-table {
54 compatible = "operating-points-v2";
58 opp-hz = /bits/ 64 <245000000>;
59 clock-latency-ns = <300>;
62 opp-hz = /bits/ 64 <250000000>;
63 clock-latency-ns = <300>;
66 opp-hz = /bits/ 64 <490000000>;
67 clock-latency-ns = <300>;
70 opp-hz = /bits/ 64 <500000000>;
71 clock-latency-ns = <300>;
74 opp-hz = /bits/ 64 <653334000>;
75 clock-latency-ns = <300>;
78 opp-hz = /bits/ 64 <666667000>;
79 clock-latency-ns = <300>;
82 opp-hz = /bits/ 64 <980000000>;
83 clock-latency-ns = <300>;
88 compatible = "arm,psci-1.0";
94 compatible = "fixed-clock";
96 clock-frequency = <25000000>;
100 emmc_pwrseq: emmc-pwrseq {
101 compatible = "mmc-pwrseq-emmc";
102 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
106 compatible = "arm,armv8-timer";
107 interrupts = <1 13 4>,
114 compatible = "simple-bus";
115 #address-cells = <1>;
117 ranges = <0 0 0 0xffffffff>;
120 compatible = "socionext,uniphier-scssi";
122 reg = <0x54006000 0x100>;
123 interrupts = <0 39 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_spi0>;
126 clocks = <&peri_clk 11>;
127 resets = <&peri_rst 11>;
131 compatible = "socionext,uniphier-scssi";
133 reg = <0x54006100 0x100>;
134 interrupts = <0 216 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_spi1>;
137 clocks = <&peri_clk 11>;
138 resets = <&peri_rst 11>;
141 serial0: serial@54006800 {
142 compatible = "socionext,uniphier-uart";
144 reg = <0x54006800 0x40>;
145 interrupts = <0 33 4>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>;
148 clocks = <&peri_clk 0>;
149 resets = <&peri_rst 0>;
152 serial1: serial@54006900 {
153 compatible = "socionext,uniphier-uart";
155 reg = <0x54006900 0x40>;
156 interrupts = <0 35 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart1>;
159 clocks = <&peri_clk 1>;
160 resets = <&peri_rst 1>;
163 serial2: serial@54006a00 {
164 compatible = "socionext,uniphier-uart";
166 reg = <0x54006a00 0x40>;
167 interrupts = <0 37 4>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 clocks = <&peri_clk 2>;
171 resets = <&peri_rst 2>;
174 serial3: serial@54006b00 {
175 compatible = "socionext,uniphier-uart";
177 reg = <0x54006b00 0x40>;
178 interrupts = <0 177 4>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
181 clocks = <&peri_clk 3>;
182 resets = <&peri_rst 3>;
185 gpio: gpio@55000000 {
186 compatible = "socionext,uniphier-gpio";
187 reg = <0x55000000 0x200>;
188 interrupt-parent = <&aidet>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
193 gpio-ranges = <&pinctrl 0 0 0>,
199 gpio-ranges-group-names = "gpio_range0",
206 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
211 compatible = "socionext,uniphier-ld11-aio";
212 reg = <0x56000000 0x80000>;
213 interrupts = <0 144 4>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_aout1>,
218 clocks = <&sys_clk 40>;
220 resets = <&sys_rst 40>;
221 #sound-dai-cells = <1>;
222 socionext,syscon = <&soc_glue>;
230 i2s_pcmin2: endpoint {
237 remote-endpoint = <&evea_line>;
242 i2s_hpcmout1: endpoint {
249 remote-endpoint = <&evea_hp>;
253 spdif_port0: port@5 {
254 spdif_hiecout1: endpoint {
259 i2s_epcmout2: endpoint {
264 i2s_epcmout3: endpoint {
268 comp_spdif_port0: port@8 {
269 comp_spdif_hiecout1: endpoint {
275 compatible = "socionext,uniphier-evea";
276 reg = <0x57900000 0x1000>;
277 clock-names = "evea", "exiv";
278 clocks = <&sys_clk 41>, <&sys_clk 42>;
279 reset-names = "evea", "exiv", "adamv";
280 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
281 #sound-dai-cells = <1>;
284 evea_line: endpoint {
285 remote-endpoint = <&i2s_line>;
291 remote-endpoint = <&i2s_hp>;
297 compatible = "socionext,uniphier-ld11-adamv",
298 "simple-mfd", "syscon";
299 reg = <0x57920000 0x1000>;
302 compatible = "socionext,uniphier-ld11-adamv-reset";
308 compatible = "socionext,uniphier-fi2c";
310 reg = <0x58780000 0x80>;
311 #address-cells = <1>;
313 interrupts = <0 41 4>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_i2c0>;
316 clocks = <&peri_clk 4>;
317 resets = <&peri_rst 4>;
318 clock-frequency = <100000>;
322 compatible = "socionext,uniphier-fi2c";
324 reg = <0x58781000 0x80>;
325 #address-cells = <1>;
327 interrupts = <0 42 4>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_i2c1>;
330 clocks = <&peri_clk 5>;
331 resets = <&peri_rst 5>;
332 clock-frequency = <100000>;
336 compatible = "socionext,uniphier-fi2c";
337 reg = <0x58782000 0x80>;
338 #address-cells = <1>;
340 interrupts = <0 43 4>;
341 clocks = <&peri_clk 6>;
342 resets = <&peri_rst 6>;
343 clock-frequency = <400000>;
347 compatible = "socionext,uniphier-fi2c";
349 reg = <0x58783000 0x80>;
350 #address-cells = <1>;
352 interrupts = <0 44 4>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_i2c3>;
355 clocks = <&peri_clk 7>;
356 resets = <&peri_rst 7>;
357 clock-frequency = <100000>;
361 compatible = "socionext,uniphier-fi2c";
363 reg = <0x58784000 0x80>;
364 #address-cells = <1>;
366 interrupts = <0 45 4>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_i2c4>;
369 clocks = <&peri_clk 8>;
370 resets = <&peri_rst 8>;
371 clock-frequency = <100000>;
375 compatible = "socionext,uniphier-fi2c";
376 reg = <0x58785000 0x80>;
377 #address-cells = <1>;
379 interrupts = <0 25 4>;
380 clocks = <&peri_clk 9>;
381 resets = <&peri_rst 9>;
382 clock-frequency = <400000>;
385 system_bus: system-bus@58c00000 {
386 compatible = "socionext,uniphier-system-bus";
388 reg = <0x58c00000 0x400>;
389 #address-cells = <2>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_system_bus>;
396 compatible = "socionext,uniphier-smpctrl";
397 reg = <0x59801000 0x400>;
401 compatible = "socionext,uniphier-ld11-sdctrl",
402 "simple-mfd", "syscon";
403 reg = <0x59810000 0x400>;
406 compatible = "socionext,uniphier-ld11-sd-reset";
412 compatible = "socionext,uniphier-ld11-perictrl",
413 "simple-mfd", "syscon";
414 reg = <0x59820000 0x200>;
417 compatible = "socionext,uniphier-ld11-peri-clock";
422 compatible = "socionext,uniphier-ld11-peri-reset";
427 emmc: sdhc@5a000000 {
428 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
429 reg = <0x5a000000 0x400>;
430 interrupts = <0 78 4>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_emmc>;
433 clocks = <&sys_clk 4>;
434 resets = <&sys_rst 4>;
438 mmc-pwrseq = <&emmc_pwrseq>;
439 cdns,phy-input-delay-legacy = <9>;
440 cdns,phy-input-delay-mmc-highspeed = <2>;
441 cdns,phy-input-delay-mmc-ddr = <3>;
442 cdns,phy-dll-delay-sdclk = <21>;
443 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
447 compatible = "socionext,uniphier-ehci", "generic-ehci";
449 reg = <0x5a800100 0x100>;
450 interrupts = <0 243 4>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_usb0>;
453 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
455 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
459 has-transaction-translator;
463 compatible = "socionext,uniphier-ehci", "generic-ehci";
465 reg = <0x5a810100 0x100>;
466 interrupts = <0 244 4>;
467 pinctrl-names = "default";
468 pinctrl-0 = <&pinctrl_usb1>;
469 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
471 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
475 has-transaction-translator;
479 compatible = "socionext,uniphier-ehci", "generic-ehci";
481 reg = <0x5a820100 0x100>;
482 interrupts = <0 245 4>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_usb2>;
485 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
487 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
491 has-transaction-translator;
495 compatible = "socionext,uniphier-ld11-mioctrl",
496 "simple-mfd", "syscon";
497 reg = <0x5b3e0000 0x800>;
500 compatible = "socionext,uniphier-ld11-mio-clock";
505 compatible = "socionext,uniphier-ld11-mio-reset";
507 resets = <&sys_rst 7>;
511 soc_glue: soc-glue@5f800000 {
512 compatible = "socionext,uniphier-ld11-soc-glue",
513 "simple-mfd", "syscon";
514 reg = <0x5f800000 0x2000>;
517 compatible = "socionext,uniphier-ld11-pinctrl";
521 compatible = "socionext,uniphier-ld11-usb2-phy";
522 #address-cells = <1>;
543 compatible = "socionext,uniphier-ld11-soc-glue-debug",
545 #address-cells = <1>;
547 ranges = <0 0x5f900000 0x2000>;
550 compatible = "socionext,uniphier-efuse";
555 compatible = "socionext,uniphier-efuse";
560 aidet: aidet@5fc20000 {
561 compatible = "socionext,uniphier-ld11-aidet";
562 reg = <0x5fc20000 0x200>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
567 gic: interrupt-controller@5fe00000 {
568 compatible = "arm,gic-v3";
569 reg = <0x5fe00000 0x10000>, /* GICD */
570 <0x5fe40000 0x80000>; /* GICR */
571 interrupt-controller;
572 #interrupt-cells = <3>;
573 interrupts = <1 9 4>;
577 compatible = "socionext,uniphier-ld11-sysctrl",
578 "simple-mfd", "syscon";
579 reg = <0x61840000 0x10000>;
582 compatible = "socionext,uniphier-ld11-clock";
587 compatible = "socionext,uniphier-ld11-reset";
592 compatible = "socionext,uniphier-wdt";
596 eth: ethernet@65000000 {
597 compatible = "socionext,uniphier-ld11-ave4";
599 reg = <0x65000000 0x8500>;
600 interrupts = <0 66 4>;
601 clock-names = "ether";
602 clocks = <&sys_clk 6>;
603 reset-names = "ether";
604 resets = <&sys_rst 6>;
605 phy-mode = "internal";
606 local-mac-address = [00 00 00 00 00 00];
607 socionext,syscon-phy-mode = <&soc_glue 0>;
610 #address-cells = <1>;
615 nand: nand@68000000 {
616 compatible = "socionext,uniphier-denali-nand-v5b";
618 reg-names = "nand_data", "denali_reg";
619 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
620 interrupts = <0 65 4>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_nand>;
623 clock-names = "nand", "nand_x", "ecc";
624 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
625 resets = <&sys_rst 2>;
630 #include "uniphier-pinctrl.dtsi"
633 drive-strength = <4>; /* default: 4mA */
637 drive-strength = <8>; /* 8mA */