arch/arm64/boot/dts/rockchip/rk3588s.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/power/rk3588-power.h>
  10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/ata/ahci.h>
  13
  14 / {
  15         compatible = "rockchip,rk3588";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu_l0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&cpu_l1>;
  32                                 };
  33                                 core2 {
  34                                         cpu = <&cpu_l2>;
  35                                 };
  36                                 core3 {
  37                                         cpu = <&cpu_l3>;
  38                                 };
  39                         };
  40                         cluster1 {
  41                                 core0 {
  42                                         cpu = <&cpu_b0>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&cpu_b1>;
  46                                 };
  47                         };
  48                         cluster2 {
  49                                 core0 {
  50                                         cpu = <&cpu_b2>;
  51                                 };
  52                                 core1 {
  53                                         cpu = <&cpu_b3>;
  54                                 };
  55                         };
  56                 };
  57
  58                 cpu_l0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a55";
  61                         reg = <0x0>;
  62                         enable-method = "psci";
  63                         capacity-dmips-mhz = <530>;
  64                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
  65                         assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
  66                         assigned-clock-rates = <816000000>;
  67                         cpu-idle-states = <&CPU_SLEEP>;
  68                         i-cache-size = <32768>;
  69                         i-cache-line-size = <64>;
  70                         i-cache-sets = <128>;
  71                         d-cache-size = <32768>;
  72                         d-cache-line-size = <64>;
  73                         d-cache-sets = <128>;
  74                         next-level-cache = <&l2_cache_l0>;
  75                         dynamic-power-coefficient = <228>;
  76                         #cooling-cells = <2>;
  77                 };
  78
  79                 cpu_l1: cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a55";
  82                         reg = <0x100>;
  83                         enable-method = "psci";
  84                         capacity-dmips-mhz = <530>;
  85                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
  86                         cpu-idle-states = <&CPU_SLEEP>;
  87                         i-cache-size = <32768>;
  88                         i-cache-line-size = <64>;
  89                         i-cache-sets = <128>;
  90                         d-cache-size = <32768>;
  91                         d-cache-line-size = <64>;
  92                         d-cache-sets = <128>;
  93                         next-level-cache = <&l2_cache_l1>;
  94                         dynamic-power-coefficient = <228>;
  95                         #cooling-cells = <2>;
  96                 };
  97
  98                 cpu_l2: cpu@200 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a55";
 101                         reg = <0x200>;
 102                         enable-method = "psci";
 103                         capacity-dmips-mhz = <530>;
 104                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
 105                         cpu-idle-states = <&CPU_SLEEP>;
 106                         i-cache-size = <32768>;
 107                         i-cache-line-size = <64>;
 108                         i-cache-sets = <128>;
 109                         d-cache-size = <32768>;
 110                         d-cache-line-size = <64>;
 111                         d-cache-sets = <128>;
 112                         next-level-cache = <&l2_cache_l2>;
 113                         dynamic-power-coefficient = <228>;
 114                         #cooling-cells = <2>;
 115                 };
 116
 117                 cpu_l3: cpu@300 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a55";
 120                         reg = <0x300>;
 121                         enable-method = "psci";
 122                         capacity-dmips-mhz = <530>;
 123                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
 124                         cpu-idle-states = <&CPU_SLEEP>;
 125                         i-cache-size = <32768>;
 126                         i-cache-line-size = <64>;
 127                         i-cache-sets = <128>;
 128                         d-cache-size = <32768>;
 129                         d-cache-line-size = <64>;
 130                         d-cache-sets = <128>;
 131                         next-level-cache = <&l2_cache_l3>;
 132                         dynamic-power-coefficient = <228>;
 133                         #cooling-cells = <2>;
 134                 };
 135
 136                 cpu_b0: cpu@400 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a76";
 139                         reg = <0x400>;
 140                         enable-method = "psci";
 141                         capacity-dmips-mhz = <1024>;
 142                         clocks = <&scmi_clk SCMI_CLK_CPUB01>;
 143                         assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
 144                         assigned-clock-rates = <816000000>;
 145                         cpu-idle-states = <&CPU_SLEEP>;
 146                         i-cache-size = <65536>;
 147                         i-cache-line-size = <64>;
 148                         i-cache-sets = <256>;
 149                         d-cache-size = <65536>;
 150                         d-cache-line-size = <64>;
 151                         d-cache-sets = <256>;
 152                         next-level-cache = <&l2_cache_b0>;
 153                         dynamic-power-coefficient = <416>;
 154                         #cooling-cells = <2>;
 155                 };
 156
 157                 cpu_b1: cpu@500 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a76";
 160                         reg = <0x500>;
 161                         enable-method = "psci";
 162                         capacity-dmips-mhz = <1024>;
 163                         clocks = <&scmi_clk SCMI_CLK_CPUB01>;
 164                         cpu-idle-states = <&CPU_SLEEP>;
 165                         i-cache-size = <65536>;
 166                         i-cache-line-size = <64>;
 167                         i-cache-sets = <256>;
 168                         d-cache-size = <65536>;
 169                         d-cache-line-size = <64>;
 170                         d-cache-sets = <256>;
 171                         next-level-cache = <&l2_cache_b1>;
 172                         dynamic-power-coefficient = <416>;
 173                         #cooling-cells = <2>;
 174                 };
 175
 176                 cpu_b2: cpu@600 {
 177                         device_type = "cpu";
 178                         compatible = "arm,cortex-a76";
 179                         reg = <0x600>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1024>;
 182                         clocks = <&scmi_clk SCMI_CLK_CPUB23>;
 183                         assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
 184                         assigned-clock-rates = <816000000>;
 185                         cpu-idle-states = <&CPU_SLEEP>;
 186                         i-cache-size = <65536>;
 187                         i-cache-line-size = <64>;
 188                         i-cache-sets = <256>;
 189                         d-cache-size = <65536>;
 190                         d-cache-line-size = <64>;
 191                         d-cache-sets = <256>;
 192                         next-level-cache = <&l2_cache_b2>;
 193                         dynamic-power-coefficient = <416>;
 194                         #cooling-cells = <2>;
 195                 };
 196
 197                 cpu_b3: cpu@700 {
 198                         device_type = "cpu";
 199                         compatible = "arm,cortex-a76";
 200                         reg = <0x700>;
 201                         enable-method = "psci";
 202                         capacity-dmips-mhz = <1024>;
 203                         clocks = <&scmi_clk SCMI_CLK_CPUB23>;
 204                         cpu-idle-states = <&CPU_SLEEP>;
 205                         i-cache-size = <65536>;
 206                         i-cache-line-size = <64>;
 207                         i-cache-sets = <256>;
 208                         d-cache-size = <65536>;
 209                         d-cache-line-size = <64>;
 210                         d-cache-sets = <256>;
 211                         next-level-cache = <&l2_cache_b3>;
 212                         dynamic-power-coefficient = <416>;
 213                         #cooling-cells = <2>;
 214                 };
 215
 216                 idle-states {
 217                         entry-method = "psci";
 218                         CPU_SLEEP: cpu-sleep {
 219                                 compatible = "arm,idle-state";
 220                                 local-timer-stop;
 221                                 arm,psci-suspend-param = <0x0010000>;
 222                                 entry-latency-us = <100>;
 223                                 exit-latency-us = <120>;
 224                                 min-residency-us = <1000>;
 225                         };
 226                 };
 227
 228                 l2_cache_l0: l2-cache-l0 {
 229                         compatible = "cache";
 230                         cache-size = <131072>;
 231                         cache-line-size = <64>;
 232                         cache-sets = <512>;
 233                         cache-level = <2>;
 234                         cache-unified;
 235                         next-level-cache = <&l3_cache>;
 236                 };
 237
 238                 l2_cache_l1: l2-cache-l1 {
 239                         compatible = "cache";
 240                         cache-size = <131072>;
 241                         cache-line-size = <64>;
 242                         cache-sets = <512>;
 243                         cache-level = <2>;
 244                         cache-unified;
 245                         next-level-cache = <&l3_cache>;
 246                 };
 247
 248                 l2_cache_l2: l2-cache-l2 {
 249                         compatible = "cache";
 250                         cache-size = <131072>;
 251                         cache-line-size = <64>;
 252                         cache-sets = <512>;
 253                         cache-level = <2>;
 254                         cache-unified;
 255                         next-level-cache = <&l3_cache>;
 256                 };
 257
 258                 l2_cache_l3: l2-cache-l3 {
 259                         compatible = "cache";
 260                         cache-size = <131072>;
 261                         cache-line-size = <64>;
 262                         cache-sets = <512>;
 263                         cache-level = <2>;
 264                         cache-unified;
 265                         next-level-cache = <&l3_cache>;
 266                 };
 267
 268                 l2_cache_b0: l2-cache-b0 {
 269                         compatible = "cache";
 270                         cache-size = <524288>;
 271                         cache-line-size = <64>;
 272                         cache-sets = <1024>;
 273                         cache-level = <2>;
 274                         cache-unified;
 275                         next-level-cache = <&l3_cache>;
 276                 };
 277
 278                 l2_cache_b1: l2-cache-b1 {
 279                         compatible = "cache";
 280                         cache-size = <524288>;
 281                         cache-line-size = <64>;
 282                         cache-sets = <1024>;
 283                         cache-level = <2>;
 284                         cache-unified;
 285                         next-level-cache = <&l3_cache>;
 286                 };
 287
 288                 l2_cache_b2: l2-cache-b2 {
 289                         compatible = "cache";
 290                         cache-size = <524288>;
 291                         cache-line-size = <64>;
 292                         cache-sets = <1024>;
 293                         cache-level = <2>;
 294                         cache-unified;
 295                         next-level-cache = <&l3_cache>;
 296                 };
 297
 298                 l2_cache_b3: l2-cache-b3 {
 299                         compatible = "cache";
 300                         cache-size = <524288>;
 301                         cache-line-size = <64>;
 302                         cache-sets = <1024>;
 303                         cache-level = <2>;
 304                         cache-unified;
 305                         next-level-cache = <&l3_cache>;
 306                 };
 307
 308                 l3_cache: l3-cache {
 309                         compatible = "cache";
 310                         cache-size = <3145728>;
 311                         cache-line-size = <64>;
 312                         cache-sets = <4096>;
 313                         cache-level = <3>;
 314                         cache-unified;
 315                 };
 316         };
 317
 318         firmware {
 319                 optee: optee {
 320                         compatible = "linaro,optee-tz";
 321                         method = "smc";
 322                 };
 323
 324                 scmi: scmi {
 325                         compatible = "arm,scmi-smc";
 326                         arm,smc-id = <0x82000010>;
 327                         shmem = <&scmi_shmem>;
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330
 331                         scmi_clk: protocol@14 {
 332                                 reg = <0x14>;
 333                                 #clock-cells = <1>;
 334                         };
 335
 336                         scmi_reset: protocol@16 {
 337                                 reg = <0x16>;
 338                                 #reset-cells = <1>;
 339                         };
 340                 };
 341         };
 342
 343         pmu-a55 {
 344                 compatible = "arm,cortex-a55-pmu";
 345                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
 346         };
 347
 348         pmu-a76 {
 349                 compatible = "arm,cortex-a76-pmu";
 350                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
 351         };
 352
 353         psci {
 354                 compatible = "arm,psci-1.0";
 355                 method = "smc";
 356         };
 357
 358         spll: clock-0 {
 359                 compatible = "fixed-clock";
 360                 clock-frequency = <702000000>;
 361                 clock-output-names = "spll";
 362                 #clock-cells = <0>;
 363         };
 364
 365         timer {
 366                 compatible = "arm,armv8-timer";
 367                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 368                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 369                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 370                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
 371                              <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 372                 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
 373         };
 374
 375         xin24m: clock-1 {
 376                 compatible = "fixed-clock";
 377                 clock-frequency = <24000000>;
 378                 clock-output-names = "xin24m";
 379                 #clock-cells = <0>;
 380         };
 381
 382         xin32k: clock-2 {
 383                 compatible = "fixed-clock";
 384                 clock-frequency = <32768>;
 385                 clock-output-names = "xin32k";
 386                 #clock-cells = <0>;
 387         };
 388
 389         pmu_sram: sram@10f000 {
 390                 compatible = "mmio-sram";
 391                 reg = <0x0 0x0010f000 0x0 0x100>;
 392                 ranges = <0 0x0 0x0010f000 0x100>;
 393                 #address-cells = <1>;
 394                 #size-cells = <1>;
 395
 396                 scmi_shmem: sram@0 {
 397                         compatible = "arm,scmi-shmem";
 398                         reg = <0x0 0x100>;
 399                 };
 400         };
 401
 402         usb_host0_ehci: usb@fc800000 {
 403                 compatible = "rockchip,rk3588-ehci", "generic-ehci";
 404                 reg = <0x0 0xfc800000 0x0 0x40000>;
 405                 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
 406                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
 407                 phys = <&u2phy2_host>;
 408                 phy-names = "usb";
 409                 power-domains = <&power RK3588_PD_USB>;
 410                 status = "disabled";
 411         };
 412
 413         usb_host0_ohci: usb@fc840000 {
 414                 compatible = "rockchip,rk3588-ohci", "generic-ohci";
 415                 reg = <0x0 0xfc840000 0x0 0x40000>;
 416                 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
 417                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
 418                 phys = <&u2phy2_host>;
 419                 phy-names = "usb";
 420                 power-domains = <&power RK3588_PD_USB>;
 421                 status = "disabled";
 422         };
 423
 424         usb_host1_ehci: usb@fc880000 {
 425                 compatible = "rockchip,rk3588-ehci", "generic-ehci";
 426                 reg = <0x0 0xfc880000 0x0 0x40000>;
 427                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
 428                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
 429                 phys = <&u2phy3_host>;
 430                 phy-names = "usb";
 431                 power-domains = <&power RK3588_PD_USB>;
 432                 status = "disabled";
 433         };
 434
 435         usb_host1_ohci: usb@fc8c0000 {
 436                 compatible = "rockchip,rk3588-ohci", "generic-ohci";
 437                 reg = <0x0 0xfc8c0000 0x0 0x40000>;
 438                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
 439                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
 440                 phys = <&u2phy3_host>;
 441                 phy-names = "usb";
 442                 power-domains = <&power RK3588_PD_USB>;
 443                 status = "disabled";
 444         };
 445
 446         usb_host2_xhci: usb@fcd00000 {
 447                 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
 448                 reg = <0x0 0xfcd00000 0x0 0x400000>;
 449                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
 450                 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
 451                          <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
 452                          <&cru CLK_PIPEPHY2_PIPE_U3_G>;
 453                 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
 454                 dr_mode = "host";
 455                 phys = <&combphy2_psu PHY_TYPE_USB3>;
 456                 phy-names = "usb3-phy";
 457                 phy_type = "utmi_wide";
 458                 resets = <&cru SRST_A_USB3OTG2>;
 459                 snps,dis_enblslpm_quirk;
 460                 snps,dis-u2-freeclk-exists-quirk;
 461                 snps,dis-del-phy-power-chg-quirk;
 462                 snps,dis-tx-ipgap-linecheck-quirk;
 463                 snps,dis_rxdet_inp3_quirk;
 464                 status = "disabled";
 465         };
 466
 467         sys_grf: syscon@fd58c000 {
 468                 compatible = "rockchip,rk3588-sys-grf", "syscon";
 469                 reg = <0x0 0xfd58c000 0x0 0x1000>;
 470         };
 471
 472         php_grf: syscon@fd5b0000 {
 473                 compatible = "rockchip,rk3588-php-grf", "syscon";
 474                 reg = <0x0 0xfd5b0000 0x0 0x1000>;
 475         };
 476
 477         pipe_phy0_grf: syscon@fd5bc000 {
 478                 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 479                 reg = <0x0 0xfd5bc000 0x0 0x100>;
 480         };
 481
 482         pipe_phy2_grf: syscon@fd5c4000 {
 483                 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 484                 reg = <0x0 0xfd5c4000 0x0 0x100>;
 485         };
 486
 487         usb2phy2_grf: syscon@fd5d8000 {
 488                 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
 489                 reg = <0x0 0xfd5d8000 0x0 0x4000>;
 490                 #address-cells = <1>;
 491                 #size-cells = <1>;
 492
 493                 u2phy2: usb2-phy@8000 {
 494                         compatible = "rockchip,rk3588-usb2phy";
 495                         reg = <0x8000 0x10>;
 496                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
 497                         resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
 498                         reset-names = "phy", "apb";
 499                         clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
 500                         clock-names = "phyclk";
 501                         clock-output-names = "usb480m_phy2";
 502                         #clock-cells = <0>;
 503                         status = "disabled";
 504
 505                         u2phy2_host: host-port {
 506                                 #phy-cells = <0>;
 507                                 status = "disabled";
 508                         };
 509                 };
 510         };
 511
 512         usb2phy3_grf: syscon@fd5dc000 {
 513                 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
 514                 reg = <0x0 0xfd5dc000 0x0 0x4000>;
 515                 #address-cells = <1>;
 516                 #size-cells = <1>;
 517
 518                 u2phy3: usb2-phy@c000 {
 519                         compatible = "rockchip,rk3588-usb2phy";
 520                         reg = <0xc000 0x10>;
 521                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
 522                         resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
 523                         reset-names = "phy", "apb";
 524                         clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
 525                         clock-names = "phyclk";
 526                         clock-output-names = "usb480m_phy3";
 527                         #clock-cells = <0>;
 528                         status = "disabled";
 529
 530                         u2phy3_host: host-port {
 531                                 #phy-cells = <0>;
 532                                 status = "disabled";
 533                         };
 534                 };
 535         };
 536
 537         ioc: syscon@fd5f0000 {
 538                 compatible = "rockchip,rk3588-ioc", "syscon";
 539                 reg = <0x0 0xfd5f0000 0x0 0x10000>;
 540         };
 541
 542         system_sram1: sram@fd600000 {
 543                 compatible = "mmio-sram";
 544                 reg = <0x0 0xfd600000 0x0 0x100000>;
 545                 ranges = <0x0 0x0 0xfd600000 0x100000>;
 546                 #address-cells = <1>;
 547                 #size-cells = <1>;
 548         };
 549
 550         cru: clock-controller@fd7c0000 {
 551                 compatible = "rockchip,rk3588-cru";
 552                 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
 553                 assigned-clocks =
 554                         <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
 555                         <&cru PLL_NPLL>, <&cru PLL_GPLL>,
 556                         <&cru ACLK_CENTER_ROOT>,
 557                         <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
 558                         <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
 559                         <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
 560                         <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
 561                         <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
 562                         <&cru CLK_GPU>;
 563                 assigned-clock-rates =
 564                         <1100000000>, <786432000>,
 565                         <850000000>, <1188000000>,
 566                         <702000000>,
 567                         <400000000>, <500000000>,
 568                         <800000000>, <100000000>,
 569                         <400000000>, <100000000>,
 570                         <200000000>, <500000000>,
 571                         <375000000>, <150000000>,
 572                         <200000000>;
 573                 rockchip,grf = <&php_grf>;
 574                 #clock-cells = <1>;
 575                 #reset-cells = <1>;
 576         };
 577
 578         i2c0: i2c@fd880000 {
 579                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
 580                 reg = <0x0 0xfd880000 0x0 0x1000>;
 581                 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
 582                 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
 583                 clock-names = "i2c", "pclk";
 584                 pinctrl-0 = <&i2c0m0_xfer>;
 585                 pinctrl-names = "default";
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 status = "disabled";
 589         };
 590
 591         uart0: serial@fd890000 {
 592                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
 593                 reg = <0x0 0xfd890000 0x0 0x100>;
 594                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
 595                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 596                 clock-names = "baudclk", "apb_pclk";
 597                 dmas = <&dmac0 6>, <&dmac0 7>;
 598                 dma-names = "tx", "rx";
 599                 pinctrl-0 = <&uart0m1_xfer>;
 600                 pinctrl-names = "default";
 601                 reg-shift = <2>;
 602                 reg-io-width = <4>;
 603                 status = "disabled";
 604         };
 605
 606         pwm0: pwm@fd8b0000 {
 607                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 608                 reg = <0x0 0xfd8b0000 0x0 0x10>;
 609                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 610                 clock-names = "pwm", "pclk";
 611                 pinctrl-0 = <&pwm0m0_pins>;
 612                 pinctrl-names = "default";
 613                 #pwm-cells = <3>;
 614                 status = "disabled";
 615         };
 616
 617         pwm1: pwm@fd8b0010 {
 618                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 619                 reg = <0x0 0xfd8b0010 0x0 0x10>;
 620                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 621                 clock-names = "pwm", "pclk";
 622                 pinctrl-0 = <&pwm1m0_pins>;
 623                 pinctrl-names = "default";
 624                 #pwm-cells = <3>;
 625                 status = "disabled";
 626         };
 627
 628         pwm2: pwm@fd8b0020 {
 629                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 630                 reg = <0x0 0xfd8b0020 0x0 0x10>;
 631                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 632                 clock-names = "pwm", "pclk";
 633                 pinctrl-0 = <&pwm2m0_pins>;
 634                 pinctrl-names = "default";
 635                 #pwm-cells = <3>;
 636                 status = "disabled";
 637         };
 638
 639         pwm3: pwm@fd8b0030 {
 640                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 641                 reg = <0x0 0xfd8b0030 0x0 0x10>;
 642                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 643                 clock-names = "pwm", "pclk";
 644                 pinctrl-0 = <&pwm3m0_pins>;
 645                 pinctrl-names = "default";
 646                 #pwm-cells = <3>;
 647                 status = "disabled";
 648         };
 649
 650         pmu: power-management@fd8d8000 {
 651                 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
 652                 reg = <0x0 0xfd8d8000 0x0 0x400>;
 653
 654                 power: power-controller {
 655                         compatible = "rockchip,rk3588-power-controller";
 656                         #address-cells = <1>;
 657                         #power-domain-cells = <1>;
 658                         #size-cells = <0>;
 659                         status = "okay";
 660
 661                         /* These power domains are grouped by VD_NPU */
 662                         power-domain@RK3588_PD_NPU {
 663                                 reg = <RK3588_PD_NPU>;
 664                                 #power-domain-cells = <0>;
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667
 668                                 power-domain@RK3588_PD_NPUTOP {
 669                                         reg = <RK3588_PD_NPUTOP>;
 670                                         clocks = <&cru HCLK_NPU_ROOT>,
 671                                                  <&cru PCLK_NPU_ROOT>,
 672                                                  <&cru CLK_NPU_DSU0>,
 673                                                  <&cru HCLK_NPU_CM0_ROOT>;
 674                                         pm_qos = <&qos_npu0_mwr>,
 675                                                  <&qos_npu0_mro>,
 676                                                  <&qos_mcu_npu>;
 677                                         #power-domain-cells = <0>;
 678                                         #address-cells = <1>;
 679                                         #size-cells = <0>;
 680
 681                                         power-domain@RK3588_PD_NPU1 {
 682                                                 reg = <RK3588_PD_NPU1>;
 683                                                 clocks = <&cru HCLK_NPU_ROOT>,
 684                                                          <&cru PCLK_NPU_ROOT>,
 685                                                          <&cru CLK_NPU_DSU0>;
 686                                                 pm_qos = <&qos_npu1>;
 687                                                 #power-domain-cells = <0>;
 688                                         };
 689                                         power-domain@RK3588_PD_NPU2 {
 690                                                 reg = <RK3588_PD_NPU2>;
 691                                                 clocks = <&cru HCLK_NPU_ROOT>,
 692                                                          <&cru PCLK_NPU_ROOT>,
 693                                                          <&cru CLK_NPU_DSU0>;
 694                                                 pm_qos = <&qos_npu2>;
 695                                                 #power-domain-cells = <0>;
 696                                         };
 697                                 };
 698                         };
 699                         /* These power domains are grouped by VD_GPU */
 700                         power-domain@RK3588_PD_GPU {
 701                                 reg = <RK3588_PD_GPU>;
 702                                 clocks = <&cru CLK_GPU>,
 703                                          <&cru CLK_GPU_COREGROUP>,
 704                                          <&cru CLK_GPU_STACKS>;
 705                                 pm_qos = <&qos_gpu_m0>,
 706                                          <&qos_gpu_m1>,
 707                                          <&qos_gpu_m2>,
 708                                          <&qos_gpu_m3>;
 709                                 #power-domain-cells = <0>;
 710                         };
 711                         /* These power domains are grouped by VD_VCODEC */
 712                         power-domain@RK3588_PD_VCODEC {
 713                                 reg = <RK3588_PD_VCODEC>;
 714                                 #address-cells = <1>;
 715                                 #size-cells = <0>;
 716                                 #power-domain-cells = <0>;
 717
 718                                 power-domain@RK3588_PD_RKVDEC0 {
 719                                         reg = <RK3588_PD_RKVDEC0>;
 720                                         clocks = <&cru HCLK_RKVDEC0>,
 721                                                  <&cru HCLK_VDPU_ROOT>,
 722                                                  <&cru ACLK_VDPU_ROOT>,
 723                                                  <&cru ACLK_RKVDEC0>,
 724                                                  <&cru ACLK_RKVDEC_CCU>;
 725                                         pm_qos = <&qos_rkvdec0>;
 726                                         #power-domain-cells = <0>;
 727                                 };
 728                                 power-domain@RK3588_PD_RKVDEC1 {
 729                                         reg = <RK3588_PD_RKVDEC1>;
 730                                         clocks = <&cru HCLK_RKVDEC1>,
 731                                                  <&cru HCLK_VDPU_ROOT>,
 732                                                  <&cru ACLK_VDPU_ROOT>,
 733                                                  <&cru ACLK_RKVDEC1>;
 734                                         pm_qos = <&qos_rkvdec1>;
 735                                         #power-domain-cells = <0>;
 736                                 };
 737                                 power-domain@RK3588_PD_VENC0 {
 738                                         reg = <RK3588_PD_VENC0>;
 739                                         clocks = <&cru HCLK_RKVENC0>,
 740                                                  <&cru ACLK_RKVENC0>;
 741                                         pm_qos = <&qos_rkvenc0_m0ro>,
 742                                                  <&qos_rkvenc0_m1ro>,
 743                                                  <&qos_rkvenc0_m2wo>;
 744                                         #address-cells = <1>;
 745                                         #size-cells = <0>;
 746                                         #power-domain-cells = <0>;
 747
 748                                         power-domain@RK3588_PD_VENC1 {
 749                                                 reg = <RK3588_PD_VENC1>;
 750                                                 clocks = <&cru HCLK_RKVENC1>,
 751                                                          <&cru HCLK_RKVENC0>,
 752                                                          <&cru ACLK_RKVENC0>,
 753                                                          <&cru ACLK_RKVENC1>;
 754                                                 pm_qos = <&qos_rkvenc1_m0ro>,
 755                                                          <&qos_rkvenc1_m1ro>,
 756                                                          <&qos_rkvenc1_m2wo>;
 757                                                 #power-domain-cells = <0>;
 758                                         };
 759                                 };
 760                         };
 761                         /* These power domains are grouped by VD_LOGIC */
 762                         power-domain@RK3588_PD_VDPU {
 763                                 reg = <RK3588_PD_VDPU>;
 764                                 clocks = <&cru HCLK_VDPU_ROOT>,
 765                                          <&cru ACLK_VDPU_LOW_ROOT>,
 766                                          <&cru ACLK_VDPU_ROOT>,
 767                                          <&cru ACLK_JPEG_DECODER_ROOT>,
 768                                          <&cru ACLK_IEP2P0>,
 769                                          <&cru HCLK_IEP2P0>,
 770                                          <&cru ACLK_JPEG_ENCODER0>,
 771                                          <&cru HCLK_JPEG_ENCODER0>,
 772                                          <&cru ACLK_JPEG_ENCODER1>,
 773                                          <&cru HCLK_JPEG_ENCODER1>,
 774                                          <&cru ACLK_JPEG_ENCODER2>,
 775                                          <&cru HCLK_JPEG_ENCODER2>,
 776                                          <&cru ACLK_JPEG_ENCODER3>,
 777                                          <&cru HCLK_JPEG_ENCODER3>,
 778                                          <&cru ACLK_JPEG_DECODER>,
 779                                          <&cru HCLK_JPEG_DECODER>,
 780                                          <&cru ACLK_RGA2>,
 781                                          <&cru HCLK_RGA2>;
 782                                 pm_qos = <&qos_iep>,
 783                                          <&qos_jpeg_dec>,
 784                                          <&qos_jpeg_enc0>,
 785                                          <&qos_jpeg_enc1>,
 786                                          <&qos_jpeg_enc2>,
 787                                          <&qos_jpeg_enc3>,
 788                                          <&qos_rga2_mro>,
 789                                          <&qos_rga2_mwo>;
 790                                 #address-cells = <1>;
 791                                 #size-cells = <0>;
 792                                 #power-domain-cells = <0>;
 793
 794
 795                                 power-domain@RK3588_PD_AV1 {
 796                                         reg = <RK3588_PD_AV1>;
 797                                         clocks = <&cru PCLK_AV1>,
 798                                                  <&cru ACLK_AV1>,
 799                                                  <&cru HCLK_VDPU_ROOT>;
 800                                         pm_qos = <&qos_av1>;
 801                                         #power-domain-cells = <0>;
 802                                 };
 803                                 power-domain@RK3588_PD_RKVDEC0 {
 804                                         reg = <RK3588_PD_RKVDEC0>;
 805                                         clocks = <&cru HCLK_RKVDEC0>,
 806                                                  <&cru HCLK_VDPU_ROOT>,
 807                                                  <&cru ACLK_VDPU_ROOT>,
 808                                                  <&cru ACLK_RKVDEC0>;
 809                                         pm_qos = <&qos_rkvdec0>;
 810                                         #power-domain-cells = <0>;
 811                                 };
 812                                 power-domain@RK3588_PD_RKVDEC1 {
 813                                         reg = <RK3588_PD_RKVDEC1>;
 814                                         clocks = <&cru HCLK_RKVDEC1>,
 815                                                  <&cru HCLK_VDPU_ROOT>,
 816                                                  <&cru ACLK_VDPU_ROOT>;
 817                                         pm_qos = <&qos_rkvdec1>;
 818                                         #power-domain-cells = <0>;
 819                                 };
 820                                 power-domain@RK3588_PD_RGA30 {
 821                                         reg = <RK3588_PD_RGA30>;
 822                                         clocks = <&cru ACLK_RGA3_0>,
 823                                                  <&cru HCLK_RGA3_0>;
 824                                         pm_qos = <&qos_rga3_0>;
 825                                         #power-domain-cells = <0>;
 826                                 };
 827                         };
 828                         power-domain@RK3588_PD_VOP {
 829                                 reg = <RK3588_PD_VOP>;
 830                                 clocks = <&cru PCLK_VOP_ROOT>,
 831                                          <&cru HCLK_VOP_ROOT>,
 832                                          <&cru ACLK_VOP>;
 833                                 pm_qos = <&qos_vop_m0>,
 834                                          <&qos_vop_m1>;
 835                                 #address-cells = <1>;
 836                                 #size-cells = <0>;
 837                                 #power-domain-cells = <0>;
 838
 839                                 power-domain@RK3588_PD_VO0 {
 840                                         reg = <RK3588_PD_VO0>;
 841                                         clocks = <&cru PCLK_VO0_ROOT>,
 842                                                  <&cru PCLK_VO0_S_ROOT>,
 843                                                  <&cru HCLK_VO0_S_ROOT>,
 844                                                  <&cru ACLK_VO0_ROOT>,
 845                                                  <&cru HCLK_HDCP0>,
 846                                                  <&cru ACLK_HDCP0>,
 847                                                  <&cru HCLK_VOP_ROOT>;
 848                                         pm_qos = <&qos_hdcp0>;
 849                                         #power-domain-cells = <0>;
 850                                 };
 851                         };
 852                         power-domain@RK3588_PD_VO1 {
 853                                 reg = <RK3588_PD_VO1>;
 854                                 clocks = <&cru PCLK_VO1_ROOT>,
 855                                          <&cru PCLK_VO1_S_ROOT>,
 856                                          <&cru HCLK_VO1_S_ROOT>,
 857                                          <&cru HCLK_HDCP1>,
 858                                          <&cru ACLK_HDCP1>,
 859                                          <&cru ACLK_HDMIRX_ROOT>,
 860                                          <&cru HCLK_VO1USB_TOP_ROOT>;
 861                                 pm_qos = <&qos_hdcp1>,
 862                                          <&qos_hdmirx>;
 863                                 #power-domain-cells = <0>;
 864                         };
 865                         power-domain@RK3588_PD_VI {
 866                                 reg = <RK3588_PD_VI>;
 867                                 clocks = <&cru HCLK_VI_ROOT>,
 868                                          <&cru PCLK_VI_ROOT>,
 869                                          <&cru HCLK_ISP0>,
 870                                          <&cru ACLK_ISP0>,
 871                                          <&cru HCLK_VICAP>,
 872                                          <&cru ACLK_VICAP>;
 873                                 pm_qos = <&qos_isp0_mro>,
 874                                          <&qos_isp0_mwo>,
 875                                          <&qos_vicap_m0>,
 876                                          <&qos_vicap_m1>;
 877                                 #address-cells = <1>;
 878                                 #size-cells = <0>;
 879                                 #power-domain-cells = <0>;
 880
 881                                 power-domain@RK3588_PD_ISP1 {
 882                                         reg = <RK3588_PD_ISP1>;
 883                                         clocks = <&cru HCLK_ISP1>,
 884                                                  <&cru ACLK_ISP1>,
 885                                                  <&cru HCLK_VI_ROOT>,
 886                                                  <&cru PCLK_VI_ROOT>;
 887                                         pm_qos = <&qos_isp1_mwo>,
 888                                                  <&qos_isp1_mro>;
 889                                         #power-domain-cells = <0>;
 890                                 };
 891                                 power-domain@RK3588_PD_FEC {
 892                                         reg = <RK3588_PD_FEC>;
 893                                         clocks = <&cru HCLK_FISHEYE0>,
 894                                                  <&cru ACLK_FISHEYE0>,
 895                                                  <&cru HCLK_FISHEYE1>,
 896                                                  <&cru ACLK_FISHEYE1>,
 897                                                  <&cru PCLK_VI_ROOT>;
 898                                         pm_qos = <&qos_fisheye0>,
 899                                                  <&qos_fisheye1>;
 900                                         #power-domain-cells = <0>;
 901                                 };
 902                         };
 903                         power-domain@RK3588_PD_RGA31 {
 904                                 reg = <RK3588_PD_RGA31>;
 905                                 clocks = <&cru HCLK_RGA3_1>,
 906                                          <&cru ACLK_RGA3_1>;
 907                                 pm_qos = <&qos_rga3_1>;
 908                                 #power-domain-cells = <0>;
 909                         };
 910                         power-domain@RK3588_PD_USB {
 911                                 reg = <RK3588_PD_USB>;
 912                                 clocks = <&cru PCLK_PHP_ROOT>,
 913                                          <&cru ACLK_USB_ROOT>,
 914                                          <&cru HCLK_USB_ROOT>,
 915                                          <&cru HCLK_HOST0>,
 916                                          <&cru HCLK_HOST_ARB0>,
 917                                          <&cru HCLK_HOST1>,
 918                                          <&cru HCLK_HOST_ARB1>;
 919                                 pm_qos = <&qos_usb3_0>,
 920                                          <&qos_usb3_1>,
 921                                          <&qos_usb2host_0>,
 922                                          <&qos_usb2host_1>;
 923                                 #power-domain-cells = <0>;
 924                         };
 925                         power-domain@RK3588_PD_GMAC {
 926                                 reg = <RK3588_PD_GMAC>;
 927                                 clocks = <&cru PCLK_PHP_ROOT>,
 928                                          <&cru ACLK_PCIE_ROOT>,
 929                                          <&cru ACLK_PHP_ROOT>;
 930                                 #power-domain-cells = <0>;
 931                         };
 932                         power-domain@RK3588_PD_PCIE {
 933                                 reg = <RK3588_PD_PCIE>;
 934                                 clocks = <&cru PCLK_PHP_ROOT>,
 935                                          <&cru ACLK_PCIE_ROOT>,
 936                                          <&cru ACLK_PHP_ROOT>;
 937                                 #power-domain-cells = <0>;
 938                         };
 939                         power-domain@RK3588_PD_SDIO {
 940                                 reg = <RK3588_PD_SDIO>;
 941                                 clocks = <&cru HCLK_SDIO>,
 942                                          <&cru HCLK_NVM_ROOT>;
 943                                 pm_qos = <&qos_sdio>;
 944                                 #power-domain-cells = <0>;
 945                         };
 946                         power-domain@RK3588_PD_AUDIO {
 947                                 reg = <RK3588_PD_AUDIO>;
 948                                 clocks = <&cru HCLK_AUDIO_ROOT>,
 949                                          <&cru PCLK_AUDIO_ROOT>;
 950                                 #power-domain-cells = <0>;
 951                         };
 952                         power-domain@RK3588_PD_SDMMC {
 953                                 reg = <RK3588_PD_SDMMC>;
 954                                 pm_qos = <&qos_sdmmc>;
 955                                 #power-domain-cells = <0>;
 956                         };
 957                 };
 958         };
 959
 960         i2s4_8ch: i2s@fddc0000 {
 961                 compatible = "rockchip,rk3588-i2s-tdm";
 962                 reg = <0x0 0xfddc0000 0x0 0x1000>;
 963                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
 964                 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
 965                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 966                 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
 967                 assigned-clock-parents = <&cru PLL_AUPLL>;
 968                 dmas = <&dmac2 0>;
 969                 dma-names = "tx";
 970                 power-domains = <&power RK3588_PD_VO0>;
 971                 resets = <&cru SRST_M_I2S4_8CH_TX>;
 972                 reset-names = "tx-m";
 973                 #sound-dai-cells = <0>;
 974                 status = "disabled";
 975         };
 976
 977         i2s5_8ch: i2s@fddf0000 {
 978                 compatible = "rockchip,rk3588-i2s-tdm";
 979                 reg = <0x0 0xfddf0000 0x0 0x1000>;
 980                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
 981                 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
 982                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 983                 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
 984                 assigned-clock-parents = <&cru PLL_AUPLL>;
 985                 dmas = <&dmac2 2>;
 986                 dma-names = "tx";
 987                 power-domains = <&power RK3588_PD_VO1>;
 988                 resets = <&cru SRST_M_I2S5_8CH_TX>;
 989                 reset-names = "tx-m";
 990                 #sound-dai-cells = <0>;
 991                 status = "disabled";
 992         };
 993
 994         i2s9_8ch: i2s@fddfc000 {
 995                 compatible = "rockchip,rk3588-i2s-tdm";
 996                 reg = <0x0 0xfddfc000 0x0 0x1000>;
 997                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
 998                 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
 999                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1000                 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1001                 assigned-clock-parents = <&cru PLL_AUPLL>;
1002                 dmas = <&dmac2 23>;
1003                 dma-names = "rx";
1004                 power-domains = <&power RK3588_PD_VO1>;
1005                 resets = <&cru SRST_M_I2S9_8CH_RX>;
1006                 reset-names = "rx-m";
1007                 #sound-dai-cells = <0>;
1008                 status = "disabled";
1009         };
1010
1011         qos_gpu_m0: qos@fdf35000 {
1012                 compatible = "rockchip,rk3588-qos", "syscon";
1013                 reg = <0x0 0xfdf35000 0x0 0x20>;
1014         };
1015
1016         qos_gpu_m1: qos@fdf35200 {
1017                 compatible = "rockchip,rk3588-qos", "syscon";
1018                 reg = <0x0 0xfdf35200 0x0 0x20>;
1019         };
1020
1021         qos_gpu_m2: qos@fdf35400 {
1022                 compatible = "rockchip,rk3588-qos", "syscon";
1023                 reg = <0x0 0xfdf35400 0x0 0x20>;
1024         };
1025
1026         qos_gpu_m3: qos@fdf35600 {
1027                 compatible = "rockchip,rk3588-qos", "syscon";
1028                 reg = <0x0 0xfdf35600 0x0 0x20>;
1029         };
1030
1031         qos_rga3_1: qos@fdf36000 {
1032                 compatible = "rockchip,rk3588-qos", "syscon";
1033                 reg = <0x0 0xfdf36000 0x0 0x20>;
1034         };
1035
1036         qos_sdio: qos@fdf39000 {
1037                 compatible = "rockchip,rk3588-qos", "syscon";
1038                 reg = <0x0 0xfdf39000 0x0 0x20>;
1039         };
1040
1041         qos_sdmmc: qos@fdf3d800 {
1042                 compatible = "rockchip,rk3588-qos", "syscon";
1043                 reg = <0x0 0xfdf3d800 0x0 0x20>;
1044         };
1045
1046         qos_usb3_1: qos@fdf3e000 {
1047                 compatible = "rockchip,rk3588-qos", "syscon";
1048                 reg = <0x0 0xfdf3e000 0x0 0x20>;
1049         };
1050
1051         qos_usb3_0: qos@fdf3e200 {
1052                 compatible = "rockchip,rk3588-qos", "syscon";
1053                 reg = <0x0 0xfdf3e200 0x0 0x20>;
1054         };
1055
1056         qos_usb2host_0: qos@fdf3e400 {
1057                 compatible = "rockchip,rk3588-qos", "syscon";
1058                 reg = <0x0 0xfdf3e400 0x0 0x20>;
1059         };
1060
1061         qos_usb2host_1: qos@fdf3e600 {
1062                 compatible = "rockchip,rk3588-qos", "syscon";
1063                 reg = <0x0 0xfdf3e600 0x0 0x20>;
1064         };
1065
1066         qos_fisheye0: qos@fdf40000 {
1067                 compatible = "rockchip,rk3588-qos", "syscon";
1068                 reg = <0x0 0xfdf40000 0x0 0x20>;
1069         };
1070
1071         qos_fisheye1: qos@fdf40200 {
1072                 compatible = "rockchip,rk3588-qos", "syscon";
1073                 reg = <0x0 0xfdf40200 0x0 0x20>;
1074         };
1075
1076         qos_isp0_mro: qos@fdf40400 {
1077                 compatible = "rockchip,rk3588-qos", "syscon";
1078                 reg = <0x0 0xfdf40400 0x0 0x20>;
1079         };
1080
1081         qos_isp0_mwo: qos@fdf40500 {
1082                 compatible = "rockchip,rk3588-qos", "syscon";
1083                 reg = <0x0 0xfdf40500 0x0 0x20>;
1084         };
1085
1086         qos_vicap_m0: qos@fdf40600 {
1087                 compatible = "rockchip,rk3588-qos", "syscon";
1088                 reg = <0x0 0xfdf40600 0x0 0x20>;
1089         };
1090
1091         qos_vicap_m1: qos@fdf40800 {
1092                 compatible = "rockchip,rk3588-qos", "syscon";
1093                 reg = <0x0 0xfdf40800 0x0 0x20>;
1094         };
1095
1096         qos_isp1_mwo: qos@fdf41000 {
1097                 compatible = "rockchip,rk3588-qos", "syscon";
1098                 reg = <0x0 0xfdf41000 0x0 0x20>;
1099         };
1100
1101         qos_isp1_mro: qos@fdf41100 {
1102                 compatible = "rockchip,rk3588-qos", "syscon";
1103                 reg = <0x0 0xfdf41100 0x0 0x20>;
1104         };
1105
1106         qos_rkvenc0_m0ro: qos@fdf60000 {
1107                 compatible = "rockchip,rk3588-qos", "syscon";
1108                 reg = <0x0 0xfdf60000 0x0 0x20>;
1109         };
1110
1111         qos_rkvenc0_m1ro: qos@fdf60200 {
1112                 compatible = "rockchip,rk3588-qos", "syscon";
1113                 reg = <0x0 0xfdf60200 0x0 0x20>;
1114         };
1115
1116         qos_rkvenc0_m2wo: qos@fdf60400 {
1117                 compatible = "rockchip,rk3588-qos", "syscon";
1118                 reg = <0x0 0xfdf60400 0x0 0x20>;
1119         };
1120
1121         qos_rkvenc1_m0ro: qos@fdf61000 {
1122                 compatible = "rockchip,rk3588-qos", "syscon";
1123                 reg = <0x0 0xfdf61000 0x0 0x20>;
1124         };
1125
1126         qos_rkvenc1_m1ro: qos@fdf61200 {
1127                 compatible = "rockchip,rk3588-qos", "syscon";
1128                 reg = <0x0 0xfdf61200 0x0 0x20>;
1129         };
1130
1131         qos_rkvenc1_m2wo: qos@fdf61400 {
1132                 compatible = "rockchip,rk3588-qos", "syscon";
1133                 reg = <0x0 0xfdf61400 0x0 0x20>;
1134         };
1135
1136         qos_rkvdec0: qos@fdf62000 {
1137                 compatible = "rockchip,rk3588-qos", "syscon";
1138                 reg = <0x0 0xfdf62000 0x0 0x20>;
1139         };
1140
1141         qos_rkvdec1: qos@fdf63000 {
1142                 compatible = "rockchip,rk3588-qos", "syscon";
1143                 reg = <0x0 0xfdf63000 0x0 0x20>;
1144         };
1145
1146         qos_av1: qos@fdf64000 {
1147                 compatible = "rockchip,rk3588-qos", "syscon";
1148                 reg = <0x0 0xfdf64000 0x0 0x20>;
1149         };
1150
1151         qos_iep: qos@fdf66000 {
1152                 compatible = "rockchip,rk3588-qos", "syscon";
1153                 reg = <0x0 0xfdf66000 0x0 0x20>;
1154         };
1155
1156         qos_jpeg_dec: qos@fdf66200 {
1157                 compatible = "rockchip,rk3588-qos", "syscon";
1158                 reg = <0x0 0xfdf66200 0x0 0x20>;
1159         };
1160
1161         qos_jpeg_enc0: qos@fdf66400 {
1162                 compatible = "rockchip,rk3588-qos", "syscon";
1163                 reg = <0x0 0xfdf66400 0x0 0x20>;
1164         };
1165
1166         qos_jpeg_enc1: qos@fdf66600 {
1167                 compatible = "rockchip,rk3588-qos", "syscon";
1168                 reg = <0x0 0xfdf66600 0x0 0x20>;
1169         };
1170
1171         qos_jpeg_enc2: qos@fdf66800 {
1172                 compatible = "rockchip,rk3588-qos", "syscon";
1173                 reg = <0x0 0xfdf66800 0x0 0x20>;
1174         };
1175
1176         qos_jpeg_enc3: qos@fdf66a00 {
1177                 compatible = "rockchip,rk3588-qos", "syscon";
1178                 reg = <0x0 0xfdf66a00 0x0 0x20>;
1179         };
1180
1181         qos_rga2_mro: qos@fdf66c00 {
1182                 compatible = "rockchip,rk3588-qos", "syscon";
1183                 reg = <0x0 0xfdf66c00 0x0 0x20>;
1184         };
1185
1186         qos_rga2_mwo: qos@fdf66e00 {
1187                 compatible = "rockchip,rk3588-qos", "syscon";
1188                 reg = <0x0 0xfdf66e00 0x0 0x20>;
1189         };
1190
1191         qos_rga3_0: qos@fdf67000 {
1192                 compatible = "rockchip,rk3588-qos", "syscon";
1193                 reg = <0x0 0xfdf67000 0x0 0x20>;
1194         };
1195
1196         qos_vdpu: qos@fdf67200 {
1197                 compatible = "rockchip,rk3588-qos", "syscon";
1198                 reg = <0x0 0xfdf67200 0x0 0x20>;
1199         };
1200
1201         qos_npu1: qos@fdf70000 {
1202                 compatible = "rockchip,rk3588-qos", "syscon";
1203                 reg = <0x0 0xfdf70000 0x0 0x20>;
1204         };
1205
1206         qos_npu2: qos@fdf71000 {
1207                 compatible = "rockchip,rk3588-qos", "syscon";
1208                 reg = <0x0 0xfdf71000 0x0 0x20>;
1209         };
1210
1211         qos_npu0_mwr: qos@fdf72000 {
1212                 compatible = "rockchip,rk3588-qos", "syscon";
1213                 reg = <0x0 0xfdf72000 0x0 0x20>;
1214         };
1215
1216         qos_npu0_mro: qos@fdf72200 {
1217                 compatible = "rockchip,rk3588-qos", "syscon";
1218                 reg = <0x0 0xfdf72200 0x0 0x20>;
1219         };
1220
1221         qos_mcu_npu: qos@fdf72400 {
1222                 compatible = "rockchip,rk3588-qos", "syscon";
1223                 reg = <0x0 0xfdf72400 0x0 0x20>;
1224         };
1225
1226         qos_hdcp0: qos@fdf80000 {
1227                 compatible = "rockchip,rk3588-qos", "syscon";
1228                 reg = <0x0 0xfdf80000 0x0 0x20>;
1229         };
1230
1231         qos_hdcp1: qos@fdf81000 {
1232                 compatible = "rockchip,rk3588-qos", "syscon";
1233                 reg = <0x0 0xfdf81000 0x0 0x20>;
1234         };
1235
1236         qos_hdmirx: qos@fdf81200 {
1237                 compatible = "rockchip,rk3588-qos", "syscon";
1238                 reg = <0x0 0xfdf81200 0x0 0x20>;
1239         };
1240
1241         qos_vop_m0: qos@fdf82000 {
1242                 compatible = "rockchip,rk3588-qos", "syscon";
1243                 reg = <0x0 0xfdf82000 0x0 0x20>;
1244         };
1245
1246         qos_vop_m1: qos@fdf82200 {
1247                 compatible = "rockchip,rk3588-qos", "syscon";
1248                 reg = <0x0 0xfdf82200 0x0 0x20>;
1249         };
1250
1251         pcie2x1l1: pcie@fe180000 {
1252                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1253                 bus-range = <0x30 0x3f>;
1254                 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1255                          <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1256                          <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1257                 clock-names = "aclk_mst", "aclk_slv",
1258                               "aclk_dbi", "pclk",
1259                               "aux", "pipe";
1260                 device_type = "pci";
1261                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1262                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1263                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1264                              <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1265                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1266                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1267                 #interrupt-cells = <1>;
1268                 interrupt-map-mask = <0 0 0 7>;
1269                 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1270                                 <0 0 0 2 &pcie2x1l1_intc 1>,
1271                                 <0 0 0 3 &pcie2x1l1_intc 2>,
1272                                 <0 0 0 4 &pcie2x1l1_intc 3>;
1273                 linux,pci-domain = <3>;
1274                 max-link-speed = <2>;
1275                 msi-map = <0x3000 &its0 0x3000 0x1000>;
1276                 num-lanes = <1>;
1277                 phys = <&combphy2_psu PHY_TYPE_PCIE>;
1278                 phy-names = "pcie-phy";
1279                 power-domains = <&power RK3588_PD_PCIE>;
1280                 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1281                          <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1282                          <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1283                 reg = <0xa 0x40c00000 0x0 0x00400000>,
1284                       <0x0 0xfe180000 0x0 0x00010000>,
1285                       <0x0 0xf3000000 0x0 0x00100000>;
1286                 reg-names = "dbi", "apb", "config";
1287                 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1288                 reset-names = "pwr", "pipe";
1289                 #address-cells = <3>;
1290                 #size-cells = <2>;
1291                 status = "disabled";
1292
1293                 pcie2x1l1_intc: legacy-interrupt-controller {
1294                         interrupt-controller;
1295                         #address-cells = <0>;
1296                         #interrupt-cells = <1>;
1297                         interrupt-parent = <&gic>;
1298                         interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1299                 };
1300         };
1301
1302         pcie2x1l2: pcie@fe190000 {
1303                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1304                 bus-range = <0x40 0x4f>;
1305                 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1306                          <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1307                          <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1308                 clock-names = "aclk_mst", "aclk_slv",
1309                               "aclk_dbi", "pclk",
1310                               "aux", "pipe";
1311                 device_type = "pci";
1312                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1313                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1314                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1315                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1316                              <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1317                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1318                 #interrupt-cells = <1>;
1319                 interrupt-map-mask = <0 0 0 7>;
1320                 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1321                                 <0 0 0 2 &pcie2x1l2_intc 1>,
1322                                 <0 0 0 3 &pcie2x1l2_intc 2>,
1323                                 <0 0 0 4 &pcie2x1l2_intc 3>;
1324                 linux,pci-domain = <4>;
1325                 max-link-speed = <2>;
1326                 msi-map = <0x4000 &its0 0x4000 0x1000>;
1327                 num-lanes = <1>;
1328                 phys = <&combphy0_ps PHY_TYPE_PCIE>;
1329                 phy-names = "pcie-phy";
1330                 power-domains = <&power RK3588_PD_PCIE>;
1331                 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1332                          <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1333                          <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1334                 reg = <0xa 0x41000000 0x0 0x00400000>,
1335                       <0x0 0xfe190000 0x0 0x00010000>,
1336                       <0x0 0xf4000000 0x0 0x00100000>;
1337                 reg-names = "dbi", "apb", "config";
1338                 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1339                 reset-names = "pwr", "pipe";
1340                 #address-cells = <3>;
1341                 #size-cells = <2>;
1342                 status = "disabled";
1343
1344                 pcie2x1l2_intc: legacy-interrupt-controller {
1345                         interrupt-controller;
1346                         #address-cells = <0>;
1347                         #interrupt-cells = <1>;
1348                         interrupt-parent = <&gic>;
1349                         interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1350                 };
1351         };
1352
1353         gmac1: ethernet@fe1c0000 {
1354                 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1355                 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1356                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1357                              <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1358                 interrupt-names = "macirq", "eth_wake_irq";
1359                 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1360                          <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1361                          <&cru CLK_GMAC1_PTP_REF>;
1362                 clock-names = "stmmaceth", "clk_mac_ref",
1363                               "pclk_mac", "aclk_mac",
1364                               "ptp_ref";
1365                 power-domains = <&power RK3588_PD_GMAC>;
1366                 resets = <&cru SRST_A_GMAC1>;
1367                 reset-names = "stmmaceth";
1368                 rockchip,grf = <&sys_grf>;
1369                 rockchip,php-grf = <&php_grf>;
1370                 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1371                 snps,mixed-burst;
1372                 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1373                 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1374                 snps,tso;
1375                 status = "disabled";
1376
1377                 mdio1: mdio {
1378                         compatible = "snps,dwmac-mdio";
1379                         #address-cells = <0x1>;
1380                         #size-cells = <0x0>;
1381                 };
1382
1383                 gmac1_stmmac_axi_setup: stmmac-axi-config {
1384                         snps,blen = <0 0 0 0 16 8 4>;
1385                         snps,wr_osr_lmt = <4>;
1386                         snps,rd_osr_lmt = <8>;
1387                 };
1388
1389                 gmac1_mtl_rx_setup: rx-queues-config {
1390                         snps,rx-queues-to-use = <2>;
1391                         queue0 {};
1392                         queue1 {};
1393                 };
1394
1395                 gmac1_mtl_tx_setup: tx-queues-config {
1396                         snps,tx-queues-to-use = <2>;
1397                         queue0 {};
1398                         queue1 {};
1399                 };
1400         };
1401
1402         sata0: sata@fe210000 {
1403                 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1404                 reg = <0 0xfe210000 0 0x1000>;
1405                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1406                 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1407                          <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1408                          <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1409                 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1410                 ports-implemented = <0x1>;
1411                 #address-cells = <1>;
1412                 #size-cells = <0>;
1413                 status = "disabled";
1414
1415                 sata-port@0 {
1416                         reg = <0>;
1417                         hba-port-cap = <HBA_PORT_FBSCP>;
1418                         phys = <&combphy0_ps PHY_TYPE_SATA>;
1419                         phy-names = "sata-phy";
1420                         snps,rx-ts-max = <32>;
1421                         snps,tx-ts-max = <32>;
1422                 };
1423         };
1424
1425         sata2: sata@fe230000 {
1426                 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1427                 reg = <0 0xfe230000 0 0x1000>;
1428                 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1429                 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1430                          <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1431                          <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1432                 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1433                 ports-implemented = <0x1>;
1434                 #address-cells = <1>;
1435                 #size-cells = <0>;
1436                 status = "disabled";
1437
1438                 sata-port@0 {
1439                         reg = <0>;
1440                         hba-port-cap = <HBA_PORT_FBSCP>;
1441                         phys = <&combphy2_psu PHY_TYPE_SATA>;
1442                         phy-names = "sata-phy";
1443                         snps,rx-ts-max = <32>;
1444                         snps,tx-ts-max = <32>;
1445                 };
1446         };
1447
1448         sdmmc: mmc@fe2c0000 {
1449                 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1450                 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1451                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1452                 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1453                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1454                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1455                 fifo-depth = <0x100>;
1456                 max-frequency = <200000000>;
1457                 pinctrl-names = "default";
1458                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1459                 power-domains = <&power RK3588_PD_SDMMC>;
1460                 status = "disabled";
1461         };
1462
1463         sdio: mmc@fe2d0000 {
1464                 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1465                 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1466                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1467                 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1468                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1469                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1470                 fifo-depth = <0x100>;
1471                 max-frequency = <200000000>;
1472                 pinctrl-names = "default";
1473                 pinctrl-0 = <&sdiom1_pins>;
1474                 power-domains = <&power RK3588_PD_SDIO>;
1475                 status = "disabled";
1476         };
1477
1478         sdhci: mmc@fe2e0000 {
1479                 compatible = "rockchip,rk3588-dwcmshc";
1480                 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1481                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1482                 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1483                 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1484                 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1485                          <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1486                          <&cru TMCLK_EMMC>;
1487                 clock-names = "core", "bus", "axi", "block", "timer";
1488                 max-frequency = <200000000>;
1489                 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1490                             <&emmc_cmd>, <&emmc_data_strobe>;
1491                 pinctrl-names = "default";
1492                 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1493                          <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1494                          <&cru SRST_T_EMMC>;
1495                 reset-names = "core", "bus", "axi", "block", "timer";
1496                 status = "disabled";
1497         };
1498
1499         i2s0_8ch: i2s@fe470000 {
1500                 compatible = "rockchip,rk3588-i2s-tdm";
1501                 reg = <0x0 0xfe470000 0x0 0x1000>;
1502                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1503                 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1504                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1505                 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1506                 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1507                 dmas = <&dmac0 0>, <&dmac0 1>;
1508                 dma-names = "tx", "rx";
1509                 power-domains = <&power RK3588_PD_AUDIO>;
1510                 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1511                 reset-names = "tx-m", "rx-m";
1512                 rockchip,trcm-sync-tx-only;
1513                 pinctrl-names = "default";
1514                 pinctrl-0 = <&i2s0_lrck
1515                              &i2s0_sclk
1516                              &i2s0_sdi0
1517                              &i2s0_sdi1
1518                              &i2s0_sdi2
1519                              &i2s0_sdi3
1520                              &i2s0_sdo0
1521                              &i2s0_sdo1
1522                              &i2s0_sdo2
1523                              &i2s0_sdo3>;
1524                 #sound-dai-cells = <0>;
1525                 status = "disabled";
1526         };
1527
1528         i2s1_8ch: i2s@fe480000 {
1529                 compatible = "rockchip,rk3588-i2s-tdm";
1530                 reg = <0x0 0xfe480000 0x0 0x1000>;
1531                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1532                 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1533                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1534                 dmas = <&dmac0 2>, <&dmac0 3>;
1535                 dma-names = "tx", "rx";
1536                 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1537                 reset-names = "tx-m", "rx-m";
1538                 rockchip,trcm-sync-tx-only;
1539                 pinctrl-names = "default";
1540                 pinctrl-0 = <&i2s1m0_lrck
1541                              &i2s1m0_sclk
1542                              &i2s1m0_sdi0
1543                              &i2s1m0_sdi1
1544                              &i2s1m0_sdi2
1545                              &i2s1m0_sdi3
1546                              &i2s1m0_sdo0
1547                              &i2s1m0_sdo1
1548                              &i2s1m0_sdo2
1549                              &i2s1m0_sdo3>;
1550                 #sound-dai-cells = <0>;
1551                 status = "disabled";
1552         };
1553
1554         i2s2_2ch: i2s@fe490000 {
1555                 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1556                 reg = <0x0 0xfe490000 0x0 0x1000>;
1557                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1558                 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1559                 clock-names = "i2s_clk", "i2s_hclk";
1560                 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1561                 assigned-clock-parents = <&cru PLL_AUPLL>;
1562                 dmas = <&dmac1 0>, <&dmac1 1>;
1563                 dma-names = "tx", "rx";
1564                 power-domains = <&power RK3588_PD_AUDIO>;
1565                 rockchip,trcm-sync-tx-only;
1566                 pinctrl-names = "default";
1567                 pinctrl-0 = <&i2s2m1_lrck
1568                              &i2s2m1_sclk
1569                              &i2s2m1_sdi
1570                              &i2s2m1_sdo>;
1571                 #sound-dai-cells = <0>;
1572                 status = "disabled";
1573         };
1574
1575         i2s3_2ch: i2s@fe4a0000 {
1576                 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1577                 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1578                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1579                 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1580                 clock-names = "i2s_clk", "i2s_hclk";
1581                 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1582                 assigned-clock-parents = <&cru PLL_AUPLL>;
1583                 dmas = <&dmac1 2>, <&dmac1 3>;
1584                 dma-names = "tx", "rx";
1585                 power-domains = <&power RK3588_PD_AUDIO>;
1586                 rockchip,trcm-sync-tx-only;
1587                 pinctrl-names = "default";
1588                 pinctrl-0 = <&i2s3_lrck
1589                              &i2s3_sclk
1590                              &i2s3_sdi
1591                              &i2s3_sdo>;
1592                 #sound-dai-cells = <0>;
1593                 status = "disabled";
1594         };
1595
1596         gic: interrupt-controller@fe600000 {
1597                 compatible = "arm,gic-v3";
1598                 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1599                       <0x0 0xfe680000 0 0x100000>; /* GICR */
1600                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1601                 interrupt-controller;
1602                 mbi-alias = <0x0 0xfe610000>;
1603                 mbi-ranges = <424 56>;
1604                 msi-controller;
1605                 ranges;
1606                 #address-cells = <2>;
1607                 #interrupt-cells = <4>;
1608                 #size-cells = <2>;
1609
1610                 its0: msi-controller@fe640000 {
1611                         compatible = "arm,gic-v3-its";
1612                         reg = <0x0 0xfe640000 0x0 0x20000>;
1613                         msi-controller;
1614                         #msi-cells = <1>;
1615                 };
1616
1617                 its1: msi-controller@fe660000 {
1618                         compatible = "arm,gic-v3-its";
1619                         reg = <0x0 0xfe660000 0x0 0x20000>;
1620                         msi-controller;
1621                         #msi-cells = <1>;
1622                 };
1623
1624                 ppi-partitions {
1625                         ppi_partition0: interrupt-partition-0 {
1626                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1627                         };
1628
1629                         ppi_partition1: interrupt-partition-1 {
1630                                 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1631                         };
1632                 };
1633         };
1634
1635         dmac0: dma-controller@fea10000 {
1636                 compatible = "arm,pl330", "arm,primecell";
1637                 reg = <0x0 0xfea10000 0x0 0x4000>;
1638                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1639                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1640                 arm,pl330-periph-burst;
1641                 clocks = <&cru ACLK_DMAC0>;
1642                 clock-names = "apb_pclk";
1643                 #dma-cells = <1>;
1644         };
1645
1646         dmac1: dma-controller@fea30000 {
1647                 compatible = "arm,pl330", "arm,primecell";
1648                 reg = <0x0 0xfea30000 0x0 0x4000>;
1649                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1650                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1651                 arm,pl330-periph-burst;
1652                 clocks = <&cru ACLK_DMAC1>;
1653                 clock-names = "apb_pclk";
1654                 #dma-cells = <1>;
1655         };
1656
1657         i2c1: i2c@fea90000 {
1658                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1659                 reg = <0x0 0xfea90000 0x0 0x1000>;
1660                 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1661                 clock-names = "i2c", "pclk";
1662                 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1663                 pinctrl-0 = <&i2c1m0_xfer>;
1664                 pinctrl-names = "default";
1665                 #address-cells = <1>;
1666                 #size-cells = <0>;
1667                 status = "disabled";
1668         };
1669
1670         i2c2: i2c@feaa0000 {
1671                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1672                 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1673                 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1674                 clock-names = "i2c", "pclk";
1675                 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1676                 pinctrl-0 = <&i2c2m0_xfer>;
1677                 pinctrl-names = "default";
1678                 #address-cells = <1>;
1679                 #size-cells = <0>;
1680                 status = "disabled";
1681         };
1682
1683         i2c3: i2c@feab0000 {
1684                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1685                 reg = <0x0 0xfeab0000 0x0 0x1000>;
1686                 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1687                 clock-names = "i2c", "pclk";
1688                 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1689                 pinctrl-0 = <&i2c3m0_xfer>;
1690                 pinctrl-names = "default";
1691                 #address-cells = <1>;
1692                 #size-cells = <0>;
1693                 status = "disabled";
1694         };
1695
1696         i2c4: i2c@feac0000 {
1697                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1698                 reg = <0x0 0xfeac0000 0x0 0x1000>;
1699                 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1700                 clock-names = "i2c", "pclk";
1701                 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1702                 pinctrl-0 = <&i2c4m0_xfer>;
1703                 pinctrl-names = "default";
1704                 #address-cells = <1>;
1705                 #size-cells = <0>;
1706                 status = "disabled";
1707         };
1708
1709         i2c5: i2c@fead0000 {
1710                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1711                 reg = <0x0 0xfead0000 0x0 0x1000>;
1712                 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1713                 clock-names = "i2c", "pclk";
1714                 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1715                 pinctrl-0 = <&i2c5m0_xfer>;
1716                 pinctrl-names = "default";
1717                 #address-cells = <1>;
1718                 #size-cells = <0>;
1719                 status = "disabled";
1720         };
1721
1722         timer0: timer@feae0000 {
1723                 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1724                 reg = <0x0 0xfeae0000 0x0 0x20>;
1725                 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1726                 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1727                 clock-names = "pclk", "timer";
1728         };
1729
1730         wdt: watchdog@feaf0000 {
1731                 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1732                 reg = <0x0 0xfeaf0000 0x0 0x100>;
1733                 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1734                 clock-names = "tclk", "pclk";
1735                 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1736         };
1737
1738         spi0: spi@feb00000 {
1739                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1740                 reg = <0x0 0xfeb00000 0x0 0x1000>;
1741                 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1742                 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1743                 clock-names = "spiclk", "apb_pclk";
1744                 dmas = <&dmac0 14>, <&dmac0 15>;
1745                 dma-names = "tx", "rx";
1746                 num-cs = <2>;
1747                 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1748                 pinctrl-names = "default";
1749                 #address-cells = <1>;
1750                 #size-cells = <0>;
1751                 status = "disabled";
1752         };
1753
1754         spi1: spi@feb10000 {
1755                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1756                 reg = <0x0 0xfeb10000 0x0 0x1000>;
1757                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1758                 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1759                 clock-names = "spiclk", "apb_pclk";
1760                 dmas = <&dmac0 16>, <&dmac0 17>;
1761                 dma-names = "tx", "rx";
1762                 num-cs = <2>;
1763                 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1764                 pinctrl-names = "default";
1765                 #address-cells = <1>;
1766                 #size-cells = <0>;
1767                 status = "disabled";
1768         };
1769
1770         spi2: spi@feb20000 {
1771                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1772                 reg = <0x0 0xfeb20000 0x0 0x1000>;
1773                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1774                 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1775                 clock-names = "spiclk", "apb_pclk";
1776                 dmas = <&dmac1 15>, <&dmac1 16>;
1777                 dma-names = "tx", "rx";
1778                 num-cs = <2>;
1779                 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1780                 pinctrl-names = "default";
1781                 #address-cells = <1>;
1782                 #size-cells = <0>;
1783                 status = "disabled";
1784         };
1785
1786         spi3: spi@feb30000 {
1787                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1788                 reg = <0x0 0xfeb30000 0x0 0x1000>;
1789                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1790                 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1791                 clock-names = "spiclk", "apb_pclk";
1792                 dmas = <&dmac1 17>, <&dmac1 18>;
1793                 dma-names = "tx", "rx";
1794                 num-cs = <2>;
1795                 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1796                 pinctrl-names = "default";
1797                 #address-cells = <1>;
1798                 #size-cells = <0>;
1799                 status = "disabled";
1800         };
1801
1802         uart1: serial@feb40000 {
1803                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1804                 reg = <0x0 0xfeb40000 0x0 0x100>;
1805                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1806                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1807                 clock-names = "baudclk", "apb_pclk";
1808                 dmas = <&dmac0 8>, <&dmac0 9>;
1809                 dma-names = "tx", "rx";
1810                 pinctrl-0 = <&uart1m1_xfer>;
1811                 pinctrl-names = "default";
1812                 reg-io-width = <4>;
1813                 reg-shift = <2>;
1814                 status = "disabled";
1815         };
1816
1817         uart2: serial@feb50000 {
1818                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1819                 reg = <0x0 0xfeb50000 0x0 0x100>;
1820                 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1821                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1822                 clock-names = "baudclk", "apb_pclk";
1823                 dmas = <&dmac0 10>, <&dmac0 11>;
1824                 dma-names = "tx", "rx";
1825                 pinctrl-0 = <&uart2m1_xfer>;
1826                 pinctrl-names = "default";
1827                 reg-io-width = <4>;
1828                 reg-shift = <2>;
1829                 status = "disabled";
1830         };
1831
1832         uart3: serial@feb60000 {
1833                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1834                 reg = <0x0 0xfeb60000 0x0 0x100>;
1835                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1836                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1837                 clock-names = "baudclk", "apb_pclk";
1838                 dmas = <&dmac0 12>, <&dmac0 13>;
1839                 dma-names = "tx", "rx";
1840                 pinctrl-0 = <&uart3m1_xfer>;
1841                 pinctrl-names = "default";
1842                 reg-io-width = <4>;
1843                 reg-shift = <2>;
1844                 status = "disabled";
1845         };
1846
1847         uart4: serial@feb70000 {
1848                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1849                 reg = <0x0 0xfeb70000 0x0 0x100>;
1850                 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1851                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1852                 clock-names = "baudclk", "apb_pclk";
1853                 dmas = <&dmac1 9>, <&dmac1 10>;
1854                 dma-names = "tx", "rx";
1855                 pinctrl-0 = <&uart4m1_xfer>;
1856                 pinctrl-names = "default";
1857                 reg-io-width = <4>;
1858                 reg-shift = <2>;
1859                 status = "disabled";
1860         };
1861
1862         uart5: serial@feb80000 {
1863                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1864                 reg = <0x0 0xfeb80000 0x0 0x100>;
1865                 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1866                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1867                 clock-names = "baudclk", "apb_pclk";
1868                 dmas = <&dmac1 11>, <&dmac1 12>;
1869                 dma-names = "tx", "rx";
1870                 pinctrl-0 = <&uart5m1_xfer>;
1871                 pinctrl-names = "default";
1872                 reg-io-width = <4>;
1873                 reg-shift = <2>;
1874                 status = "disabled";
1875         };
1876
1877         uart6: serial@feb90000 {
1878                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1879                 reg = <0x0 0xfeb90000 0x0 0x100>;
1880                 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1881                 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1882                 clock-names = "baudclk", "apb_pclk";
1883                 dmas = <&dmac1 13>, <&dmac1 14>;
1884                 dma-names = "tx", "rx";
1885                 pinctrl-0 = <&uart6m1_xfer>;
1886                 pinctrl-names = "default";
1887                 reg-io-width = <4>;
1888                 reg-shift = <2>;
1889                 status = "disabled";
1890         };
1891
1892         uart7: serial@feba0000 {
1893                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1894                 reg = <0x0 0xfeba0000 0x0 0x100>;
1895                 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1896                 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1897                 clock-names = "baudclk", "apb_pclk";
1898                 dmas = <&dmac2 7>, <&dmac2 8>;
1899                 dma-names = "tx", "rx";
1900                 pinctrl-0 = <&uart7m1_xfer>;
1901                 pinctrl-names = "default";
1902                 reg-io-width = <4>;
1903                 reg-shift = <2>;
1904                 status = "disabled";
1905         };
1906
1907         uart8: serial@febb0000 {
1908                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1909                 reg = <0x0 0xfebb0000 0x0 0x100>;
1910                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1911                 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1912                 clock-names = "baudclk", "apb_pclk";
1913                 dmas = <&dmac2 9>, <&dmac2 10>;
1914                 dma-names = "tx", "rx";
1915                 pinctrl-0 = <&uart8m1_xfer>;
1916                 pinctrl-names = "default";
1917                 reg-io-width = <4>;
1918                 reg-shift = <2>;
1919                 status = "disabled";
1920         };
1921
1922         uart9: serial@febc0000 {
1923                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1924                 reg = <0x0 0xfebc0000 0x0 0x100>;
1925                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1926                 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1927                 clock-names = "baudclk", "apb_pclk";
1928                 dmas = <&dmac2 11>, <&dmac2 12>;
1929                 dma-names = "tx", "rx";
1930                 pinctrl-0 = <&uart9m1_xfer>;
1931                 pinctrl-names = "default";
1932                 reg-io-width = <4>;
1933                 reg-shift = <2>;
1934                 status = "disabled";
1935         };
1936
1937         pwm4: pwm@febd0000 {
1938                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1939                 reg = <0x0 0xfebd0000 0x0 0x10>;
1940                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1941                 clock-names = "pwm", "pclk";
1942                 pinctrl-0 = <&pwm4m0_pins>;
1943                 pinctrl-names = "default";
1944                 #pwm-cells = <3>;
1945                 status = "disabled";
1946         };
1947
1948         pwm5: pwm@febd0010 {
1949                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1950                 reg = <0x0 0xfebd0010 0x0 0x10>;
1951                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1952                 clock-names = "pwm", "pclk";
1953                 pinctrl-0 = <&pwm5m0_pins>;
1954                 pinctrl-names = "default";
1955                 #pwm-cells = <3>;
1956                 status = "disabled";
1957         };
1958
1959         pwm6: pwm@febd0020 {
1960                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1961                 reg = <0x0 0xfebd0020 0x0 0x10>;
1962                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1963                 clock-names = "pwm", "pclk";
1964                 pinctrl-0 = <&pwm6m0_pins>;
1965                 pinctrl-names = "default";
1966                 #pwm-cells = <3>;
1967                 status = "disabled";
1968         };
1969
1970         pwm7: pwm@febd0030 {
1971                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1972                 reg = <0x0 0xfebd0030 0x0 0x10>;
1973                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1974                 clock-names = "pwm", "pclk";
1975                 pinctrl-0 = <&pwm7m0_pins>;
1976                 pinctrl-names = "default";
1977                 #pwm-cells = <3>;
1978                 status = "disabled";
1979         };
1980
1981         pwm8: pwm@febe0000 {
1982                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1983                 reg = <0x0 0xfebe0000 0x0 0x10>;
1984                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1985                 clock-names = "pwm", "pclk";
1986                 pinctrl-0 = <&pwm8m0_pins>;
1987                 pinctrl-names = "default";
1988                 #pwm-cells = <3>;
1989                 status = "disabled";
1990         };
1991
1992         pwm9: pwm@febe0010 {
1993                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1994                 reg = <0x0 0xfebe0010 0x0 0x10>;
1995                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1996                 clock-names = "pwm", "pclk";
1997                 pinctrl-0 = <&pwm9m0_pins>;
1998                 pinctrl-names = "default";
1999                 #pwm-cells = <3>;
2000                 status = "disabled";
2001         };
2002
2003         pwm10: pwm@febe0020 {
2004                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2005                 reg = <0x0 0xfebe0020 0x0 0x10>;
2006                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2007                 clock-names = "pwm", "pclk";
2008                 pinctrl-0 = <&pwm10m0_pins>;
2009                 pinctrl-names = "default";
2010                 #pwm-cells = <3>;
2011                 status = "disabled";
2012         };
2013
2014         pwm11: pwm@febe0030 {
2015                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2016                 reg = <0x0 0xfebe0030 0x0 0x10>;
2017                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2018                 clock-names = "pwm", "pclk";
2019                 pinctrl-0 = <&pwm11m0_pins>;
2020                 pinctrl-names = "default";
2021                 #pwm-cells = <3>;
2022                 status = "disabled";
2023         };
2024
2025         pwm12: pwm@febf0000 {
2026                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2027                 reg = <0x0 0xfebf0000 0x0 0x10>;
2028                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2029                 clock-names = "pwm", "pclk";
2030                 pinctrl-0 = <&pwm12m0_pins>;
2031                 pinctrl-names = "default";
2032                 #pwm-cells = <3>;
2033                 status = "disabled";
2034         };
2035
2036         pwm13: pwm@febf0010 {
2037                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2038                 reg = <0x0 0xfebf0010 0x0 0x10>;
2039                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2040                 clock-names = "pwm", "pclk";
2041                 pinctrl-0 = <&pwm13m0_pins>;
2042                 pinctrl-names = "default";
2043                 #pwm-cells = <3>;
2044                 status = "disabled";
2045         };
2046
2047         pwm14: pwm@febf0020 {
2048                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2049                 reg = <0x0 0xfebf0020 0x0 0x10>;
2050                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2051                 clock-names = "pwm", "pclk";
2052                 pinctrl-0 = <&pwm14m0_pins>;
2053                 pinctrl-names = "default";
2054                 #pwm-cells = <3>;
2055                 status = "disabled";
2056         };
2057
2058         pwm15: pwm@febf0030 {
2059                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2060                 reg = <0x0 0xfebf0030 0x0 0x10>;
2061                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2062                 clock-names = "pwm", "pclk";
2063                 pinctrl-0 = <&pwm15m0_pins>;
2064                 pinctrl-names = "default";
2065                 #pwm-cells = <3>;
2066                 status = "disabled";
2067         };
2068
2069         tsadc: tsadc@fec00000 {
2070                 compatible = "rockchip,rk3588-tsadc";
2071                 reg = <0x0 0xfec00000 0x0 0x400>;
2072                 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2073                 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2074                 clock-names = "tsadc", "apb_pclk";
2075                 assigned-clocks = <&cru CLK_TSADC>;
2076                 assigned-clock-rates = <2000000>;
2077                 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2078                 reset-names = "tsadc-apb", "tsadc";
2079                 rockchip,hw-tshut-temp = <120000>;
2080                 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2081                 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2082                 pinctrl-0 = <&tsadc_gpio_func>;
2083                 pinctrl-1 = <&tsadc_shut>;
2084                 pinctrl-names = "gpio", "otpout";
2085                 #thermal-sensor-cells = <1>;
2086                 status = "disabled";
2087         };
2088
2089         saradc: adc@fec10000 {
2090                 compatible = "rockchip,rk3588-saradc";
2091                 reg = <0x0 0xfec10000 0x0 0x10000>;
2092                 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2093                 #io-channel-cells = <1>;
2094                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2095                 clock-names = "saradc", "apb_pclk";
2096                 resets = <&cru SRST_P_SARADC>;
2097                 reset-names = "saradc-apb";
2098                 status = "disabled";
2099         };
2100
2101         i2c6: i2c@fec80000 {
2102                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2103                 reg = <0x0 0xfec80000 0x0 0x1000>;
2104                 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2105                 clock-names = "i2c", "pclk";
2106                 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2107                 pinctrl-0 = <&i2c6m0_xfer>;
2108                 pinctrl-names = "default";
2109                 #address-cells = <1>;
2110                 #size-cells = <0>;
2111                 status = "disabled";
2112         };
2113
2114         i2c7: i2c@fec90000 {
2115                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2116                 reg = <0x0 0xfec90000 0x0 0x1000>;
2117                 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2118                 clock-names = "i2c", "pclk";
2119                 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2120                 pinctrl-0 = <&i2c7m0_xfer>;
2121                 pinctrl-names = "default";
2122                 #address-cells = <1>;
2123                 #size-cells = <0>;
2124                 status = "disabled";
2125         };
2126
2127         i2c8: i2c@feca0000 {
2128                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2129                 reg = <0x0 0xfeca0000 0x0 0x1000>;
2130                 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2131                 clock-names = "i2c", "pclk";
2132                 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2133                 pinctrl-0 = <&i2c8m0_xfer>;
2134                 pinctrl-names = "default";
2135                 #address-cells = <1>;
2136                 #size-cells = <0>;
2137                 status = "disabled";
2138         };
2139
2140         spi4: spi@fecb0000 {
2141                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2142                 reg = <0x0 0xfecb0000 0x0 0x1000>;
2143                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2144                 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2145                 clock-names = "spiclk", "apb_pclk";
2146                 dmas = <&dmac2 13>, <&dmac2 14>;
2147                 dma-names = "tx", "rx";
2148                 num-cs = <2>;
2149                 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2150                 pinctrl-names = "default";
2151                 #address-cells = <1>;
2152                 #size-cells = <0>;
2153                 status = "disabled";
2154         };
2155
2156         otp: efuse@fecc0000 {
2157                 compatible = "rockchip,rk3588-otp";
2158                 reg = <0x0 0xfecc0000 0x0 0x400>;
2159                 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2160                          <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2161                 clock-names = "otp", "apb_pclk", "phy", "arb";
2162                 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2163                          <&cru SRST_OTPC_ARB>;
2164                 reset-names = "otp", "apb", "arb";
2165                 #address-cells = <1>;
2166                 #size-cells = <1>;
2167
2168                 cpu_code: cpu-code@2 {
2169                         reg = <0x02 0x2>;
2170                 };
2171
2172                 otp_id: id@7 {
2173                         reg = <0x07 0x10>;
2174                 };
2175
2176                 cpub0_leakage: cpu-leakage@17 {
2177                         reg = <0x17 0x1>;
2178                 };
2179
2180                 cpub1_leakage: cpu-leakage@18 {
2181                         reg = <0x18 0x1>;
2182                 };
2183
2184                 cpul_leakage: cpu-leakage@19 {
2185                         reg = <0x19 0x1>;
2186                 };
2187
2188                 log_leakage: log-leakage@1a {
2189                         reg = <0x1a 0x1>;
2190                 };
2191
2192                 gpu_leakage: gpu-leakage@1b {
2193                         reg = <0x1b 0x1>;
2194                 };
2195
2196                 otp_cpu_version: cpu-version@1c {
2197                         reg = <0x1c 0x1>;
2198                         bits = <3 3>;
2199                 };
2200
2201                 npu_leakage: npu-leakage@28 {
2202                         reg = <0x28 0x1>;
2203                 };
2204
2205                 codec_leakage: codec-leakage@29 {
2206                         reg = <0x29 0x1>;
2207                 };
2208         };
2209
2210         dmac2: dma-controller@fed10000 {
2211                 compatible = "arm,pl330", "arm,primecell";
2212                 reg = <0x0 0xfed10000 0x0 0x4000>;
2213                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2214                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2215                 arm,pl330-periph-burst;
2216                 clocks = <&cru ACLK_DMAC2>;
2217                 clock-names = "apb_pclk";
2218                 #dma-cells = <1>;
2219         };
2220
2221         combphy0_ps: phy@fee00000 {
2222                 compatible = "rockchip,rk3588-naneng-combphy";
2223                 reg = <0x0 0xfee00000 0x0 0x100>;
2224                 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2225                          <&cru PCLK_PHP_ROOT>;
2226                 clock-names = "ref", "apb", "pipe";
2227                 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2228                 assigned-clock-rates = <100000000>;
2229                 #phy-cells = <1>;
2230                 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2231                 reset-names = "phy", "apb";
2232                 rockchip,pipe-grf = <&php_grf>;
2233                 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2234                 status = "disabled";
2235         };
2236
2237         combphy2_psu: phy@fee20000 {
2238                 compatible = "rockchip,rk3588-naneng-combphy";
2239                 reg = <0x0 0xfee20000 0x0 0x100>;
2240                 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2241                          <&cru PCLK_PHP_ROOT>;
2242                 clock-names = "ref", "apb", "pipe";
2243                 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2244                 assigned-clock-rates = <100000000>;
2245                 #phy-cells = <1>;
2246                 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2247                 reset-names = "phy", "apb";
2248                 rockchip,pipe-grf = <&php_grf>;
2249                 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2250                 status = "disabled";
2251         };
2252
2253         system_sram2: sram@ff001000 {
2254                 compatible = "mmio-sram";
2255                 reg = <0x0 0xff001000 0x0 0xef000>;
2256                 ranges = <0x0 0x0 0xff001000 0xef000>;
2257                 #address-cells = <1>;
2258                 #size-cells = <1>;
2259         };
2260
2261         pinctrl: pinctrl {
2262                 compatible = "rockchip,rk3588-pinctrl";
2263                 ranges;
2264                 rockchip,grf = <&ioc>;
2265                 #address-cells = <2>;
2266                 #size-cells = <2>;
2267
2268                 gpio0: gpio@fd8a0000 {
2269                         compatible = "rockchip,gpio-bank";
2270                         reg = <0x0 0xfd8a0000 0x0 0x100>;
2271                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2272                         clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2273                         gpio-controller;
2274                         gpio-ranges = <&pinctrl 0 0 32>;
2275                         interrupt-controller;
2276                         #gpio-cells = <2>;
2277                         #interrupt-cells = <2>;
2278                 };
2279
2280                 gpio1: gpio@fec20000 {
2281                         compatible = "rockchip,gpio-bank";
2282                         reg = <0x0 0xfec20000 0x0 0x100>;
2283                         interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2284                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2285                         gpio-controller;
2286                         gpio-ranges = <&pinctrl 0 32 32>;
2287                         interrupt-controller;
2288                         #gpio-cells = <2>;
2289                         #interrupt-cells = <2>;
2290                 };
2291
2292                 gpio2: gpio@fec30000 {
2293                         compatible = "rockchip,gpio-bank";
2294                         reg = <0x0 0xfec30000 0x0 0x100>;
2295                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2296                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2297                         gpio-controller;
2298                         gpio-ranges = <&pinctrl 0 64 32>;
2299                         interrupt-controller;
2300                         #gpio-cells = <2>;
2301                         #interrupt-cells = <2>;
2302                 };
2303
2304                 gpio3: gpio@fec40000 {
2305                         compatible = "rockchip,gpio-bank";
2306                         reg = <0x0 0xfec40000 0x0 0x100>;
2307                         interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2308                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2309                         gpio-controller;
2310                         gpio-ranges = <&pinctrl 0 96 32>;
2311                         interrupt-controller;
2312                         #gpio-cells = <2>;
2313                         #interrupt-cells = <2>;
2314                 };
2315
2316                 gpio4: gpio@fec50000 {
2317                         compatible = "rockchip,gpio-bank";
2318                         reg = <0x0 0xfec50000 0x0 0x100>;
2319                         interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2320                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2321                         gpio-controller;
2322                         gpio-ranges = <&pinctrl 0 128 32>;
2323                         interrupt-controller;
2324                         #gpio-cells = <2>;
2325                         #interrupt-cells = <2>;
2326                 };
2327         };
2328 };
2329
2330 #include "rk3588s-pinctrl.dtsi"