arch/arm64/boot/dts/rockchip/rk3588s.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/power/rk3588-power.h>
  10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/ata/ahci.h>
  13
  14 / {
  15         compatible = "rockchip,rk3588";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu_l0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&cpu_l1>;
  32                                 };
  33                                 core2 {
  34                                         cpu = <&cpu_l2>;
  35                                 };
  36                                 core3 {
  37                                         cpu = <&cpu_l3>;
  38                                 };
  39                         };
  40                         cluster1 {
  41                                 core0 {
  42                                         cpu = <&cpu_b0>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&cpu_b1>;
  46                                 };
  47                         };
  48                         cluster2 {
  49                                 core0 {
  50                                         cpu = <&cpu_b2>;
  51                                 };
  52                                 core1 {
  53                                         cpu = <&cpu_b3>;
  54                                 };
  55                         };
  56                 };
  57
  58                 cpu_l0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a55";
  61                         reg = <0x0>;
  62                         enable-method = "psci";
  63                         capacity-dmips-mhz = <530>;
  64                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
  65                         assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
  66                         assigned-clock-rates = <816000000>;
  67                         cpu-idle-states = <&CPU_SLEEP>;
  68                         i-cache-size = <32768>;
  69                         i-cache-line-size = <64>;
  70                         i-cache-sets = <128>;
  71                         d-cache-size = <32768>;
  72                         d-cache-line-size = <64>;
  73                         d-cache-sets = <128>;
  74                         next-level-cache = <&l2_cache_l0>;
  75                         dynamic-power-coefficient = <228>;
  76                         #cooling-cells = <2>;
  77                 };
  78
  79                 cpu_l1: cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a55";
  82                         reg = <0x100>;
  83                         enable-method = "psci";
  84                         capacity-dmips-mhz = <530>;
  85                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
  86                         cpu-idle-states = <&CPU_SLEEP>;
  87                         i-cache-size = <32768>;
  88                         i-cache-line-size = <64>;
  89                         i-cache-sets = <128>;
  90                         d-cache-size = <32768>;
  91                         d-cache-line-size = <64>;
  92                         d-cache-sets = <128>;
  93                         next-level-cache = <&l2_cache_l1>;
  94                         dynamic-power-coefficient = <228>;
  95                         #cooling-cells = <2>;
  96                 };
  97
  98                 cpu_l2: cpu@200 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a55";
 101                         reg = <0x200>;
 102                         enable-method = "psci";
 103                         capacity-dmips-mhz = <530>;
 104                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
 105                         cpu-idle-states = <&CPU_SLEEP>;
 106                         i-cache-size = <32768>;
 107                         i-cache-line-size = <64>;
 108                         i-cache-sets = <128>;
 109                         d-cache-size = <32768>;
 110                         d-cache-line-size = <64>;
 111                         d-cache-sets = <128>;
 112                         next-level-cache = <&l2_cache_l2>;
 113                         dynamic-power-coefficient = <228>;
 114                         #cooling-cells = <2>;
 115                 };
 116
 117                 cpu_l3: cpu@300 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a55";
 120                         reg = <0x300>;
 121                         enable-method = "psci";
 122                         capacity-dmips-mhz = <530>;
 123                         clocks = <&scmi_clk SCMI_CLK_CPUL>;
 124                         cpu-idle-states = <&CPU_SLEEP>;
 125                         i-cache-size = <32768>;
 126                         i-cache-line-size = <64>;
 127                         i-cache-sets = <128>;
 128                         d-cache-size = <32768>;
 129                         d-cache-line-size = <64>;
 130                         d-cache-sets = <128>;
 131                         next-level-cache = <&l2_cache_l3>;
 132                         dynamic-power-coefficient = <228>;
 133                         #cooling-cells = <2>;
 134                 };
 135
 136                 cpu_b0: cpu@400 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a76";
 139                         reg = <0x400>;
 140                         enable-method = "psci";
 141                         capacity-dmips-mhz = <1024>;
 142                         clocks = <&scmi_clk SCMI_CLK_CPUB01>;
 143                         assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
 144                         assigned-clock-rates = <816000000>;
 145                         cpu-idle-states = <&CPU_SLEEP>;
 146                         i-cache-size = <65536>;
 147                         i-cache-line-size = <64>;
 148                         i-cache-sets = <256>;
 149                         d-cache-size = <65536>;
 150                         d-cache-line-size = <64>;
 151                         d-cache-sets = <256>;
 152                         next-level-cache = <&l2_cache_b0>;
 153                         dynamic-power-coefficient = <416>;
 154                         #cooling-cells = <2>;
 155                 };
 156
 157                 cpu_b1: cpu@500 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a76";
 160                         reg = <0x500>;
 161                         enable-method = "psci";
 162                         capacity-dmips-mhz = <1024>;
 163                         clocks = <&scmi_clk SCMI_CLK_CPUB01>;
 164                         cpu-idle-states = <&CPU_SLEEP>;
 165                         i-cache-size = <65536>;
 166                         i-cache-line-size = <64>;
 167                         i-cache-sets = <256>;
 168                         d-cache-size = <65536>;
 169                         d-cache-line-size = <64>;
 170                         d-cache-sets = <256>;
 171                         next-level-cache = <&l2_cache_b1>;
 172                         dynamic-power-coefficient = <416>;
 173                         #cooling-cells = <2>;
 174                 };
 175
 176                 cpu_b2: cpu@600 {
 177                         device_type = "cpu";
 178                         compatible = "arm,cortex-a76";
 179                         reg = <0x600>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1024>;
 182                         clocks = <&scmi_clk SCMI_CLK_CPUB23>;
 183                         assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
 184                         assigned-clock-rates = <816000000>;
 185                         cpu-idle-states = <&CPU_SLEEP>;
 186                         i-cache-size = <65536>;
 187                         i-cache-line-size = <64>;
 188                         i-cache-sets = <256>;
 189                         d-cache-size = <65536>;
 190                         d-cache-line-size = <64>;
 191                         d-cache-sets = <256>;
 192                         next-level-cache = <&l2_cache_b2>;
 193                         dynamic-power-coefficient = <416>;
 194                         #cooling-cells = <2>;
 195                 };
 196
 197                 cpu_b3: cpu@700 {
 198                         device_type = "cpu";
 199                         compatible = "arm,cortex-a76";
 200                         reg = <0x700>;
 201                         enable-method = "psci";
 202                         capacity-dmips-mhz = <1024>;
 203                         clocks = <&scmi_clk SCMI_CLK_CPUB23>;
 204                         cpu-idle-states = <&CPU_SLEEP>;
 205                         i-cache-size = <65536>;
 206                         i-cache-line-size = <64>;
 207                         i-cache-sets = <256>;
 208                         d-cache-size = <65536>;
 209                         d-cache-line-size = <64>;
 210                         d-cache-sets = <256>;
 211                         next-level-cache = <&l2_cache_b3>;
 212                         dynamic-power-coefficient = <416>;
 213                         #cooling-cells = <2>;
 214                 };
 215
 216                 idle-states {
 217                         entry-method = "psci";
 218                         CPU_SLEEP: cpu-sleep {
 219                                 compatible = "arm,idle-state";
 220                                 local-timer-stop;
 221                                 arm,psci-suspend-param = <0x0010000>;
 222                                 entry-latency-us = <100>;
 223                                 exit-latency-us = <120>;
 224                                 min-residency-us = <1000>;
 225                         };
 226                 };
 227
 228                 l2_cache_l0: l2-cache-l0 {
 229                         compatible = "cache";
 230                         cache-size = <131072>;
 231                         cache-line-size = <64>;
 232                         cache-sets = <512>;
 233                         cache-level = <2>;
 234                         cache-unified;
 235                         next-level-cache = <&l3_cache>;
 236                 };
 237
 238                 l2_cache_l1: l2-cache-l1 {
 239                         compatible = "cache";
 240                         cache-size = <131072>;
 241                         cache-line-size = <64>;
 242                         cache-sets = <512>;
 243                         cache-level = <2>;
 244                         cache-unified;
 245                         next-level-cache = <&l3_cache>;
 246                 };
 247
 248                 l2_cache_l2: l2-cache-l2 {
 249                         compatible = "cache";
 250                         cache-size = <131072>;
 251                         cache-line-size = <64>;
 252                         cache-sets = <512>;
 253                         cache-level = <2>;
 254                         cache-unified;
 255                         next-level-cache = <&l3_cache>;
 256                 };
 257
 258                 l2_cache_l3: l2-cache-l3 {
 259                         compatible = "cache";
 260                         cache-size = <131072>;
 261                         cache-line-size = <64>;
 262                         cache-sets = <512>;
 263                         cache-level = <2>;
 264                         cache-unified;
 265                         next-level-cache = <&l3_cache>;
 266                 };
 267
 268                 l2_cache_b0: l2-cache-b0 {
 269                         compatible = "cache";
 270                         cache-size = <524288>;
 271                         cache-line-size = <64>;
 272                         cache-sets = <1024>;
 273                         cache-level = <2>;
 274                         cache-unified;
 275                         next-level-cache = <&l3_cache>;
 276                 };
 277
 278                 l2_cache_b1: l2-cache-b1 {
 279                         compatible = "cache";
 280                         cache-size = <524288>;
 281                         cache-line-size = <64>;
 282                         cache-sets = <1024>;
 283                         cache-level = <2>;
 284                         cache-unified;
 285                         next-level-cache = <&l3_cache>;
 286                 };
 287
 288                 l2_cache_b2: l2-cache-b2 {
 289                         compatible = "cache";
 290                         cache-size = <524288>;
 291                         cache-line-size = <64>;
 292                         cache-sets = <1024>;
 293                         cache-level = <2>;
 294                         cache-unified;
 295                         next-level-cache = <&l3_cache>;
 296                 };
 297
 298                 l2_cache_b3: l2-cache-b3 {
 299                         compatible = "cache";
 300                         cache-size = <524288>;
 301                         cache-line-size = <64>;
 302                         cache-sets = <1024>;
 303                         cache-level = <2>;
 304                         cache-unified;
 305                         next-level-cache = <&l3_cache>;
 306                 };
 307
 308                 l3_cache: l3-cache {
 309                         compatible = "cache";
 310                         cache-size = <3145728>;
 311                         cache-line-size = <64>;
 312                         cache-sets = <4096>;
 313                         cache-level = <3>;
 314                         cache-unified;
 315                 };
 316         };
 317
 318         firmware {
 319                 optee: optee {
 320                         compatible = "linaro,optee-tz";
 321                         method = "smc";
 322                 };
 323
 324                 scmi: scmi {
 325                         compatible = "arm,scmi-smc";
 326                         arm,smc-id = <0x82000010>;
 327                         shmem = <&scmi_shmem>;
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330
 331                         scmi_clk: protocol@14 {
 332                                 reg = <0x14>;
 333                                 #clock-cells = <1>;
 334                         };
 335
 336                         scmi_reset: protocol@16 {
 337                                 reg = <0x16>;
 338                                 #reset-cells = <1>;
 339                         };
 340                 };
 341         };
 342
 343         pmu-a55 {
 344                 compatible = "arm,cortex-a55-pmu";
 345                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
 346         };
 347
 348         pmu-a76 {
 349                 compatible = "arm,cortex-a76-pmu";
 350                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
 351         };
 352
 353         psci {
 354                 compatible = "arm,psci-1.0";
 355                 method = "smc";
 356         };
 357
 358         spll: clock-0 {
 359                 compatible = "fixed-clock";
 360                 clock-frequency = <702000000>;
 361                 clock-output-names = "spll";
 362                 #clock-cells = <0>;
 363         };
 364
 365         timer {
 366                 compatible = "arm,armv8-timer";
 367                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 368                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 369                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 370                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
 371                              <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 372                 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
 373         };
 374
 375         xin24m: clock-1 {
 376                 compatible = "fixed-clock";
 377                 clock-frequency = <24000000>;
 378                 clock-output-names = "xin24m";
 379                 #clock-cells = <0>;
 380         };
 381
 382         xin32k: clock-2 {
 383                 compatible = "fixed-clock";
 384                 clock-frequency = <32768>;
 385                 clock-output-names = "xin32k";
 386                 #clock-cells = <0>;
 387         };
 388
 389         pmu_sram: sram@10f000 {
 390                 compatible = "mmio-sram";
 391                 reg = <0x0 0x0010f000 0x0 0x100>;
 392                 ranges = <0 0x0 0x0010f000 0x100>;
 393                 #address-cells = <1>;
 394                 #size-cells = <1>;
 395
 396                 scmi_shmem: sram@0 {
 397                         compatible = "arm,scmi-shmem";
 398                         reg = <0x0 0x100>;
 399                 };
 400         };
 401
 402         usb_host0_ehci: usb@fc800000 {
 403                 compatible = "rockchip,rk3588-ehci", "generic-ehci";
 404                 reg = <0x0 0xfc800000 0x0 0x40000>;
 405                 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
 406                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
 407                 phys = <&u2phy2_host>;
 408                 phy-names = "usb";
 409                 power-domains = <&power RK3588_PD_USB>;
 410                 status = "disabled";
 411         };
 412
 413         usb_host0_ohci: usb@fc840000 {
 414                 compatible = "rockchip,rk3588-ohci", "generic-ohci";
 415                 reg = <0x0 0xfc840000 0x0 0x40000>;
 416                 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
 417                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
 418                 phys = <&u2phy2_host>;
 419                 phy-names = "usb";
 420                 power-domains = <&power RK3588_PD_USB>;
 421                 status = "disabled";
 422         };
 423
 424         usb_host1_ehci: usb@fc880000 {
 425                 compatible = "rockchip,rk3588-ehci", "generic-ehci";
 426                 reg = <0x0 0xfc880000 0x0 0x40000>;
 427                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
 428                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
 429                 phys = <&u2phy3_host>;
 430                 phy-names = "usb";
 431                 power-domains = <&power RK3588_PD_USB>;
 432                 status = "disabled";
 433         };
 434
 435         usb_host1_ohci: usb@fc8c0000 {
 436                 compatible = "rockchip,rk3588-ohci", "generic-ohci";
 437                 reg = <0x0 0xfc8c0000 0x0 0x40000>;
 438                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
 439                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
 440                 phys = <&u2phy3_host>;
 441                 phy-names = "usb";
 442                 power-domains = <&power RK3588_PD_USB>;
 443                 status = "disabled";
 444         };
 445
 446         pmu1grf: syscon@fd58a000 {
 447                 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
 448                 reg = <0x0 0xfd58a000 0x0 0x10000>;
 449         };
 450
 451         sys_grf: syscon@fd58c000 {
 452                 compatible = "rockchip,rk3588-sys-grf", "syscon";
 453                 reg = <0x0 0xfd58c000 0x0 0x1000>;
 454         };
 455
 456         php_grf: syscon@fd5b0000 {
 457                 compatible = "rockchip,rk3588-php-grf", "syscon";
 458                 reg = <0x0 0xfd5b0000 0x0 0x1000>;
 459         };
 460
 461         pipe_phy0_grf: syscon@fd5bc000 {
 462                 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 463                 reg = <0x0 0xfd5bc000 0x0 0x100>;
 464         };
 465
 466         pipe_phy2_grf: syscon@fd5c4000 {
 467                 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 468                 reg = <0x0 0xfd5c4000 0x0 0x100>;
 469         };
 470
 471         usb2phy2_grf: syscon@fd5d8000 {
 472                 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
 473                 reg = <0x0 0xfd5d8000 0x0 0x4000>;
 474                 #address-cells = <1>;
 475                 #size-cells = <1>;
 476
 477                 u2phy2: usb2-phy@8000 {
 478                         compatible = "rockchip,rk3588-usb2phy";
 479                         reg = <0x8000 0x10>;
 480                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
 481                         resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
 482                         reset-names = "phy", "apb";
 483                         clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
 484                         clock-names = "phyclk";
 485                         clock-output-names = "usb480m_phy2";
 486                         #clock-cells = <0>;
 487                         status = "disabled";
 488
 489                         u2phy2_host: host-port {
 490                                 #phy-cells = <0>;
 491                                 status = "disabled";
 492                         };
 493                 };
 494         };
 495
 496         usb2phy3_grf: syscon@fd5dc000 {
 497                 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
 498                 reg = <0x0 0xfd5dc000 0x0 0x4000>;
 499                 #address-cells = <1>;
 500                 #size-cells = <1>;
 501
 502                 u2phy3: usb2-phy@c000 {
 503                         compatible = "rockchip,rk3588-usb2phy";
 504                         reg = <0xc000 0x10>;
 505                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
 506                         resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
 507                         reset-names = "phy", "apb";
 508                         clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
 509                         clock-names = "phyclk";
 510                         clock-output-names = "usb480m_phy3";
 511                         #clock-cells = <0>;
 512                         status = "disabled";
 513
 514                         u2phy3_host: host-port {
 515                                 #phy-cells = <0>;
 516                                 status = "disabled";
 517                         };
 518                 };
 519         };
 520
 521         ioc: syscon@fd5f0000 {
 522                 compatible = "rockchip,rk3588-ioc", "syscon";
 523                 reg = <0x0 0xfd5f0000 0x0 0x10000>;
 524         };
 525
 526         system_sram1: sram@fd600000 {
 527                 compatible = "mmio-sram";
 528                 reg = <0x0 0xfd600000 0x0 0x100000>;
 529                 ranges = <0x0 0x0 0xfd600000 0x100000>;
 530                 #address-cells = <1>;
 531                 #size-cells = <1>;
 532         };
 533
 534         cru: clock-controller@fd7c0000 {
 535                 compatible = "rockchip,rk3588-cru";
 536                 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
 537                 assigned-clocks =
 538                         <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
 539                         <&cru PLL_NPLL>, <&cru PLL_GPLL>,
 540                         <&cru ACLK_CENTER_ROOT>,
 541                         <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
 542                         <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
 543                         <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
 544                         <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
 545                         <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
 546                         <&cru CLK_GPU>;
 547                 assigned-clock-rates =
 548                         <1100000000>, <786432000>,
 549                         <850000000>, <1188000000>,
 550                         <702000000>,
 551                         <400000000>, <500000000>,
 552                         <800000000>, <100000000>,
 553                         <400000000>, <100000000>,
 554                         <200000000>, <500000000>,
 555                         <375000000>, <150000000>,
 556                         <200000000>;
 557                 rockchip,grf = <&php_grf>;
 558                 #clock-cells = <1>;
 559                 #reset-cells = <1>;
 560         };
 561
 562         i2c0: i2c@fd880000 {
 563                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
 564                 reg = <0x0 0xfd880000 0x0 0x1000>;
 565                 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
 566                 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
 567                 clock-names = "i2c", "pclk";
 568                 pinctrl-0 = <&i2c0m0_xfer>;
 569                 pinctrl-names = "default";
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 status = "disabled";
 573         };
 574
 575         uart0: serial@fd890000 {
 576                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
 577                 reg = <0x0 0xfd890000 0x0 0x100>;
 578                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
 579                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 580                 clock-names = "baudclk", "apb_pclk";
 581                 dmas = <&dmac0 6>, <&dmac0 7>;
 582                 dma-names = "tx", "rx";
 583                 pinctrl-0 = <&uart0m1_xfer>;
 584                 pinctrl-names = "default";
 585                 reg-shift = <2>;
 586                 reg-io-width = <4>;
 587                 status = "disabled";
 588         };
 589
 590         pwm0: pwm@fd8b0000 {
 591                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 592                 reg = <0x0 0xfd8b0000 0x0 0x10>;
 593                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 594                 clock-names = "pwm", "pclk";
 595                 pinctrl-0 = <&pwm0m0_pins>;
 596                 pinctrl-names = "default";
 597                 #pwm-cells = <3>;
 598                 status = "disabled";
 599         };
 600
 601         pwm1: pwm@fd8b0010 {
 602                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 603                 reg = <0x0 0xfd8b0010 0x0 0x10>;
 604                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 605                 clock-names = "pwm", "pclk";
 606                 pinctrl-0 = <&pwm1m0_pins>;
 607                 pinctrl-names = "default";
 608                 #pwm-cells = <3>;
 609                 status = "disabled";
 610         };
 611
 612         pwm2: pwm@fd8b0020 {
 613                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 614                 reg = <0x0 0xfd8b0020 0x0 0x10>;
 615                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 616                 clock-names = "pwm", "pclk";
 617                 pinctrl-0 = <&pwm2m0_pins>;
 618                 pinctrl-names = "default";
 619                 #pwm-cells = <3>;
 620                 status = "disabled";
 621         };
 622
 623         pwm3: pwm@fd8b0030 {
 624                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
 625                 reg = <0x0 0xfd8b0030 0x0 0x10>;
 626                 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
 627                 clock-names = "pwm", "pclk";
 628                 pinctrl-0 = <&pwm3m0_pins>;
 629                 pinctrl-names = "default";
 630                 #pwm-cells = <3>;
 631                 status = "disabled";
 632         };
 633
 634         pmu: power-management@fd8d8000 {
 635                 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
 636                 reg = <0x0 0xfd8d8000 0x0 0x400>;
 637
 638                 power: power-controller {
 639                         compatible = "rockchip,rk3588-power-controller";
 640                         #address-cells = <1>;
 641                         #power-domain-cells = <1>;
 642                         #size-cells = <0>;
 643                         status = "okay";
 644
 645                         /* These power domains are grouped by VD_NPU */
 646                         power-domain@RK3588_PD_NPU {
 647                                 reg = <RK3588_PD_NPU>;
 648                                 #power-domain-cells = <0>;
 649                                 #address-cells = <1>;
 650                                 #size-cells = <0>;
 651
 652                                 power-domain@RK3588_PD_NPUTOP {
 653                                         reg = <RK3588_PD_NPUTOP>;
 654                                         clocks = <&cru HCLK_NPU_ROOT>,
 655                                                  <&cru PCLK_NPU_ROOT>,
 656                                                  <&cru CLK_NPU_DSU0>,
 657                                                  <&cru HCLK_NPU_CM0_ROOT>;
 658                                         pm_qos = <&qos_npu0_mwr>,
 659                                                  <&qos_npu0_mro>,
 660                                                  <&qos_mcu_npu>;
 661                                         #power-domain-cells = <0>;
 662                                         #address-cells = <1>;
 663                                         #size-cells = <0>;
 664
 665                                         power-domain@RK3588_PD_NPU1 {
 666                                                 reg = <RK3588_PD_NPU1>;
 667                                                 clocks = <&cru HCLK_NPU_ROOT>,
 668                                                          <&cru PCLK_NPU_ROOT>,
 669                                                          <&cru CLK_NPU_DSU0>;
 670                                                 pm_qos = <&qos_npu1>;
 671                                                 #power-domain-cells = <0>;
 672                                         };
 673                                         power-domain@RK3588_PD_NPU2 {
 674                                                 reg = <RK3588_PD_NPU2>;
 675                                                 clocks = <&cru HCLK_NPU_ROOT>,
 676                                                          <&cru PCLK_NPU_ROOT>,
 677                                                          <&cru CLK_NPU_DSU0>;
 678                                                 pm_qos = <&qos_npu2>;
 679                                                 #power-domain-cells = <0>;
 680                                         };
 681                                 };
 682                         };
 683                         /* These power domains are grouped by VD_GPU */
 684                         power-domain@RK3588_PD_GPU {
 685                                 reg = <RK3588_PD_GPU>;
 686                                 clocks = <&cru CLK_GPU>,
 687                                          <&cru CLK_GPU_COREGROUP>,
 688                                          <&cru CLK_GPU_STACKS>;
 689                                 pm_qos = <&qos_gpu_m0>,
 690                                          <&qos_gpu_m1>,
 691                                          <&qos_gpu_m2>,
 692                                          <&qos_gpu_m3>;
 693                                 #power-domain-cells = <0>;
 694                         };
 695                         /* These power domains are grouped by VD_VCODEC */
 696                         power-domain@RK3588_PD_VCODEC {
 697                                 reg = <RK3588_PD_VCODEC>;
 698                                 #address-cells = <1>;
 699                                 #size-cells = <0>;
 700                                 #power-domain-cells = <0>;
 701
 702                                 power-domain@RK3588_PD_RKVDEC0 {
 703                                         reg = <RK3588_PD_RKVDEC0>;
 704                                         clocks = <&cru HCLK_RKVDEC0>,
 705                                                  <&cru HCLK_VDPU_ROOT>,
 706                                                  <&cru ACLK_VDPU_ROOT>,
 707                                                  <&cru ACLK_RKVDEC0>,
 708                                                  <&cru ACLK_RKVDEC_CCU>;
 709                                         pm_qos = <&qos_rkvdec0>;
 710                                         #power-domain-cells = <0>;
 711                                 };
 712                                 power-domain@RK3588_PD_RKVDEC1 {
 713                                         reg = <RK3588_PD_RKVDEC1>;
 714                                         clocks = <&cru HCLK_RKVDEC1>,
 715                                                  <&cru HCLK_VDPU_ROOT>,
 716                                                  <&cru ACLK_VDPU_ROOT>,
 717                                                  <&cru ACLK_RKVDEC1>;
 718                                         pm_qos = <&qos_rkvdec1>;
 719                                         #power-domain-cells = <0>;
 720                                 };
 721                                 power-domain@RK3588_PD_VENC0 {
 722                                         reg = <RK3588_PD_VENC0>;
 723                                         clocks = <&cru HCLK_RKVENC0>,
 724                                                  <&cru ACLK_RKVENC0>;
 725                                         pm_qos = <&qos_rkvenc0_m0ro>,
 726                                                  <&qos_rkvenc0_m1ro>,
 727                                                  <&qos_rkvenc0_m2wo>;
 728                                         #address-cells = <1>;
 729                                         #size-cells = <0>;
 730                                         #power-domain-cells = <0>;
 731
 732                                         power-domain@RK3588_PD_VENC1 {
 733                                                 reg = <RK3588_PD_VENC1>;
 734                                                 clocks = <&cru HCLK_RKVENC1>,
 735                                                          <&cru HCLK_RKVENC0>,
 736                                                          <&cru ACLK_RKVENC0>,
 737                                                          <&cru ACLK_RKVENC1>;
 738                                                 pm_qos = <&qos_rkvenc1_m0ro>,
 739                                                          <&qos_rkvenc1_m1ro>,
 740                                                          <&qos_rkvenc1_m2wo>;
 741                                                 #power-domain-cells = <0>;
 742                                         };
 743                                 };
 744                         };
 745                         /* These power domains are grouped by VD_LOGIC */
 746                         power-domain@RK3588_PD_VDPU {
 747                                 reg = <RK3588_PD_VDPU>;
 748                                 clocks = <&cru HCLK_VDPU_ROOT>,
 749                                          <&cru ACLK_VDPU_LOW_ROOT>,
 750                                          <&cru ACLK_VDPU_ROOT>,
 751                                          <&cru ACLK_JPEG_DECODER_ROOT>,
 752                                          <&cru ACLK_IEP2P0>,
 753                                          <&cru HCLK_IEP2P0>,
 754                                          <&cru ACLK_JPEG_ENCODER0>,
 755                                          <&cru HCLK_JPEG_ENCODER0>,
 756                                          <&cru ACLK_JPEG_ENCODER1>,
 757                                          <&cru HCLK_JPEG_ENCODER1>,
 758                                          <&cru ACLK_JPEG_ENCODER2>,
 759                                          <&cru HCLK_JPEG_ENCODER2>,
 760                                          <&cru ACLK_JPEG_ENCODER3>,
 761                                          <&cru HCLK_JPEG_ENCODER3>,
 762                                          <&cru ACLK_JPEG_DECODER>,
 763                                          <&cru HCLK_JPEG_DECODER>,
 764                                          <&cru ACLK_RGA2>,
 765                                          <&cru HCLK_RGA2>;
 766                                 pm_qos = <&qos_iep>,
 767                                          <&qos_jpeg_dec>,
 768                                          <&qos_jpeg_enc0>,
 769                                          <&qos_jpeg_enc1>,
 770                                          <&qos_jpeg_enc2>,
 771                                          <&qos_jpeg_enc3>,
 772                                          <&qos_rga2_mro>,
 773                                          <&qos_rga2_mwo>;
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 #power-domain-cells = <0>;
 777
 778
 779                                 power-domain@RK3588_PD_AV1 {
 780                                         reg = <RK3588_PD_AV1>;
 781                                         clocks = <&cru PCLK_AV1>,
 782                                                  <&cru ACLK_AV1>,
 783                                                  <&cru HCLK_VDPU_ROOT>;
 784                                         pm_qos = <&qos_av1>;
 785                                         #power-domain-cells = <0>;
 786                                 };
 787                                 power-domain@RK3588_PD_RKVDEC0 {
 788                                         reg = <RK3588_PD_RKVDEC0>;
 789                                         clocks = <&cru HCLK_RKVDEC0>,
 790                                                  <&cru HCLK_VDPU_ROOT>,
 791                                                  <&cru ACLK_VDPU_ROOT>,
 792                                                  <&cru ACLK_RKVDEC0>;
 793                                         pm_qos = <&qos_rkvdec0>;
 794                                         #power-domain-cells = <0>;
 795                                 };
 796                                 power-domain@RK3588_PD_RKVDEC1 {
 797                                         reg = <RK3588_PD_RKVDEC1>;
 798                                         clocks = <&cru HCLK_RKVDEC1>,
 799                                                  <&cru HCLK_VDPU_ROOT>,
 800                                                  <&cru ACLK_VDPU_ROOT>;
 801                                         pm_qos = <&qos_rkvdec1>;
 802                                         #power-domain-cells = <0>;
 803                                 };
 804                                 power-domain@RK3588_PD_RGA30 {
 805                                         reg = <RK3588_PD_RGA30>;
 806                                         clocks = <&cru ACLK_RGA3_0>,
 807                                                  <&cru HCLK_RGA3_0>;
 808                                         pm_qos = <&qos_rga3_0>;
 809                                         #power-domain-cells = <0>;
 810                                 };
 811                         };
 812                         power-domain@RK3588_PD_VOP {
 813                                 reg = <RK3588_PD_VOP>;
 814                                 clocks = <&cru PCLK_VOP_ROOT>,
 815                                          <&cru HCLK_VOP_ROOT>,
 816                                          <&cru ACLK_VOP>;
 817                                 pm_qos = <&qos_vop_m0>,
 818                                          <&qos_vop_m1>;
 819                                 #address-cells = <1>;
 820                                 #size-cells = <0>;
 821                                 #power-domain-cells = <0>;
 822
 823                                 power-domain@RK3588_PD_VO0 {
 824                                         reg = <RK3588_PD_VO0>;
 825                                         clocks = <&cru PCLK_VO0_ROOT>,
 826                                                  <&cru PCLK_VO0_S_ROOT>,
 827                                                  <&cru HCLK_VO0_S_ROOT>,
 828                                                  <&cru ACLK_VO0_ROOT>,
 829                                                  <&cru HCLK_HDCP0>,
 830                                                  <&cru ACLK_HDCP0>,
 831                                                  <&cru HCLK_VOP_ROOT>;
 832                                         pm_qos = <&qos_hdcp0>;
 833                                         #power-domain-cells = <0>;
 834                                 };
 835                         };
 836                         power-domain@RK3588_PD_VO1 {
 837                                 reg = <RK3588_PD_VO1>;
 838                                 clocks = <&cru PCLK_VO1_ROOT>,
 839                                          <&cru PCLK_VO1_S_ROOT>,
 840                                          <&cru HCLK_VO1_S_ROOT>,
 841                                          <&cru HCLK_HDCP1>,
 842                                          <&cru ACLK_HDCP1>,
 843                                          <&cru ACLK_HDMIRX_ROOT>,
 844                                          <&cru HCLK_VO1USB_TOP_ROOT>;
 845                                 pm_qos = <&qos_hdcp1>,
 846                                          <&qos_hdmirx>;
 847                                 #power-domain-cells = <0>;
 848                         };
 849                         power-domain@RK3588_PD_VI {
 850                                 reg = <RK3588_PD_VI>;
 851                                 clocks = <&cru HCLK_VI_ROOT>,
 852                                          <&cru PCLK_VI_ROOT>,
 853                                          <&cru HCLK_ISP0>,
 854                                          <&cru ACLK_ISP0>,
 855                                          <&cru HCLK_VICAP>,
 856                                          <&cru ACLK_VICAP>;
 857                                 pm_qos = <&qos_isp0_mro>,
 858                                          <&qos_isp0_mwo>,
 859                                          <&qos_vicap_m0>,
 860                                          <&qos_vicap_m1>;
 861                                 #address-cells = <1>;
 862                                 #size-cells = <0>;
 863                                 #power-domain-cells = <0>;
 864
 865                                 power-domain@RK3588_PD_ISP1 {
 866                                         reg = <RK3588_PD_ISP1>;
 867                                         clocks = <&cru HCLK_ISP1>,
 868                                                  <&cru ACLK_ISP1>,
 869                                                  <&cru HCLK_VI_ROOT>,
 870                                                  <&cru PCLK_VI_ROOT>;
 871                                         pm_qos = <&qos_isp1_mwo>,
 872                                                  <&qos_isp1_mro>;
 873                                         #power-domain-cells = <0>;
 874                                 };
 875                                 power-domain@RK3588_PD_FEC {
 876                                         reg = <RK3588_PD_FEC>;
 877                                         clocks = <&cru HCLK_FISHEYE0>,
 878                                                  <&cru ACLK_FISHEYE0>,
 879                                                  <&cru HCLK_FISHEYE1>,
 880                                                  <&cru ACLK_FISHEYE1>,
 881                                                  <&cru PCLK_VI_ROOT>;
 882                                         pm_qos = <&qos_fisheye0>,
 883                                                  <&qos_fisheye1>;
 884                                         #power-domain-cells = <0>;
 885                                 };
 886                         };
 887                         power-domain@RK3588_PD_RGA31 {
 888                                 reg = <RK3588_PD_RGA31>;
 889                                 clocks = <&cru HCLK_RGA3_1>,
 890                                          <&cru ACLK_RGA3_1>;
 891                                 pm_qos = <&qos_rga3_1>;
 892                                 #power-domain-cells = <0>;
 893                         };
 894                         power-domain@RK3588_PD_USB {
 895                                 reg = <RK3588_PD_USB>;
 896                                 clocks = <&cru PCLK_PHP_ROOT>,
 897                                          <&cru ACLK_USB_ROOT>,
 898                                          <&cru HCLK_USB_ROOT>,
 899                                          <&cru HCLK_HOST0>,
 900                                          <&cru HCLK_HOST_ARB0>,
 901                                          <&cru HCLK_HOST1>,
 902                                          <&cru HCLK_HOST_ARB1>;
 903                                 pm_qos = <&qos_usb3_0>,
 904                                          <&qos_usb3_1>,
 905                                          <&qos_usb2host_0>,
 906                                          <&qos_usb2host_1>;
 907                                 #power-domain-cells = <0>;
 908                         };
 909                         power-domain@RK3588_PD_GMAC {
 910                                 reg = <RK3588_PD_GMAC>;
 911                                 clocks = <&cru PCLK_PHP_ROOT>,
 912                                          <&cru ACLK_PCIE_ROOT>,
 913                                          <&cru ACLK_PHP_ROOT>;
 914                                 #power-domain-cells = <0>;
 915                         };
 916                         power-domain@RK3588_PD_PCIE {
 917                                 reg = <RK3588_PD_PCIE>;
 918                                 clocks = <&cru PCLK_PHP_ROOT>,
 919                                          <&cru ACLK_PCIE_ROOT>,
 920                                          <&cru ACLK_PHP_ROOT>;
 921                                 #power-domain-cells = <0>;
 922                         };
 923                         power-domain@RK3588_PD_SDIO {
 924                                 reg = <RK3588_PD_SDIO>;
 925                                 clocks = <&cru HCLK_SDIO>,
 926                                          <&cru HCLK_NVM_ROOT>;
 927                                 pm_qos = <&qos_sdio>;
 928                                 #power-domain-cells = <0>;
 929                         };
 930                         power-domain@RK3588_PD_AUDIO {
 931                                 reg = <RK3588_PD_AUDIO>;
 932                                 clocks = <&cru HCLK_AUDIO_ROOT>,
 933                                          <&cru PCLK_AUDIO_ROOT>;
 934                                 #power-domain-cells = <0>;
 935                         };
 936                         power-domain@RK3588_PD_SDMMC {
 937                                 reg = <RK3588_PD_SDMMC>;
 938                                 pm_qos = <&qos_sdmmc>;
 939                                 #power-domain-cells = <0>;
 940                         };
 941                 };
 942         };
 943
 944         i2s4_8ch: i2s@fddc0000 {
 945                 compatible = "rockchip,rk3588-i2s-tdm";
 946                 reg = <0x0 0xfddc0000 0x0 0x1000>;
 947                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
 948                 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
 949                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 950                 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
 951                 assigned-clock-parents = <&cru PLL_AUPLL>;
 952                 dmas = <&dmac2 0>;
 953                 dma-names = "tx";
 954                 power-domains = <&power RK3588_PD_VO0>;
 955                 resets = <&cru SRST_M_I2S4_8CH_TX>;
 956                 reset-names = "tx-m";
 957                 #sound-dai-cells = <0>;
 958                 status = "disabled";
 959         };
 960
 961         i2s5_8ch: i2s@fddf0000 {
 962                 compatible = "rockchip,rk3588-i2s-tdm";
 963                 reg = <0x0 0xfddf0000 0x0 0x1000>;
 964                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
 965                 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
 966                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 967                 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
 968                 assigned-clock-parents = <&cru PLL_AUPLL>;
 969                 dmas = <&dmac2 2>;
 970                 dma-names = "tx";
 971                 power-domains = <&power RK3588_PD_VO1>;
 972                 resets = <&cru SRST_M_I2S5_8CH_TX>;
 973                 reset-names = "tx-m";
 974                 #sound-dai-cells = <0>;
 975                 status = "disabled";
 976         };
 977
 978         i2s9_8ch: i2s@fddfc000 {
 979                 compatible = "rockchip,rk3588-i2s-tdm";
 980                 reg = <0x0 0xfddfc000 0x0 0x1000>;
 981                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
 982                 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
 983                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 984                 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
 985                 assigned-clock-parents = <&cru PLL_AUPLL>;
 986                 dmas = <&dmac2 23>;
 987                 dma-names = "rx";
 988                 power-domains = <&power RK3588_PD_VO1>;
 989                 resets = <&cru SRST_M_I2S9_8CH_RX>;
 990                 reset-names = "rx-m";
 991                 #sound-dai-cells = <0>;
 992                 status = "disabled";
 993         };
 994
 995         qos_gpu_m0: qos@fdf35000 {
 996                 compatible = "rockchip,rk3588-qos", "syscon";
 997                 reg = <0x0 0xfdf35000 0x0 0x20>;
 998         };
 999
1000         qos_gpu_m1: qos@fdf35200 {
1001                 compatible = "rockchip,rk3588-qos", "syscon";
1002                 reg = <0x0 0xfdf35200 0x0 0x20>;
1003         };
1004
1005         qos_gpu_m2: qos@fdf35400 {
1006                 compatible = "rockchip,rk3588-qos", "syscon";
1007                 reg = <0x0 0xfdf35400 0x0 0x20>;
1008         };
1009
1010         qos_gpu_m3: qos@fdf35600 {
1011                 compatible = "rockchip,rk3588-qos", "syscon";
1012                 reg = <0x0 0xfdf35600 0x0 0x20>;
1013         };
1014
1015         qos_rga3_1: qos@fdf36000 {
1016                 compatible = "rockchip,rk3588-qos", "syscon";
1017                 reg = <0x0 0xfdf36000 0x0 0x20>;
1018         };
1019
1020         qos_sdio: qos@fdf39000 {
1021                 compatible = "rockchip,rk3588-qos", "syscon";
1022                 reg = <0x0 0xfdf39000 0x0 0x20>;
1023         };
1024
1025         qos_sdmmc: qos@fdf3d800 {
1026                 compatible = "rockchip,rk3588-qos", "syscon";
1027                 reg = <0x0 0xfdf3d800 0x0 0x20>;
1028         };
1029
1030         qos_usb3_1: qos@fdf3e000 {
1031                 compatible = "rockchip,rk3588-qos", "syscon";
1032                 reg = <0x0 0xfdf3e000 0x0 0x20>;
1033         };
1034
1035         qos_usb3_0: qos@fdf3e200 {
1036                 compatible = "rockchip,rk3588-qos", "syscon";
1037                 reg = <0x0 0xfdf3e200 0x0 0x20>;
1038         };
1039
1040         qos_usb2host_0: qos@fdf3e400 {
1041                 compatible = "rockchip,rk3588-qos", "syscon";
1042                 reg = <0x0 0xfdf3e400 0x0 0x20>;
1043         };
1044
1045         qos_usb2host_1: qos@fdf3e600 {
1046                 compatible = "rockchip,rk3588-qos", "syscon";
1047                 reg = <0x0 0xfdf3e600 0x0 0x20>;
1048         };
1049
1050         qos_fisheye0: qos@fdf40000 {
1051                 compatible = "rockchip,rk3588-qos", "syscon";
1052                 reg = <0x0 0xfdf40000 0x0 0x20>;
1053         };
1054
1055         qos_fisheye1: qos@fdf40200 {
1056                 compatible = "rockchip,rk3588-qos", "syscon";
1057                 reg = <0x0 0xfdf40200 0x0 0x20>;
1058         };
1059
1060         qos_isp0_mro: qos@fdf40400 {
1061                 compatible = "rockchip,rk3588-qos", "syscon";
1062                 reg = <0x0 0xfdf40400 0x0 0x20>;
1063         };
1064
1065         qos_isp0_mwo: qos@fdf40500 {
1066                 compatible = "rockchip,rk3588-qos", "syscon";
1067                 reg = <0x0 0xfdf40500 0x0 0x20>;
1068         };
1069
1070         qos_vicap_m0: qos@fdf40600 {
1071                 compatible = "rockchip,rk3588-qos", "syscon";
1072                 reg = <0x0 0xfdf40600 0x0 0x20>;
1073         };
1074
1075         qos_vicap_m1: qos@fdf40800 {
1076                 compatible = "rockchip,rk3588-qos", "syscon";
1077                 reg = <0x0 0xfdf40800 0x0 0x20>;
1078         };
1079
1080         qos_isp1_mwo: qos@fdf41000 {
1081                 compatible = "rockchip,rk3588-qos", "syscon";
1082                 reg = <0x0 0xfdf41000 0x0 0x20>;
1083         };
1084
1085         qos_isp1_mro: qos@fdf41100 {
1086                 compatible = "rockchip,rk3588-qos", "syscon";
1087                 reg = <0x0 0xfdf41100 0x0 0x20>;
1088         };
1089
1090         qos_rkvenc0_m0ro: qos@fdf60000 {
1091                 compatible = "rockchip,rk3588-qos", "syscon";
1092                 reg = <0x0 0xfdf60000 0x0 0x20>;
1093         };
1094
1095         qos_rkvenc0_m1ro: qos@fdf60200 {
1096                 compatible = "rockchip,rk3588-qos", "syscon";
1097                 reg = <0x0 0xfdf60200 0x0 0x20>;
1098         };
1099
1100         qos_rkvenc0_m2wo: qos@fdf60400 {
1101                 compatible = "rockchip,rk3588-qos", "syscon";
1102                 reg = <0x0 0xfdf60400 0x0 0x20>;
1103         };
1104
1105         qos_rkvenc1_m0ro: qos@fdf61000 {
1106                 compatible = "rockchip,rk3588-qos", "syscon";
1107                 reg = <0x0 0xfdf61000 0x0 0x20>;
1108         };
1109
1110         qos_rkvenc1_m1ro: qos@fdf61200 {
1111                 compatible = "rockchip,rk3588-qos", "syscon";
1112                 reg = <0x0 0xfdf61200 0x0 0x20>;
1113         };
1114
1115         qos_rkvenc1_m2wo: qos@fdf61400 {
1116                 compatible = "rockchip,rk3588-qos", "syscon";
1117                 reg = <0x0 0xfdf61400 0x0 0x20>;
1118         };
1119
1120         qos_rkvdec0: qos@fdf62000 {
1121                 compatible = "rockchip,rk3588-qos", "syscon";
1122                 reg = <0x0 0xfdf62000 0x0 0x20>;
1123         };
1124
1125         qos_rkvdec1: qos@fdf63000 {
1126                 compatible = "rockchip,rk3588-qos", "syscon";
1127                 reg = <0x0 0xfdf63000 0x0 0x20>;
1128         };
1129
1130         qos_av1: qos@fdf64000 {
1131                 compatible = "rockchip,rk3588-qos", "syscon";
1132                 reg = <0x0 0xfdf64000 0x0 0x20>;
1133         };
1134
1135         qos_iep: qos@fdf66000 {
1136                 compatible = "rockchip,rk3588-qos", "syscon";
1137                 reg = <0x0 0xfdf66000 0x0 0x20>;
1138         };
1139
1140         qos_jpeg_dec: qos@fdf66200 {
1141                 compatible = "rockchip,rk3588-qos", "syscon";
1142                 reg = <0x0 0xfdf66200 0x0 0x20>;
1143         };
1144
1145         qos_jpeg_enc0: qos@fdf66400 {
1146                 compatible = "rockchip,rk3588-qos", "syscon";
1147                 reg = <0x0 0xfdf66400 0x0 0x20>;
1148         };
1149
1150         qos_jpeg_enc1: qos@fdf66600 {
1151                 compatible = "rockchip,rk3588-qos", "syscon";
1152                 reg = <0x0 0xfdf66600 0x0 0x20>;
1153         };
1154
1155         qos_jpeg_enc2: qos@fdf66800 {
1156                 compatible = "rockchip,rk3588-qos", "syscon";
1157                 reg = <0x0 0xfdf66800 0x0 0x20>;
1158         };
1159
1160         qos_jpeg_enc3: qos@fdf66a00 {
1161                 compatible = "rockchip,rk3588-qos", "syscon";
1162                 reg = <0x0 0xfdf66a00 0x0 0x20>;
1163         };
1164
1165         qos_rga2_mro: qos@fdf66c00 {
1166                 compatible = "rockchip,rk3588-qos", "syscon";
1167                 reg = <0x0 0xfdf66c00 0x0 0x20>;
1168         };
1169
1170         qos_rga2_mwo: qos@fdf66e00 {
1171                 compatible = "rockchip,rk3588-qos", "syscon";
1172                 reg = <0x0 0xfdf66e00 0x0 0x20>;
1173         };
1174
1175         qos_rga3_0: qos@fdf67000 {
1176                 compatible = "rockchip,rk3588-qos", "syscon";
1177                 reg = <0x0 0xfdf67000 0x0 0x20>;
1178         };
1179
1180         qos_vdpu: qos@fdf67200 {
1181                 compatible = "rockchip,rk3588-qos", "syscon";
1182                 reg = <0x0 0xfdf67200 0x0 0x20>;
1183         };
1184
1185         qos_npu1: qos@fdf70000 {
1186                 compatible = "rockchip,rk3588-qos", "syscon";
1187                 reg = <0x0 0xfdf70000 0x0 0x20>;
1188         };
1189
1190         qos_npu2: qos@fdf71000 {
1191                 compatible = "rockchip,rk3588-qos", "syscon";
1192                 reg = <0x0 0xfdf71000 0x0 0x20>;
1193         };
1194
1195         qos_npu0_mwr: qos@fdf72000 {
1196                 compatible = "rockchip,rk3588-qos", "syscon";
1197                 reg = <0x0 0xfdf72000 0x0 0x20>;
1198         };
1199
1200         qos_npu0_mro: qos@fdf72200 {
1201                 compatible = "rockchip,rk3588-qos", "syscon";
1202                 reg = <0x0 0xfdf72200 0x0 0x20>;
1203         };
1204
1205         qos_mcu_npu: qos@fdf72400 {
1206                 compatible = "rockchip,rk3588-qos", "syscon";
1207                 reg = <0x0 0xfdf72400 0x0 0x20>;
1208         };
1209
1210         qos_hdcp0: qos@fdf80000 {
1211                 compatible = "rockchip,rk3588-qos", "syscon";
1212                 reg = <0x0 0xfdf80000 0x0 0x20>;
1213         };
1214
1215         qos_hdcp1: qos@fdf81000 {
1216                 compatible = "rockchip,rk3588-qos", "syscon";
1217                 reg = <0x0 0xfdf81000 0x0 0x20>;
1218         };
1219
1220         qos_hdmirx: qos@fdf81200 {
1221                 compatible = "rockchip,rk3588-qos", "syscon";
1222                 reg = <0x0 0xfdf81200 0x0 0x20>;
1223         };
1224
1225         qos_vop_m0: qos@fdf82000 {
1226                 compatible = "rockchip,rk3588-qos", "syscon";
1227                 reg = <0x0 0xfdf82000 0x0 0x20>;
1228         };
1229
1230         qos_vop_m1: qos@fdf82200 {
1231                 compatible = "rockchip,rk3588-qos", "syscon";
1232                 reg = <0x0 0xfdf82200 0x0 0x20>;
1233         };
1234
1235         pcie2x1l1: pcie@fe180000 {
1236                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1237                 bus-range = <0x30 0x3f>;
1238                 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1239                          <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1240                          <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1241                 clock-names = "aclk_mst", "aclk_slv",
1242                               "aclk_dbi", "pclk",
1243                               "aux", "pipe";
1244                 device_type = "pci";
1245                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1246                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1247                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1248                              <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1249                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1250                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1251                 #interrupt-cells = <1>;
1252                 interrupt-map-mask = <0 0 0 7>;
1253                 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1254                                 <0 0 0 2 &pcie2x1l1_intc 1>,
1255                                 <0 0 0 3 &pcie2x1l1_intc 2>,
1256                                 <0 0 0 4 &pcie2x1l1_intc 3>;
1257                 linux,pci-domain = <3>;
1258                 max-link-speed = <2>;
1259                 msi-map = <0x3000 &its0 0x3000 0x1000>;
1260                 num-lanes = <1>;
1261                 phys = <&combphy2_psu PHY_TYPE_PCIE>;
1262                 phy-names = "pcie-phy";
1263                 power-domains = <&power RK3588_PD_PCIE>;
1264                 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1265                          <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1266                          <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1267                 reg = <0xa 0x40c00000 0x0 0x00400000>,
1268                       <0x0 0xfe180000 0x0 0x00010000>,
1269                       <0x0 0xf3000000 0x0 0x00100000>;
1270                 reg-names = "dbi", "apb", "config";
1271                 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1272                 reset-names = "pwr", "pipe";
1273                 #address-cells = <3>;
1274                 #size-cells = <2>;
1275                 status = "disabled";
1276
1277                 pcie2x1l1_intc: legacy-interrupt-controller {
1278                         interrupt-controller;
1279                         #address-cells = <0>;
1280                         #interrupt-cells = <1>;
1281                         interrupt-parent = <&gic>;
1282                         interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1283                 };
1284         };
1285
1286         pcie2x1l2: pcie@fe190000 {
1287                 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1288                 bus-range = <0x40 0x4f>;
1289                 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1290                          <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1291                          <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1292                 clock-names = "aclk_mst", "aclk_slv",
1293                               "aclk_dbi", "pclk",
1294                               "aux", "pipe";
1295                 device_type = "pci";
1296                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1297                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1298                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1299                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1300                              <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1301                 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1302                 #interrupt-cells = <1>;
1303                 interrupt-map-mask = <0 0 0 7>;
1304                 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1305                                 <0 0 0 2 &pcie2x1l2_intc 1>,
1306                                 <0 0 0 3 &pcie2x1l2_intc 2>,
1307                                 <0 0 0 4 &pcie2x1l2_intc 3>;
1308                 linux,pci-domain = <4>;
1309                 max-link-speed = <2>;
1310                 msi-map = <0x4000 &its0 0x4000 0x1000>;
1311                 num-lanes = <1>;
1312                 phys = <&combphy0_ps PHY_TYPE_PCIE>;
1313                 phy-names = "pcie-phy";
1314                 power-domains = <&power RK3588_PD_PCIE>;
1315                 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1316                          <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1317                          <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1318                 reg = <0xa 0x41000000 0x0 0x00400000>,
1319                       <0x0 0xfe190000 0x0 0x00010000>,
1320                       <0x0 0xf4000000 0x0 0x00100000>;
1321                 reg-names = "dbi", "apb", "config";
1322                 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1323                 reset-names = "pwr", "pipe";
1324                 #address-cells = <3>;
1325                 #size-cells = <2>;
1326                 status = "disabled";
1327
1328                 pcie2x1l2_intc: legacy-interrupt-controller {
1329                         interrupt-controller;
1330                         #address-cells = <0>;
1331                         #interrupt-cells = <1>;
1332                         interrupt-parent = <&gic>;
1333                         interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1334                 };
1335         };
1336
1337         dfi: dfi@fe060000 {
1338                 reg = <0x00 0xfe060000 0x00 0x10000>;
1339                 compatible = "rockchip,rk3588-dfi";
1340                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1341                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1342                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1343                              <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1344                 interrupt-names = "ch0", "ch1", "ch2", "ch3";
1345                 rockchip,pmu = <&pmu1grf>;
1346         };
1347
1348         gmac1: ethernet@fe1c0000 {
1349                 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1350                 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1351                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1352                              <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1353                 interrupt-names = "macirq", "eth_wake_irq";
1354                 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1355                          <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1356                          <&cru CLK_GMAC1_PTP_REF>;
1357                 clock-names = "stmmaceth", "clk_mac_ref",
1358                               "pclk_mac", "aclk_mac",
1359                               "ptp_ref";
1360                 power-domains = <&power RK3588_PD_GMAC>;
1361                 resets = <&cru SRST_A_GMAC1>;
1362                 reset-names = "stmmaceth";
1363                 rockchip,grf = <&sys_grf>;
1364                 rockchip,php-grf = <&php_grf>;
1365                 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1366                 snps,mixed-burst;
1367                 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1368                 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1369                 snps,tso;
1370                 status = "disabled";
1371
1372                 mdio1: mdio {
1373                         compatible = "snps,dwmac-mdio";
1374                         #address-cells = <0x1>;
1375                         #size-cells = <0x0>;
1376                 };
1377
1378                 gmac1_stmmac_axi_setup: stmmac-axi-config {
1379                         snps,blen = <0 0 0 0 16 8 4>;
1380                         snps,wr_osr_lmt = <4>;
1381                         snps,rd_osr_lmt = <8>;
1382                 };
1383
1384                 gmac1_mtl_rx_setup: rx-queues-config {
1385                         snps,rx-queues-to-use = <2>;
1386                         queue0 {};
1387                         queue1 {};
1388                 };
1389
1390                 gmac1_mtl_tx_setup: tx-queues-config {
1391                         snps,tx-queues-to-use = <2>;
1392                         queue0 {};
1393                         queue1 {};
1394                 };
1395         };
1396
1397         sata0: sata@fe210000 {
1398                 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1399                 reg = <0 0xfe210000 0 0x1000>;
1400                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1401                 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1402                          <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1403                          <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1404                 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1405                 ports-implemented = <0x1>;
1406                 #address-cells = <1>;
1407                 #size-cells = <0>;
1408                 status = "disabled";
1409
1410                 sata-port@0 {
1411                         reg = <0>;
1412                         hba-port-cap = <HBA_PORT_FBSCP>;
1413                         phys = <&combphy0_ps PHY_TYPE_SATA>;
1414                         phy-names = "sata-phy";
1415                         snps,rx-ts-max = <32>;
1416                         snps,tx-ts-max = <32>;
1417                 };
1418         };
1419
1420         sata2: sata@fe230000 {
1421                 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1422                 reg = <0 0xfe230000 0 0x1000>;
1423                 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1424                 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1425                          <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1426                          <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1427                 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1428                 ports-implemented = <0x1>;
1429                 #address-cells = <1>;
1430                 #size-cells = <0>;
1431                 status = "disabled";
1432
1433                 sata-port@0 {
1434                         reg = <0>;
1435                         hba-port-cap = <HBA_PORT_FBSCP>;
1436                         phys = <&combphy2_psu PHY_TYPE_SATA>;
1437                         phy-names = "sata-phy";
1438                         snps,rx-ts-max = <32>;
1439                         snps,tx-ts-max = <32>;
1440                 };
1441         };
1442
1443         sfc: spi@fe2b0000 {
1444                 compatible = "rockchip,sfc";
1445                 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1446                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1447                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1448                 clock-names = "clk_sfc", "hclk_sfc";
1449                 #address-cells = <1>;
1450                 #size-cells = <0>;
1451                 status = "disabled";
1452         };
1453
1454         sdmmc: mmc@fe2c0000 {
1455                 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1456                 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1457                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1458                 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1459                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1460                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1461                 fifo-depth = <0x100>;
1462                 max-frequency = <200000000>;
1463                 pinctrl-names = "default";
1464                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1465                 power-domains = <&power RK3588_PD_SDMMC>;
1466                 status = "disabled";
1467         };
1468
1469         sdio: mmc@fe2d0000 {
1470                 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1471                 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1472                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1473                 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1474                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1475                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1476                 fifo-depth = <0x100>;
1477                 max-frequency = <200000000>;
1478                 pinctrl-names = "default";
1479                 pinctrl-0 = <&sdiom1_pins>;
1480                 power-domains = <&power RK3588_PD_SDIO>;
1481                 status = "disabled";
1482         };
1483
1484         sdhci: mmc@fe2e0000 {
1485                 compatible = "rockchip,rk3588-dwcmshc";
1486                 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1487                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1488                 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1489                 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1490                 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1491                          <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1492                          <&cru TMCLK_EMMC>;
1493                 clock-names = "core", "bus", "axi", "block", "timer";
1494                 max-frequency = <200000000>;
1495                 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1496                             <&emmc_cmd>, <&emmc_data_strobe>;
1497                 pinctrl-names = "default";
1498                 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1499                          <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1500                          <&cru SRST_T_EMMC>;
1501                 reset-names = "core", "bus", "axi", "block", "timer";
1502                 status = "disabled";
1503         };
1504
1505         i2s0_8ch: i2s@fe470000 {
1506                 compatible = "rockchip,rk3588-i2s-tdm";
1507                 reg = <0x0 0xfe470000 0x0 0x1000>;
1508                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1509                 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1510                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1511                 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1512                 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1513                 dmas = <&dmac0 0>, <&dmac0 1>;
1514                 dma-names = "tx", "rx";
1515                 power-domains = <&power RK3588_PD_AUDIO>;
1516                 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1517                 reset-names = "tx-m", "rx-m";
1518                 rockchip,trcm-sync-tx-only;
1519                 pinctrl-names = "default";
1520                 pinctrl-0 = <&i2s0_lrck
1521                              &i2s0_sclk
1522                              &i2s0_sdi0
1523                              &i2s0_sdi1
1524                              &i2s0_sdi2
1525                              &i2s0_sdi3
1526                              &i2s0_sdo0
1527                              &i2s0_sdo1
1528                              &i2s0_sdo2
1529                              &i2s0_sdo3>;
1530                 #sound-dai-cells = <0>;
1531                 status = "disabled";
1532         };
1533
1534         i2s1_8ch: i2s@fe480000 {
1535                 compatible = "rockchip,rk3588-i2s-tdm";
1536                 reg = <0x0 0xfe480000 0x0 0x1000>;
1537                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1538                 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1539                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1540                 dmas = <&dmac0 2>, <&dmac0 3>;
1541                 dma-names = "tx", "rx";
1542                 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1543                 reset-names = "tx-m", "rx-m";
1544                 rockchip,trcm-sync-tx-only;
1545                 pinctrl-names = "default";
1546                 pinctrl-0 = <&i2s1m0_lrck
1547                              &i2s1m0_sclk
1548                              &i2s1m0_sdi0
1549                              &i2s1m0_sdi1
1550                              &i2s1m0_sdi2
1551                              &i2s1m0_sdi3
1552                              &i2s1m0_sdo0
1553                              &i2s1m0_sdo1
1554                              &i2s1m0_sdo2
1555                              &i2s1m0_sdo3>;
1556                 #sound-dai-cells = <0>;
1557                 status = "disabled";
1558         };
1559
1560         i2s2_2ch: i2s@fe490000 {
1561                 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1562                 reg = <0x0 0xfe490000 0x0 0x1000>;
1563                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1564                 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1565                 clock-names = "i2s_clk", "i2s_hclk";
1566                 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1567                 assigned-clock-parents = <&cru PLL_AUPLL>;
1568                 dmas = <&dmac1 0>, <&dmac1 1>;
1569                 dma-names = "tx", "rx";
1570                 power-domains = <&power RK3588_PD_AUDIO>;
1571                 rockchip,trcm-sync-tx-only;
1572                 pinctrl-names = "default";
1573                 pinctrl-0 = <&i2s2m1_lrck
1574                              &i2s2m1_sclk
1575                              &i2s2m1_sdi
1576                              &i2s2m1_sdo>;
1577                 #sound-dai-cells = <0>;
1578                 status = "disabled";
1579         };
1580
1581         i2s3_2ch: i2s@fe4a0000 {
1582                 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1583                 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1584                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1585                 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1586                 clock-names = "i2s_clk", "i2s_hclk";
1587                 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1588                 assigned-clock-parents = <&cru PLL_AUPLL>;
1589                 dmas = <&dmac1 2>, <&dmac1 3>;
1590                 dma-names = "tx", "rx";
1591                 power-domains = <&power RK3588_PD_AUDIO>;
1592                 rockchip,trcm-sync-tx-only;
1593                 pinctrl-names = "default";
1594                 pinctrl-0 = <&i2s3_lrck
1595                              &i2s3_sclk
1596                              &i2s3_sdi
1597                              &i2s3_sdo>;
1598                 #sound-dai-cells = <0>;
1599                 status = "disabled";
1600         };
1601
1602         gic: interrupt-controller@fe600000 {
1603                 compatible = "arm,gic-v3";
1604                 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1605                       <0x0 0xfe680000 0 0x100000>; /* GICR */
1606                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1607                 interrupt-controller;
1608                 mbi-alias = <0x0 0xfe610000>;
1609                 mbi-ranges = <424 56>;
1610                 msi-controller;
1611                 ranges;
1612                 #address-cells = <2>;
1613                 #interrupt-cells = <4>;
1614                 #size-cells = <2>;
1615
1616                 its0: msi-controller@fe640000 {
1617                         compatible = "arm,gic-v3-its";
1618                         reg = <0x0 0xfe640000 0x0 0x20000>;
1619                         msi-controller;
1620                         #msi-cells = <1>;
1621                 };
1622
1623                 its1: msi-controller@fe660000 {
1624                         compatible = "arm,gic-v3-its";
1625                         reg = <0x0 0xfe660000 0x0 0x20000>;
1626                         msi-controller;
1627                         #msi-cells = <1>;
1628                 };
1629
1630                 ppi-partitions {
1631                         ppi_partition0: interrupt-partition-0 {
1632                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1633                         };
1634
1635                         ppi_partition1: interrupt-partition-1 {
1636                                 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1637                         };
1638                 };
1639         };
1640
1641         dmac0: dma-controller@fea10000 {
1642                 compatible = "arm,pl330", "arm,primecell";
1643                 reg = <0x0 0xfea10000 0x0 0x4000>;
1644                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1645                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1646                 arm,pl330-periph-burst;
1647                 clocks = <&cru ACLK_DMAC0>;
1648                 clock-names = "apb_pclk";
1649                 #dma-cells = <1>;
1650         };
1651
1652         dmac1: dma-controller@fea30000 {
1653                 compatible = "arm,pl330", "arm,primecell";
1654                 reg = <0x0 0xfea30000 0x0 0x4000>;
1655                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1656                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1657                 arm,pl330-periph-burst;
1658                 clocks = <&cru ACLK_DMAC1>;
1659                 clock-names = "apb_pclk";
1660                 #dma-cells = <1>;
1661         };
1662
1663         i2c1: i2c@fea90000 {
1664                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1665                 reg = <0x0 0xfea90000 0x0 0x1000>;
1666                 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1667                 clock-names = "i2c", "pclk";
1668                 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1669                 pinctrl-0 = <&i2c1m0_xfer>;
1670                 pinctrl-names = "default";
1671                 #address-cells = <1>;
1672                 #size-cells = <0>;
1673                 status = "disabled";
1674         };
1675
1676         i2c2: i2c@feaa0000 {
1677                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1678                 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1679                 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1680                 clock-names = "i2c", "pclk";
1681                 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1682                 pinctrl-0 = <&i2c2m0_xfer>;
1683                 pinctrl-names = "default";
1684                 #address-cells = <1>;
1685                 #size-cells = <0>;
1686                 status = "disabled";
1687         };
1688
1689         i2c3: i2c@feab0000 {
1690                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1691                 reg = <0x0 0xfeab0000 0x0 0x1000>;
1692                 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1693                 clock-names = "i2c", "pclk";
1694                 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1695                 pinctrl-0 = <&i2c3m0_xfer>;
1696                 pinctrl-names = "default";
1697                 #address-cells = <1>;
1698                 #size-cells = <0>;
1699                 status = "disabled";
1700         };
1701
1702         i2c4: i2c@feac0000 {
1703                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1704                 reg = <0x0 0xfeac0000 0x0 0x1000>;
1705                 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1706                 clock-names = "i2c", "pclk";
1707                 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1708                 pinctrl-0 = <&i2c4m0_xfer>;
1709                 pinctrl-names = "default";
1710                 #address-cells = <1>;
1711                 #size-cells = <0>;
1712                 status = "disabled";
1713         };
1714
1715         i2c5: i2c@fead0000 {
1716                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1717                 reg = <0x0 0xfead0000 0x0 0x1000>;
1718                 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1719                 clock-names = "i2c", "pclk";
1720                 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1721                 pinctrl-0 = <&i2c5m0_xfer>;
1722                 pinctrl-names = "default";
1723                 #address-cells = <1>;
1724                 #size-cells = <0>;
1725                 status = "disabled";
1726         };
1727
1728         timer0: timer@feae0000 {
1729                 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1730                 reg = <0x0 0xfeae0000 0x0 0x20>;
1731                 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1732                 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1733                 clock-names = "pclk", "timer";
1734         };
1735
1736         wdt: watchdog@feaf0000 {
1737                 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1738                 reg = <0x0 0xfeaf0000 0x0 0x100>;
1739                 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1740                 clock-names = "tclk", "pclk";
1741                 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1742         };
1743
1744         spi0: spi@feb00000 {
1745                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1746                 reg = <0x0 0xfeb00000 0x0 0x1000>;
1747                 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1748                 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1749                 clock-names = "spiclk", "apb_pclk";
1750                 dmas = <&dmac0 14>, <&dmac0 15>;
1751                 dma-names = "tx", "rx";
1752                 num-cs = <2>;
1753                 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1754                 pinctrl-names = "default";
1755                 #address-cells = <1>;
1756                 #size-cells = <0>;
1757                 status = "disabled";
1758         };
1759
1760         spi1: spi@feb10000 {
1761                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1762                 reg = <0x0 0xfeb10000 0x0 0x1000>;
1763                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1764                 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1765                 clock-names = "spiclk", "apb_pclk";
1766                 dmas = <&dmac0 16>, <&dmac0 17>;
1767                 dma-names = "tx", "rx";
1768                 num-cs = <2>;
1769                 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1770                 pinctrl-names = "default";
1771                 #address-cells = <1>;
1772                 #size-cells = <0>;
1773                 status = "disabled";
1774         };
1775
1776         spi2: spi@feb20000 {
1777                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1778                 reg = <0x0 0xfeb20000 0x0 0x1000>;
1779                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1780                 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1781                 clock-names = "spiclk", "apb_pclk";
1782                 dmas = <&dmac1 15>, <&dmac1 16>;
1783                 dma-names = "tx", "rx";
1784                 num-cs = <2>;
1785                 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1786                 pinctrl-names = "default";
1787                 #address-cells = <1>;
1788                 #size-cells = <0>;
1789                 status = "disabled";
1790         };
1791
1792         spi3: spi@feb30000 {
1793                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1794                 reg = <0x0 0xfeb30000 0x0 0x1000>;
1795                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1796                 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1797                 clock-names = "spiclk", "apb_pclk";
1798                 dmas = <&dmac1 17>, <&dmac1 18>;
1799                 dma-names = "tx", "rx";
1800                 num-cs = <2>;
1801                 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1802                 pinctrl-names = "default";
1803                 #address-cells = <1>;
1804                 #size-cells = <0>;
1805                 status = "disabled";
1806         };
1807
1808         uart1: serial@feb40000 {
1809                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1810                 reg = <0x0 0xfeb40000 0x0 0x100>;
1811                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1812                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1813                 clock-names = "baudclk", "apb_pclk";
1814                 dmas = <&dmac0 8>, <&dmac0 9>;
1815                 dma-names = "tx", "rx";
1816                 pinctrl-0 = <&uart1m1_xfer>;
1817                 pinctrl-names = "default";
1818                 reg-io-width = <4>;
1819                 reg-shift = <2>;
1820                 status = "disabled";
1821         };
1822
1823         uart2: serial@feb50000 {
1824                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1825                 reg = <0x0 0xfeb50000 0x0 0x100>;
1826                 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1827                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1828                 clock-names = "baudclk", "apb_pclk";
1829                 dmas = <&dmac0 10>, <&dmac0 11>;
1830                 dma-names = "tx", "rx";
1831                 pinctrl-0 = <&uart2m1_xfer>;
1832                 pinctrl-names = "default";
1833                 reg-io-width = <4>;
1834                 reg-shift = <2>;
1835                 status = "disabled";
1836         };
1837
1838         uart3: serial@feb60000 {
1839                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1840                 reg = <0x0 0xfeb60000 0x0 0x100>;
1841                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1842                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1843                 clock-names = "baudclk", "apb_pclk";
1844                 dmas = <&dmac0 12>, <&dmac0 13>;
1845                 dma-names = "tx", "rx";
1846                 pinctrl-0 = <&uart3m1_xfer>;
1847                 pinctrl-names = "default";
1848                 reg-io-width = <4>;
1849                 reg-shift = <2>;
1850                 status = "disabled";
1851         };
1852
1853         uart4: serial@feb70000 {
1854                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1855                 reg = <0x0 0xfeb70000 0x0 0x100>;
1856                 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1857                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1858                 clock-names = "baudclk", "apb_pclk";
1859                 dmas = <&dmac1 9>, <&dmac1 10>;
1860                 dma-names = "tx", "rx";
1861                 pinctrl-0 = <&uart4m1_xfer>;
1862                 pinctrl-names = "default";
1863                 reg-io-width = <4>;
1864                 reg-shift = <2>;
1865                 status = "disabled";
1866         };
1867
1868         uart5: serial@feb80000 {
1869                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1870                 reg = <0x0 0xfeb80000 0x0 0x100>;
1871                 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1872                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1873                 clock-names = "baudclk", "apb_pclk";
1874                 dmas = <&dmac1 11>, <&dmac1 12>;
1875                 dma-names = "tx", "rx";
1876                 pinctrl-0 = <&uart5m1_xfer>;
1877                 pinctrl-names = "default";
1878                 reg-io-width = <4>;
1879                 reg-shift = <2>;
1880                 status = "disabled";
1881         };
1882
1883         uart6: serial@feb90000 {
1884                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1885                 reg = <0x0 0xfeb90000 0x0 0x100>;
1886                 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1887                 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1888                 clock-names = "baudclk", "apb_pclk";
1889                 dmas = <&dmac1 13>, <&dmac1 14>;
1890                 dma-names = "tx", "rx";
1891                 pinctrl-0 = <&uart6m1_xfer>;
1892                 pinctrl-names = "default";
1893                 reg-io-width = <4>;
1894                 reg-shift = <2>;
1895                 status = "disabled";
1896         };
1897
1898         uart7: serial@feba0000 {
1899                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1900                 reg = <0x0 0xfeba0000 0x0 0x100>;
1901                 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1902                 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1903                 clock-names = "baudclk", "apb_pclk";
1904                 dmas = <&dmac2 7>, <&dmac2 8>;
1905                 dma-names = "tx", "rx";
1906                 pinctrl-0 = <&uart7m1_xfer>;
1907                 pinctrl-names = "default";
1908                 reg-io-width = <4>;
1909                 reg-shift = <2>;
1910                 status = "disabled";
1911         };
1912
1913         uart8: serial@febb0000 {
1914                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1915                 reg = <0x0 0xfebb0000 0x0 0x100>;
1916                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1917                 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1918                 clock-names = "baudclk", "apb_pclk";
1919                 dmas = <&dmac2 9>, <&dmac2 10>;
1920                 dma-names = "tx", "rx";
1921                 pinctrl-0 = <&uart8m1_xfer>;
1922                 pinctrl-names = "default";
1923                 reg-io-width = <4>;
1924                 reg-shift = <2>;
1925                 status = "disabled";
1926         };
1927
1928         uart9: serial@febc0000 {
1929                 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1930                 reg = <0x0 0xfebc0000 0x0 0x100>;
1931                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1932                 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1933                 clock-names = "baudclk", "apb_pclk";
1934                 dmas = <&dmac2 11>, <&dmac2 12>;
1935                 dma-names = "tx", "rx";
1936                 pinctrl-0 = <&uart9m1_xfer>;
1937                 pinctrl-names = "default";
1938                 reg-io-width = <4>;
1939                 reg-shift = <2>;
1940                 status = "disabled";
1941         };
1942
1943         pwm4: pwm@febd0000 {
1944                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1945                 reg = <0x0 0xfebd0000 0x0 0x10>;
1946                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1947                 clock-names = "pwm", "pclk";
1948                 pinctrl-0 = <&pwm4m0_pins>;
1949                 pinctrl-names = "default";
1950                 #pwm-cells = <3>;
1951                 status = "disabled";
1952         };
1953
1954         pwm5: pwm@febd0010 {
1955                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1956                 reg = <0x0 0xfebd0010 0x0 0x10>;
1957                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1958                 clock-names = "pwm", "pclk";
1959                 pinctrl-0 = <&pwm5m0_pins>;
1960                 pinctrl-names = "default";
1961                 #pwm-cells = <3>;
1962                 status = "disabled";
1963         };
1964
1965         pwm6: pwm@febd0020 {
1966                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1967                 reg = <0x0 0xfebd0020 0x0 0x10>;
1968                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1969                 clock-names = "pwm", "pclk";
1970                 pinctrl-0 = <&pwm6m0_pins>;
1971                 pinctrl-names = "default";
1972                 #pwm-cells = <3>;
1973                 status = "disabled";
1974         };
1975
1976         pwm7: pwm@febd0030 {
1977                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1978                 reg = <0x0 0xfebd0030 0x0 0x10>;
1979                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1980                 clock-names = "pwm", "pclk";
1981                 pinctrl-0 = <&pwm7m0_pins>;
1982                 pinctrl-names = "default";
1983                 #pwm-cells = <3>;
1984                 status = "disabled";
1985         };
1986
1987         pwm8: pwm@febe0000 {
1988                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1989                 reg = <0x0 0xfebe0000 0x0 0x10>;
1990                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1991                 clock-names = "pwm", "pclk";
1992                 pinctrl-0 = <&pwm8m0_pins>;
1993                 pinctrl-names = "default";
1994                 #pwm-cells = <3>;
1995                 status = "disabled";
1996         };
1997
1998         pwm9: pwm@febe0010 {
1999                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2000                 reg = <0x0 0xfebe0010 0x0 0x10>;
2001                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2002                 clock-names = "pwm", "pclk";
2003                 pinctrl-0 = <&pwm9m0_pins>;
2004                 pinctrl-names = "default";
2005                 #pwm-cells = <3>;
2006                 status = "disabled";
2007         };
2008
2009         pwm10: pwm@febe0020 {
2010                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2011                 reg = <0x0 0xfebe0020 0x0 0x10>;
2012                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2013                 clock-names = "pwm", "pclk";
2014                 pinctrl-0 = <&pwm10m0_pins>;
2015                 pinctrl-names = "default";
2016                 #pwm-cells = <3>;
2017                 status = "disabled";
2018         };
2019
2020         pwm11: pwm@febe0030 {
2021                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2022                 reg = <0x0 0xfebe0030 0x0 0x10>;
2023                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2024                 clock-names = "pwm", "pclk";
2025                 pinctrl-0 = <&pwm11m0_pins>;
2026                 pinctrl-names = "default";
2027                 #pwm-cells = <3>;
2028                 status = "disabled";
2029         };
2030
2031         pwm12: pwm@febf0000 {
2032                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2033                 reg = <0x0 0xfebf0000 0x0 0x10>;
2034                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2035                 clock-names = "pwm", "pclk";
2036                 pinctrl-0 = <&pwm12m0_pins>;
2037                 pinctrl-names = "default";
2038                 #pwm-cells = <3>;
2039                 status = "disabled";
2040         };
2041
2042         pwm13: pwm@febf0010 {
2043                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2044                 reg = <0x0 0xfebf0010 0x0 0x10>;
2045                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2046                 clock-names = "pwm", "pclk";
2047                 pinctrl-0 = <&pwm13m0_pins>;
2048                 pinctrl-names = "default";
2049                 #pwm-cells = <3>;
2050                 status = "disabled";
2051         };
2052
2053         pwm14: pwm@febf0020 {
2054                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2055                 reg = <0x0 0xfebf0020 0x0 0x10>;
2056                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2057                 clock-names = "pwm", "pclk";
2058                 pinctrl-0 = <&pwm14m0_pins>;
2059                 pinctrl-names = "default";
2060                 #pwm-cells = <3>;
2061                 status = "disabled";
2062         };
2063
2064         pwm15: pwm@febf0030 {
2065                 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2066                 reg = <0x0 0xfebf0030 0x0 0x10>;
2067                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2068                 clock-names = "pwm", "pclk";
2069                 pinctrl-0 = <&pwm15m0_pins>;
2070                 pinctrl-names = "default";
2071                 #pwm-cells = <3>;
2072                 status = "disabled";
2073         };
2074
2075         tsadc: tsadc@fec00000 {
2076                 compatible = "rockchip,rk3588-tsadc";
2077                 reg = <0x0 0xfec00000 0x0 0x400>;
2078                 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2079                 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2080                 clock-names = "tsadc", "apb_pclk";
2081                 assigned-clocks = <&cru CLK_TSADC>;
2082                 assigned-clock-rates = <2000000>;
2083                 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2084                 reset-names = "tsadc-apb", "tsadc";
2085                 rockchip,hw-tshut-temp = <120000>;
2086                 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2087                 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2088                 pinctrl-0 = <&tsadc_gpio_func>;
2089                 pinctrl-1 = <&tsadc_shut>;
2090                 pinctrl-names = "gpio", "otpout";
2091                 #thermal-sensor-cells = <1>;
2092                 status = "disabled";
2093         };
2094
2095         saradc: adc@fec10000 {
2096                 compatible = "rockchip,rk3588-saradc";
2097                 reg = <0x0 0xfec10000 0x0 0x10000>;
2098                 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2099                 #io-channel-cells = <1>;
2100                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2101                 clock-names = "saradc", "apb_pclk";
2102                 resets = <&cru SRST_P_SARADC>;
2103                 reset-names = "saradc-apb";
2104                 status = "disabled";
2105         };
2106
2107         i2c6: i2c@fec80000 {
2108                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2109                 reg = <0x0 0xfec80000 0x0 0x1000>;
2110                 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2111                 clock-names = "i2c", "pclk";
2112                 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2113                 pinctrl-0 = <&i2c6m0_xfer>;
2114                 pinctrl-names = "default";
2115                 #address-cells = <1>;
2116                 #size-cells = <0>;
2117                 status = "disabled";
2118         };
2119
2120         i2c7: i2c@fec90000 {
2121                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2122                 reg = <0x0 0xfec90000 0x0 0x1000>;
2123                 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2124                 clock-names = "i2c", "pclk";
2125                 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2126                 pinctrl-0 = <&i2c7m0_xfer>;
2127                 pinctrl-names = "default";
2128                 #address-cells = <1>;
2129                 #size-cells = <0>;
2130                 status = "disabled";
2131         };
2132
2133         i2c8: i2c@feca0000 {
2134                 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2135                 reg = <0x0 0xfeca0000 0x0 0x1000>;
2136                 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2137                 clock-names = "i2c", "pclk";
2138                 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2139                 pinctrl-0 = <&i2c8m0_xfer>;
2140                 pinctrl-names = "default";
2141                 #address-cells = <1>;
2142                 #size-cells = <0>;
2143                 status = "disabled";
2144         };
2145
2146         spi4: spi@fecb0000 {
2147                 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2148                 reg = <0x0 0xfecb0000 0x0 0x1000>;
2149                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2150                 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2151                 clock-names = "spiclk", "apb_pclk";
2152                 dmas = <&dmac2 13>, <&dmac2 14>;
2153                 dma-names = "tx", "rx";
2154                 num-cs = <2>;
2155                 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2156                 pinctrl-names = "default";
2157                 #address-cells = <1>;
2158                 #size-cells = <0>;
2159                 status = "disabled";
2160         };
2161
2162         otp: efuse@fecc0000 {
2163                 compatible = "rockchip,rk3588-otp";
2164                 reg = <0x0 0xfecc0000 0x0 0x400>;
2165                 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2166                          <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2167                 clock-names = "otp", "apb_pclk", "phy", "arb";
2168                 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2169                          <&cru SRST_OTPC_ARB>;
2170                 reset-names = "otp", "apb", "arb";
2171                 #address-cells = <1>;
2172                 #size-cells = <1>;
2173
2174                 cpu_code: cpu-code@2 {
2175                         reg = <0x02 0x2>;
2176                 };
2177
2178                 otp_id: id@7 {
2179                         reg = <0x07 0x10>;
2180                 };
2181
2182                 cpub0_leakage: cpu-leakage@17 {
2183                         reg = <0x17 0x1>;
2184                 };
2185
2186                 cpub1_leakage: cpu-leakage@18 {
2187                         reg = <0x18 0x1>;
2188                 };
2189
2190                 cpul_leakage: cpu-leakage@19 {
2191                         reg = <0x19 0x1>;
2192                 };
2193
2194                 log_leakage: log-leakage@1a {
2195                         reg = <0x1a 0x1>;
2196                 };
2197
2198                 gpu_leakage: gpu-leakage@1b {
2199                         reg = <0x1b 0x1>;
2200                 };
2201
2202                 otp_cpu_version: cpu-version@1c {
2203                         reg = <0x1c 0x1>;
2204                         bits = <3 3>;
2205                 };
2206
2207                 npu_leakage: npu-leakage@28 {
2208                         reg = <0x28 0x1>;
2209                 };
2210
2211                 codec_leakage: codec-leakage@29 {
2212                         reg = <0x29 0x1>;
2213                 };
2214         };
2215
2216         dmac2: dma-controller@fed10000 {
2217                 compatible = "arm,pl330", "arm,primecell";
2218                 reg = <0x0 0xfed10000 0x0 0x4000>;
2219                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2220                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2221                 arm,pl330-periph-burst;
2222                 clocks = <&cru ACLK_DMAC2>;
2223                 clock-names = "apb_pclk";
2224                 #dma-cells = <1>;
2225         };
2226
2227         combphy0_ps: phy@fee00000 {
2228                 compatible = "rockchip,rk3588-naneng-combphy";
2229                 reg = <0x0 0xfee00000 0x0 0x100>;
2230                 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2231                          <&cru PCLK_PHP_ROOT>;
2232                 clock-names = "ref", "apb", "pipe";
2233                 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2234                 assigned-clock-rates = <100000000>;
2235                 #phy-cells = <1>;
2236                 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2237                 reset-names = "phy", "apb";
2238                 rockchip,pipe-grf = <&php_grf>;
2239                 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2240                 status = "disabled";
2241         };
2242
2243         combphy2_psu: phy@fee20000 {
2244                 compatible = "rockchip,rk3588-naneng-combphy";
2245                 reg = <0x0 0xfee20000 0x0 0x100>;
2246                 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2247                          <&cru PCLK_PHP_ROOT>;
2248                 clock-names = "ref", "apb", "pipe";
2249                 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2250                 assigned-clock-rates = <100000000>;
2251                 #phy-cells = <1>;
2252                 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2253                 reset-names = "phy", "apb";
2254                 rockchip,pipe-grf = <&php_grf>;
2255                 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2256                 status = "disabled";
2257         };
2258
2259         system_sram2: sram@ff001000 {
2260                 compatible = "mmio-sram";
2261                 reg = <0x0 0xff001000 0x0 0xef000>;
2262                 ranges = <0x0 0x0 0xff001000 0xef000>;
2263                 #address-cells = <1>;
2264                 #size-cells = <1>;
2265         };
2266
2267         pinctrl: pinctrl {
2268                 compatible = "rockchip,rk3588-pinctrl";
2269                 ranges;
2270                 rockchip,grf = <&ioc>;
2271                 #address-cells = <2>;
2272                 #size-cells = <2>;
2273
2274                 gpio0: gpio@fd8a0000 {
2275                         compatible = "rockchip,gpio-bank";
2276                         reg = <0x0 0xfd8a0000 0x0 0x100>;
2277                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2278                         clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2279                         gpio-controller;
2280                         gpio-ranges = <&pinctrl 0 0 32>;
2281                         interrupt-controller;
2282                         #gpio-cells = <2>;
2283                         #interrupt-cells = <2>;
2284                 };
2285
2286                 gpio1: gpio@fec20000 {
2287                         compatible = "rockchip,gpio-bank";
2288                         reg = <0x0 0xfec20000 0x0 0x100>;
2289                         interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2290                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2291                         gpio-controller;
2292                         gpio-ranges = <&pinctrl 0 32 32>;
2293                         interrupt-controller;
2294                         #gpio-cells = <2>;
2295                         #interrupt-cells = <2>;
2296                 };
2297
2298                 gpio2: gpio@fec30000 {
2299                         compatible = "rockchip,gpio-bank";
2300                         reg = <0x0 0xfec30000 0x0 0x100>;
2301                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2302                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2303                         gpio-controller;
2304                         gpio-ranges = <&pinctrl 0 64 32>;
2305                         interrupt-controller;
2306                         #gpio-cells = <2>;
2307                         #interrupt-cells = <2>;
2308                 };
2309
2310                 gpio3: gpio@fec40000 {
2311                         compatible = "rockchip,gpio-bank";
2312                         reg = <0x0 0xfec40000 0x0 0x100>;
2313                         interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2314                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2315                         gpio-controller;
2316                         gpio-ranges = <&pinctrl 0 96 32>;
2317                         interrupt-controller;
2318                         #gpio-cells = <2>;
2319                         #interrupt-cells = <2>;
2320                 };
2321
2322                 gpio4: gpio@fec50000 {
2323                         compatible = "rockchip,gpio-bank";
2324                         reg = <0x0 0xfec50000 0x0 0x100>;
2325                         interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2326                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2327                         gpio-controller;
2328                         gpio-ranges = <&pinctrl 0 128 32>;
2329                         interrupt-controller;
2330                         #gpio-cells = <2>;
2331                         #interrupt-cells = <2>;
2332                 };
2333         };
2334
2335         av1d: video-codec@fdc70000 {
2336                 compatible = "rockchip,rk3588-av1-vpu";
2337                 reg = <0x0 0xfdc70000 0x0 0x800>;
2338                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
2339                 interrupt-names = "vdpu";
2340                 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2341                 assigned-clock-rates = <400000000>, <400000000>;
2342                 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2343                 clock-names = "aclk", "hclk";
2344                 power-domains = <&power RK3588_PD_AV1>;
2345                 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
2346         };
2347 };
2348
2349 #include "rk3588s-pinctrl.dtsi"