arch/arm64/boot/dts/rockchip/rk356x.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rk3568-cru.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/phy/phy.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3568-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 gpio0 = &gpio0;
  22                 gpio1 = &gpio1;
  23                 gpio2 = &gpio2;
  24                 gpio3 = &gpio3;
  25                 gpio4 = &gpio4;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 serial5 = &uart5;
  38                 serial6 = &uart6;
  39                 serial7 = &uart7;
  40                 serial8 = &uart8;
  41                 serial9 = &uart9;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45                 spi3 = &spi3;
  46         };
  47
  48         cpus {
  49                 #address-cells = <2>;
  50                 #size-cells = <0>;
  51
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a55";
  55                         reg = <0x0 0x0>;
  56                         clocks = <&scmi_clk 0>;
  57                         #cooling-cells = <2>;
  58                         enable-method = "psci";
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu1: cpu@100 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a55";
  65                         reg = <0x0 0x100>;
  66                         #cooling-cells = <2>;
  67                         enable-method = "psci";
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                 };
  70
  71                 cpu2: cpu@200 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a55";
  74                         reg = <0x0 0x200>;
  75                         #cooling-cells = <2>;
  76                         enable-method = "psci";
  77                         operating-points-v2 = <&cpu0_opp_table>;
  78                 };
  79
  80                 cpu3: cpu@300 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a55";
  83                         reg = <0x0 0x300>;
  84                         #cooling-cells = <2>;
  85                         enable-method = "psci";
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                 };
  88         };
  89
  90         cpu0_opp_table: opp-table-0 {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp-408000000 {
  95                         opp-hz = /bits/ 64 <408000000>;
  96                         opp-microvolt = <900000 900000 1150000>;
  97                         clock-latency-ns = <40000>;
  98                 };
  99
 100                 opp-600000000 {
 101                         opp-hz = /bits/ 64 <600000000>;
 102                         opp-microvolt = <900000 900000 1150000>;
 103                 };
 104
 105                 opp-816000000 {
 106                         opp-hz = /bits/ 64 <816000000>;
 107                         opp-microvolt = <900000 900000 1150000>;
 108                         opp-suspend;
 109                 };
 110
 111                 opp-1104000000 {
 112                         opp-hz = /bits/ 64 <1104000000>;
 113                         opp-microvolt = <900000 900000 1150000>;
 114                 };
 115
 116                 opp-1416000000 {
 117                         opp-hz = /bits/ 64 <1416000000>;
 118                         opp-microvolt = <900000 900000 1150000>;
 119                 };
 120
 121                 opp-1608000000 {
 122                         opp-hz = /bits/ 64 <1608000000>;
 123                         opp-microvolt = <975000 975000 1150000>;
 124                 };
 125
 126                 opp-1800000000 {
 127                         opp-hz = /bits/ 64 <1800000000>;
 128                         opp-microvolt = <1050000 1050000 1150000>;
 129                 };
 130         };
 131
 132         firmware {
 133                 scmi: scmi {
 134                         compatible = "arm,scmi-smc";
 135                         arm,smc-id = <0x82000010>;
 136                         shmem = <&scmi_shmem>;
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139
 140                         scmi_clk: protocol@14 {
 141                                 reg = <0x14>;
 142                                 #clock-cells = <1>;
 143                         };
 144                 };
 145         };
 146
 147         gpu_opp_table: opp-table-1 {
 148                 compatible = "operating-points-v2";
 149
 150                 opp-200000000 {
 151                         opp-hz = /bits/ 64 <200000000>;
 152                         opp-microvolt = <825000>;
 153                 };
 154
 155                 opp-300000000 {
 156                         opp-hz = /bits/ 64 <300000000>;
 157                         opp-microvolt = <825000>;
 158                 };
 159
 160                 opp-400000000 {
 161                         opp-hz = /bits/ 64 <400000000>;
 162                         opp-microvolt = <825000>;
 163                 };
 164
 165                 opp-600000000 {
 166                         opp-hz = /bits/ 64 <600000000>;
 167                         opp-microvolt = <825000>;
 168                 };
 169
 170                 opp-700000000 {
 171                         opp-hz = /bits/ 64 <700000000>;
 172                         opp-microvolt = <900000>;
 173                 };
 174
 175                 opp-800000000 {
 176                         opp-hz = /bits/ 64 <800000000>;
 177                         opp-microvolt = <1000000>;
 178                 };
 179         };
 180
 181         pmu {
 182                 compatible = "arm,cortex-a55-pmu";
 183                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
 187                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 188         };
 189
 190         psci {
 191                 compatible = "arm,psci-1.0";
 192                 method = "smc";
 193         };
 194
 195         timer {
 196                 compatible = "arm,armv8-timer";
 197                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 201                 arm,no-tick-in-suspend;
 202         };
 203
 204         xin24m: xin24m {
 205                 compatible = "fixed-clock";
 206                 clock-frequency = <24000000>;
 207                 clock-output-names = "xin24m";
 208                 #clock-cells = <0>;
 209         };
 210
 211         xin32k: xin32k {
 212                 compatible = "fixed-clock";
 213                 clock-frequency = <32768>;
 214                 clock-output-names = "xin32k";
 215                 pinctrl-0 = <&clk32k_out0>;
 216                 pinctrl-names = "default";
 217                 #clock-cells = <0>;
 218         };
 219
 220         sram@10f000 {
 221                 compatible = "mmio-sram";
 222                 reg = <0x0 0x0010f000 0x0 0x100>;
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 ranges = <0 0x0 0x0010f000 0x100>;
 226
 227                 scmi_shmem: sram@0 {
 228                         compatible = "arm,scmi-shmem";
 229                         reg = <0x0 0x100>;
 230                 };
 231         };
 232
 233         gic: interrupt-controller@fd400000 {
 234                 compatible = "arm,gic-v3";
 235                 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
 236                       <0x0 0xfd460000 0 0x80000>; /* GICR */
 237                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 238                 interrupt-controller;
 239                 #interrupt-cells = <3>;
 240                 mbi-alias = <0x0 0xfd410000>;
 241                 mbi-ranges = <296 24>;
 242                 msi-controller;
 243         };
 244
 245         usb_host0_ehci: usb@fd800000 {
 246                 compatible = "generic-ehci";
 247                 reg = <0x0 0xfd800000 0x0 0x40000>;
 248                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 250                          <&cru PCLK_USB>;
 251                 phys = <&usb2phy1_otg>;
 252                 phy-names = "usb";
 253                 status = "disabled";
 254         };
 255
 256         usb_host0_ohci: usb@fd840000 {
 257                 compatible = "generic-ohci";
 258                 reg = <0x0 0xfd840000 0x0 0x40000>;
 259                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 261                          <&cru PCLK_USB>;
 262                 phys = <&usb2phy1_otg>;
 263                 phy-names = "usb";
 264                 status = "disabled";
 265         };
 266
 267         usb_host1_ehci: usb@fd880000 {
 268                 compatible = "generic-ehci";
 269                 reg = <0x0 0xfd880000 0x0 0x40000>;
 270                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 272                          <&cru PCLK_USB>;
 273                 phys = <&usb2phy1_host>;
 274                 phy-names = "usb";
 275                 status = "disabled";
 276         };
 277
 278         usb_host1_ohci: usb@fd8c0000 {
 279                 compatible = "generic-ohci";
 280                 reg = <0x0 0xfd8c0000 0x0 0x40000>;
 281                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 283                          <&cru PCLK_USB>;
 284                 phys = <&usb2phy1_host>;
 285                 phy-names = "usb";
 286                 status = "disabled";
 287         };
 288
 289         pmugrf: syscon@fdc20000 {
 290                 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
 291                 reg = <0x0 0xfdc20000 0x0 0x10000>;
 292
 293                 pmu_io_domains: io-domains {
 294                         compatible = "rockchip,rk3568-pmu-io-voltage-domain";
 295                         status = "disabled";
 296                 };
 297         };
 298
 299         pipegrf: syscon@fdc50000 {
 300                 compatible = "rockchip,rk3568-pipe-grf", "syscon";
 301                 reg = <0x0 0xfdc50000 0x0 0x1000>;
 302         };
 303
 304         grf: syscon@fdc60000 {
 305                 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 306                 reg = <0x0 0xfdc60000 0x0 0x10000>;
 307         };
 308
 309         pipe_phy_grf1: syscon@fdc80000 {
 310                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 311                 reg = <0x0 0xfdc80000 0x0 0x1000>;
 312         };
 313
 314         pipe_phy_grf2: syscon@fdc90000 {
 315                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 316                 reg = <0x0 0xfdc90000 0x0 0x1000>;
 317         };
 318
 319         usb2phy0_grf: syscon@fdca0000 {
 320                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 321                 reg = <0x0 0xfdca0000 0x0 0x8000>;
 322         };
 323
 324         usb2phy1_grf: syscon@fdca8000 {
 325                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 326                 reg = <0x0 0xfdca8000 0x0 0x8000>;
 327         };
 328
 329         pmucru: clock-controller@fdd00000 {
 330                 compatible = "rockchip,rk3568-pmucru";
 331                 reg = <0x0 0xfdd00000 0x0 0x1000>;
 332                 #clock-cells = <1>;
 333                 #reset-cells = <1>;
 334         };
 335
 336         cru: clock-controller@fdd20000 {
 337                 compatible = "rockchip,rk3568-cru";
 338                 reg = <0x0 0xfdd20000 0x0 0x1000>;
 339                 #clock-cells = <1>;
 340                 #reset-cells = <1>;
 341                 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
 342                 assigned-clock-rates = <1200000000>, <200000000>;
 343                 rockchip,grf = <&grf>;
 344         };
 345
 346         i2c0: i2c@fdd40000 {
 347                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 348                 reg = <0x0 0xfdd40000 0x0 0x1000>;
 349                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 350                 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
 351                 clock-names = "i2c", "pclk";
 352                 pinctrl-0 = <&i2c0_xfer>;
 353                 pinctrl-names = "default";
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 status = "disabled";
 357         };
 358
 359         uart0: serial@fdd50000 {
 360                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 361                 reg = <0x0 0xfdd50000 0x0 0x100>;
 362                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
 364                 clock-names = "baudclk", "apb_pclk";
 365                 dmas = <&dmac0 0>, <&dmac0 1>;
 366                 pinctrl-0 = <&uart0_xfer>;
 367                 pinctrl-names = "default";
 368                 reg-io-width = <4>;
 369                 reg-shift = <2>;
 370                 status = "disabled";
 371         };
 372
 373         pwm0: pwm@fdd70000 {
 374                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 375                 reg = <0x0 0xfdd70000 0x0 0x10>;
 376                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 377                 clock-names = "pwm", "pclk";
 378                 pinctrl-0 = <&pwm0m0_pins>;
 379                 pinctrl-names = "default";
 380                 #pwm-cells = <3>;
 381                 status = "disabled";
 382         };
 383
 384         pwm1: pwm@fdd70010 {
 385                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 386                 reg = <0x0 0xfdd70010 0x0 0x10>;
 387                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 388                 clock-names = "pwm", "pclk";
 389                 pinctrl-0 = <&pwm1m0_pins>;
 390                 pinctrl-names = "default";
 391                 #pwm-cells = <3>;
 392                 status = "disabled";
 393         };
 394
 395         pwm2: pwm@fdd70020 {
 396                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 397                 reg = <0x0 0xfdd70020 0x0 0x10>;
 398                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 399                 clock-names = "pwm", "pclk";
 400                 pinctrl-0 = <&pwm2m0_pins>;
 401                 pinctrl-names = "default";
 402                 #pwm-cells = <3>;
 403                 status = "disabled";
 404         };
 405
 406         pwm3: pwm@fdd70030 {
 407                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 408                 reg = <0x0 0xfdd70030 0x0 0x10>;
 409                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 410                 clock-names = "pwm", "pclk";
 411                 pinctrl-0 = <&pwm3_pins>;
 412                 pinctrl-names = "default";
 413                 #pwm-cells = <3>;
 414                 status = "disabled";
 415         };
 416
 417         pmu: power-management@fdd90000 {
 418                 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
 419                 reg = <0x0 0xfdd90000 0x0 0x1000>;
 420
 421                 power: power-controller {
 422                         compatible = "rockchip,rk3568-power-controller";
 423                         #power-domain-cells = <1>;
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426
 427                         /* These power domains are grouped by VD_GPU */
 428                         power-domain@RK3568_PD_GPU {
 429                                 reg = <RK3568_PD_GPU>;
 430                                 clocks = <&cru ACLK_GPU_PRE>,
 431                                          <&cru PCLK_GPU_PRE>;
 432                                 pm_qos = <&qos_gpu>;
 433                                 #power-domain-cells = <0>;
 434                         };
 435
 436                         /* These power domains are grouped by VD_LOGIC */
 437                         power-domain@RK3568_PD_VI {
 438                                 reg = <RK3568_PD_VI>;
 439                                 clocks = <&cru HCLK_VI>,
 440                                          <&cru PCLK_VI>;
 441                                 pm_qos = <&qos_isp>,
 442                                          <&qos_vicap0>,
 443                                          <&qos_vicap1>;
 444                                 #power-domain-cells = <0>;
 445                         };
 446
 447                         power-domain@RK3568_PD_VO {
 448                                 reg = <RK3568_PD_VO>;
 449                                 clocks = <&cru HCLK_VO>,
 450                                          <&cru PCLK_VO>,
 451                                          <&cru ACLK_VOP_PRE>;
 452                                 pm_qos = <&qos_hdcp>,
 453                                          <&qos_vop_m0>,
 454                                          <&qos_vop_m1>;
 455                                 #power-domain-cells = <0>;
 456                         };
 457
 458                         power-domain@RK3568_PD_RGA {
 459                                 reg = <RK3568_PD_RGA>;
 460                                 clocks = <&cru HCLK_RGA_PRE>,
 461                                          <&cru PCLK_RGA_PRE>;
 462                                 pm_qos = <&qos_ebc>,
 463                                          <&qos_iep>,
 464                                          <&qos_jpeg_dec>,
 465                                          <&qos_jpeg_enc>,
 466                                          <&qos_rga_rd>,
 467                                          <&qos_rga_wr>;
 468                                 #power-domain-cells = <0>;
 469                         };
 470
 471                         power-domain@RK3568_PD_VPU {
 472                                 reg = <RK3568_PD_VPU>;
 473                                 clocks = <&cru HCLK_VPU_PRE>;
 474                                 pm_qos = <&qos_vpu>;
 475                                 #power-domain-cells = <0>;
 476                         };
 477
 478                         power-domain@RK3568_PD_RKVDEC {
 479                                 clocks = <&cru HCLK_RKVDEC_PRE>;
 480                                 reg = <RK3568_PD_RKVDEC>;
 481                                 pm_qos = <&qos_rkvdec>;
 482                                 #power-domain-cells = <0>;
 483                         };
 484
 485                         power-domain@RK3568_PD_RKVENC {
 486                                 reg = <RK3568_PD_RKVENC>;
 487                                 clocks = <&cru HCLK_RKVENC_PRE>;
 488                                 pm_qos = <&qos_rkvenc_rd_m0>,
 489                                          <&qos_rkvenc_rd_m1>,
 490                                          <&qos_rkvenc_wr_m0>;
 491                                 #power-domain-cells = <0>;
 492                         };
 493                 };
 494         };
 495
 496         gpu: gpu@fde60000 {
 497                 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
 498                 reg = <0x0 0xfde60000 0x0 0x4000>;
 499                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 500                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 501                              <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 502                 interrupt-names = "job", "mmu", "gpu";
 503                 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
 504                 clock-names = "gpu", "bus";
 505                 #cooling-cells = <2>;
 506                 operating-points-v2 = <&gpu_opp_table>;
 507                 power-domains = <&power RK3568_PD_GPU>;
 508                 status = "disabled";
 509         };
 510
 511         sdmmc2: mmc@fe000000 {
 512                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 513                 reg = <0x0 0xfe000000 0x0 0x4000>;
 514                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 515                 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
 516                          <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
 517                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 518                 fifo-depth = <0x100>;
 519                 max-frequency = <150000000>;
 520                 resets = <&cru SRST_SDMMC2>;
 521                 reset-names = "reset";
 522                 status = "disabled";
 523         };
 524
 525         gmac1: ethernet@fe010000 {
 526                 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
 527                 reg = <0x0 0xfe010000 0x0 0x10000>;
 528                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 529                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 530                 interrupt-names = "macirq", "eth_wake_irq";
 531                 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
 532                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
 533                          <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
 534                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
 535                 clock-names = "stmmaceth", "mac_clk_rx",
 536                               "mac_clk_tx", "clk_mac_refout",
 537                               "aclk_mac", "pclk_mac",
 538                               "clk_mac_speed", "ptp_ref";
 539                 resets = <&cru SRST_A_GMAC1>;
 540                 reset-names = "stmmaceth";
 541                 rockchip,grf = <&grf>;
 542                 snps,axi-config = <&gmac1_stmmac_axi_setup>;
 543                 snps,mixed-burst;
 544                 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
 545                 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
 546                 snps,tso;
 547                 status = "disabled";
 548
 549                 mdio1: mdio {
 550                         compatible = "snps,dwmac-mdio";
 551                         #address-cells = <0x1>;
 552                         #size-cells = <0x0>;
 553                 };
 554
 555                 gmac1_stmmac_axi_setup: stmmac-axi-config {
 556                         snps,blen = <0 0 0 0 16 8 4>;
 557                         snps,rd_osr_lmt = <8>;
 558                         snps,wr_osr_lmt = <4>;
 559                 };
 560
 561                 gmac1_mtl_rx_setup: rx-queues-config {
 562                         snps,rx-queues-to-use = <1>;
 563                         queue0 {};
 564                 };
 565
 566                 gmac1_mtl_tx_setup: tx-queues-config {
 567                         snps,tx-queues-to-use = <1>;
 568                         queue0 {};
 569                 };
 570         };
 571
 572         qos_gpu: qos@fe128000 {
 573                 compatible = "rockchip,rk3568-qos", "syscon";
 574                 reg = <0x0 0xfe128000 0x0 0x20>;
 575         };
 576
 577         qos_rkvenc_rd_m0: qos@fe138080 {
 578                 compatible = "rockchip,rk3568-qos", "syscon";
 579                 reg = <0x0 0xfe138080 0x0 0x20>;
 580         };
 581
 582         qos_rkvenc_rd_m1: qos@fe138100 {
 583                 compatible = "rockchip,rk3568-qos", "syscon";
 584                 reg = <0x0 0xfe138100 0x0 0x20>;
 585         };
 586
 587         qos_rkvenc_wr_m0: qos@fe138180 {
 588                 compatible = "rockchip,rk3568-qos", "syscon";
 589                 reg = <0x0 0xfe138180 0x0 0x20>;
 590         };
 591
 592         qos_isp: qos@fe148000 {
 593                 compatible = "rockchip,rk3568-qos", "syscon";
 594                 reg = <0x0 0xfe148000 0x0 0x20>;
 595         };
 596
 597         qos_vicap0: qos@fe148080 {
 598                 compatible = "rockchip,rk3568-qos", "syscon";
 599                 reg = <0x0 0xfe148080 0x0 0x20>;
 600         };
 601
 602         qos_vicap1: qos@fe148100 {
 603                 compatible = "rockchip,rk3568-qos", "syscon";
 604                 reg = <0x0 0xfe148100 0x0 0x20>;
 605         };
 606
 607         qos_vpu: qos@fe150000 {
 608                 compatible = "rockchip,rk3568-qos", "syscon";
 609                 reg = <0x0 0xfe150000 0x0 0x20>;
 610         };
 611
 612         qos_ebc: qos@fe158000 {
 613                 compatible = "rockchip,rk3568-qos", "syscon";
 614                 reg = <0x0 0xfe158000 0x0 0x20>;
 615         };
 616
 617         qos_iep: qos@fe158100 {
 618                 compatible = "rockchip,rk3568-qos", "syscon";
 619                 reg = <0x0 0xfe158100 0x0 0x20>;
 620         };
 621
 622         qos_jpeg_dec: qos@fe158180 {
 623                 compatible = "rockchip,rk3568-qos", "syscon";
 624                 reg = <0x0 0xfe158180 0x0 0x20>;
 625         };
 626
 627         qos_jpeg_enc: qos@fe158200 {
 628                 compatible = "rockchip,rk3568-qos", "syscon";
 629                 reg = <0x0 0xfe158200 0x0 0x20>;
 630         };
 631
 632         qos_rga_rd: qos@fe158280 {
 633                 compatible = "rockchip,rk3568-qos", "syscon";
 634                 reg = <0x0 0xfe158280 0x0 0x20>;
 635         };
 636
 637         qos_rga_wr: qos@fe158300 {
 638                 compatible = "rockchip,rk3568-qos", "syscon";
 639                 reg = <0x0 0xfe158300 0x0 0x20>;
 640         };
 641
 642         qos_npu: qos@fe180000 {
 643                 compatible = "rockchip,rk3568-qos", "syscon";
 644                 reg = <0x0 0xfe180000 0x0 0x20>;
 645         };
 646
 647         qos_pcie2x1: qos@fe190000 {
 648                 compatible = "rockchip,rk3568-qos", "syscon";
 649                 reg = <0x0 0xfe190000 0x0 0x20>;
 650         };
 651
 652         qos_sata1: qos@fe190280 {
 653                 compatible = "rockchip,rk3568-qos", "syscon";
 654                 reg = <0x0 0xfe190280 0x0 0x20>;
 655         };
 656
 657         qos_sata2: qos@fe190300 {
 658                 compatible = "rockchip,rk3568-qos", "syscon";
 659                 reg = <0x0 0xfe190300 0x0 0x20>;
 660         };
 661
 662         qos_usb3_0: qos@fe190380 {
 663                 compatible = "rockchip,rk3568-qos", "syscon";
 664                 reg = <0x0 0xfe190380 0x0 0x20>;
 665         };
 666
 667         qos_usb3_1: qos@fe190400 {
 668                 compatible = "rockchip,rk3568-qos", "syscon";
 669                 reg = <0x0 0xfe190400 0x0 0x20>;
 670         };
 671
 672         qos_rkvdec: qos@fe198000 {
 673                 compatible = "rockchip,rk3568-qos", "syscon";
 674                 reg = <0x0 0xfe198000 0x0 0x20>;
 675         };
 676
 677         qos_hdcp: qos@fe1a8000 {
 678                 compatible = "rockchip,rk3568-qos", "syscon";
 679                 reg = <0x0 0xfe1a8000 0x0 0x20>;
 680         };
 681
 682         qos_vop_m0: qos@fe1a8080 {
 683                 compatible = "rockchip,rk3568-qos", "syscon";
 684                 reg = <0x0 0xfe1a8080 0x0 0x20>;
 685         };
 686
 687         qos_vop_m1: qos@fe1a8100 {
 688                 compatible = "rockchip,rk3568-qos", "syscon";
 689                 reg = <0x0 0xfe1a8100 0x0 0x20>;
 690         };
 691
 692         sdmmc0: mmc@fe2b0000 {
 693                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 694                 reg = <0x0 0xfe2b0000 0x0 0x4000>;
 695                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
 697                          <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
 698                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 699                 fifo-depth = <0x100>;
 700                 max-frequency = <150000000>;
 701                 resets = <&cru SRST_SDMMC0>;
 702                 reset-names = "reset";
 703                 status = "disabled";
 704         };
 705
 706         sdmmc1: mmc@fe2c0000 {
 707                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 708                 reg = <0x0 0xfe2c0000 0x0 0x4000>;
 709                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 710                 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
 711                          <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
 712                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 713                 fifo-depth = <0x100>;
 714                 max-frequency = <150000000>;
 715                 resets = <&cru SRST_SDMMC1>;
 716                 reset-names = "reset";
 717                 status = "disabled";
 718         };
 719
 720         sdhci: mmc@fe310000 {
 721                 compatible = "rockchip,rk3568-dwcmshc";
 722                 reg = <0x0 0xfe310000 0x0 0x10000>;
 723                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 724                 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
 725                 assigned-clock-rates = <200000000>, <24000000>;
 726                 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
 727                          <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
 728                          <&cru TCLK_EMMC>;
 729                 clock-names = "core", "bus", "axi", "block", "timer";
 730                 status = "disabled";
 731         };
 732
 733         spdif: spdif@fe460000 {
 734                 compatible = "rockchip,rk3568-spdif";
 735                 reg = <0x0 0xfe460000 0x0 0x1000>;
 736                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 737                 clock-names = "mclk", "hclk";
 738                 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
 739                 dmas = <&dmac1 1>;
 740                 dma-names = "tx";
 741                 pinctrl-names = "default";
 742                 pinctrl-0 = <&spdifm0_tx>;
 743                 #sound-dai-cells = <0>;
 744                 status = "disabled";
 745         };
 746
 747         i2s1_8ch: i2s@fe410000 {
 748                 compatible = "rockchip,rk3568-i2s-tdm";
 749                 reg = <0x0 0xfe410000 0x0 0x1000>;
 750                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 751                 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
 752                 assigned-clock-rates = <1188000000>, <1188000000>;
 753                 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
 754                          <&cru HCLK_I2S1_8CH>;
 755                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 756                 dmas = <&dmac1 3>, <&dmac1 2>;
 757                 dma-names = "rx", "tx";
 758                 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
 759                 reset-names = "tx-m", "rx-m";
 760                 rockchip,grf = <&grf>;
 761                 pinctrl-names = "default";
 762                 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
 763                              &i2s1m0_lrcktx &i2s1m0_lrckrx
 764                              &i2s1m0_sdi0   &i2s1m0_sdi1
 765                              &i2s1m0_sdi2   &i2s1m0_sdi3
 766                              &i2s1m0_sdo0   &i2s1m0_sdo1
 767                              &i2s1m0_sdo2   &i2s1m0_sdo3>;
 768                 #sound-dai-cells = <0>;
 769                 status = "disabled";
 770         };
 771
 772         i2s3_2ch: i2s@fe430000 {
 773                 compatible = "rockchip,rk3568-i2s-tdm";
 774                 reg = <0x0 0xfe430000 0x0 0x1000>;
 775                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 776                 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
 777                          <&cru HCLK_I2S3_2CH>;
 778                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 779                 dmas = <&dmac1 6>, <&dmac1 7>;
 780                 dma-names = "tx", "rx";
 781                 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
 782                 reset-names = "tx-m", "rx-m";
 783                 rockchip,grf = <&grf>;
 784                 #sound-dai-cells = <0>;
 785                 status = "disabled";
 786         };
 787
 788         pdm: pdm@fe440000 {
 789                 compatible = "rockchip,rk3568-pdm";
 790                 reg = <0x0 0xfe440000 0x0 0x1000>;
 791                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 792                 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
 793                 clock-names = "pdm_clk", "pdm_hclk";
 794                 dmas = <&dmac1 9>;
 795                 dma-names = "rx";
 796                 pinctrl-0 = <&pdmm0_clk
 797                              &pdmm0_clk1
 798                              &pdmm0_sdi0
 799                              &pdmm0_sdi1
 800                              &pdmm0_sdi2
 801                              &pdmm0_sdi3>;
 802                 pinctrl-names = "default";
 803                 resets = <&cru SRST_M_PDM>;
 804                 reset-names = "pdm-m";
 805                 #sound-dai-cells = <0>;
 806                 status = "disabled";
 807         };
 808
 809         dmac0: dma-controller@fe530000 {
 810                 compatible = "arm,pl330", "arm,primecell";
 811                 reg = <0x0 0xfe530000 0x0 0x4000>;
 812                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 813                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 814                 arm,pl330-periph-burst;
 815                 clocks = <&cru ACLK_BUS>;
 816                 clock-names = "apb_pclk";
 817                 #dma-cells = <1>;
 818         };
 819
 820         dmac1: dma-controller@fe550000 {
 821                 compatible = "arm,pl330", "arm,primecell";
 822                 reg = <0x0 0xfe550000 0x0 0x4000>;
 823                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 824                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 825                 arm,pl330-periph-burst;
 826                 clocks = <&cru ACLK_BUS>;
 827                 clock-names = "apb_pclk";
 828                 #dma-cells = <1>;
 829         };
 830
 831         i2c1: i2c@fe5a0000 {
 832                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 833                 reg = <0x0 0xfe5a0000 0x0 0x1000>;
 834                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 835                 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
 836                 clock-names = "i2c", "pclk";
 837                 pinctrl-0 = <&i2c1_xfer>;
 838                 pinctrl-names = "default";
 839                 #address-cells = <1>;
 840                 #size-cells = <0>;
 841                 status = "disabled";
 842         };
 843
 844         i2c2: i2c@fe5b0000 {
 845                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 846                 reg = <0x0 0xfe5b0000 0x0 0x1000>;
 847                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 848                 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
 849                 clock-names = "i2c", "pclk";
 850                 pinctrl-0 = <&i2c2m0_xfer>;
 851                 pinctrl-names = "default";
 852                 #address-cells = <1>;
 853                 #size-cells = <0>;
 854                 status = "disabled";
 855         };
 856
 857         i2c3: i2c@fe5c0000 {
 858                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 859                 reg = <0x0 0xfe5c0000 0x0 0x1000>;
 860                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 861                 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
 862                 clock-names = "i2c", "pclk";
 863                 pinctrl-0 = <&i2c3m0_xfer>;
 864                 pinctrl-names = "default";
 865                 #address-cells = <1>;
 866                 #size-cells = <0>;
 867                 status = "disabled";
 868         };
 869
 870         i2c4: i2c@fe5d0000 {
 871                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 872                 reg = <0x0 0xfe5d0000 0x0 0x1000>;
 873                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 874                 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
 875                 clock-names = "i2c", "pclk";
 876                 pinctrl-0 = <&i2c4m0_xfer>;
 877                 pinctrl-names = "default";
 878                 #address-cells = <1>;
 879                 #size-cells = <0>;
 880                 status = "disabled";
 881         };
 882
 883         i2c5: i2c@fe5e0000 {
 884                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 885                 reg = <0x0 0xfe5e0000 0x0 0x1000>;
 886                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 887                 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
 888                 clock-names = "i2c", "pclk";
 889                 pinctrl-0 = <&i2c5m0_xfer>;
 890                 pinctrl-names = "default";
 891                 #address-cells = <1>;
 892                 #size-cells = <0>;
 893                 status = "disabled";
 894         };
 895
 896         wdt: watchdog@fe600000 {
 897                 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
 898                 reg = <0x0 0xfe600000 0x0 0x100>;
 899                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 900                 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
 901                 clock-names = "tclk", "pclk";
 902         };
 903
 904         spi0: spi@fe610000 {
 905                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 906                 reg = <0x0 0xfe610000 0x0 0x1000>;
 907                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 908                 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
 909                 clock-names = "spiclk", "apb_pclk";
 910                 dmas = <&dmac0 20>, <&dmac0 21>;
 911                 dma-names = "tx", "rx";
 912                 pinctrl-names = "default";
 913                 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
 914                 #address-cells = <1>;
 915                 #size-cells = <0>;
 916                 status = "disabled";
 917         };
 918
 919         spi1: spi@fe620000 {
 920                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 921                 reg = <0x0 0xfe620000 0x0 0x1000>;
 922                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 923                 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
 924                 clock-names = "spiclk", "apb_pclk";
 925                 dmas = <&dmac0 22>, <&dmac0 23>;
 926                 dma-names = "tx", "rx";
 927                 pinctrl-names = "default";
 928                 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
 929                 #address-cells = <1>;
 930                 #size-cells = <0>;
 931                 status = "disabled";
 932         };
 933
 934         spi2: spi@fe630000 {
 935                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 936                 reg = <0x0 0xfe630000 0x0 0x1000>;
 937                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 938                 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
 939                 clock-names = "spiclk", "apb_pclk";
 940                 dmas = <&dmac0 24>, <&dmac0 25>;
 941                 dma-names = "tx", "rx";
 942                 pinctrl-names = "default";
 943                 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
 944                 #address-cells = <1>;
 945                 #size-cells = <0>;
 946                 status = "disabled";
 947         };
 948
 949         spi3: spi@fe640000 {
 950                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 951                 reg = <0x0 0xfe640000 0x0 0x1000>;
 952                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 953                 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
 954                 clock-names = "spiclk", "apb_pclk";
 955                 dmas = <&dmac0 26>, <&dmac0 27>;
 956                 dma-names = "tx", "rx";
 957                 pinctrl-names = "default";
 958                 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
 959                 #address-cells = <1>;
 960                 #size-cells = <0>;
 961                 status = "disabled";
 962         };
 963
 964         uart1: serial@fe650000 {
 965                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 966                 reg = <0x0 0xfe650000 0x0 0x100>;
 967                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 968                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 969                 clock-names = "baudclk", "apb_pclk";
 970                 dmas = <&dmac0 2>, <&dmac0 3>;
 971                 pinctrl-0 = <&uart1m0_xfer>;
 972                 pinctrl-names = "default";
 973                 reg-io-width = <4>;
 974                 reg-shift = <2>;
 975                 status = "disabled";
 976         };
 977
 978         uart2: serial@fe660000 {
 979                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 980                 reg = <0x0 0xfe660000 0x0 0x100>;
 981                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 982                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 983                 clock-names = "baudclk", "apb_pclk";
 984                 dmas = <&dmac0 4>, <&dmac0 5>;
 985                 pinctrl-0 = <&uart2m0_xfer>;
 986                 pinctrl-names = "default";
 987                 reg-io-width = <4>;
 988                 reg-shift = <2>;
 989                 status = "disabled";
 990         };
 991
 992         uart3: serial@fe670000 {
 993                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 994                 reg = <0x0 0xfe670000 0x0 0x100>;
 995                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 996                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 997                 clock-names = "baudclk", "apb_pclk";
 998                 dmas = <&dmac0 6>, <&dmac0 7>;
 999                 pinctrl-0 = <&uart3m0_xfer>;
1000                 pinctrl-names = "default";
1001                 reg-io-width = <4>;
1002                 reg-shift = <2>;
1003                 status = "disabled";
1004         };
1005
1006         uart4: serial@fe680000 {
1007                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1008                 reg = <0x0 0xfe680000 0x0 0x100>;
1009                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1011                 clock-names = "baudclk", "apb_pclk";
1012                 dmas = <&dmac0 8>, <&dmac0 9>;
1013                 pinctrl-0 = <&uart4m0_xfer>;
1014                 pinctrl-names = "default";
1015                 reg-io-width = <4>;
1016                 reg-shift = <2>;
1017                 status = "disabled";
1018         };
1019
1020         uart5: serial@fe690000 {
1021                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1022                 reg = <0x0 0xfe690000 0x0 0x100>;
1023                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1024                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1025                 clock-names = "baudclk", "apb_pclk";
1026                 dmas = <&dmac0 10>, <&dmac0 11>;
1027                 pinctrl-0 = <&uart5m0_xfer>;
1028                 pinctrl-names = "default";
1029                 reg-io-width = <4>;
1030                 reg-shift = <2>;
1031                 status = "disabled";
1032         };
1033
1034         uart6: serial@fe6a0000 {
1035                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1036                 reg = <0x0 0xfe6a0000 0x0 0x100>;
1037                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1038                 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1039                 clock-names = "baudclk", "apb_pclk";
1040                 dmas = <&dmac0 12>, <&dmac0 13>;
1041                 pinctrl-0 = <&uart6m0_xfer>;
1042                 pinctrl-names = "default";
1043                 reg-io-width = <4>;
1044                 reg-shift = <2>;
1045                 status = "disabled";
1046         };
1047
1048         uart7: serial@fe6b0000 {
1049                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1050                 reg = <0x0 0xfe6b0000 0x0 0x100>;
1051                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1052                 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1053                 clock-names = "baudclk", "apb_pclk";
1054                 dmas = <&dmac0 14>, <&dmac0 15>;
1055                 pinctrl-0 = <&uart7m0_xfer>;
1056                 pinctrl-names = "default";
1057                 reg-io-width = <4>;
1058                 reg-shift = <2>;
1059                 status = "disabled";
1060         };
1061
1062         uart8: serial@fe6c0000 {
1063                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1064                 reg = <0x0 0xfe6c0000 0x0 0x100>;
1065                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1066                 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1067                 clock-names = "baudclk", "apb_pclk";
1068                 dmas = <&dmac0 16>, <&dmac0 17>;
1069                 pinctrl-0 = <&uart8m0_xfer>;
1070                 pinctrl-names = "default";
1071                 reg-io-width = <4>;
1072                 reg-shift = <2>;
1073                 status = "disabled";
1074         };
1075
1076         uart9: serial@fe6d0000 {
1077                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1078                 reg = <0x0 0xfe6d0000 0x0 0x100>;
1079                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1080                 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1081                 clock-names = "baudclk", "apb_pclk";
1082                 dmas = <&dmac0 18>, <&dmac0 19>;
1083                 pinctrl-0 = <&uart9m0_xfer>;
1084                 pinctrl-names = "default";
1085                 reg-io-width = <4>;
1086                 reg-shift = <2>;
1087                 status = "disabled";
1088         };
1089
1090         thermal_zones: thermal-zones {
1091                 cpu_thermal: cpu-thermal {
1092                         polling-delay-passive = <100>;
1093                         polling-delay = <1000>;
1094
1095                         thermal-sensors = <&tsadc 0>;
1096
1097                         trips {
1098                                 cpu_alert0: cpu_alert0 {
1099                                         temperature = <70000>;
1100                                         hysteresis = <2000>;
1101                                         type = "passive";
1102                                 };
1103                                 cpu_alert1: cpu_alert1 {
1104                                         temperature = <75000>;
1105                                         hysteresis = <2000>;
1106                                         type = "passive";
1107                                 };
1108                                 cpu_crit: cpu_crit {
1109                                         temperature = <95000>;
1110                                         hysteresis = <2000>;
1111                                         type = "critical";
1112                                 };
1113                         };
1114
1115                         cooling-maps {
1116                                 map0 {
1117                                         trip = <&cpu_alert0>;
1118                                         cooling-device =
1119                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1120                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1121                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1122                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1123                                 };
1124                         };
1125                 };
1126
1127                 gpu_thermal: gpu-thermal {
1128                         polling-delay-passive = <20>; /* milliseconds */
1129                         polling-delay = <1000>; /* milliseconds */
1130
1131                         thermal-sensors = <&tsadc 1>;
1132
1133                         trips {
1134                                 gpu_threshold: gpu-threshold {
1135                                         temperature = <70000>;
1136                                         hysteresis = <2000>;
1137                                         type = "passive";
1138                                 };
1139                                 gpu_target: gpu-target {
1140                                         temperature = <75000>;
1141                                         hysteresis = <2000>;
1142                                         type = "passive";
1143                                 };
1144                                 gpu_crit: gpu-crit {
1145                                         temperature = <95000>;
1146                                         hysteresis = <2000>;
1147                                         type = "critical";
1148                                 };
1149                         };
1150
1151                         cooling-maps {
1152                                 map0 {
1153                                         trip = <&gpu_target>;
1154                                         cooling-device =
1155                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1156                                 };
1157                         };
1158                 };
1159         };
1160
1161         tsadc: tsadc@fe710000 {
1162                 compatible = "rockchip,rk3568-tsadc";
1163                 reg = <0x0 0xfe710000 0x0 0x100>;
1164                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1165                 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1166                 assigned-clock-rates = <17000000>, <700000>;
1167                 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1168                 clock-names = "tsadc", "apb_pclk";
1169                 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1170                          <&cru SRST_TSADCPHY>;
1171                 rockchip,grf = <&grf>;
1172                 rockchip,hw-tshut-temp = <95000>;
1173                 pinctrl-names = "init", "default", "sleep";
1174                 pinctrl-0 = <&tsadc_pin>;
1175                 pinctrl-1 = <&tsadc_shutorg>;
1176                 pinctrl-2 = <&tsadc_pin>;
1177                 #thermal-sensor-cells = <1>;
1178                 status = "disabled";
1179         };
1180
1181         saradc: saradc@fe720000 {
1182                 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1183                 reg = <0x0 0xfe720000 0x0 0x100>;
1184                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1185                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1186                 clock-names = "saradc", "apb_pclk";
1187                 resets = <&cru SRST_P_SARADC>;
1188                 reset-names = "saradc-apb";
1189                 #io-channel-cells = <1>;
1190                 status = "disabled";
1191         };
1192
1193         pwm4: pwm@fe6e0000 {
1194                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1195                 reg = <0x0 0xfe6e0000 0x0 0x10>;
1196                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1197                 clock-names = "pwm", "pclk";
1198                 pinctrl-0 = <&pwm4_pins>;
1199                 pinctrl-names = "default";
1200                 #pwm-cells = <3>;
1201                 status = "disabled";
1202         };
1203
1204         pwm5: pwm@fe6e0010 {
1205                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1206                 reg = <0x0 0xfe6e0010 0x0 0x10>;
1207                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1208                 clock-names = "pwm", "pclk";
1209                 pinctrl-0 = <&pwm5_pins>;
1210                 pinctrl-names = "default";
1211                 #pwm-cells = <3>;
1212                 status = "disabled";
1213         };
1214
1215         pwm6: pwm@fe6e0020 {
1216                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1217                 reg = <0x0 0xfe6e0020 0x0 0x10>;
1218                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1219                 clock-names = "pwm", "pclk";
1220                 pinctrl-0 = <&pwm6_pins>;
1221                 pinctrl-names = "default";
1222                 #pwm-cells = <3>;
1223                 status = "disabled";
1224         };
1225
1226         pwm7: pwm@fe6e0030 {
1227                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1228                 reg = <0x0 0xfe6e0030 0x0 0x10>;
1229                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1230                 clock-names = "pwm", "pclk";
1231                 pinctrl-0 = <&pwm7_pins>;
1232                 pinctrl-names = "default";
1233                 #pwm-cells = <3>;
1234                 status = "disabled";
1235         };
1236
1237         pwm8: pwm@fe6f0000 {
1238                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1239                 reg = <0x0 0xfe6f0000 0x0 0x10>;
1240                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1241                 clock-names = "pwm", "pclk";
1242                 pinctrl-0 = <&pwm8m0_pins>;
1243                 pinctrl-names = "default";
1244                 #pwm-cells = <3>;
1245                 status = "disabled";
1246         };
1247
1248         pwm9: pwm@fe6f0010 {
1249                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1250                 reg = <0x0 0xfe6f0010 0x0 0x10>;
1251                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1252                 clock-names = "pwm", "pclk";
1253                 pinctrl-0 = <&pwm9m0_pins>;
1254                 pinctrl-names = "default";
1255                 #pwm-cells = <3>;
1256                 status = "disabled";
1257         };
1258
1259         pwm10: pwm@fe6f0020 {
1260                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1261                 reg = <0x0 0xfe6f0020 0x0 0x10>;
1262                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1263                 clock-names = "pwm", "pclk";
1264                 pinctrl-0 = <&pwm10m0_pins>;
1265                 pinctrl-names = "default";
1266                 #pwm-cells = <3>;
1267                 status = "disabled";
1268         };
1269
1270         pwm11: pwm@fe6f0030 {
1271                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1272                 reg = <0x0 0xfe6f0030 0x0 0x10>;
1273                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1274                 clock-names = "pwm", "pclk";
1275                 pinctrl-0 = <&pwm11m0_pins>;
1276                 pinctrl-names = "default";
1277                 #pwm-cells = <3>;
1278                 status = "disabled";
1279         };
1280
1281         pwm12: pwm@fe700000 {
1282                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1283                 reg = <0x0 0xfe700000 0x0 0x10>;
1284                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1285                 clock-names = "pwm", "pclk";
1286                 pinctrl-0 = <&pwm12m0_pins>;
1287                 pinctrl-names = "default";
1288                 #pwm-cells = <3>;
1289                 status = "disabled";
1290         };
1291
1292         pwm13: pwm@fe700010 {
1293                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1294                 reg = <0x0 0xfe700010 0x0 0x10>;
1295                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1296                 clock-names = "pwm", "pclk";
1297                 pinctrl-0 = <&pwm13m0_pins>;
1298                 pinctrl-names = "default";
1299                 #pwm-cells = <3>;
1300                 status = "disabled";
1301         };
1302
1303         pwm14: pwm@fe700020 {
1304                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1305                 reg = <0x0 0xfe700020 0x0 0x10>;
1306                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1307                 clock-names = "pwm", "pclk";
1308                 pinctrl-0 = <&pwm14m0_pins>;
1309                 pinctrl-names = "default";
1310                 #pwm-cells = <3>;
1311                 status = "disabled";
1312         };
1313
1314         pwm15: pwm@fe700030 {
1315                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1316                 reg = <0x0 0xfe700030 0x0 0x10>;
1317                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1318                 clock-names = "pwm", "pclk";
1319                 pinctrl-0 = <&pwm15m0_pins>;
1320                 pinctrl-names = "default";
1321                 #pwm-cells = <3>;
1322                 status = "disabled";
1323         };
1324
1325         combphy1: phy@fe830000 {
1326                 compatible = "rockchip,rk3568-naneng-combphy";
1327                 reg = <0x0 0xfe830000 0x0 0x100>;
1328                 clocks = <&pmucru CLK_PCIEPHY1_REF>,
1329                          <&cru PCLK_PIPEPHY1>,
1330                          <&cru PCLK_PIPE>;
1331                 clock-names = "ref", "apb", "pipe";
1332                 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1333                 assigned-clock-rates = <100000000>;
1334                 resets = <&cru SRST_PIPEPHY1>;
1335                 rockchip,pipe-grf = <&pipegrf>;
1336                 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1337                 #phy-cells = <1>;
1338                 status = "disabled";
1339         };
1340
1341         combphy2: phy@fe840000 {
1342                 compatible = "rockchip,rk3568-naneng-combphy";
1343                 reg = <0x0 0xfe840000 0x0 0x100>;
1344                 clocks = <&pmucru CLK_PCIEPHY2_REF>,
1345                          <&cru PCLK_PIPEPHY2>,
1346                          <&cru PCLK_PIPE>;
1347                 clock-names = "ref", "apb", "pipe";
1348                 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1349                 assigned-clock-rates = <100000000>;
1350                 resets = <&cru SRST_PIPEPHY2>;
1351                 rockchip,pipe-grf = <&pipegrf>;
1352                 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1353                 #phy-cells = <1>;
1354                 status = "disabled";
1355         };
1356
1357         usb2phy0: usb2phy@fe8a0000 {
1358                 compatible = "rockchip,rk3568-usb2phy";
1359                 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1360                 clocks = <&pmucru CLK_USBPHY0_REF>;
1361                 clock-names = "phyclk";
1362                 clock-output-names = "clk_usbphy0_480m";
1363                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1364                 rockchip,usbgrf = <&usb2phy0_grf>;
1365                 #clock-cells = <0>;
1366                 status = "disabled";
1367
1368                 usb2phy0_host: host-port {
1369                         #phy-cells = <0>;
1370                         status = "disabled";
1371                 };
1372
1373                 usb2phy0_otg: otg-port {
1374                         #phy-cells = <0>;
1375                         status = "disabled";
1376                 };
1377         };
1378
1379         usb2phy1: usb2phy@fe8b0000 {
1380                 compatible = "rockchip,rk3568-usb2phy";
1381                 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1382                 clocks = <&pmucru CLK_USBPHY1_REF>;
1383                 clock-names = "phyclk";
1384                 clock-output-names = "clk_usbphy1_480m";
1385                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1386                 rockchip,usbgrf = <&usb2phy1_grf>;
1387                 #clock-cells = <0>;
1388                 status = "disabled";
1389
1390                 usb2phy1_host: host-port {
1391                         #phy-cells = <0>;
1392                         status = "disabled";
1393                 };
1394
1395                 usb2phy1_otg: otg-port {
1396                         #phy-cells = <0>;
1397                         status = "disabled";
1398                 };
1399         };
1400
1401         pinctrl: pinctrl {
1402                 compatible = "rockchip,rk3568-pinctrl";
1403                 rockchip,grf = <&grf>;
1404                 rockchip,pmu = <&pmugrf>;
1405                 #address-cells = <2>;
1406                 #size-cells = <2>;
1407                 ranges;
1408
1409                 gpio0: gpio@fdd60000 {
1410                         compatible = "rockchip,gpio-bank";
1411                         reg = <0x0 0xfdd60000 0x0 0x100>;
1412                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1413                         clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
1414                         gpio-controller;
1415                         #gpio-cells = <2>;
1416                         interrupt-controller;
1417                         #interrupt-cells = <2>;
1418                 };
1419
1420                 gpio1: gpio@fe740000 {
1421                         compatible = "rockchip,gpio-bank";
1422                         reg = <0x0 0xfe740000 0x0 0x100>;
1423                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1424                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1425                         gpio-controller;
1426                         #gpio-cells = <2>;
1427                         interrupt-controller;
1428                         #interrupt-cells = <2>;
1429                 };
1430
1431                 gpio2: gpio@fe750000 {
1432                         compatible = "rockchip,gpio-bank";
1433                         reg = <0x0 0xfe750000 0x0 0x100>;
1434                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1435                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1436                         gpio-controller;
1437                         #gpio-cells = <2>;
1438                         interrupt-controller;
1439                         #interrupt-cells = <2>;
1440                 };
1441
1442                 gpio3: gpio@fe760000 {
1443                         compatible = "rockchip,gpio-bank";
1444                         reg = <0x0 0xfe760000 0x0 0x100>;
1445                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1446                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1447                         gpio-controller;
1448                         #gpio-cells = <2>;
1449                         interrupt-controller;
1450                         #interrupt-cells = <2>;
1451                 };
1452
1453                 gpio4: gpio@fe770000 {
1454                         compatible = "rockchip,gpio-bank";
1455                         reg = <0x0 0xfe770000 0x0 0x100>;
1456                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1457                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1458                         gpio-controller;
1459                         #gpio-cells = <2>;
1460                         interrupt-controller;
1461                         #interrupt-cells = <2>;
1462                 };
1463         };
1464 };
1465
1466 #include "rk3568-pinctrl.dtsi"