1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
9 compatible = "rockchip,rk3568";
11 qos_pcie3x1: qos@fe190080 {
12 compatible = "rockchip,rk3568-qos", "syscon";
13 reg = <0x0 0xfe190080 0x0 0x20>;
16 qos_pcie3x2: qos@fe190100 {
17 compatible = "rockchip,rk3568-qos", "syscon";
18 reg = <0x0 0xfe190100 0x0 0x20>;
21 qos_sata0: qos@fe190200 {
22 compatible = "rockchip,rk3568-qos", "syscon";
23 reg = <0x0 0xfe190200 0x0 0x20>;
26 gmac0: ethernet@fe2a0000 {
27 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
28 reg = <0x0 0xfe2a0000 0x0 0x10000>;
29 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
31 interrupt-names = "macirq", "eth_wake_irq";
32 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
33 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
34 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
35 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
37 clock-names = "stmmaceth", "mac_clk_rx",
38 "mac_clk_tx", "clk_mac_refout",
39 "aclk_mac", "pclk_mac",
40 "clk_mac_speed", "ptp_ref",
42 resets = <&cru SRST_A_GMAC0>;
43 reset-names = "stmmaceth";
44 rockchip,grf = <&grf>;
45 snps,axi-config = <&gmac0_stmmac_axi_setup>;
47 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
48 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
53 compatible = "snps,dwmac-mdio";
54 #address-cells = <0x1>;
58 gmac0_stmmac_axi_setup: stmmac-axi-config {
59 snps,blen = <0 0 0 0 16 8 4>;
60 snps,rd_osr_lmt = <8>;
61 snps,wr_osr_lmt = <4>;
64 gmac0_mtl_rx_setup: rx-queues-config {
65 snps,rx-queues-to-use = <1>;
69 gmac0_mtl_tx_setup: tx-queues-config {
70 snps,tx-queues-to-use = <1>;
78 opp-hz = /bits/ 64 <1992000000>;
79 opp-microvolt = <1150000 1150000 1150000>;
84 power-domain@RK3568_PD_PIPE {
85 reg = <RK3568_PD_PIPE>;
86 clocks = <&cru PCLK_PIPE>;
87 pm_qos = <&qos_pcie2x1>,
95 #power-domain-cells = <0>;