1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
75 clocks = <&cru ARMCLKL>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
87 clocks = <&cru ARMCLKL>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
99 clocks = <&cru ARMCLKL>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
111 clocks = <&cru ARMCLKL>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
123 clocks = <&cru ARMCLKB>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 compatible = "arm,cortex-a72";
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 clocks = <&cru ARMCLKB>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <436>;
138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
142 entry-method = "psci";
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
180 compatible = "arm,psci-1.0";
185 compatible = "arm,armv8-timer";
186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
190 arm,no-tick-in-suspend;
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
200 pcie0: pcie@f8000000 {
201 compatible = "rockchip,rk3399-pcie";
202 reg = <0x0 0xf8000000 0x0 0x2000000>,
203 <0x0 0xfd000000 0x0 0x1000000>;
204 reg-names = "axi-base", "apb-base";
206 #address-cells = <3>;
208 #interrupt-cells = <1>;
210 bus-range = <0x0 0x1f>;
211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
213 clock-names = "aclk", "aclk-perf",
215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
218 interrupt-names = "sys", "legacy", "client";
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
221 <0 0 0 2 &pcie0_intc 1>,
222 <0 0 0 3 &pcie0_intc 2>,
223 <0 0 0 4 &pcie0_intc 3>;
224 max-link-speed = <1>;
225 msi-map = <0x0 &its 0x0 0x1000>;
226 phys = <&pcie_phy 0>, <&pcie_phy 1>,
227 <&pcie_phy 2>, <&pcie_phy 3>;
228 phy-names = "pcie-phy-0", "pcie-phy-1",
229 "pcie-phy-2", "pcie-phy-3";
230 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
237 "pm", "pclk", "aclk";
240 pcie0_intc: interrupt-controller {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <1>;
247 gmac: ethernet@fe300000 {
248 compatible = "rockchip,rk3399-gmac";
249 reg = <0x0 0xfe300000 0x0 0x10000>;
250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
251 interrupt-names = "macirq";
252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
256 clock-names = "stmmaceth", "mac_clk_rx",
257 "mac_clk_tx", "clk_mac_ref",
258 "clk_mac_refout", "aclk_mac",
260 power-domains = <&power RK3399_PD_GMAC>;
261 resets = <&cru SRST_A_GMAC>;
262 reset-names = "stmmaceth";
263 rockchip,grf = <&grf>;
268 sdio0: mmc@fe310000 {
269 compatible = "rockchip,rk3399-dw-mshc",
270 "rockchip,rk3288-dw-mshc";
271 reg = <0x0 0xfe310000 0x0 0x4000>;
272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
273 max-frequency = <150000000>;
274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
278 power-domains = <&power RK3399_PD_SDIOAUDIO>;
279 resets = <&cru SRST_SDIO0>;
280 reset-names = "reset";
284 sdmmc: mmc@fe320000 {
285 compatible = "rockchip,rk3399-dw-mshc",
286 "rockchip,rk3288-dw-mshc";
287 reg = <0x0 0xfe320000 0x0 0x4000>;
288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
289 max-frequency = <150000000>;
290 assigned-clocks = <&cru HCLK_SD>;
291 assigned-clock-rates = <200000000>;
292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
296 power-domains = <&power RK3399_PD_SD>;
297 resets = <&cru SRST_SDMMC>;
298 reset-names = "reset";
302 sdhci: mmc@fe330000 {
303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
304 reg = <0x0 0xfe330000 0x0 0x10000>;
305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
306 arasan,soc-ctl-syscon = <&grf>;
307 assigned-clocks = <&cru SCLK_EMMC>;
308 assigned-clock-rates = <200000000>;
309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
310 clock-names = "clk_xin", "clk_ahb";
311 clock-output-names = "emmc_cardclock";
314 phy-names = "phy_arasan";
315 power-domains = <&power RK3399_PD_EMMC>;
320 usb_host0_ehci: usb@fe380000 {
321 compatible = "generic-ehci";
322 reg = <0x0 0xfe380000 0x0 0x20000>;
323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
326 phys = <&u2phy0_host>;
331 usb_host0_ohci: usb@fe3a0000 {
332 compatible = "generic-ohci";
333 reg = <0x0 0xfe3a0000 0x0 0x20000>;
334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
337 phys = <&u2phy0_host>;
342 usb_host1_ehci: usb@fe3c0000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe3c0000 0x0 0x20000>;
345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
348 phys = <&u2phy1_host>;
353 usb_host1_ohci: usb@fe3e0000 {
354 compatible = "generic-ohci";
355 reg = <0x0 0xfe3e0000 0x0 0x20000>;
356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
359 phys = <&u2phy1_host>;
364 usbdrd3_0: usb@fe800000 {
365 compatible = "rockchip,rk3399-dwc3";
366 #address-cells = <2>;
369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
372 clock-names = "ref_clk", "suspend_clk",
373 "bus_clk", "aclk_usb3_rksoc_axi_perf",
374 "aclk_usb3", "grf_clk";
375 resets = <&cru SRST_A_USB3_OTG0>;
376 reset-names = "usb3-otg";
379 usbdrd_dwc3_0: usb@fe800000 {
380 compatible = "snps,dwc3";
381 reg = <0x0 0xfe800000 0x0 0x100000>;
382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
384 <&cru SCLK_USB3OTG0_SUSPEND>;
385 clock-names = "ref", "bus_early", "suspend";
387 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
388 phy-names = "usb2-phy", "usb3-phy";
389 phy_type = "utmi_wide";
390 snps,dis_enblslpm_quirk;
391 snps,dis-u2-freeclk-exists-quirk;
392 snps,dis_u2_susphy_quirk;
393 snps,dis-del-phy-power-chg-quirk;
394 snps,dis-tx-ipgap-linecheck-quirk;
395 power-domains = <&power RK3399_PD_USB3>;
400 usbdrd3_1: usb@fe900000 {
401 compatible = "rockchip,rk3399-dwc3";
402 #address-cells = <2>;
405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
408 clock-names = "ref_clk", "suspend_clk",
409 "bus_clk", "aclk_usb3_rksoc_axi_perf",
410 "aclk_usb3", "grf_clk";
411 resets = <&cru SRST_A_USB3_OTG1>;
412 reset-names = "usb3-otg";
415 usbdrd_dwc3_1: usb@fe900000 {
416 compatible = "snps,dwc3";
417 reg = <0x0 0xfe900000 0x0 0x100000>;
418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
420 <&cru SCLK_USB3OTG1_SUSPEND>;
421 clock-names = "ref", "bus_early", "suspend";
423 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
424 phy-names = "usb2-phy", "usb3-phy";
425 phy_type = "utmi_wide";
426 snps,dis_enblslpm_quirk;
427 snps,dis-u2-freeclk-exists-quirk;
428 snps,dis_u2_susphy_quirk;
429 snps,dis-del-phy-power-chg-quirk;
430 snps,dis-tx-ipgap-linecheck-quirk;
431 power-domains = <&power RK3399_PD_USB3>;
436 cdn_dp: dp@fec00000 {
437 compatible = "rockchip,rk3399-cdn-dp";
438 reg = <0x0 0xfec00000 0x0 0x100000>;
439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
441 assigned-clock-rates = <100000000>, <200000000>;
442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
444 clock-names = "core-clk", "pclk", "spdif", "grf";
445 phys = <&tcphy0_dp>, <&tcphy1_dp>;
446 power-domains = <&power RK3399_PD_HDCP>;
447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
449 reset-names = "spdif", "dptx", "apb", "core";
450 rockchip,grf = <&grf>;
451 #sound-dai-cells = <1>;
456 #address-cells = <1>;
459 dp_in_vopb: endpoint@0 {
461 remote-endpoint = <&vopb_out_dp>;
464 dp_in_vopl: endpoint@1 {
466 remote-endpoint = <&vopl_out_dp>;
472 gic: interrupt-controller@fee00000 {
473 compatible = "arm,gic-v3";
474 #interrupt-cells = <4>;
475 #address-cells = <2>;
478 interrupt-controller;
480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
481 <0x0 0xfef00000 0 0xc0000>, /* GICR */
482 <0x0 0xfff00000 0 0x10000>, /* GICC */
483 <0x0 0xfff10000 0 0x10000>, /* GICH */
484 <0x0 0xfff20000 0 0x10000>; /* GICV */
485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
486 its: interrupt-controller@fee20000 {
487 compatible = "arm,gic-v3-its";
490 reg = <0x0 0xfee20000 0x0 0x20000>;
494 ppi_cluster0: interrupt-partition-0 {
495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
498 ppi_cluster1: interrupt-partition-1 {
499 affinity = <&cpu_b0 &cpu_b1>;
504 saradc: saradc@ff100000 {
505 compatible = "rockchip,rk3399-saradc";
506 reg = <0x0 0xff100000 0x0 0x100>;
507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
508 #io-channel-cells = <1>;
509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
510 clock-names = "saradc", "apb_pclk";
511 resets = <&cru SRST_P_SARADC>;
512 reset-names = "saradc-apb";
517 compatible = "rockchip,rk3399-i2c";
518 reg = <0x0 0xff110000 0x0 0x1000>;
519 assigned-clocks = <&cru SCLK_I2C1>;
520 assigned-clock-rates = <200000000>;
521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
522 clock-names = "i2c", "pclk";
523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c1_xfer>;
526 #address-cells = <1>;
532 compatible = "rockchip,rk3399-i2c";
533 reg = <0x0 0xff120000 0x0 0x1000>;
534 assigned-clocks = <&cru SCLK_I2C2>;
535 assigned-clock-rates = <200000000>;
536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
537 clock-names = "i2c", "pclk";
538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c2_xfer>;
541 #address-cells = <1>;
547 compatible = "rockchip,rk3399-i2c";
548 reg = <0x0 0xff130000 0x0 0x1000>;
549 assigned-clocks = <&cru SCLK_I2C3>;
550 assigned-clock-rates = <200000000>;
551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c3_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff140000 0x0 0x1000>;
564 assigned-clocks = <&cru SCLK_I2C5>;
565 assigned-clock-rates = <200000000>;
566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
567 clock-names = "i2c", "pclk";
568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c5_xfer>;
571 #address-cells = <1>;
577 compatible = "rockchip,rk3399-i2c";
578 reg = <0x0 0xff150000 0x0 0x1000>;
579 assigned-clocks = <&cru SCLK_I2C6>;
580 assigned-clock-rates = <200000000>;
581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
582 clock-names = "i2c", "pclk";
583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c6_xfer>;
586 #address-cells = <1>;
592 compatible = "rockchip,rk3399-i2c";
593 reg = <0x0 0xff160000 0x0 0x1000>;
594 assigned-clocks = <&cru SCLK_I2C7>;
595 assigned-clock-rates = <200000000>;
596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
597 clock-names = "i2c", "pclk";
598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c7_xfer>;
601 #address-cells = <1>;
606 uart0: serial@ff180000 {
607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
608 reg = <0x0 0xff180000 0x0 0x100>;
609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
610 clock-names = "baudclk", "apb_pclk";
611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&uart0_xfer>;
619 uart1: serial@ff190000 {
620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
621 reg = <0x0 0xff190000 0x0 0x100>;
622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
623 clock-names = "baudclk", "apb_pclk";
624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&uart1_xfer>;
632 uart2: serial@ff1a0000 {
633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
634 reg = <0x0 0xff1a0000 0x0 0x100>;
635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
636 clock-names = "baudclk", "apb_pclk";
637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart2c_xfer>;
645 uart3: serial@ff1b0000 {
646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
647 reg = <0x0 0xff1b0000 0x0 0x100>;
648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
649 clock-names = "baudclk", "apb_pclk";
650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&uart3_xfer>;
659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
660 reg = <0x0 0xff1c0000 0x0 0x1000>;
661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
662 clock-names = "spiclk", "apb_pclk";
663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
664 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
665 dma-names = "tx", "rx";
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
668 #address-cells = <1>;
674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
675 reg = <0x0 0xff1d0000 0x0 0x1000>;
676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
677 clock-names = "spiclk", "apb_pclk";
678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
679 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
680 dma-names = "tx", "rx";
681 pinctrl-names = "default";
682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
683 #address-cells = <1>;
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
690 reg = <0x0 0xff1e0000 0x0 0x1000>;
691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
692 clock-names = "spiclk", "apb_pclk";
693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
694 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
695 dma-names = "tx", "rx";
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
698 #address-cells = <1>;
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1f0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
707 clock-names = "spiclk", "apb_pclk";
708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
709 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
710 dma-names = "tx", "rx";
711 pinctrl-names = "default";
712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
713 #address-cells = <1>;
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
720 reg = <0x0 0xff200000 0x0 0x1000>;
721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
722 clock-names = "spiclk", "apb_pclk";
723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
724 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
725 dma-names = "tx", "rx";
726 pinctrl-names = "default";
727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
728 power-domains = <&power RK3399_PD_SDIOAUDIO>;
729 #address-cells = <1>;
734 thermal_zones: thermal-zones {
735 cpu_thermal: cpu-thermal {
736 polling-delay-passive = <100>;
737 polling-delay = <1000>;
739 thermal-sensors = <&tsadc 0>;
742 cpu_alert0: cpu_alert0 {
743 temperature = <70000>;
747 cpu_alert1: cpu_alert1 {
748 temperature = <75000>;
753 temperature = <95000>;
761 trip = <&cpu_alert0>;
763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
767 trip = <&cpu_alert1>;
769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 gpu_thermal: gpu-thermal {
780 polling-delay-passive = <100>;
781 polling-delay = <1000>;
783 thermal-sensors = <&tsadc 1>;
786 gpu_alert0: gpu_alert0 {
787 temperature = <75000>;
792 temperature = <95000>;
800 trip = <&gpu_alert0>;
802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
808 tsadc: tsadc@ff260000 {
809 compatible = "rockchip,rk3399-tsadc";
810 reg = <0x0 0xff260000 0x0 0x100>;
811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
812 assigned-clocks = <&cru SCLK_TSADC>;
813 assigned-clock-rates = <750000>;
814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
815 clock-names = "tsadc", "apb_pclk";
816 resets = <&cru SRST_TSADC>;
817 reset-names = "tsadc-apb";
818 rockchip,grf = <&grf>;
819 rockchip,hw-tshut-temp = <95000>;
820 pinctrl-names = "init", "default", "sleep";
821 pinctrl-0 = <&otp_pin>;
822 pinctrl-1 = <&otp_out>;
823 pinctrl-2 = <&otp_pin>;
824 #thermal-sensor-cells = <1>;
828 qos_emmc: qos@ffa58000 {
829 compatible = "rockchip,rk3399-qos", "syscon";
830 reg = <0x0 0xffa58000 0x0 0x20>;
833 qos_gmac: qos@ffa5c000 {
834 compatible = "rockchip,rk3399-qos", "syscon";
835 reg = <0x0 0xffa5c000 0x0 0x20>;
838 qos_pcie: qos@ffa60080 {
839 compatible = "rockchip,rk3399-qos", "syscon";
840 reg = <0x0 0xffa60080 0x0 0x20>;
843 qos_usb_host0: qos@ffa60100 {
844 compatible = "rockchip,rk3399-qos", "syscon";
845 reg = <0x0 0xffa60100 0x0 0x20>;
848 qos_usb_host1: qos@ffa60180 {
849 compatible = "rockchip,rk3399-qos", "syscon";
850 reg = <0x0 0xffa60180 0x0 0x20>;
853 qos_usb_otg0: qos@ffa70000 {
854 compatible = "rockchip,rk3399-qos", "syscon";
855 reg = <0x0 0xffa70000 0x0 0x20>;
858 qos_usb_otg1: qos@ffa70080 {
859 compatible = "rockchip,rk3399-qos", "syscon";
860 reg = <0x0 0xffa70080 0x0 0x20>;
863 qos_sd: qos@ffa74000 {
864 compatible = "rockchip,rk3399-qos", "syscon";
865 reg = <0x0 0xffa74000 0x0 0x20>;
868 qos_sdioaudio: qos@ffa76000 {
869 compatible = "rockchip,rk3399-qos", "syscon";
870 reg = <0x0 0xffa76000 0x0 0x20>;
873 qos_hdcp: qos@ffa90000 {
874 compatible = "rockchip,rk3399-qos", "syscon";
875 reg = <0x0 0xffa90000 0x0 0x20>;
878 qos_iep: qos@ffa98000 {
879 compatible = "rockchip,rk3399-qos", "syscon";
880 reg = <0x0 0xffa98000 0x0 0x20>;
883 qos_isp0_m0: qos@ffaa0000 {
884 compatible = "rockchip,rk3399-qos", "syscon";
885 reg = <0x0 0xffaa0000 0x0 0x20>;
888 qos_isp0_m1: qos@ffaa0080 {
889 compatible = "rockchip,rk3399-qos", "syscon";
890 reg = <0x0 0xffaa0080 0x0 0x20>;
893 qos_isp1_m0: qos@ffaa8000 {
894 compatible = "rockchip,rk3399-qos", "syscon";
895 reg = <0x0 0xffaa8000 0x0 0x20>;
898 qos_isp1_m1: qos@ffaa8080 {
899 compatible = "rockchip,rk3399-qos", "syscon";
900 reg = <0x0 0xffaa8080 0x0 0x20>;
903 qos_rga_r: qos@ffab0000 {
904 compatible = "rockchip,rk3399-qos", "syscon";
905 reg = <0x0 0xffab0000 0x0 0x20>;
908 qos_rga_w: qos@ffab0080 {
909 compatible = "rockchip,rk3399-qos", "syscon";
910 reg = <0x0 0xffab0080 0x0 0x20>;
913 qos_video_m0: qos@ffab8000 {
914 compatible = "rockchip,rk3399-qos", "syscon";
915 reg = <0x0 0xffab8000 0x0 0x20>;
918 qos_video_m1_r: qos@ffac0000 {
919 compatible = "rockchip,rk3399-qos", "syscon";
920 reg = <0x0 0xffac0000 0x0 0x20>;
923 qos_video_m1_w: qos@ffac0080 {
924 compatible = "rockchip,rk3399-qos", "syscon";
925 reg = <0x0 0xffac0080 0x0 0x20>;
928 qos_vop_big_r: qos@ffac8000 {
929 compatible = "rockchip,rk3399-qos", "syscon";
930 reg = <0x0 0xffac8000 0x0 0x20>;
933 qos_vop_big_w: qos@ffac8080 {
934 compatible = "rockchip,rk3399-qos", "syscon";
935 reg = <0x0 0xffac8080 0x0 0x20>;
938 qos_vop_little: qos@ffad0000 {
939 compatible = "rockchip,rk3399-qos", "syscon";
940 reg = <0x0 0xffad0000 0x0 0x20>;
943 qos_perihp: qos@ffad8080 {
944 compatible = "rockchip,rk3399-qos", "syscon";
945 reg = <0x0 0xffad8080 0x0 0x20>;
948 qos_gpu: qos@ffae0000 {
949 compatible = "rockchip,rk3399-qos", "syscon";
950 reg = <0x0 0xffae0000 0x0 0x20>;
953 pmu: power-management@ff310000 {
954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
955 reg = <0x0 0xff310000 0x0 0x1000>;
958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
960 * Some of the power domains are grouped together for every
962 * The detail contents as below.
964 power: power-controller {
965 compatible = "rockchip,rk3399-power-controller";
966 #power-domain-cells = <1>;
967 #address-cells = <1>;
970 /* These power domains are grouped by VD_CENTER */
971 power-domain@RK3399_PD_IEP {
972 reg = <RK3399_PD_IEP>;
973 clocks = <&cru ACLK_IEP>,
976 #power-domain-cells = <0>;
978 power-domain@RK3399_PD_RGA {
979 reg = <RK3399_PD_RGA>;
980 clocks = <&cru ACLK_RGA>,
982 pm_qos = <&qos_rga_r>,
984 #power-domain-cells = <0>;
986 power-domain@RK3399_PD_VCODEC {
987 reg = <RK3399_PD_VCODEC>;
988 clocks = <&cru ACLK_VCODEC>,
990 pm_qos = <&qos_video_m0>;
991 #power-domain-cells = <0>;
993 power-domain@RK3399_PD_VDU {
994 reg = <RK3399_PD_VDU>;
995 clocks = <&cru ACLK_VDU>,
997 pm_qos = <&qos_video_m1_r>,
999 #power-domain-cells = <0>;
1002 /* These power domains are grouped by VD_GPU */
1003 power-domain@RK3399_PD_GPU {
1004 reg = <RK3399_PD_GPU>;
1005 clocks = <&cru ACLK_GPU>;
1006 pm_qos = <&qos_gpu>;
1007 #power-domain-cells = <0>;
1010 /* These power domains are grouped by VD_LOGIC */
1011 power-domain@RK3399_PD_EDP {
1012 reg = <RK3399_PD_EDP>;
1013 clocks = <&cru PCLK_EDP_CTRL>;
1014 #power-domain-cells = <0>;
1016 power-domain@RK3399_PD_EMMC {
1017 reg = <RK3399_PD_EMMC>;
1018 clocks = <&cru ACLK_EMMC>;
1019 pm_qos = <&qos_emmc>;
1020 #power-domain-cells = <0>;
1022 power-domain@RK3399_PD_GMAC {
1023 reg = <RK3399_PD_GMAC>;
1024 clocks = <&cru ACLK_GMAC>,
1026 pm_qos = <&qos_gmac>;
1027 #power-domain-cells = <0>;
1029 power-domain@RK3399_PD_SD {
1030 reg = <RK3399_PD_SD>;
1031 clocks = <&cru HCLK_SDMMC>,
1034 #power-domain-cells = <0>;
1036 power-domain@RK3399_PD_SDIOAUDIO {
1037 reg = <RK3399_PD_SDIOAUDIO>;
1038 clocks = <&cru HCLK_SDIO>;
1039 pm_qos = <&qos_sdioaudio>;
1040 #power-domain-cells = <0>;
1042 power-domain@RK3399_PD_TCPD0 {
1043 reg = <RK3399_PD_TCPD0>;
1044 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1045 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1046 #power-domain-cells = <0>;
1048 power-domain@RK3399_PD_TCPD1 {
1049 reg = <RK3399_PD_TCPD1>;
1050 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1051 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1052 #power-domain-cells = <0>;
1054 power-domain@RK3399_PD_USB3 {
1055 reg = <RK3399_PD_USB3>;
1056 clocks = <&cru ACLK_USB3>;
1057 pm_qos = <&qos_usb_otg0>,
1059 #power-domain-cells = <0>;
1061 power-domain@RK3399_PD_VIO {
1062 reg = <RK3399_PD_VIO>;
1063 #power-domain-cells = <1>;
1064 #address-cells = <1>;
1067 power-domain@RK3399_PD_HDCP {
1068 reg = <RK3399_PD_HDCP>;
1069 clocks = <&cru ACLK_HDCP>,
1072 pm_qos = <&qos_hdcp>;
1073 #power-domain-cells = <0>;
1075 power-domain@RK3399_PD_ISP0 {
1076 reg = <RK3399_PD_ISP0>;
1077 clocks = <&cru ACLK_ISP0>,
1079 pm_qos = <&qos_isp0_m0>,
1081 #power-domain-cells = <0>;
1083 power-domain@RK3399_PD_ISP1 {
1084 reg = <RK3399_PD_ISP1>;
1085 clocks = <&cru ACLK_ISP1>,
1087 pm_qos = <&qos_isp1_m0>,
1089 #power-domain-cells = <0>;
1091 power-domain@RK3399_PD_VO {
1092 reg = <RK3399_PD_VO>;
1093 #power-domain-cells = <1>;
1094 #address-cells = <1>;
1097 power-domain@RK3399_PD_VOPB {
1098 reg = <RK3399_PD_VOPB>;
1099 clocks = <&cru ACLK_VOP0>,
1101 pm_qos = <&qos_vop_big_r>,
1103 #power-domain-cells = <0>;
1105 power-domain@RK3399_PD_VOPL {
1106 reg = <RK3399_PD_VOPL>;
1107 clocks = <&cru ACLK_VOP1>,
1109 pm_qos = <&qos_vop_little>;
1110 #power-domain-cells = <0>;
1117 pmugrf: syscon@ff320000 {
1118 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1119 reg = <0x0 0xff320000 0x0 0x1000>;
1121 pmu_io_domains: io-domains {
1122 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1123 status = "disabled";
1127 spi3: spi@ff350000 {
1128 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1129 reg = <0x0 0xff350000 0x0 0x1000>;
1130 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1131 clock-names = "spiclk", "apb_pclk";
1132 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1135 #address-cells = <1>;
1137 status = "disabled";
1140 uart4: serial@ff370000 {
1141 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1142 reg = <0x0 0xff370000 0x0 0x100>;
1143 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1144 clock-names = "baudclk", "apb_pclk";
1145 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&uart4_xfer>;
1150 status = "disabled";
1153 i2c0: i2c@ff3c0000 {
1154 compatible = "rockchip,rk3399-i2c";
1155 reg = <0x0 0xff3c0000 0x0 0x1000>;
1156 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1157 assigned-clock-rates = <200000000>;
1158 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1159 clock-names = "i2c", "pclk";
1160 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c0_xfer>;
1163 #address-cells = <1>;
1165 status = "disabled";
1168 i2c4: i2c@ff3d0000 {
1169 compatible = "rockchip,rk3399-i2c";
1170 reg = <0x0 0xff3d0000 0x0 0x1000>;
1171 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1172 assigned-clock-rates = <200000000>;
1173 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1174 clock-names = "i2c", "pclk";
1175 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&i2c4_xfer>;
1178 #address-cells = <1>;
1180 status = "disabled";
1183 i2c8: i2c@ff3e0000 {
1184 compatible = "rockchip,rk3399-i2c";
1185 reg = <0x0 0xff3e0000 0x0 0x1000>;
1186 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1187 assigned-clock-rates = <200000000>;
1188 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1189 clock-names = "i2c", "pclk";
1190 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1191 pinctrl-names = "default";
1192 pinctrl-0 = <&i2c8_xfer>;
1193 #address-cells = <1>;
1195 status = "disabled";
1198 pwm0: pwm@ff420000 {
1199 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1200 reg = <0x0 0xff420000 0x0 0x10>;
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&pwm0_pin>;
1204 clocks = <&pmucru PCLK_RKPWM_PMU>;
1205 status = "disabled";
1208 pwm1: pwm@ff420010 {
1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1210 reg = <0x0 0xff420010 0x0 0x10>;
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pwm1_pin>;
1214 clocks = <&pmucru PCLK_RKPWM_PMU>;
1215 status = "disabled";
1218 pwm2: pwm@ff420020 {
1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220 reg = <0x0 0xff420020 0x0 0x10>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&pwm2_pin>;
1224 clocks = <&pmucru PCLK_RKPWM_PMU>;
1225 status = "disabled";
1228 pwm3: pwm@ff420030 {
1229 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1230 reg = <0x0 0xff420030 0x0 0x10>;
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&pwm3a_pin>;
1234 clocks = <&pmucru PCLK_RKPWM_PMU>;
1235 status = "disabled";
1238 vpu: video-codec@ff650000 {
1239 compatible = "rockchip,rk3399-vpu";
1240 reg = <0x0 0xff650000 0x0 0x800>;
1241 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1242 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1243 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1244 clock-names = "aclk", "hclk";
1245 iommus = <&vpu_mmu>;
1246 power-domains = <&power RK3399_PD_VCODEC>;
1249 vpu_mmu: iommu@ff650800 {
1250 compatible = "rockchip,iommu";
1251 reg = <0x0 0xff650800 0x0 0x40>;
1252 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1253 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1254 clock-names = "aclk", "iface";
1256 power-domains = <&power RK3399_PD_VCODEC>;
1259 vdec: video-codec@ff660000 {
1260 compatible = "rockchip,rk3399-vdec";
1261 reg = <0x0 0xff660000 0x0 0x400>;
1262 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1263 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1264 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1265 clock-names = "axi", "ahb", "cabac", "core";
1266 iommus = <&vdec_mmu>;
1267 power-domains = <&power RK3399_PD_VDU>;
1270 vdec_mmu: iommu@ff660480 {
1271 compatible = "rockchip,iommu";
1272 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1273 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1274 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1275 clock-names = "aclk", "iface";
1276 power-domains = <&power RK3399_PD_VDU>;
1280 iep_mmu: iommu@ff670800 {
1281 compatible = "rockchip,iommu";
1282 reg = <0x0 0xff670800 0x0 0x40>;
1283 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1284 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1285 clock-names = "aclk", "iface";
1287 status = "disabled";
1291 compatible = "rockchip,rk3399-rga";
1292 reg = <0x0 0xff680000 0x0 0x10000>;
1293 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1294 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1295 clock-names = "aclk", "hclk", "sclk";
1296 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1297 reset-names = "core", "axi", "ahb";
1298 power-domains = <&power RK3399_PD_RGA>;
1301 efuse0: efuse@ff690000 {
1302 compatible = "rockchip,rk3399-efuse";
1303 reg = <0x0 0xff690000 0x0 0x80>;
1304 #address-cells = <1>;
1306 clocks = <&cru PCLK_EFUSE1024NS>;
1307 clock-names = "pclk_efuse";
1313 cpub_leakage: cpu-leakage@17 {
1316 gpu_leakage: gpu-leakage@18 {
1319 center_leakage: center-leakage@19 {
1322 cpul_leakage: cpu-leakage@1a {
1325 logic_leakage: logic-leakage@1b {
1328 wafer_info: wafer-info@1c {
1333 dmac_bus: dma-controller@ff6d0000 {
1334 compatible = "arm,pl330", "arm,primecell";
1335 reg = <0x0 0xff6d0000 0x0 0x4000>;
1336 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1337 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1339 arm,pl330-periph-burst;
1340 clocks = <&cru ACLK_DMAC0_PERILP>;
1341 clock-names = "apb_pclk";
1344 dmac_peri: dma-controller@ff6e0000 {
1345 compatible = "arm,pl330", "arm,primecell";
1346 reg = <0x0 0xff6e0000 0x0 0x4000>;
1347 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1348 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1350 arm,pl330-periph-burst;
1351 clocks = <&cru ACLK_DMAC1_PERILP>;
1352 clock-names = "apb_pclk";
1355 pmucru: pmu-clock-controller@ff750000 {
1356 compatible = "rockchip,rk3399-pmucru";
1357 reg = <0x0 0xff750000 0x0 0x1000>;
1358 rockchip,grf = <&pmugrf>;
1361 assigned-clocks = <&pmucru PLL_PPLL>;
1362 assigned-clock-rates = <676000000>;
1365 cru: clock-controller@ff760000 {
1366 compatible = "rockchip,rk3399-cru";
1367 reg = <0x0 0xff760000 0x0 0x1000>;
1368 rockchip,grf = <&grf>;
1372 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1374 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1376 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1377 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1378 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1379 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1380 <&cru ACLK_GIC_PRE>,
1382 assigned-clock-rates =
1383 <594000000>, <800000000>,
1385 <150000000>, <75000000>,
1387 <100000000>, <100000000>,
1388 <50000000>, <600000000>,
1389 <100000000>, <50000000>,
1390 <400000000>, <400000000>,
1395 grf: syscon@ff770000 {
1396 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1397 reg = <0x0 0xff770000 0x0 0x10000>;
1398 #address-cells = <1>;
1401 io_domains: io-domains {
1402 compatible = "rockchip,rk3399-io-voltage-domain";
1403 status = "disabled";
1406 mipi_dphy_rx0: mipi-dphy-rx0 {
1407 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1408 clocks = <&cru SCLK_MIPIDPHY_REF>,
1409 <&cru SCLK_DPHY_RX0_CFG>,
1410 <&cru PCLK_VIO_GRF>;
1411 clock-names = "dphy-ref", "dphy-cfg", "grf";
1412 power-domains = <&power RK3399_PD_VIO>;
1414 status = "disabled";
1417 u2phy0: usb2phy@e450 {
1418 compatible = "rockchip,rk3399-usb2phy";
1419 reg = <0xe450 0x10>;
1420 clocks = <&cru SCLK_USB2PHY0_REF>;
1421 clock-names = "phyclk";
1423 clock-output-names = "clk_usbphy0_480m";
1424 status = "disabled";
1426 u2phy0_host: host-port {
1428 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1429 interrupt-names = "linestate";
1430 status = "disabled";
1433 u2phy0_otg: otg-port {
1435 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1436 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1437 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1438 interrupt-names = "otg-bvalid", "otg-id",
1440 status = "disabled";
1444 u2phy1: usb2phy@e460 {
1445 compatible = "rockchip,rk3399-usb2phy";
1446 reg = <0xe460 0x10>;
1447 clocks = <&cru SCLK_USB2PHY1_REF>;
1448 clock-names = "phyclk";
1450 clock-output-names = "clk_usbphy1_480m";
1451 status = "disabled";
1453 u2phy1_host: host-port {
1455 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1456 interrupt-names = "linestate";
1457 status = "disabled";
1460 u2phy1_otg: otg-port {
1462 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1463 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1464 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1465 interrupt-names = "otg-bvalid", "otg-id",
1467 status = "disabled";
1471 emmc_phy: phy@f780 {
1472 compatible = "rockchip,rk3399-emmc-phy";
1473 reg = <0xf780 0x24>;
1475 clock-names = "emmcclk";
1477 status = "disabled";
1480 pcie_phy: pcie-phy {
1481 compatible = "rockchip,rk3399-pcie-phy";
1482 clocks = <&cru SCLK_PCIEPHY_REF>;
1483 clock-names = "refclk";
1485 resets = <&cru SRST_PCIEPHY>;
1486 drive-impedance-ohm = <50>;
1487 reset-names = "phy";
1488 status = "disabled";
1492 tcphy0: phy@ff7c0000 {
1493 compatible = "rockchip,rk3399-typec-phy";
1494 reg = <0x0 0xff7c0000 0x0 0x40000>;
1495 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1496 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1497 clock-names = "tcpdcore", "tcpdphy-ref";
1498 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1499 assigned-clock-rates = <50000000>;
1500 power-domains = <&power RK3399_PD_TCPD0>;
1501 resets = <&cru SRST_UPHY0>,
1502 <&cru SRST_UPHY0_PIPE_L00>,
1503 <&cru SRST_P_UPHY0_TCPHY>;
1504 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1505 rockchip,grf = <&grf>;
1506 status = "disabled";
1508 tcphy0_dp: dp-port {
1512 tcphy0_usb3: usb3-port {
1517 tcphy1: phy@ff800000 {
1518 compatible = "rockchip,rk3399-typec-phy";
1519 reg = <0x0 0xff800000 0x0 0x40000>;
1520 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1521 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1522 clock-names = "tcpdcore", "tcpdphy-ref";
1523 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1524 assigned-clock-rates = <50000000>;
1525 power-domains = <&power RK3399_PD_TCPD1>;
1526 resets = <&cru SRST_UPHY1>,
1527 <&cru SRST_UPHY1_PIPE_L00>,
1528 <&cru SRST_P_UPHY1_TCPHY>;
1529 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1530 rockchip,grf = <&grf>;
1531 status = "disabled";
1533 tcphy1_dp: dp-port {
1537 tcphy1_usb3: usb3-port {
1543 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1544 reg = <0x0 0xff848000 0x0 0x100>;
1545 clocks = <&cru PCLK_WDT>;
1546 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1549 rktimer: rktimer@ff850000 {
1550 compatible = "rockchip,rk3399-timer";
1551 reg = <0x0 0xff850000 0x0 0x1000>;
1552 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1553 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1554 clock-names = "pclk", "timer";
1557 spdif: spdif@ff870000 {
1558 compatible = "rockchip,rk3399-spdif";
1559 reg = <0x0 0xff870000 0x0 0x1000>;
1560 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1561 dmas = <&dmac_bus 7>;
1563 clock-names = "mclk", "hclk";
1564 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&spdif_bus>;
1567 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1568 #sound-dai-cells = <0>;
1569 status = "disabled";
1572 i2s0: i2s@ff880000 {
1573 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1574 reg = <0x0 0xff880000 0x0 0x1000>;
1575 rockchip,grf = <&grf>;
1576 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1577 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1578 dma-names = "tx", "rx";
1579 clock-names = "i2s_clk", "i2s_hclk";
1580 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&i2s0_8ch_bus>;
1583 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1584 #sound-dai-cells = <0>;
1585 status = "disabled";
1588 i2s1: i2s@ff890000 {
1589 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1590 reg = <0x0 0xff890000 0x0 0x1000>;
1591 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1592 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1593 dma-names = "tx", "rx";
1594 clock-names = "i2s_clk", "i2s_hclk";
1595 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1596 pinctrl-names = "default";
1597 pinctrl-0 = <&i2s1_2ch_bus>;
1598 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1599 #sound-dai-cells = <0>;
1600 status = "disabled";
1603 i2s2: i2s@ff8a0000 {
1604 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1605 reg = <0x0 0xff8a0000 0x0 0x1000>;
1606 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1607 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1608 dma-names = "tx", "rx";
1609 clock-names = "i2s_clk", "i2s_hclk";
1610 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1611 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1612 #sound-dai-cells = <0>;
1613 status = "disabled";
1616 vopl: vop@ff8f0000 {
1617 compatible = "rockchip,rk3399-vop-lit";
1618 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1619 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1620 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1621 assigned-clock-rates = <400000000>, <100000000>;
1622 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1623 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1624 iommus = <&vopl_mmu>;
1625 power-domains = <&power RK3399_PD_VOPL>;
1626 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1627 reset-names = "axi", "ahb", "dclk";
1628 status = "disabled";
1631 #address-cells = <1>;
1634 vopl_out_mipi: endpoint@0 {
1636 remote-endpoint = <&mipi_in_vopl>;
1639 vopl_out_edp: endpoint@1 {
1641 remote-endpoint = <&edp_in_vopl>;
1644 vopl_out_hdmi: endpoint@2 {
1646 remote-endpoint = <&hdmi_in_vopl>;
1649 vopl_out_mipi1: endpoint@3 {
1651 remote-endpoint = <&mipi1_in_vopl>;
1654 vopl_out_dp: endpoint@4 {
1656 remote-endpoint = <&dp_in_vopl>;
1661 vopl_mmu: iommu@ff8f3f00 {
1662 compatible = "rockchip,iommu";
1663 reg = <0x0 0xff8f3f00 0x0 0x100>;
1664 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1665 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1666 clock-names = "aclk", "iface";
1667 power-domains = <&power RK3399_PD_VOPL>;
1669 status = "disabled";
1672 vopb: vop@ff900000 {
1673 compatible = "rockchip,rk3399-vop-big";
1674 reg = <0x0 0xff900000 0x0 0x3efc>;
1675 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1676 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1677 assigned-clock-rates = <400000000>, <100000000>;
1678 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1679 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1680 iommus = <&vopb_mmu>;
1681 power-domains = <&power RK3399_PD_VOPB>;
1682 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1683 reset-names = "axi", "ahb", "dclk";
1684 status = "disabled";
1687 #address-cells = <1>;
1690 vopb_out_edp: endpoint@0 {
1692 remote-endpoint = <&edp_in_vopb>;
1695 vopb_out_mipi: endpoint@1 {
1697 remote-endpoint = <&mipi_in_vopb>;
1700 vopb_out_hdmi: endpoint@2 {
1702 remote-endpoint = <&hdmi_in_vopb>;
1705 vopb_out_mipi1: endpoint@3 {
1707 remote-endpoint = <&mipi1_in_vopb>;
1710 vopb_out_dp: endpoint@4 {
1712 remote-endpoint = <&dp_in_vopb>;
1717 vopb_mmu: iommu@ff903f00 {
1718 compatible = "rockchip,iommu";
1719 reg = <0x0 0xff903f00 0x0 0x100>;
1720 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1721 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1722 clock-names = "aclk", "iface";
1723 power-domains = <&power RK3399_PD_VOPB>;
1725 status = "disabled";
1728 isp0: isp0@ff910000 {
1729 compatible = "rockchip,rk3399-cif-isp";
1730 reg = <0x0 0xff910000 0x0 0x4000>;
1731 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1732 clocks = <&cru SCLK_ISP0>,
1733 <&cru ACLK_ISP0_WRAPPER>,
1734 <&cru HCLK_ISP0_WRAPPER>;
1735 clock-names = "isp", "aclk", "hclk";
1736 iommus = <&isp0_mmu>;
1737 phys = <&mipi_dphy_rx0>;
1739 power-domains = <&power RK3399_PD_ISP0>;
1740 status = "disabled";
1743 #address-cells = <1>;
1748 #address-cells = <1>;
1754 isp0_mmu: iommu@ff914000 {
1755 compatible = "rockchip,iommu";
1756 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1757 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1758 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1759 clock-names = "aclk", "iface";
1761 power-domains = <&power RK3399_PD_ISP0>;
1762 rockchip,disable-mmu-reset;
1765 isp1_mmu: iommu@ff924000 {
1766 compatible = "rockchip,iommu";
1767 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1768 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1769 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1770 clock-names = "aclk", "iface";
1772 power-domains = <&power RK3399_PD_ISP1>;
1773 rockchip,disable-mmu-reset;
1776 hdmi_sound: hdmi-sound {
1777 compatible = "simple-audio-card";
1778 simple-audio-card,format = "i2s";
1779 simple-audio-card,mclk-fs = <256>;
1780 simple-audio-card,name = "hdmi-sound";
1781 status = "disabled";
1783 simple-audio-card,cpu {
1784 sound-dai = <&i2s2>;
1786 simple-audio-card,codec {
1787 sound-dai = <&hdmi>;
1791 hdmi: hdmi@ff940000 {
1792 compatible = "rockchip,rk3399-dw-hdmi";
1793 reg = <0x0 0xff940000 0x0 0x20000>;
1794 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1795 clocks = <&cru PCLK_HDMI_CTRL>,
1796 <&cru SCLK_HDMI_SFR>,
1798 <&cru PCLK_VIO_GRF>,
1799 <&cru SCLK_HDMI_CEC>;
1800 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1801 power-domains = <&power RK3399_PD_HDCP>;
1803 rockchip,grf = <&grf>;
1804 #sound-dai-cells = <0>;
1805 status = "disabled";
1809 #address-cells = <1>;
1812 hdmi_in_vopb: endpoint@0 {
1814 remote-endpoint = <&vopb_out_hdmi>;
1816 hdmi_in_vopl: endpoint@1 {
1818 remote-endpoint = <&vopl_out_hdmi>;
1824 mipi_dsi: mipi@ff960000 {
1825 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1826 reg = <0x0 0xff960000 0x0 0x8000>;
1827 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1828 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1829 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1830 clock-names = "ref", "pclk", "phy_cfg", "grf";
1831 power-domains = <&power RK3399_PD_VIO>;
1832 resets = <&cru SRST_P_MIPI_DSI0>;
1833 reset-names = "apb";
1834 rockchip,grf = <&grf>;
1835 #address-cells = <1>;
1837 status = "disabled";
1840 #address-cells = <1>;
1845 #address-cells = <1>;
1848 mipi_in_vopb: endpoint@0 {
1850 remote-endpoint = <&vopb_out_mipi>;
1852 mipi_in_vopl: endpoint@1 {
1854 remote-endpoint = <&vopl_out_mipi>;
1860 mipi_dsi1: mipi@ff968000 {
1861 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1862 reg = <0x0 0xff968000 0x0 0x8000>;
1863 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1864 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1865 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1866 clock-names = "ref", "pclk", "phy_cfg", "grf";
1867 power-domains = <&power RK3399_PD_VIO>;
1868 resets = <&cru SRST_P_MIPI_DSI1>;
1869 reset-names = "apb";
1870 rockchip,grf = <&grf>;
1871 #address-cells = <1>;
1874 status = "disabled";
1877 #address-cells = <1>;
1882 #address-cells = <1>;
1885 mipi1_in_vopb: endpoint@0 {
1887 remote-endpoint = <&vopb_out_mipi1>;
1890 mipi1_in_vopl: endpoint@1 {
1892 remote-endpoint = <&vopl_out_mipi1>;
1899 compatible = "rockchip,rk3399-edp";
1900 reg = <0x0 0xff970000 0x0 0x8000>;
1901 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1902 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1903 clock-names = "dp", "pclk", "grf";
1904 pinctrl-names = "default";
1905 pinctrl-0 = <&edp_hpd>;
1906 power-domains = <&power RK3399_PD_EDP>;
1907 resets = <&cru SRST_P_EDP_CTRL>;
1909 rockchip,grf = <&grf>;
1910 status = "disabled";
1913 #address-cells = <1>;
1917 #address-cells = <1>;
1920 edp_in_vopb: endpoint@0 {
1922 remote-endpoint = <&vopb_out_edp>;
1925 edp_in_vopl: endpoint@1 {
1927 remote-endpoint = <&vopl_out_edp>;
1934 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1935 reg = <0x0 0xff9a0000 0x0 0x10000>;
1936 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1937 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1938 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1939 interrupt-names = "job", "mmu", "gpu";
1940 clocks = <&cru ACLK_GPU>;
1941 #cooling-cells = <2>;
1942 power-domains = <&power RK3399_PD_GPU>;
1943 status = "disabled";
1947 compatible = "rockchip,rk3399-pinctrl";
1948 rockchip,grf = <&grf>;
1949 rockchip,pmu = <&pmugrf>;
1950 #address-cells = <2>;
1954 gpio0: gpio0@ff720000 {
1955 compatible = "rockchip,gpio-bank";
1956 reg = <0x0 0xff720000 0x0 0x100>;
1957 clocks = <&pmucru PCLK_GPIO0_PMU>;
1958 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1961 #gpio-cells = <0x2>;
1963 interrupt-controller;
1964 #interrupt-cells = <0x2>;
1967 gpio1: gpio1@ff730000 {
1968 compatible = "rockchip,gpio-bank";
1969 reg = <0x0 0xff730000 0x0 0x100>;
1970 clocks = <&pmucru PCLK_GPIO1_PMU>;
1971 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1974 #gpio-cells = <0x2>;
1976 interrupt-controller;
1977 #interrupt-cells = <0x2>;
1980 gpio2: gpio2@ff780000 {
1981 compatible = "rockchip,gpio-bank";
1982 reg = <0x0 0xff780000 0x0 0x100>;
1983 clocks = <&cru PCLK_GPIO2>;
1984 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1987 #gpio-cells = <0x2>;
1989 interrupt-controller;
1990 #interrupt-cells = <0x2>;
1993 gpio3: gpio3@ff788000 {
1994 compatible = "rockchip,gpio-bank";
1995 reg = <0x0 0xff788000 0x0 0x100>;
1996 clocks = <&cru PCLK_GPIO3>;
1997 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2000 #gpio-cells = <0x2>;
2002 interrupt-controller;
2003 #interrupt-cells = <0x2>;
2006 gpio4: gpio4@ff790000 {
2007 compatible = "rockchip,gpio-bank";
2008 reg = <0x0 0xff790000 0x0 0x100>;
2009 clocks = <&cru PCLK_GPIO4>;
2010 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2013 #gpio-cells = <0x2>;
2015 interrupt-controller;
2016 #interrupt-cells = <0x2>;
2019 pcfg_pull_up: pcfg-pull-up {
2023 pcfg_pull_down: pcfg-pull-down {
2027 pcfg_pull_none: pcfg-pull-none {
2031 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2033 drive-strength = <12>;
2036 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2038 drive-strength = <13>;
2041 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2043 drive-strength = <18>;
2046 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2048 drive-strength = <20>;
2051 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2053 drive-strength = <2>;
2056 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2058 drive-strength = <8>;
2061 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2063 drive-strength = <18>;
2066 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2068 drive-strength = <20>;
2071 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2073 drive-strength = <4>;
2076 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2078 drive-strength = <8>;
2081 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2083 drive-strength = <12>;
2086 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2088 drive-strength = <18>;
2091 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2093 drive-strength = <20>;
2096 pcfg_output_high: pcfg-output-high {
2100 pcfg_output_low: pcfg-output-low {
2106 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2113 <4 RK_PC7 2 &pcfg_pull_none>;
2118 rgmii_pins: rgmii-pins {
2121 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2123 <3 RK_PB6 1 &pcfg_pull_none>,
2125 <3 RK_PB5 1 &pcfg_pull_none>,
2127 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2129 <3 RK_PB3 1 &pcfg_pull_none>,
2131 <3 RK_PB1 1 &pcfg_pull_none>,
2133 <3 RK_PB0 1 &pcfg_pull_none>,
2135 <3 RK_PA7 1 &pcfg_pull_none>,
2137 <3 RK_PA6 1 &pcfg_pull_none>,
2139 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2141 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2143 <3 RK_PA3 1 &pcfg_pull_none>,
2145 <3 RK_PA2 1 &pcfg_pull_none>,
2147 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2149 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2152 rmii_pins: rmii-pins {
2155 <3 RK_PB5 1 &pcfg_pull_none>,
2157 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2159 <3 RK_PB3 1 &pcfg_pull_none>,
2161 <3 RK_PB2 1 &pcfg_pull_none>,
2163 <3 RK_PB1 1 &pcfg_pull_none>,
2165 <3 RK_PB0 1 &pcfg_pull_none>,
2167 <3 RK_PA7 1 &pcfg_pull_none>,
2169 <3 RK_PA6 1 &pcfg_pull_none>,
2171 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2173 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2178 i2c0_xfer: i2c0-xfer {
2180 <1 RK_PB7 2 &pcfg_pull_none>,
2181 <1 RK_PC0 2 &pcfg_pull_none>;
2186 i2c1_xfer: i2c1-xfer {
2188 <4 RK_PA2 1 &pcfg_pull_none>,
2189 <4 RK_PA1 1 &pcfg_pull_none>;
2194 i2c2_xfer: i2c2-xfer {
2196 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2197 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2202 i2c3_xfer: i2c3-xfer {
2204 <4 RK_PC1 1 &pcfg_pull_none>,
2205 <4 RK_PC0 1 &pcfg_pull_none>;
2210 i2c4_xfer: i2c4-xfer {
2212 <1 RK_PB4 1 &pcfg_pull_none>,
2213 <1 RK_PB3 1 &pcfg_pull_none>;
2218 i2c5_xfer: i2c5-xfer {
2220 <3 RK_PB3 2 &pcfg_pull_none>,
2221 <3 RK_PB2 2 &pcfg_pull_none>;
2226 i2c6_xfer: i2c6-xfer {
2228 <2 RK_PB2 2 &pcfg_pull_none>,
2229 <2 RK_PB1 2 &pcfg_pull_none>;
2234 i2c7_xfer: i2c7-xfer {
2236 <2 RK_PB0 2 &pcfg_pull_none>,
2237 <2 RK_PA7 2 &pcfg_pull_none>;
2242 i2c8_xfer: i2c8-xfer {
2244 <1 RK_PC5 1 &pcfg_pull_none>,
2245 <1 RK_PC4 1 &pcfg_pull_none>;
2250 i2s0_2ch_bus: i2s0-2ch-bus {
2252 <3 RK_PD0 1 &pcfg_pull_none>,
2253 <3 RK_PD1 1 &pcfg_pull_none>,
2254 <3 RK_PD2 1 &pcfg_pull_none>,
2255 <3 RK_PD3 1 &pcfg_pull_none>,
2256 <3 RK_PD7 1 &pcfg_pull_none>,
2257 <4 RK_PA0 1 &pcfg_pull_none>;
2260 i2s0_8ch_bus: i2s0-8ch-bus {
2262 <3 RK_PD0 1 &pcfg_pull_none>,
2263 <3 RK_PD1 1 &pcfg_pull_none>,
2264 <3 RK_PD2 1 &pcfg_pull_none>,
2265 <3 RK_PD3 1 &pcfg_pull_none>,
2266 <3 RK_PD4 1 &pcfg_pull_none>,
2267 <3 RK_PD5 1 &pcfg_pull_none>,
2268 <3 RK_PD6 1 &pcfg_pull_none>,
2269 <3 RK_PD7 1 &pcfg_pull_none>,
2270 <4 RK_PA0 1 &pcfg_pull_none>;
2275 i2s1_2ch_bus: i2s1-2ch-bus {
2277 <4 RK_PA3 1 &pcfg_pull_none>,
2278 <4 RK_PA4 1 &pcfg_pull_none>,
2279 <4 RK_PA5 1 &pcfg_pull_none>,
2280 <4 RK_PA6 1 &pcfg_pull_none>,
2281 <4 RK_PA7 1 &pcfg_pull_none>;
2286 sdio0_bus1: sdio0-bus1 {
2288 <2 RK_PC4 1 &pcfg_pull_up>;
2291 sdio0_bus4: sdio0-bus4 {
2293 <2 RK_PC4 1 &pcfg_pull_up>,
2294 <2 RK_PC5 1 &pcfg_pull_up>,
2295 <2 RK_PC6 1 &pcfg_pull_up>,
2296 <2 RK_PC7 1 &pcfg_pull_up>;
2299 sdio0_cmd: sdio0-cmd {
2301 <2 RK_PD0 1 &pcfg_pull_up>;
2304 sdio0_clk: sdio0-clk {
2306 <2 RK_PD1 1 &pcfg_pull_none>;
2309 sdio0_cd: sdio0-cd {
2311 <2 RK_PD2 1 &pcfg_pull_up>;
2314 sdio0_pwr: sdio0-pwr {
2316 <2 RK_PD3 1 &pcfg_pull_up>;
2319 sdio0_bkpwr: sdio0-bkpwr {
2321 <2 RK_PD4 1 &pcfg_pull_up>;
2324 sdio0_wp: sdio0-wp {
2326 <0 RK_PA3 1 &pcfg_pull_up>;
2329 sdio0_int: sdio0-int {
2331 <0 RK_PA4 1 &pcfg_pull_up>;
2336 sdmmc_bus1: sdmmc-bus1 {
2338 <4 RK_PB0 1 &pcfg_pull_up>;
2341 sdmmc_bus4: sdmmc-bus4 {
2343 <4 RK_PB0 1 &pcfg_pull_up>,
2344 <4 RK_PB1 1 &pcfg_pull_up>,
2345 <4 RK_PB2 1 &pcfg_pull_up>,
2346 <4 RK_PB3 1 &pcfg_pull_up>;
2349 sdmmc_clk: sdmmc-clk {
2351 <4 RK_PB4 1 &pcfg_pull_none>;
2354 sdmmc_cmd: sdmmc-cmd {
2356 <4 RK_PB5 1 &pcfg_pull_up>;
2359 sdmmc_cd: sdmmc-cd {
2361 <0 RK_PA7 1 &pcfg_pull_up>;
2364 sdmmc_wp: sdmmc-wp {
2366 <0 RK_PB0 1 &pcfg_pull_up>;
2371 ap_pwroff: ap-pwroff {
2372 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2375 ddrio_pwroff: ddrio-pwroff {
2376 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2381 spdif_bus: spdif-bus {
2383 <4 RK_PC5 1 &pcfg_pull_none>;
2386 spdif_bus_1: spdif-bus-1 {
2388 <3 RK_PC0 3 &pcfg_pull_none>;
2393 spi0_clk: spi0-clk {
2395 <3 RK_PA6 2 &pcfg_pull_up>;
2397 spi0_cs0: spi0-cs0 {
2399 <3 RK_PA7 2 &pcfg_pull_up>;
2401 spi0_cs1: spi0-cs1 {
2403 <3 RK_PB0 2 &pcfg_pull_up>;
2407 <3 RK_PA5 2 &pcfg_pull_up>;
2411 <3 RK_PA4 2 &pcfg_pull_up>;
2416 spi1_clk: spi1-clk {
2418 <1 RK_PB1 2 &pcfg_pull_up>;
2420 spi1_cs0: spi1-cs0 {
2422 <1 RK_PB2 2 &pcfg_pull_up>;
2426 <1 RK_PA7 2 &pcfg_pull_up>;
2430 <1 RK_PB0 2 &pcfg_pull_up>;
2435 spi2_clk: spi2-clk {
2437 <2 RK_PB3 1 &pcfg_pull_up>;
2439 spi2_cs0: spi2-cs0 {
2441 <2 RK_PB4 1 &pcfg_pull_up>;
2445 <2 RK_PB1 1 &pcfg_pull_up>;
2449 <2 RK_PB2 1 &pcfg_pull_up>;
2454 spi3_clk: spi3-clk {
2456 <1 RK_PC1 1 &pcfg_pull_up>;
2458 spi3_cs0: spi3-cs0 {
2460 <1 RK_PC2 1 &pcfg_pull_up>;
2464 <1 RK_PB7 1 &pcfg_pull_up>;
2468 <1 RK_PC0 1 &pcfg_pull_up>;
2473 spi4_clk: spi4-clk {
2475 <3 RK_PA2 2 &pcfg_pull_up>;
2477 spi4_cs0: spi4-cs0 {
2479 <3 RK_PA3 2 &pcfg_pull_up>;
2483 <3 RK_PA0 2 &pcfg_pull_up>;
2487 <3 RK_PA1 2 &pcfg_pull_up>;
2492 spi5_clk: spi5-clk {
2494 <2 RK_PC6 2 &pcfg_pull_up>;
2496 spi5_cs0: spi5-cs0 {
2498 <2 RK_PC7 2 &pcfg_pull_up>;
2502 <2 RK_PC4 2 &pcfg_pull_up>;
2506 <2 RK_PC5 2 &pcfg_pull_up>;
2511 test_clkout0: test-clkout0 {
2513 <0 RK_PA0 1 &pcfg_pull_none>;
2516 test_clkout1: test-clkout1 {
2518 <2 RK_PD1 2 &pcfg_pull_none>;
2521 test_clkout2: test-clkout2 {
2523 <0 RK_PB0 3 &pcfg_pull_none>;
2529 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2533 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2538 uart0_xfer: uart0-xfer {
2540 <2 RK_PC0 1 &pcfg_pull_up>,
2541 <2 RK_PC1 1 &pcfg_pull_none>;
2544 uart0_cts: uart0-cts {
2546 <2 RK_PC2 1 &pcfg_pull_none>;
2549 uart0_rts: uart0-rts {
2551 <2 RK_PC3 1 &pcfg_pull_none>;
2556 uart1_xfer: uart1-xfer {
2558 <3 RK_PB4 2 &pcfg_pull_up>,
2559 <3 RK_PB5 2 &pcfg_pull_none>;
2564 uart2a_xfer: uart2a-xfer {
2566 <4 RK_PB0 2 &pcfg_pull_up>,
2567 <4 RK_PB1 2 &pcfg_pull_none>;
2572 uart2b_xfer: uart2b-xfer {
2574 <4 RK_PC0 2 &pcfg_pull_up>,
2575 <4 RK_PC1 2 &pcfg_pull_none>;
2580 uart2c_xfer: uart2c-xfer {
2582 <4 RK_PC3 1 &pcfg_pull_up>,
2583 <4 RK_PC4 1 &pcfg_pull_none>;
2588 uart3_xfer: uart3-xfer {
2590 <3 RK_PB6 2 &pcfg_pull_up>,
2591 <3 RK_PB7 2 &pcfg_pull_none>;
2594 uart3_cts: uart3-cts {
2596 <3 RK_PC0 2 &pcfg_pull_none>;
2599 uart3_rts: uart3-rts {
2601 <3 RK_PC1 2 &pcfg_pull_none>;
2606 uart4_xfer: uart4-xfer {
2608 <1 RK_PA7 1 &pcfg_pull_up>,
2609 <1 RK_PB0 1 &pcfg_pull_none>;
2614 uarthdcp_xfer: uarthdcp-xfer {
2616 <4 RK_PC5 2 &pcfg_pull_up>,
2617 <4 RK_PC6 2 &pcfg_pull_none>;
2622 pwm0_pin: pwm0-pin {
2624 <4 RK_PC2 1 &pcfg_pull_none>;
2627 pwm0_pin_pull_down: pwm0-pin-pull-down {
2629 <4 RK_PC2 1 &pcfg_pull_down>;
2632 vop0_pwm_pin: vop0-pwm-pin {
2634 <4 RK_PC2 2 &pcfg_pull_none>;
2637 vop1_pwm_pin: vop1-pwm-pin {
2639 <4 RK_PC2 3 &pcfg_pull_none>;
2644 pwm1_pin: pwm1-pin {
2646 <4 RK_PC6 1 &pcfg_pull_none>;
2649 pwm1_pin_pull_down: pwm1-pin-pull-down {
2651 <4 RK_PC6 1 &pcfg_pull_down>;
2656 pwm2_pin: pwm2-pin {
2658 <1 RK_PC3 1 &pcfg_pull_none>;
2661 pwm2_pin_pull_down: pwm2-pin-pull-down {
2663 <1 RK_PC3 1 &pcfg_pull_down>;
2668 pwm3a_pin: pwm3a-pin {
2670 <0 RK_PA6 1 &pcfg_pull_none>;
2675 pwm3b_pin: pwm3b-pin {
2677 <1 RK_PB6 1 &pcfg_pull_none>;
2682 hdmi_i2c_xfer: hdmi-i2c-xfer {
2684 <4 RK_PC1 3 &pcfg_pull_none>,
2685 <4 RK_PC0 3 &pcfg_pull_none>;
2688 hdmi_cec: hdmi-cec {
2690 <4 RK_PC7 1 &pcfg_pull_none>;
2695 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2697 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2700 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2702 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;