1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
75 clocks = <&cru ARMCLKL>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
87 clocks = <&cru ARMCLKL>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
99 clocks = <&cru ARMCLKL>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
111 clocks = <&cru ARMCLKL>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
123 clocks = <&cru ARMCLKB>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 compatible = "arm,cortex-a72";
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 clocks = <&cru ARMCLKB>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <436>;
138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
142 entry-method = "psci";
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
165 compatible = "rockchip,display-subsystem";
166 ports = <&vopl_out>, <&vopb_out>;
170 compatible = "arm,cortex-a53-pmu";
171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
175 compatible = "arm,cortex-a72-pmu";
176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
180 compatible = "arm,psci-1.0";
185 compatible = "arm,armv8-timer";
186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
190 arm,no-tick-in-suspend;
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
200 pcie0: pcie@f8000000 {
201 compatible = "rockchip,rk3399-pcie";
202 reg = <0x0 0xf8000000 0x0 0x2000000>,
203 <0x0 0xfd000000 0x0 0x1000000>;
204 reg-names = "axi-base", "apb-base";
206 #address-cells = <3>;
208 #interrupt-cells = <1>;
210 bus-range = <0x0 0x1f>;
211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
213 clock-names = "aclk", "aclk-perf",
215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
218 interrupt-names = "sys", "legacy", "client";
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
221 <0 0 0 2 &pcie0_intc 1>,
222 <0 0 0 3 &pcie0_intc 2>,
223 <0 0 0 4 &pcie0_intc 3>;
224 max-link-speed = <1>;
225 msi-map = <0x0 &its 0x0 0x1000>;
226 phys = <&pcie_phy 0>, <&pcie_phy 1>,
227 <&pcie_phy 2>, <&pcie_phy 3>;
228 phy-names = "pcie-phy-0", "pcie-phy-1",
229 "pcie-phy-2", "pcie-phy-3";
230 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
237 "pm", "pclk", "aclk";
240 pcie0_intc: interrupt-controller {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <1>;
247 gmac: ethernet@fe300000 {
248 compatible = "rockchip,rk3399-gmac";
249 reg = <0x0 0xfe300000 0x0 0x10000>;
250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
251 interrupt-names = "macirq";
252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
256 clock-names = "stmmaceth", "mac_clk_rx",
257 "mac_clk_tx", "clk_mac_ref",
258 "clk_mac_refout", "aclk_mac",
260 power-domains = <&power RK3399_PD_GMAC>;
261 resets = <&cru SRST_A_GMAC>;
262 reset-names = "stmmaceth";
263 rockchip,grf = <&grf>;
268 sdio0: mmc@fe310000 {
269 compatible = "rockchip,rk3399-dw-mshc",
270 "rockchip,rk3288-dw-mshc";
271 reg = <0x0 0xfe310000 0x0 0x4000>;
272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
273 max-frequency = <150000000>;
274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
278 power-domains = <&power RK3399_PD_SDIOAUDIO>;
279 resets = <&cru SRST_SDIO0>;
280 reset-names = "reset";
284 sdmmc: mmc@fe320000 {
285 compatible = "rockchip,rk3399-dw-mshc",
286 "rockchip,rk3288-dw-mshc";
287 reg = <0x0 0xfe320000 0x0 0x4000>;
288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
289 max-frequency = <150000000>;
290 assigned-clocks = <&cru HCLK_SD>;
291 assigned-clock-rates = <200000000>;
292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
296 power-domains = <&power RK3399_PD_SD>;
297 resets = <&cru SRST_SDMMC>;
298 reset-names = "reset";
302 sdhci: mmc@fe330000 {
303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
304 reg = <0x0 0xfe330000 0x0 0x10000>;
305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
306 arasan,soc-ctl-syscon = <&grf>;
307 assigned-clocks = <&cru SCLK_EMMC>;
308 assigned-clock-rates = <200000000>;
309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
310 clock-names = "clk_xin", "clk_ahb";
311 clock-output-names = "emmc_cardclock";
314 phy-names = "phy_arasan";
315 power-domains = <&power RK3399_PD_EMMC>;
320 usb_host0_ehci: usb@fe380000 {
321 compatible = "generic-ehci";
322 reg = <0x0 0xfe380000 0x0 0x20000>;
323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
326 phys = <&u2phy0_host>;
331 usb_host0_ohci: usb@fe3a0000 {
332 compatible = "generic-ohci";
333 reg = <0x0 0xfe3a0000 0x0 0x20000>;
334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
337 phys = <&u2phy0_host>;
342 usb_host1_ehci: usb@fe3c0000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe3c0000 0x0 0x20000>;
345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
348 phys = <&u2phy1_host>;
353 usb_host1_ohci: usb@fe3e0000 {
354 compatible = "generic-ohci";
355 reg = <0x0 0xfe3e0000 0x0 0x20000>;
356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
359 phys = <&u2phy1_host>;
364 usbdrd3_0: usb@fe800000 {
365 compatible = "rockchip,rk3399-dwc3";
366 #address-cells = <2>;
369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
372 clock-names = "ref_clk", "suspend_clk",
373 "bus_clk", "aclk_usb3_rksoc_axi_perf",
374 "aclk_usb3", "grf_clk";
375 resets = <&cru SRST_A_USB3_OTG0>;
376 reset-names = "usb3-otg";
379 usbdrd_dwc3_0: usb@fe800000 {
380 compatible = "snps,dwc3";
381 reg = <0x0 0xfe800000 0x0 0x100000>;
382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
384 <&cru SCLK_USB3OTG0_SUSPEND>;
385 clock-names = "ref", "bus_early", "suspend";
387 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
388 phy-names = "usb2-phy", "usb3-phy";
389 phy_type = "utmi_wide";
390 snps,dis_enblslpm_quirk;
391 snps,dis-u2-freeclk-exists-quirk;
392 snps,dis_u2_susphy_quirk;
393 snps,dis-del-phy-power-chg-quirk;
394 snps,dis-tx-ipgap-linecheck-quirk;
395 power-domains = <&power RK3399_PD_USB3>;
400 usbdrd3_1: usb@fe900000 {
401 compatible = "rockchip,rk3399-dwc3";
402 #address-cells = <2>;
405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
408 clock-names = "ref_clk", "suspend_clk",
409 "bus_clk", "aclk_usb3_rksoc_axi_perf",
410 "aclk_usb3", "grf_clk";
411 resets = <&cru SRST_A_USB3_OTG1>;
412 reset-names = "usb3-otg";
415 usbdrd_dwc3_1: usb@fe900000 {
416 compatible = "snps,dwc3";
417 reg = <0x0 0xfe900000 0x0 0x100000>;
418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
420 <&cru SCLK_USB3OTG1_SUSPEND>;
421 clock-names = "ref", "bus_early", "suspend";
423 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
424 phy-names = "usb2-phy", "usb3-phy";
425 phy_type = "utmi_wide";
426 snps,dis_enblslpm_quirk;
427 snps,dis-u2-freeclk-exists-quirk;
428 snps,dis_u2_susphy_quirk;
429 snps,dis-del-phy-power-chg-quirk;
430 snps,dis-tx-ipgap-linecheck-quirk;
431 power-domains = <&power RK3399_PD_USB3>;
436 cdn_dp: dp@fec00000 {
437 compatible = "rockchip,rk3399-cdn-dp";
438 reg = <0x0 0xfec00000 0x0 0x100000>;
439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
441 assigned-clock-rates = <100000000>, <200000000>;
442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
444 clock-names = "core-clk", "pclk", "spdif", "grf";
445 phys = <&tcphy0_dp>, <&tcphy1_dp>;
446 power-domains = <&power RK3399_PD_HDCP>;
447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
449 reset-names = "spdif", "dptx", "apb", "core";
450 rockchip,grf = <&grf>;
451 #sound-dai-cells = <1>;
456 #address-cells = <1>;
459 dp_in_vopb: endpoint@0 {
461 remote-endpoint = <&vopb_out_dp>;
464 dp_in_vopl: endpoint@1 {
466 remote-endpoint = <&vopl_out_dp>;
472 gic: interrupt-controller@fee00000 {
473 compatible = "arm,gic-v3";
474 #interrupt-cells = <4>;
475 #address-cells = <2>;
478 interrupt-controller;
480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
481 <0x0 0xfef00000 0 0xc0000>, /* GICR */
482 <0x0 0xfff00000 0 0x10000>, /* GICC */
483 <0x0 0xfff10000 0 0x10000>, /* GICH */
484 <0x0 0xfff20000 0 0x10000>; /* GICV */
485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
486 its: interrupt-controller@fee20000 {
487 compatible = "arm,gic-v3-its";
490 reg = <0x0 0xfee20000 0x0 0x20000>;
494 ppi_cluster0: interrupt-partition-0 {
495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
498 ppi_cluster1: interrupt-partition-1 {
499 affinity = <&cpu_b0 &cpu_b1>;
504 saradc: saradc@ff100000 {
505 compatible = "rockchip,rk3399-saradc";
506 reg = <0x0 0xff100000 0x0 0x100>;
507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
508 #io-channel-cells = <1>;
509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
510 clock-names = "saradc", "apb_pclk";
511 resets = <&cru SRST_P_SARADC>;
512 reset-names = "saradc-apb";
517 compatible = "rockchip,rk3399-i2c";
518 reg = <0x0 0xff110000 0x0 0x1000>;
519 assigned-clocks = <&cru SCLK_I2C1>;
520 assigned-clock-rates = <200000000>;
521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
522 clock-names = "i2c", "pclk";
523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c1_xfer>;
526 #address-cells = <1>;
532 compatible = "rockchip,rk3399-i2c";
533 reg = <0x0 0xff120000 0x0 0x1000>;
534 assigned-clocks = <&cru SCLK_I2C2>;
535 assigned-clock-rates = <200000000>;
536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
537 clock-names = "i2c", "pclk";
538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c2_xfer>;
541 #address-cells = <1>;
547 compatible = "rockchip,rk3399-i2c";
548 reg = <0x0 0xff130000 0x0 0x1000>;
549 assigned-clocks = <&cru SCLK_I2C3>;
550 assigned-clock-rates = <200000000>;
551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c3_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff140000 0x0 0x1000>;
564 assigned-clocks = <&cru SCLK_I2C5>;
565 assigned-clock-rates = <200000000>;
566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
567 clock-names = "i2c", "pclk";
568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c5_xfer>;
571 #address-cells = <1>;
577 compatible = "rockchip,rk3399-i2c";
578 reg = <0x0 0xff150000 0x0 0x1000>;
579 assigned-clocks = <&cru SCLK_I2C6>;
580 assigned-clock-rates = <200000000>;
581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
582 clock-names = "i2c", "pclk";
583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c6_xfer>;
586 #address-cells = <1>;
592 compatible = "rockchip,rk3399-i2c";
593 reg = <0x0 0xff160000 0x0 0x1000>;
594 assigned-clocks = <&cru SCLK_I2C7>;
595 assigned-clock-rates = <200000000>;
596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
597 clock-names = "i2c", "pclk";
598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c7_xfer>;
601 #address-cells = <1>;
606 uart0: serial@ff180000 {
607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
608 reg = <0x0 0xff180000 0x0 0x100>;
609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
610 clock-names = "baudclk", "apb_pclk";
611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&uart0_xfer>;
619 uart1: serial@ff190000 {
620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
621 reg = <0x0 0xff190000 0x0 0x100>;
622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
623 clock-names = "baudclk", "apb_pclk";
624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&uart1_xfer>;
632 uart2: serial@ff1a0000 {
633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
634 reg = <0x0 0xff1a0000 0x0 0x100>;
635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
636 clock-names = "baudclk", "apb_pclk";
637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart2c_xfer>;
645 uart3: serial@ff1b0000 {
646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
647 reg = <0x0 0xff1b0000 0x0 0x100>;
648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
649 clock-names = "baudclk", "apb_pclk";
650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&uart3_xfer>;
659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
660 reg = <0x0 0xff1c0000 0x0 0x1000>;
661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
662 clock-names = "spiclk", "apb_pclk";
663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
664 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
665 dma-names = "tx", "rx";
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
668 #address-cells = <1>;
674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
675 reg = <0x0 0xff1d0000 0x0 0x1000>;
676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
677 clock-names = "spiclk", "apb_pclk";
678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
679 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
680 dma-names = "tx", "rx";
681 pinctrl-names = "default";
682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
683 #address-cells = <1>;
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
690 reg = <0x0 0xff1e0000 0x0 0x1000>;
691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
692 clock-names = "spiclk", "apb_pclk";
693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
694 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
695 dma-names = "tx", "rx";
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
698 #address-cells = <1>;
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1f0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
707 clock-names = "spiclk", "apb_pclk";
708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
709 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
710 dma-names = "tx", "rx";
711 pinctrl-names = "default";
712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
713 #address-cells = <1>;
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
720 reg = <0x0 0xff200000 0x0 0x1000>;
721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
722 clock-names = "spiclk", "apb_pclk";
723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
724 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
725 dma-names = "tx", "rx";
726 pinctrl-names = "default";
727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
728 power-domains = <&power RK3399_PD_SDIOAUDIO>;
729 #address-cells = <1>;
734 thermal_zones: thermal-zones {
735 cpu_thermal: cpu-thermal {
736 polling-delay-passive = <100>;
737 polling-delay = <1000>;
739 thermal-sensors = <&tsadc 0>;
742 cpu_alert0: cpu_alert0 {
743 temperature = <70000>;
747 cpu_alert1: cpu_alert1 {
748 temperature = <75000>;
753 temperature = <95000>;
761 trip = <&cpu_alert0>;
763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
767 trip = <&cpu_alert1>;
769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 gpu_thermal: gpu-thermal {
780 polling-delay-passive = <100>;
781 polling-delay = <1000>;
783 thermal-sensors = <&tsadc 1>;
786 gpu_alert0: gpu_alert0 {
787 temperature = <75000>;
792 temperature = <95000>;
800 trip = <&gpu_alert0>;
802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
808 tsadc: tsadc@ff260000 {
809 compatible = "rockchip,rk3399-tsadc";
810 reg = <0x0 0xff260000 0x0 0x100>;
811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
812 assigned-clocks = <&cru SCLK_TSADC>;
813 assigned-clock-rates = <750000>;
814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
815 clock-names = "tsadc", "apb_pclk";
816 resets = <&cru SRST_TSADC>;
817 reset-names = "tsadc-apb";
818 rockchip,grf = <&grf>;
819 rockchip,hw-tshut-temp = <95000>;
820 pinctrl-names = "init", "default", "sleep";
821 pinctrl-0 = <&otp_pin>;
822 pinctrl-1 = <&otp_out>;
823 pinctrl-2 = <&otp_pin>;
824 #thermal-sensor-cells = <1>;
828 qos_emmc: qos@ffa58000 {
829 compatible = "rockchip,rk3399-qos", "syscon";
830 reg = <0x0 0xffa58000 0x0 0x20>;
833 qos_gmac: qos@ffa5c000 {
834 compatible = "rockchip,rk3399-qos", "syscon";
835 reg = <0x0 0xffa5c000 0x0 0x20>;
838 qos_pcie: qos@ffa60080 {
839 compatible = "rockchip,rk3399-qos", "syscon";
840 reg = <0x0 0xffa60080 0x0 0x20>;
843 qos_usb_host0: qos@ffa60100 {
844 compatible = "rockchip,rk3399-qos", "syscon";
845 reg = <0x0 0xffa60100 0x0 0x20>;
848 qos_usb_host1: qos@ffa60180 {
849 compatible = "rockchip,rk3399-qos", "syscon";
850 reg = <0x0 0xffa60180 0x0 0x20>;
853 qos_usb_otg0: qos@ffa70000 {
854 compatible = "rockchip,rk3399-qos", "syscon";
855 reg = <0x0 0xffa70000 0x0 0x20>;
858 qos_usb_otg1: qos@ffa70080 {
859 compatible = "rockchip,rk3399-qos", "syscon";
860 reg = <0x0 0xffa70080 0x0 0x20>;
863 qos_sd: qos@ffa74000 {
864 compatible = "rockchip,rk3399-qos", "syscon";
865 reg = <0x0 0xffa74000 0x0 0x20>;
868 qos_sdioaudio: qos@ffa76000 {
869 compatible = "rockchip,rk3399-qos", "syscon";
870 reg = <0x0 0xffa76000 0x0 0x20>;
873 qos_hdcp: qos@ffa90000 {
874 compatible = "rockchip,rk3399-qos", "syscon";
875 reg = <0x0 0xffa90000 0x0 0x20>;
878 qos_iep: qos@ffa98000 {
879 compatible = "rockchip,rk3399-qos", "syscon";
880 reg = <0x0 0xffa98000 0x0 0x20>;
883 qos_isp0_m0: qos@ffaa0000 {
884 compatible = "rockchip,rk3399-qos", "syscon";
885 reg = <0x0 0xffaa0000 0x0 0x20>;
888 qos_isp0_m1: qos@ffaa0080 {
889 compatible = "rockchip,rk3399-qos", "syscon";
890 reg = <0x0 0xffaa0080 0x0 0x20>;
893 qos_isp1_m0: qos@ffaa8000 {
894 compatible = "rockchip,rk3399-qos", "syscon";
895 reg = <0x0 0xffaa8000 0x0 0x20>;
898 qos_isp1_m1: qos@ffaa8080 {
899 compatible = "rockchip,rk3399-qos", "syscon";
900 reg = <0x0 0xffaa8080 0x0 0x20>;
903 qos_rga_r: qos@ffab0000 {
904 compatible = "rockchip,rk3399-qos", "syscon";
905 reg = <0x0 0xffab0000 0x0 0x20>;
908 qos_rga_w: qos@ffab0080 {
909 compatible = "rockchip,rk3399-qos", "syscon";
910 reg = <0x0 0xffab0080 0x0 0x20>;
913 qos_video_m0: qos@ffab8000 {
914 compatible = "rockchip,rk3399-qos", "syscon";
915 reg = <0x0 0xffab8000 0x0 0x20>;
918 qos_video_m1_r: qos@ffac0000 {
919 compatible = "rockchip,rk3399-qos", "syscon";
920 reg = <0x0 0xffac0000 0x0 0x20>;
923 qos_video_m1_w: qos@ffac0080 {
924 compatible = "rockchip,rk3399-qos", "syscon";
925 reg = <0x0 0xffac0080 0x0 0x20>;
928 qos_vop_big_r: qos@ffac8000 {
929 compatible = "rockchip,rk3399-qos", "syscon";
930 reg = <0x0 0xffac8000 0x0 0x20>;
933 qos_vop_big_w: qos@ffac8080 {
934 compatible = "rockchip,rk3399-qos", "syscon";
935 reg = <0x0 0xffac8080 0x0 0x20>;
938 qos_vop_little: qos@ffad0000 {
939 compatible = "rockchip,rk3399-qos", "syscon";
940 reg = <0x0 0xffad0000 0x0 0x20>;
943 qos_perihp: qos@ffad8080 {
944 compatible = "rockchip,rk3399-qos", "syscon";
945 reg = <0x0 0xffad8080 0x0 0x20>;
948 qos_gpu: qos@ffae0000 {
949 compatible = "rockchip,rk3399-qos", "syscon";
950 reg = <0x0 0xffae0000 0x0 0x20>;
953 pmu: power-management@ff310000 {
954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
955 reg = <0x0 0xff310000 0x0 0x1000>;
958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
960 * Some of the power domains are grouped together for every
962 * The detail contents as below.
964 power: power-controller {
965 compatible = "rockchip,rk3399-power-controller";
966 #power-domain-cells = <1>;
967 #address-cells = <1>;
970 /* These power domains are grouped by VD_CENTER */
971 pd_iep@RK3399_PD_IEP {
972 reg = <RK3399_PD_IEP>;
973 clocks = <&cru ACLK_IEP>,
977 pd_rga@RK3399_PD_RGA {
978 reg = <RK3399_PD_RGA>;
979 clocks = <&cru ACLK_RGA>,
981 pm_qos = <&qos_rga_r>,
984 pd_vcodec@RK3399_PD_VCODEC {
985 reg = <RK3399_PD_VCODEC>;
986 clocks = <&cru ACLK_VCODEC>,
988 pm_qos = <&qos_video_m0>;
990 pd_vdu@RK3399_PD_VDU {
991 reg = <RK3399_PD_VDU>;
992 clocks = <&cru ACLK_VDU>,
994 pm_qos = <&qos_video_m1_r>,
998 /* These power domains are grouped by VD_GPU */
999 pd_gpu@RK3399_PD_GPU {
1000 reg = <RK3399_PD_GPU>;
1001 clocks = <&cru ACLK_GPU>;
1002 pm_qos = <&qos_gpu>;
1005 /* These power domains are grouped by VD_LOGIC */
1006 pd_edp@RK3399_PD_EDP {
1007 reg = <RK3399_PD_EDP>;
1008 clocks = <&cru PCLK_EDP_CTRL>;
1010 pd_emmc@RK3399_PD_EMMC {
1011 reg = <RK3399_PD_EMMC>;
1012 clocks = <&cru ACLK_EMMC>;
1013 pm_qos = <&qos_emmc>;
1015 pd_gmac@RK3399_PD_GMAC {
1016 reg = <RK3399_PD_GMAC>;
1017 clocks = <&cru ACLK_GMAC>,
1019 pm_qos = <&qos_gmac>;
1021 pd_sd@RK3399_PD_SD {
1022 reg = <RK3399_PD_SD>;
1023 clocks = <&cru HCLK_SDMMC>,
1027 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1028 reg = <RK3399_PD_SDIOAUDIO>;
1029 clocks = <&cru HCLK_SDIO>;
1030 pm_qos = <&qos_sdioaudio>;
1032 pd_tcpc0@RK3399_PD_TCPD0 {
1033 reg = <RK3399_PD_TCPD0>;
1034 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1035 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1037 pd_tcpc1@RK3399_PD_TCPD1 {
1038 reg = <RK3399_PD_TCPD1>;
1039 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1040 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1042 pd_usb3@RK3399_PD_USB3 {
1043 reg = <RK3399_PD_USB3>;
1044 clocks = <&cru ACLK_USB3>;
1045 pm_qos = <&qos_usb_otg0>,
1048 pd_vio@RK3399_PD_VIO {
1049 reg = <RK3399_PD_VIO>;
1050 #address-cells = <1>;
1053 pd_hdcp@RK3399_PD_HDCP {
1054 reg = <RK3399_PD_HDCP>;
1055 clocks = <&cru ACLK_HDCP>,
1058 pm_qos = <&qos_hdcp>;
1060 pd_isp0@RK3399_PD_ISP0 {
1061 reg = <RK3399_PD_ISP0>;
1062 clocks = <&cru ACLK_ISP0>,
1064 pm_qos = <&qos_isp0_m0>,
1067 pd_isp1@RK3399_PD_ISP1 {
1068 reg = <RK3399_PD_ISP1>;
1069 clocks = <&cru ACLK_ISP1>,
1071 pm_qos = <&qos_isp1_m0>,
1074 pd_vo@RK3399_PD_VO {
1075 reg = <RK3399_PD_VO>;
1076 #address-cells = <1>;
1079 pd_vopb@RK3399_PD_VOPB {
1080 reg = <RK3399_PD_VOPB>;
1081 clocks = <&cru ACLK_VOP0>,
1083 pm_qos = <&qos_vop_big_r>,
1086 pd_vopl@RK3399_PD_VOPL {
1087 reg = <RK3399_PD_VOPL>;
1088 clocks = <&cru ACLK_VOP1>,
1090 pm_qos = <&qos_vop_little>;
1097 pmugrf: syscon@ff320000 {
1098 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1099 reg = <0x0 0xff320000 0x0 0x1000>;
1101 pmu_io_domains: io-domains {
1102 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1103 status = "disabled";
1107 spi3: spi@ff350000 {
1108 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1109 reg = <0x0 0xff350000 0x0 0x1000>;
1110 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1111 clock-names = "spiclk", "apb_pclk";
1112 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1115 #address-cells = <1>;
1117 status = "disabled";
1120 uart4: serial@ff370000 {
1121 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1122 reg = <0x0 0xff370000 0x0 0x100>;
1123 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1124 clock-names = "baudclk", "apb_pclk";
1125 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&uart4_xfer>;
1130 status = "disabled";
1133 i2c0: i2c@ff3c0000 {
1134 compatible = "rockchip,rk3399-i2c";
1135 reg = <0x0 0xff3c0000 0x0 0x1000>;
1136 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1137 assigned-clock-rates = <200000000>;
1138 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1139 clock-names = "i2c", "pclk";
1140 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&i2c0_xfer>;
1143 #address-cells = <1>;
1145 status = "disabled";
1148 i2c4: i2c@ff3d0000 {
1149 compatible = "rockchip,rk3399-i2c";
1150 reg = <0x0 0xff3d0000 0x0 0x1000>;
1151 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1152 assigned-clock-rates = <200000000>;
1153 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1154 clock-names = "i2c", "pclk";
1155 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&i2c4_xfer>;
1158 #address-cells = <1>;
1160 status = "disabled";
1163 i2c8: i2c@ff3e0000 {
1164 compatible = "rockchip,rk3399-i2c";
1165 reg = <0x0 0xff3e0000 0x0 0x1000>;
1166 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1167 assigned-clock-rates = <200000000>;
1168 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1169 clock-names = "i2c", "pclk";
1170 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&i2c8_xfer>;
1173 #address-cells = <1>;
1175 status = "disabled";
1178 pwm0: pwm@ff420000 {
1179 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1180 reg = <0x0 0xff420000 0x0 0x10>;
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&pwm0_pin>;
1184 clocks = <&pmucru PCLK_RKPWM_PMU>;
1185 clock-names = "pwm";
1186 status = "disabled";
1189 pwm1: pwm@ff420010 {
1190 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1191 reg = <0x0 0xff420010 0x0 0x10>;
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&pwm1_pin>;
1195 clocks = <&pmucru PCLK_RKPWM_PMU>;
1196 clock-names = "pwm";
1197 status = "disabled";
1200 pwm2: pwm@ff420020 {
1201 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1202 reg = <0x0 0xff420020 0x0 0x10>;
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&pwm2_pin>;
1206 clocks = <&pmucru PCLK_RKPWM_PMU>;
1207 clock-names = "pwm";
1208 status = "disabled";
1211 pwm3: pwm@ff420030 {
1212 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1213 reg = <0x0 0xff420030 0x0 0x10>;
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&pwm3a_pin>;
1217 clocks = <&pmucru PCLK_RKPWM_PMU>;
1218 clock-names = "pwm";
1219 status = "disabled";
1222 vpu: video-codec@ff650000 {
1223 compatible = "rockchip,rk3399-vpu";
1224 reg = <0x0 0xff650000 0x0 0x800>;
1225 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1226 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1227 interrupt-names = "vepu", "vdpu";
1228 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1229 clock-names = "aclk", "hclk";
1230 iommus = <&vpu_mmu>;
1231 power-domains = <&power RK3399_PD_VCODEC>;
1234 vpu_mmu: iommu@ff650800 {
1235 compatible = "rockchip,iommu";
1236 reg = <0x0 0xff650800 0x0 0x40>;
1237 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1238 interrupt-names = "vpu_mmu";
1239 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1240 clock-names = "aclk", "iface";
1242 power-domains = <&power RK3399_PD_VCODEC>;
1245 vdec: video-codec@ff660000 {
1246 compatible = "rockchip,rk3399-vdec";
1247 reg = <0x0 0xff660000 0x0 0x400>;
1248 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1249 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1250 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1251 clock-names = "axi", "ahb", "cabac", "core";
1252 iommus = <&vdec_mmu>;
1253 power-domains = <&power RK3399_PD_VDU>;
1256 vdec_mmu: iommu@ff660480 {
1257 compatible = "rockchip,iommu";
1258 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1259 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1260 interrupt-names = "vdec_mmu";
1261 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1262 clock-names = "aclk", "iface";
1263 power-domains = <&power RK3399_PD_VDU>;
1267 iep_mmu: iommu@ff670800 {
1268 compatible = "rockchip,iommu";
1269 reg = <0x0 0xff670800 0x0 0x40>;
1270 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1271 interrupt-names = "iep_mmu";
1272 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1273 clock-names = "aclk", "iface";
1275 status = "disabled";
1279 compatible = "rockchip,rk3399-rga";
1280 reg = <0x0 0xff680000 0x0 0x10000>;
1281 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1282 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1283 clock-names = "aclk", "hclk", "sclk";
1284 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1285 reset-names = "core", "axi", "ahb";
1286 power-domains = <&power RK3399_PD_RGA>;
1289 efuse0: efuse@ff690000 {
1290 compatible = "rockchip,rk3399-efuse";
1291 reg = <0x0 0xff690000 0x0 0x80>;
1292 #address-cells = <1>;
1294 clocks = <&cru PCLK_EFUSE1024NS>;
1295 clock-names = "pclk_efuse";
1301 cpub_leakage: cpu-leakage@17 {
1304 gpu_leakage: gpu-leakage@18 {
1307 center_leakage: center-leakage@19 {
1310 cpul_leakage: cpu-leakage@1a {
1313 logic_leakage: logic-leakage@1b {
1316 wafer_info: wafer-info@1c {
1321 dmac_bus: dma-controller@ff6d0000 {
1322 compatible = "arm,pl330", "arm,primecell";
1323 reg = <0x0 0xff6d0000 0x0 0x4000>;
1324 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1325 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1327 arm,pl330-periph-burst;
1328 clocks = <&cru ACLK_DMAC0_PERILP>;
1329 clock-names = "apb_pclk";
1332 dmac_peri: dma-controller@ff6e0000 {
1333 compatible = "arm,pl330", "arm,primecell";
1334 reg = <0x0 0xff6e0000 0x0 0x4000>;
1335 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1336 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1338 arm,pl330-periph-burst;
1339 clocks = <&cru ACLK_DMAC1_PERILP>;
1340 clock-names = "apb_pclk";
1343 pmucru: pmu-clock-controller@ff750000 {
1344 compatible = "rockchip,rk3399-pmucru";
1345 reg = <0x0 0xff750000 0x0 0x1000>;
1346 rockchip,grf = <&pmugrf>;
1349 assigned-clocks = <&pmucru PLL_PPLL>;
1350 assigned-clock-rates = <676000000>;
1353 cru: clock-controller@ff760000 {
1354 compatible = "rockchip,rk3399-cru";
1355 reg = <0x0 0xff760000 0x0 0x1000>;
1356 rockchip,grf = <&grf>;
1360 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1362 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1364 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1365 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1366 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1367 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1368 <&cru ACLK_GIC_PRE>,
1370 assigned-clock-rates =
1371 <594000000>, <800000000>,
1373 <150000000>, <75000000>,
1375 <100000000>, <100000000>,
1376 <50000000>, <600000000>,
1377 <100000000>, <50000000>,
1378 <400000000>, <400000000>,
1383 grf: syscon@ff770000 {
1384 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1385 reg = <0x0 0xff770000 0x0 0x10000>;
1386 #address-cells = <1>;
1389 io_domains: io-domains {
1390 compatible = "rockchip,rk3399-io-voltage-domain";
1391 status = "disabled";
1394 mipi_dphy_rx0: mipi-dphy-rx0 {
1395 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1396 clocks = <&cru SCLK_MIPIDPHY_REF>,
1397 <&cru SCLK_DPHY_RX0_CFG>,
1398 <&cru PCLK_VIO_GRF>;
1399 clock-names = "dphy-ref", "dphy-cfg", "grf";
1400 power-domains = <&power RK3399_PD_VIO>;
1402 status = "disabled";
1405 u2phy0: usb2-phy@e450 {
1406 compatible = "rockchip,rk3399-usb2phy";
1407 reg = <0xe450 0x10>;
1408 clocks = <&cru SCLK_USB2PHY0_REF>;
1409 clock-names = "phyclk";
1411 clock-output-names = "clk_usbphy0_480m";
1412 status = "disabled";
1414 u2phy0_host: host-port {
1416 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1417 interrupt-names = "linestate";
1418 status = "disabled";
1421 u2phy0_otg: otg-port {
1423 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1424 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1425 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1426 interrupt-names = "otg-bvalid", "otg-id",
1428 status = "disabled";
1432 u2phy1: usb2-phy@e460 {
1433 compatible = "rockchip,rk3399-usb2phy";
1434 reg = <0xe460 0x10>;
1435 clocks = <&cru SCLK_USB2PHY1_REF>;
1436 clock-names = "phyclk";
1438 clock-output-names = "clk_usbphy1_480m";
1439 status = "disabled";
1441 u2phy1_host: host-port {
1443 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1444 interrupt-names = "linestate";
1445 status = "disabled";
1448 u2phy1_otg: otg-port {
1450 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1451 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1452 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1453 interrupt-names = "otg-bvalid", "otg-id",
1455 status = "disabled";
1459 emmc_phy: phy@f780 {
1460 compatible = "rockchip,rk3399-emmc-phy";
1461 reg = <0xf780 0x24>;
1463 clock-names = "emmcclk";
1465 status = "disabled";
1468 pcie_phy: pcie-phy {
1469 compatible = "rockchip,rk3399-pcie-phy";
1470 clocks = <&cru SCLK_PCIEPHY_REF>;
1471 clock-names = "refclk";
1473 resets = <&cru SRST_PCIEPHY>;
1474 drive-impedance-ohm = <50>;
1475 reset-names = "phy";
1476 status = "disabled";
1480 tcphy0: phy@ff7c0000 {
1481 compatible = "rockchip,rk3399-typec-phy";
1482 reg = <0x0 0xff7c0000 0x0 0x40000>;
1483 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1484 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1485 clock-names = "tcpdcore", "tcpdphy-ref";
1486 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1487 assigned-clock-rates = <50000000>;
1488 power-domains = <&power RK3399_PD_TCPD0>;
1489 resets = <&cru SRST_UPHY0>,
1490 <&cru SRST_UPHY0_PIPE_L00>,
1491 <&cru SRST_P_UPHY0_TCPHY>;
1492 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1493 rockchip,grf = <&grf>;
1494 status = "disabled";
1496 tcphy0_dp: dp-port {
1500 tcphy0_usb3: usb3-port {
1505 tcphy1: phy@ff800000 {
1506 compatible = "rockchip,rk3399-typec-phy";
1507 reg = <0x0 0xff800000 0x0 0x40000>;
1508 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1509 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1510 clock-names = "tcpdcore", "tcpdphy-ref";
1511 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1512 assigned-clock-rates = <50000000>;
1513 power-domains = <&power RK3399_PD_TCPD1>;
1514 resets = <&cru SRST_UPHY1>,
1515 <&cru SRST_UPHY1_PIPE_L00>,
1516 <&cru SRST_P_UPHY1_TCPHY>;
1517 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1518 rockchip,grf = <&grf>;
1519 status = "disabled";
1521 tcphy1_dp: dp-port {
1525 tcphy1_usb3: usb3-port {
1531 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1532 reg = <0x0 0xff848000 0x0 0x100>;
1533 clocks = <&cru PCLK_WDT>;
1534 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1537 rktimer: rktimer@ff850000 {
1538 compatible = "rockchip,rk3399-timer";
1539 reg = <0x0 0xff850000 0x0 0x1000>;
1540 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1541 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1542 clock-names = "pclk", "timer";
1545 spdif: spdif@ff870000 {
1546 compatible = "rockchip,rk3399-spdif";
1547 reg = <0x0 0xff870000 0x0 0x1000>;
1548 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1549 dmas = <&dmac_bus 7>;
1551 clock-names = "mclk", "hclk";
1552 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1553 pinctrl-names = "default";
1554 pinctrl-0 = <&spdif_bus>;
1555 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1556 #sound-dai-cells = <0>;
1557 status = "disabled";
1560 i2s0: i2s@ff880000 {
1561 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1562 reg = <0x0 0xff880000 0x0 0x1000>;
1563 rockchip,grf = <&grf>;
1564 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1565 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1566 dma-names = "tx", "rx";
1567 clock-names = "i2s_clk", "i2s_hclk";
1568 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1569 pinctrl-names = "default";
1570 pinctrl-0 = <&i2s0_8ch_bus>;
1571 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1572 #sound-dai-cells = <0>;
1573 status = "disabled";
1576 i2s1: i2s@ff890000 {
1577 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1578 reg = <0x0 0xff890000 0x0 0x1000>;
1579 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1580 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1581 dma-names = "tx", "rx";
1582 clock-names = "i2s_clk", "i2s_hclk";
1583 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1584 pinctrl-names = "default";
1585 pinctrl-0 = <&i2s1_2ch_bus>;
1586 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1587 #sound-dai-cells = <0>;
1588 status = "disabled";
1591 i2s2: i2s@ff8a0000 {
1592 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1593 reg = <0x0 0xff8a0000 0x0 0x1000>;
1594 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1595 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1596 dma-names = "tx", "rx";
1597 clock-names = "i2s_clk", "i2s_hclk";
1598 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1599 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1600 #sound-dai-cells = <0>;
1601 status = "disabled";
1604 vopl: vop@ff8f0000 {
1605 compatible = "rockchip,rk3399-vop-lit";
1606 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1607 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1608 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1609 assigned-clock-rates = <400000000>, <100000000>;
1610 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1611 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1612 iommus = <&vopl_mmu>;
1613 power-domains = <&power RK3399_PD_VOPL>;
1614 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1615 reset-names = "axi", "ahb", "dclk";
1616 status = "disabled";
1619 #address-cells = <1>;
1622 vopl_out_mipi: endpoint@0 {
1624 remote-endpoint = <&mipi_in_vopl>;
1627 vopl_out_edp: endpoint@1 {
1629 remote-endpoint = <&edp_in_vopl>;
1632 vopl_out_hdmi: endpoint@2 {
1634 remote-endpoint = <&hdmi_in_vopl>;
1637 vopl_out_mipi1: endpoint@3 {
1639 remote-endpoint = <&mipi1_in_vopl>;
1642 vopl_out_dp: endpoint@4 {
1644 remote-endpoint = <&dp_in_vopl>;
1649 vopl_mmu: iommu@ff8f3f00 {
1650 compatible = "rockchip,iommu";
1651 reg = <0x0 0xff8f3f00 0x0 0x100>;
1652 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1653 interrupt-names = "vopl_mmu";
1654 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1655 clock-names = "aclk", "iface";
1656 power-domains = <&power RK3399_PD_VOPL>;
1658 status = "disabled";
1661 vopb: vop@ff900000 {
1662 compatible = "rockchip,rk3399-vop-big";
1663 reg = <0x0 0xff900000 0x0 0x3efc>;
1664 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1665 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1666 assigned-clock-rates = <400000000>, <100000000>;
1667 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1668 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1669 iommus = <&vopb_mmu>;
1670 power-domains = <&power RK3399_PD_VOPB>;
1671 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1672 reset-names = "axi", "ahb", "dclk";
1673 status = "disabled";
1676 #address-cells = <1>;
1679 vopb_out_edp: endpoint@0 {
1681 remote-endpoint = <&edp_in_vopb>;
1684 vopb_out_mipi: endpoint@1 {
1686 remote-endpoint = <&mipi_in_vopb>;
1689 vopb_out_hdmi: endpoint@2 {
1691 remote-endpoint = <&hdmi_in_vopb>;
1694 vopb_out_mipi1: endpoint@3 {
1696 remote-endpoint = <&mipi1_in_vopb>;
1699 vopb_out_dp: endpoint@4 {
1701 remote-endpoint = <&dp_in_vopb>;
1706 vopb_mmu: iommu@ff903f00 {
1707 compatible = "rockchip,iommu";
1708 reg = <0x0 0xff903f00 0x0 0x100>;
1709 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1710 interrupt-names = "vopb_mmu";
1711 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1712 clock-names = "aclk", "iface";
1713 power-domains = <&power RK3399_PD_VOPB>;
1715 status = "disabled";
1718 isp0: isp0@ff910000 {
1719 compatible = "rockchip,rk3399-cif-isp";
1720 reg = <0x0 0xff910000 0x0 0x4000>;
1721 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1722 clocks = <&cru SCLK_ISP0>,
1723 <&cru ACLK_ISP0_WRAPPER>,
1724 <&cru HCLK_ISP0_WRAPPER>;
1725 clock-names = "isp", "aclk", "hclk";
1726 iommus = <&isp0_mmu>;
1727 phys = <&mipi_dphy_rx0>;
1729 power-domains = <&power RK3399_PD_ISP0>;
1730 status = "disabled";
1733 #address-cells = <1>;
1738 #address-cells = <1>;
1744 isp0_mmu: iommu@ff914000 {
1745 compatible = "rockchip,iommu";
1746 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1747 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1748 interrupt-names = "isp0_mmu";
1749 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1750 clock-names = "aclk", "iface";
1752 power-domains = <&power RK3399_PD_ISP0>;
1753 rockchip,disable-mmu-reset;
1756 isp1_mmu: iommu@ff924000 {
1757 compatible = "rockchip,iommu";
1758 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1759 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1760 interrupt-names = "isp1_mmu";
1761 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1762 clock-names = "aclk", "iface";
1764 power-domains = <&power RK3399_PD_ISP1>;
1765 rockchip,disable-mmu-reset;
1768 hdmi_sound: hdmi-sound {
1769 compatible = "simple-audio-card";
1770 simple-audio-card,format = "i2s";
1771 simple-audio-card,mclk-fs = <256>;
1772 simple-audio-card,name = "hdmi-sound";
1773 status = "disabled";
1775 simple-audio-card,cpu {
1776 sound-dai = <&i2s2>;
1778 simple-audio-card,codec {
1779 sound-dai = <&hdmi>;
1783 hdmi: hdmi@ff940000 {
1784 compatible = "rockchip,rk3399-dw-hdmi";
1785 reg = <0x0 0xff940000 0x0 0x20000>;
1786 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1787 clocks = <&cru PCLK_HDMI_CTRL>,
1788 <&cru SCLK_HDMI_SFR>,
1790 <&cru PCLK_VIO_GRF>,
1791 <&cru SCLK_HDMI_CEC>;
1792 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1793 power-domains = <&power RK3399_PD_HDCP>;
1795 rockchip,grf = <&grf>;
1796 #sound-dai-cells = <0>;
1797 status = "disabled";
1801 #address-cells = <1>;
1804 hdmi_in_vopb: endpoint@0 {
1806 remote-endpoint = <&vopb_out_hdmi>;
1808 hdmi_in_vopl: endpoint@1 {
1810 remote-endpoint = <&vopl_out_hdmi>;
1816 mipi_dsi: mipi@ff960000 {
1817 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1818 reg = <0x0 0xff960000 0x0 0x8000>;
1819 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1820 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1821 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1822 clock-names = "ref", "pclk", "phy_cfg", "grf";
1823 power-domains = <&power RK3399_PD_VIO>;
1824 resets = <&cru SRST_P_MIPI_DSI0>;
1825 reset-names = "apb";
1826 rockchip,grf = <&grf>;
1827 #address-cells = <1>;
1829 status = "disabled";
1832 #address-cells = <1>;
1837 #address-cells = <1>;
1840 mipi_in_vopb: endpoint@0 {
1842 remote-endpoint = <&vopb_out_mipi>;
1844 mipi_in_vopl: endpoint@1 {
1846 remote-endpoint = <&vopl_out_mipi>;
1852 mipi_dsi1: mipi@ff968000 {
1853 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1854 reg = <0x0 0xff968000 0x0 0x8000>;
1855 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1856 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1857 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1858 clock-names = "ref", "pclk", "phy_cfg", "grf";
1859 power-domains = <&power RK3399_PD_VIO>;
1860 resets = <&cru SRST_P_MIPI_DSI1>;
1861 reset-names = "apb";
1862 rockchip,grf = <&grf>;
1863 #address-cells = <1>;
1865 status = "disabled";
1868 #address-cells = <1>;
1873 #address-cells = <1>;
1876 mipi1_in_vopb: endpoint@0 {
1878 remote-endpoint = <&vopb_out_mipi1>;
1881 mipi1_in_vopl: endpoint@1 {
1883 remote-endpoint = <&vopl_out_mipi1>;
1890 compatible = "rockchip,rk3399-edp";
1891 reg = <0x0 0xff970000 0x0 0x8000>;
1892 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1893 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1894 clock-names = "dp", "pclk", "grf";
1895 pinctrl-names = "default";
1896 pinctrl-0 = <&edp_hpd>;
1897 power-domains = <&power RK3399_PD_EDP>;
1898 resets = <&cru SRST_P_EDP_CTRL>;
1900 rockchip,grf = <&grf>;
1901 status = "disabled";
1904 #address-cells = <1>;
1908 #address-cells = <1>;
1911 edp_in_vopb: endpoint@0 {
1913 remote-endpoint = <&vopb_out_edp>;
1916 edp_in_vopl: endpoint@1 {
1918 remote-endpoint = <&vopl_out_edp>;
1925 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1926 reg = <0x0 0xff9a0000 0x0 0x10000>;
1927 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1928 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1929 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1930 interrupt-names = "job", "mmu", "gpu";
1931 clocks = <&cru ACLK_GPU>;
1932 #cooling-cells = <2>;
1933 power-domains = <&power RK3399_PD_GPU>;
1934 status = "disabled";
1938 compatible = "rockchip,rk3399-pinctrl";
1939 rockchip,grf = <&grf>;
1940 rockchip,pmu = <&pmugrf>;
1941 #address-cells = <2>;
1945 gpio0: gpio0@ff720000 {
1946 compatible = "rockchip,gpio-bank";
1947 reg = <0x0 0xff720000 0x0 0x100>;
1948 clocks = <&pmucru PCLK_GPIO0_PMU>;
1949 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1952 #gpio-cells = <0x2>;
1954 interrupt-controller;
1955 #interrupt-cells = <0x2>;
1958 gpio1: gpio1@ff730000 {
1959 compatible = "rockchip,gpio-bank";
1960 reg = <0x0 0xff730000 0x0 0x100>;
1961 clocks = <&pmucru PCLK_GPIO1_PMU>;
1962 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1965 #gpio-cells = <0x2>;
1967 interrupt-controller;
1968 #interrupt-cells = <0x2>;
1971 gpio2: gpio2@ff780000 {
1972 compatible = "rockchip,gpio-bank";
1973 reg = <0x0 0xff780000 0x0 0x100>;
1974 clocks = <&cru PCLK_GPIO2>;
1975 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1978 #gpio-cells = <0x2>;
1980 interrupt-controller;
1981 #interrupt-cells = <0x2>;
1984 gpio3: gpio3@ff788000 {
1985 compatible = "rockchip,gpio-bank";
1986 reg = <0x0 0xff788000 0x0 0x100>;
1987 clocks = <&cru PCLK_GPIO3>;
1988 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1991 #gpio-cells = <0x2>;
1993 interrupt-controller;
1994 #interrupt-cells = <0x2>;
1997 gpio4: gpio4@ff790000 {
1998 compatible = "rockchip,gpio-bank";
1999 reg = <0x0 0xff790000 0x0 0x100>;
2000 clocks = <&cru PCLK_GPIO4>;
2001 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2004 #gpio-cells = <0x2>;
2006 interrupt-controller;
2007 #interrupt-cells = <0x2>;
2010 pcfg_pull_up: pcfg-pull-up {
2014 pcfg_pull_down: pcfg-pull-down {
2018 pcfg_pull_none: pcfg-pull-none {
2022 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2024 drive-strength = <12>;
2027 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2029 drive-strength = <13>;
2032 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2034 drive-strength = <18>;
2037 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2039 drive-strength = <20>;
2042 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2044 drive-strength = <2>;
2047 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2049 drive-strength = <8>;
2052 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2054 drive-strength = <18>;
2057 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2059 drive-strength = <20>;
2062 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2064 drive-strength = <4>;
2067 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2069 drive-strength = <8>;
2072 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2074 drive-strength = <12>;
2077 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2079 drive-strength = <18>;
2082 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2084 drive-strength = <20>;
2087 pcfg_output_high: pcfg-output-high {
2091 pcfg_output_low: pcfg-output-low {
2097 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2104 <4 RK_PC7 2 &pcfg_pull_none>;
2109 rgmii_pins: rgmii-pins {
2112 <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2114 <3 RK_PB6 1 &pcfg_pull_none>,
2116 <3 RK_PB5 1 &pcfg_pull_none>,
2118 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2120 <3 RK_PB3 1 &pcfg_pull_none>,
2122 <3 RK_PB1 1 &pcfg_pull_none>,
2124 <3 RK_PB0 1 &pcfg_pull_none>,
2126 <3 RK_PA7 1 &pcfg_pull_none>,
2128 <3 RK_PA6 1 &pcfg_pull_none>,
2130 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2132 <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2134 <3 RK_PA3 1 &pcfg_pull_none>,
2136 <3 RK_PA2 1 &pcfg_pull_none>,
2138 <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2140 <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2143 rmii_pins: rmii-pins {
2146 <3 RK_PB5 1 &pcfg_pull_none>,
2148 <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2150 <3 RK_PB3 1 &pcfg_pull_none>,
2152 <3 RK_PB2 1 &pcfg_pull_none>,
2154 <3 RK_PB1 1 &pcfg_pull_none>,
2156 <3 RK_PB0 1 &pcfg_pull_none>,
2158 <3 RK_PA7 1 &pcfg_pull_none>,
2160 <3 RK_PA6 1 &pcfg_pull_none>,
2162 <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2164 <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2169 i2c0_xfer: i2c0-xfer {
2171 <1 RK_PB7 2 &pcfg_pull_none>,
2172 <1 RK_PC0 2 &pcfg_pull_none>;
2177 i2c1_xfer: i2c1-xfer {
2179 <4 RK_PA2 1 &pcfg_pull_none>,
2180 <4 RK_PA1 1 &pcfg_pull_none>;
2185 i2c2_xfer: i2c2-xfer {
2187 <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2188 <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2193 i2c3_xfer: i2c3-xfer {
2195 <4 RK_PC1 1 &pcfg_pull_none>,
2196 <4 RK_PC0 1 &pcfg_pull_none>;
2201 i2c4_xfer: i2c4-xfer {
2203 <1 RK_PB4 1 &pcfg_pull_none>,
2204 <1 RK_PB3 1 &pcfg_pull_none>;
2209 i2c5_xfer: i2c5-xfer {
2211 <3 RK_PB3 2 &pcfg_pull_none>,
2212 <3 RK_PB2 2 &pcfg_pull_none>;
2217 i2c6_xfer: i2c6-xfer {
2219 <2 RK_PB2 2 &pcfg_pull_none>,
2220 <2 RK_PB1 2 &pcfg_pull_none>;
2225 i2c7_xfer: i2c7-xfer {
2227 <2 RK_PB0 2 &pcfg_pull_none>,
2228 <2 RK_PA7 2 &pcfg_pull_none>;
2233 i2c8_xfer: i2c8-xfer {
2235 <1 RK_PC5 1 &pcfg_pull_none>,
2236 <1 RK_PC4 1 &pcfg_pull_none>;
2241 i2s0_2ch_bus: i2s0-2ch-bus {
2243 <3 RK_PD0 1 &pcfg_pull_none>,
2244 <3 RK_PD1 1 &pcfg_pull_none>,
2245 <3 RK_PD2 1 &pcfg_pull_none>,
2246 <3 RK_PD3 1 &pcfg_pull_none>,
2247 <3 RK_PD7 1 &pcfg_pull_none>,
2248 <4 RK_PA0 1 &pcfg_pull_none>;
2251 i2s0_8ch_bus: i2s0-8ch-bus {
2253 <3 RK_PD0 1 &pcfg_pull_none>,
2254 <3 RK_PD1 1 &pcfg_pull_none>,
2255 <3 RK_PD2 1 &pcfg_pull_none>,
2256 <3 RK_PD3 1 &pcfg_pull_none>,
2257 <3 RK_PD4 1 &pcfg_pull_none>,
2258 <3 RK_PD5 1 &pcfg_pull_none>,
2259 <3 RK_PD6 1 &pcfg_pull_none>,
2260 <3 RK_PD7 1 &pcfg_pull_none>,
2261 <4 RK_PA0 1 &pcfg_pull_none>;
2266 i2s1_2ch_bus: i2s1-2ch-bus {
2268 <4 RK_PA3 1 &pcfg_pull_none>,
2269 <4 RK_PA4 1 &pcfg_pull_none>,
2270 <4 RK_PA5 1 &pcfg_pull_none>,
2271 <4 RK_PA6 1 &pcfg_pull_none>,
2272 <4 RK_PA7 1 &pcfg_pull_none>;
2277 sdio0_bus1: sdio0-bus1 {
2279 <2 RK_PC4 1 &pcfg_pull_up>;
2282 sdio0_bus4: sdio0-bus4 {
2284 <2 RK_PC4 1 &pcfg_pull_up>,
2285 <2 RK_PC5 1 &pcfg_pull_up>,
2286 <2 RK_PC6 1 &pcfg_pull_up>,
2287 <2 RK_PC7 1 &pcfg_pull_up>;
2290 sdio0_cmd: sdio0-cmd {
2292 <2 RK_PD0 1 &pcfg_pull_up>;
2295 sdio0_clk: sdio0-clk {
2297 <2 RK_PD1 1 &pcfg_pull_none>;
2300 sdio0_cd: sdio0-cd {
2302 <2 RK_PD2 1 &pcfg_pull_up>;
2305 sdio0_pwr: sdio0-pwr {
2307 <2 RK_PD3 1 &pcfg_pull_up>;
2310 sdio0_bkpwr: sdio0-bkpwr {
2312 <2 RK_PD4 1 &pcfg_pull_up>;
2315 sdio0_wp: sdio0-wp {
2317 <0 RK_PA3 1 &pcfg_pull_up>;
2320 sdio0_int: sdio0-int {
2322 <0 RK_PA4 1 &pcfg_pull_up>;
2327 sdmmc_bus1: sdmmc-bus1 {
2329 <4 RK_PB0 1 &pcfg_pull_up>;
2332 sdmmc_bus4: sdmmc-bus4 {
2334 <4 RK_PB0 1 &pcfg_pull_up>,
2335 <4 RK_PB1 1 &pcfg_pull_up>,
2336 <4 RK_PB2 1 &pcfg_pull_up>,
2337 <4 RK_PB3 1 &pcfg_pull_up>;
2340 sdmmc_clk: sdmmc-clk {
2342 <4 RK_PB4 1 &pcfg_pull_none>;
2345 sdmmc_cmd: sdmmc-cmd {
2347 <4 RK_PB5 1 &pcfg_pull_up>;
2350 sdmmc_cd: sdmmc-cd {
2352 <0 RK_PA7 1 &pcfg_pull_up>;
2355 sdmmc_wp: sdmmc-wp {
2357 <0 RK_PB0 1 &pcfg_pull_up>;
2362 ap_pwroff: ap-pwroff {
2363 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2366 ddrio_pwroff: ddrio-pwroff {
2367 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2372 spdif_bus: spdif-bus {
2374 <4 RK_PC5 1 &pcfg_pull_none>;
2377 spdif_bus_1: spdif-bus-1 {
2379 <3 RK_PC0 3 &pcfg_pull_none>;
2384 spi0_clk: spi0-clk {
2386 <3 RK_PA6 2 &pcfg_pull_up>;
2388 spi0_cs0: spi0-cs0 {
2390 <3 RK_PA7 2 &pcfg_pull_up>;
2392 spi0_cs1: spi0-cs1 {
2394 <3 RK_PB0 2 &pcfg_pull_up>;
2398 <3 RK_PA5 2 &pcfg_pull_up>;
2402 <3 RK_PA4 2 &pcfg_pull_up>;
2407 spi1_clk: spi1-clk {
2409 <1 RK_PB1 2 &pcfg_pull_up>;
2411 spi1_cs0: spi1-cs0 {
2413 <1 RK_PB2 2 &pcfg_pull_up>;
2417 <1 RK_PA7 2 &pcfg_pull_up>;
2421 <1 RK_PB0 2 &pcfg_pull_up>;
2426 spi2_clk: spi2-clk {
2428 <2 RK_PB3 1 &pcfg_pull_up>;
2430 spi2_cs0: spi2-cs0 {
2432 <2 RK_PB4 1 &pcfg_pull_up>;
2436 <2 RK_PB1 1 &pcfg_pull_up>;
2440 <2 RK_PB2 1 &pcfg_pull_up>;
2445 spi3_clk: spi3-clk {
2447 <1 RK_PC1 1 &pcfg_pull_up>;
2449 spi3_cs0: spi3-cs0 {
2451 <1 RK_PC2 1 &pcfg_pull_up>;
2455 <1 RK_PB7 1 &pcfg_pull_up>;
2459 <1 RK_PC0 1 &pcfg_pull_up>;
2464 spi4_clk: spi4-clk {
2466 <3 RK_PA2 2 &pcfg_pull_up>;
2468 spi4_cs0: spi4-cs0 {
2470 <3 RK_PA3 2 &pcfg_pull_up>;
2474 <3 RK_PA0 2 &pcfg_pull_up>;
2478 <3 RK_PA1 2 &pcfg_pull_up>;
2483 spi5_clk: spi5-clk {
2485 <2 RK_PC6 2 &pcfg_pull_up>;
2487 spi5_cs0: spi5-cs0 {
2489 <2 RK_PC7 2 &pcfg_pull_up>;
2493 <2 RK_PC4 2 &pcfg_pull_up>;
2497 <2 RK_PC5 2 &pcfg_pull_up>;
2502 test_clkout0: test-clkout0 {
2504 <0 RK_PA0 1 &pcfg_pull_none>;
2507 test_clkout1: test-clkout1 {
2509 <2 RK_PD1 2 &pcfg_pull_none>;
2512 test_clkout2: test-clkout2 {
2514 <0 RK_PB0 3 &pcfg_pull_none>;
2520 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2524 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2529 uart0_xfer: uart0-xfer {
2531 <2 RK_PC0 1 &pcfg_pull_up>,
2532 <2 RK_PC1 1 &pcfg_pull_none>;
2535 uart0_cts: uart0-cts {
2537 <2 RK_PC2 1 &pcfg_pull_none>;
2540 uart0_rts: uart0-rts {
2542 <2 RK_PC3 1 &pcfg_pull_none>;
2547 uart1_xfer: uart1-xfer {
2549 <3 RK_PB4 2 &pcfg_pull_up>,
2550 <3 RK_PB5 2 &pcfg_pull_none>;
2555 uart2a_xfer: uart2a-xfer {
2557 <4 RK_PB0 2 &pcfg_pull_up>,
2558 <4 RK_PB1 2 &pcfg_pull_none>;
2563 uart2b_xfer: uart2b-xfer {
2565 <4 RK_PC0 2 &pcfg_pull_up>,
2566 <4 RK_PC1 2 &pcfg_pull_none>;
2571 uart2c_xfer: uart2c-xfer {
2573 <4 RK_PC3 1 &pcfg_pull_up>,
2574 <4 RK_PC4 1 &pcfg_pull_none>;
2579 uart3_xfer: uart3-xfer {
2581 <3 RK_PB6 2 &pcfg_pull_up>,
2582 <3 RK_PB7 2 &pcfg_pull_none>;
2585 uart3_cts: uart3-cts {
2587 <3 RK_PC0 2 &pcfg_pull_none>;
2590 uart3_rts: uart3-rts {
2592 <3 RK_PC1 2 &pcfg_pull_none>;
2597 uart4_xfer: uart4-xfer {
2599 <1 RK_PA7 1 &pcfg_pull_up>,
2600 <1 RK_PB0 1 &pcfg_pull_none>;
2605 uarthdcp_xfer: uarthdcp-xfer {
2607 <4 RK_PC5 2 &pcfg_pull_up>,
2608 <4 RK_PC6 2 &pcfg_pull_none>;
2613 pwm0_pin: pwm0-pin {
2615 <4 RK_PC2 1 &pcfg_pull_none>;
2618 pwm0_pin_pull_down: pwm0-pin-pull-down {
2620 <4 RK_PC2 1 &pcfg_pull_down>;
2623 vop0_pwm_pin: vop0-pwm-pin {
2625 <4 RK_PC2 2 &pcfg_pull_none>;
2628 vop1_pwm_pin: vop1-pwm-pin {
2630 <4 RK_PC2 3 &pcfg_pull_none>;
2635 pwm1_pin: pwm1-pin {
2637 <4 RK_PC6 1 &pcfg_pull_none>;
2640 pwm1_pin_pull_down: pwm1-pin-pull-down {
2642 <4 RK_PC6 1 &pcfg_pull_down>;
2647 pwm2_pin: pwm2-pin {
2649 <1 RK_PC3 1 &pcfg_pull_none>;
2652 pwm2_pin_pull_down: pwm2-pin-pull-down {
2654 <1 RK_PC3 1 &pcfg_pull_down>;
2659 pwm3a_pin: pwm3a-pin {
2661 <0 RK_PA6 1 &pcfg_pull_none>;
2666 pwm3b_pin: pwm3b-pin {
2668 <1 RK_PB6 1 &pcfg_pull_none>;
2673 hdmi_i2c_xfer: hdmi-i2c-xfer {
2675 <4 RK_PC1 3 &pcfg_pull_none>,
2676 <4 RK_PC0 3 &pcfg_pull_none>;
2679 hdmi_cec: hdmi-cec {
2681 <4 RK_PC7 1 &pcfg_pull_none>;
2686 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2688 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2691 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2693 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;