2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/pwm/pwm.h>
45 #include "rk3399.dtsi"
46 #include "rk3399-opp.dtsi"
49 model = "Firefly-RK3399 Board";
50 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
52 backlight: backlight {
53 compatible = "pwm-backlight";
54 enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
55 pwms = <&pwm0 0 25000 0>;
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73 128 129 130 131 132 133 134 135
74 136 137 138 139 140 141 142 143
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80 184 185 186 187 188 189 190 191
81 192 193 194 195 196 197 198 199
82 200 201 202 203 204 205 206 207
83 208 209 210 211 212 213 214 215
84 216 217 218 219 220 221 222 223
85 224 225 226 227 228 229 230 231
86 232 233 234 235 236 237 238 239
87 240 241 242 243 244 245 246 247
88 248 249 250 251 252 253 254 255>;
89 default-brightness-level = <200>;
92 clkin_gmac: external-gmac-clock {
93 compatible = "fixed-clock";
94 clock-frequency = <125000000>;
95 clock-output-names = "clkin_gmac";
100 compatible = "regulator-fixed";
101 regulator-name = "dc_12v";
104 regulator-min-microvolt = <12000000>;
105 regulator-max-microvolt = <12000000>;
109 compatible = "simple-audio-card";
110 simple-audio-card,name = "rockchip,rt5640-codec";
111 simple-audio-card,format = "i2s";
112 simple-audio-card,mclk-fs = <256>;
113 simple-audio-card,widgets =
114 "Microphone", "Mic Jack",
115 "Headphone", "Headphone Jack";
116 simple-audio-card,routing =
117 "Mic Jack", "MICBIAS1",
119 "Headphone Jack", "HPOL",
120 "Headphone Jack", "HPOR";
122 simple-audio-card,cpu {
126 simple-audio-card,codec {
127 sound-dai = <&rt5640>;
131 sdio_pwrseq: sdio-pwrseq {
132 compatible = "mmc-pwrseq-simple";
134 clock-names = "ext_clock";
135 pinctrl-names = "default";
136 pinctrl-0 = <&wifi_enable_h>;
139 * On the module itself this is one of these (depending
140 * on the actual card populated):
141 * - SDIO_RESET_L_WL_REG_ON
142 * - PDN (power down when low)
144 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
147 /* switched by pmic_sleep */
148 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
149 compatible = "regulator-fixed";
150 regulator-name = "vcc1v8_s3";
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <1800000>;
155 vin-supply = <&vcc_1v8>;
158 vcc3v3_pcie: vcc3v3-pcie-regulator {
159 compatible = "regulator-fixed";
161 gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pcie_pwr_en>;
164 regulator-name = "vcc3v3_pcie";
167 vin-supply = <&dc_12v>;
170 vcc3v3_sys: vcc3v3-sys {
171 compatible = "regulator-fixed";
172 regulator-name = "vcc3v3_sys";
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
177 vin-supply = <&vcc_sys>;
180 /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
181 vcc5v0_host: vcc5v0-host-regulator {
182 compatible = "regulator-fixed";
184 gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&vcc5v0_host_en>;
187 regulator-name = "vcc5v0_host";
189 vin-supply = <&vcc_sys>;
193 compatible = "regulator-fixed";
194 regulator-name = "vcc_sys";
197 regulator-min-microvolt = <5000000>;
198 regulator-max-microvolt = <5000000>;
199 vin-supply = <&dc_12v>;
203 compatible = "pwm-regulator";
204 pwms = <&pwm2 0 25000 1>;
205 regulator-name = "vdd_log";
208 regulator-min-microvolt = <800000>;
209 regulator-max-microvolt = <1400000>;
210 vin-supply = <&vcc_sys>;
215 cpu-supply = <&vdd_cpu_l>;
219 cpu-supply = <&vdd_cpu_l>;
223 cpu-supply = <&vdd_cpu_l>;
227 cpu-supply = <&vdd_cpu_l>;
231 cpu-supply = <&vdd_cpu_b>;
235 cpu-supply = <&vdd_cpu_b>;
243 assigned-clocks = <&cru SCLK_RMII_SRC>;
244 assigned-clock-parents = <&clkin_gmac>;
245 clock_in_out = "input";
246 phy-supply = <&vcc_lan>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&rgmii_pins>;
250 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
251 snps,reset-active-low;
252 snps,reset-delays-us = <0 10000 50000>;
259 clock-frequency = <400000>;
260 i2c-scl-rising-time-ns = <168>;
261 i2c-scl-falling-time-ns = <4>;
265 compatible = "rockchip,rk808";
267 interrupt-parent = <&gpio1>;
268 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
270 clock-output-names = "xin32k", "rk808-clkout2";
271 pinctrl-names = "default";
272 pinctrl-0 = <&pmic_int_l>;
273 rockchip,system-power-controller;
276 vcc1-supply = <&vcc_sys>;
277 vcc2-supply = <&vcc_sys>;
278 vcc3-supply = <&vcc_sys>;
279 vcc4-supply = <&vcc_sys>;
280 vcc6-supply = <&vcc_sys>;
281 vcc7-supply = <&vcc_sys>;
282 vcc8-supply = <&vcc3v3_sys>;
283 vcc9-supply = <&vcc_sys>;
284 vcc10-supply = <&vcc_sys>;
285 vcc11-supply = <&vcc_sys>;
286 vcc12-supply = <&vcc3v3_sys>;
287 vddio-supply = <&vcc1v8_pmu>;
290 vdd_center: DCDC_REG1 {
291 regulator-name = "vdd_center";
294 regulator-min-microvolt = <750000>;
295 regulator-max-microvolt = <1350000>;
296 regulator-ramp-delay = <6001>;
297 regulator-state-mem {
298 regulator-off-in-suspend;
302 vdd_cpu_l: DCDC_REG2 {
303 regulator-name = "vdd_cpu_l";
306 regulator-min-microvolt = <750000>;
307 regulator-max-microvolt = <1350000>;
308 regulator-ramp-delay = <6001>;
309 regulator-state-mem {
310 regulator-off-in-suspend;
315 regulator-name = "vcc_ddr";
318 regulator-state-mem {
319 regulator-on-in-suspend;
324 regulator-name = "vcc_1v8";
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <1800000>;
329 regulator-state-mem {
330 regulator-on-in-suspend;
331 regulator-suspend-microvolt = <1800000>;
335 vcc1v8_dvp: LDO_REG1 {
336 regulator-name = "vcc1v8_dvp";
339 regulator-min-microvolt = <1800000>;
340 regulator-max-microvolt = <1800000>;
341 regulator-state-mem {
342 regulator-off-in-suspend;
346 vcc2v8_dvp: LDO_REG2 {
347 regulator-name = "vcc2v8_dvp";
350 regulator-min-microvolt = <2800000>;
351 regulator-max-microvolt = <2800000>;
352 regulator-state-mem {
353 regulator-off-in-suspend;
357 vcc1v8_pmu: LDO_REG3 {
358 regulator-name = "vcc1v8_pmu";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>;
363 regulator-state-mem {
364 regulator-on-in-suspend;
365 regulator-suspend-microvolt = <1800000>;
370 regulator-name = "vcc_sdio";
373 regulator-min-microvolt = <1800000>;
374 regulator-max-microvolt = <3300000>;
375 regulator-state-mem {
376 regulator-on-in-suspend;
377 regulator-suspend-microvolt = <3300000>;
381 vcca3v0_codec: LDO_REG5 {
382 regulator-name = "vcca3v0_codec";
385 regulator-min-microvolt = <3000000>;
386 regulator-max-microvolt = <3000000>;
387 regulator-state-mem {
388 regulator-off-in-suspend;
393 regulator-name = "vcc_1v5";
396 regulator-min-microvolt = <1500000>;
397 regulator-max-microvolt = <1500000>;
398 regulator-state-mem {
399 regulator-on-in-suspend;
400 regulator-suspend-microvolt = <1500000>;
404 vcca1v8_codec: LDO_REG7 {
405 regulator-name = "vcca1v8_codec";
408 regulator-min-microvolt = <1800000>;
409 regulator-max-microvolt = <1800000>;
410 regulator-state-mem {
411 regulator-off-in-suspend;
416 regulator-name = "vcc_3v0";
419 regulator-min-microvolt = <3000000>;
420 regulator-max-microvolt = <3000000>;
421 regulator-state-mem {
422 regulator-on-in-suspend;
423 regulator-suspend-microvolt = <3000000>;
427 vcc3v3_s3: vcc_lan: SWITCH_REG1 {
428 regulator-name = "vcc3v3_s3";
431 regulator-state-mem {
432 regulator-off-in-suspend;
436 vcc3v3_s0: SWITCH_REG2 {
437 regulator-name = "vcc3v3_s0";
440 regulator-state-mem {
441 regulator-off-in-suspend;
447 vdd_cpu_b: regulator@40 {
448 compatible = "silergy,syr827";
450 fcs,suspend-voltage-selector = <0>;
451 regulator-name = "vdd_cpu_b";
452 regulator-min-microvolt = <712500>;
453 regulator-max-microvolt = <1500000>;
454 regulator-ramp-delay = <1000>;
457 vin-supply = <&vcc_sys>;
459 regulator-state-mem {
460 regulator-off-in-suspend;
464 vdd_gpu: regulator@41 {
465 compatible = "silergy,syr828";
467 fcs,suspend-voltage-selector = <1>;
468 regulator-name = "vdd_gpu";
469 regulator-min-microvolt = <712500>;
470 regulator-max-microvolt = <1500000>;
471 regulator-ramp-delay = <1000>;
474 vin-supply = <&vcc_sys>;
476 regulator-state-mem {
477 regulator-off-in-suspend;
483 i2c-scl-rising-time-ns = <300>;
484 i2c-scl-falling-time-ns = <15>;
488 compatible = "realtek,rt5640";
490 clocks = <&cru SCLK_I2S_8CH_OUT>;
491 clock-names = "mclk";
492 realtek,in1-differential;
493 #sound-dai-cells = <0>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&rt5640_hpcon>;
500 i2c-scl-rising-time-ns = <450>;
501 i2c-scl-falling-time-ns = <15>;
506 i2c-scl-rising-time-ns = <600>;
507 i2c-scl-falling-time-ns = <20>;
511 compatible = "invensense,mpu6500";
513 interrupt-parent = <&gpio1>;
514 interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
519 rockchip,playback-channels = <8>;
520 rockchip,capture-channels = <8>;
521 #sound-dai-cells = <0>;
526 rockchip,playback-channels = <2>;
527 rockchip,capture-channels = <2>;
528 #sound-dai-cells = <0>;
533 #sound-dai-cells = <0>;
540 bt656-supply = <&vcc1v8_dvp>;
541 audio-supply = <&vcca1v8_codec>;
542 sdmmc-supply = <&vcc_sdio>;
543 gpio1830-supply = <&vcc_3v0>;
551 ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pcie_clkreqn_cpm>;
559 pmu1830-supply = <&vcc_3v0>;
566 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
571 lcd_panel_reset: lcd-panel-reset {
572 rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
577 pcie_pwr_en: pcie-pwr-en {
578 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
581 pcie_3g_drv: pcie-3g-drv {
582 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
587 vsel1_gpio: vsel1-gpio {
588 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
591 vsel2_gpio: vsel2-gpio {
592 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
597 wifi_enable_h: wifi-enable-h {
598 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
603 rt5640_hpcon: rt5640-hpcon {
604 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
609 pmic_int_l: pmic-int-l {
610 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
615 vcc5v0_host_en: vcc5v0-host-en {
616 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
630 vref-supply = <&vcca1v8_s3>;
638 cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
640 max-frequency = <150000000>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
649 mmc-hs400-enhanced-strobe;
655 /* tshut mode 0:CRU 1:GPIO */
656 rockchip,hw-tshut-mode = <1>;
657 /* tshut polarity 0:LOW 1:HIGH */
658 rockchip,hw-tshut-polarity = <1>;
665 u2phy0_otg: otg-port {
669 u2phy0_host: host-port {
670 phy-supply = <&vcc5v0_host>;
678 u2phy1_otg: otg-port {
682 u2phy1_host: host-port {
683 phy-supply = <&vcc5v0_host>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&uart0_xfer &uart0_cts>;