arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   4  */
   5
   6 #include <dt-bindings/clock/rk3368-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3368-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3368";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &uart2;
  32                 serial3 = &uart3;
  33                 serial4 = &uart4;
  34                 spi0 = &spi0;
  35                 spi1 = &spi1;
  36                 spi2 = &spi2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <0x2>;
  41                 #size-cells = <0x0>;
  42
  43                 cpu-map {
  44                         cluster0 {
  45                                 core0 {
  46                                         cpu = <&cpu_b0>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu_b1>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu_b2>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu_b3>;
  56                                 };
  57                         };
  58
  59                         cluster1 {
  60                                 core0 {
  61                                         cpu = <&cpu_l0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu_l1>;
  65                                 };
  66                                 core2 {
  67                                         cpu = <&cpu_l2>;
  68                                 };
  69                                 core3 {
  70                                         cpu = <&cpu_l3>;
  71                                 };
  72                         };
  73                 };
  74
  75                 cpu_l0: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53";
  78                         reg = <0x0 0x0>;
  79                         enable-method = "psci";
  80                         #cooling-cells = <2>; /* min followed by max */
  81                 };
  82
  83                 cpu_l1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         #cooling-cells = <2>; /* min followed by max */
  89                 };
  90
  91                 cpu_l2: cpu@2 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53";
  94                         reg = <0x0 0x2>;
  95                         enable-method = "psci";
  96                         #cooling-cells = <2>; /* min followed by max */
  97                 };
  98
  99                 cpu_l3: cpu@3 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53";
 102                         reg = <0x0 0x3>;
 103                         enable-method = "psci";
 104                         #cooling-cells = <2>; /* min followed by max */
 105                 };
 106
 107                 cpu_b0: cpu@100 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a53";
 110                         reg = <0x0 0x100>;
 111                         enable-method = "psci";
 112                         #cooling-cells = <2>; /* min followed by max */
 113                 };
 114
 115                 cpu_b1: cpu@101 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53";
 118                         reg = <0x0 0x101>;
 119                         enable-method = "psci";
 120                         #cooling-cells = <2>; /* min followed by max */
 121                 };
 122
 123                 cpu_b2: cpu@102 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53";
 126                         reg = <0x0 0x102>;
 127                         enable-method = "psci";
 128                         #cooling-cells = <2>; /* min followed by max */
 129                 };
 130
 131                 cpu_b3: cpu@103 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53";
 134                         reg = <0x0 0x103>;
 135                         enable-method = "psci";
 136                         #cooling-cells = <2>; /* min followed by max */
 137                 };
 138         };
 139
 140         arm-pmu {
 141                 compatible = "arm,armv8-pmuv3";
 142                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 150                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 151                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 152                                      <&cpu_b2>, <&cpu_b3>;
 153         };
 154
 155         psci {
 156                 compatible = "arm,psci-0.2";
 157                 method = "smc";
 158         };
 159
 160         timer {
 161                 compatible = "arm,armv8-timer";
 162                 interrupts = <GIC_PPI 13
 163                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 164                              <GIC_PPI 14
 165                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 166                              <GIC_PPI 11
 167                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 168                              <GIC_PPI 10
 169                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 170         };
 171
 172         xin24m: oscillator {
 173                 compatible = "fixed-clock";
 174                 clock-frequency = <24000000>;
 175                 clock-output-names = "xin24m";
 176                 #clock-cells = <0>;
 177         };
 178
 179         sdmmc: mmc@ff0c0000 {
 180                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 181                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 182                 max-frequency = <150000000>;
 183                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 184                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 185                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 186                 fifo-depth = <0x100>;
 187                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 188                 resets = <&cru SRST_MMC0>;
 189                 reset-names = "reset";
 190                 status = "disabled";
 191         };
 192
 193         sdio0: mmc@ff0d0000 {
 194                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 195                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 196                 max-frequency = <150000000>;
 197                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 198                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 199                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 200                 fifo-depth = <0x100>;
 201                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 202                 resets = <&cru SRST_SDIO0>;
 203                 reset-names = "reset";
 204                 status = "disabled";
 205         };
 206
 207         emmc: mmc@ff0f0000 {
 208                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 209                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 210                 max-frequency = <150000000>;
 211                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 212                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 213                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 214                 fifo-depth = <0x100>;
 215                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 216                 resets = <&cru SRST_EMMC>;
 217                 reset-names = "reset";
 218                 status = "disabled";
 219         };
 220
 221         saradc: saradc@ff100000 {
 222                 compatible = "rockchip,saradc";
 223                 reg = <0x0 0xff100000 0x0 0x100>;
 224                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 225                 #io-channel-cells = <1>;
 226                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 227                 clock-names = "saradc", "apb_pclk";
 228                 resets = <&cru SRST_SARADC>;
 229                 reset-names = "saradc-apb";
 230                 status = "disabled";
 231         };
 232
 233         spi0: spi@ff110000 {
 234                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 235                 reg = <0x0 0xff110000 0x0 0x1000>;
 236                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 237                 clock-names = "spiclk", "apb_pclk";
 238                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 status = "disabled";
 244         };
 245
 246         spi1: spi@ff120000 {
 247                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 248                 reg = <0x0 0xff120000 0x0 0x1000>;
 249                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 250                 clock-names = "spiclk", "apb_pclk";
 251                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 252                 pinctrl-names = "default";
 253                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 status = "disabled";
 257         };
 258
 259         spi2: spi@ff130000 {
 260                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 261                 reg = <0x0 0xff130000 0x0 0x1000>;
 262                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 263                 clock-names = "spiclk", "apb_pclk";
 264                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 265                 pinctrl-names = "default";
 266                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 267                 #address-cells = <1>;
 268                 #size-cells = <0>;
 269                 status = "disabled";
 270         };
 271
 272         i2c2: i2c@ff140000 {
 273                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 274                 reg = <0x0 0xff140000 0x0 0x1000>;
 275                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 clock-names = "i2c";
 279                 clocks = <&cru PCLK_I2C2>;
 280                 pinctrl-names = "default";
 281                 pinctrl-0 = <&i2c2_xfer>;
 282                 status = "disabled";
 283         };
 284
 285         i2c3: i2c@ff150000 {
 286                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 287                 reg = <0x0 0xff150000 0x0 0x1000>;
 288                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291                 clock-names = "i2c";
 292                 clocks = <&cru PCLK_I2C3>;
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&i2c3_xfer>;
 295                 status = "disabled";
 296         };
 297
 298         i2c4: i2c@ff160000 {
 299                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 300                 reg = <0x0 0xff160000 0x0 0x1000>;
 301                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 clock-names = "i2c";
 305                 clocks = <&cru PCLK_I2C4>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&i2c4_xfer>;
 308                 status = "disabled";
 309         };
 310
 311         i2c5: i2c@ff170000 {
 312                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 313                 reg = <0x0 0xff170000 0x0 0x1000>;
 314                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 clock-names = "i2c";
 318                 clocks = <&cru PCLK_I2C5>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&i2c5_xfer>;
 321                 status = "disabled";
 322         };
 323
 324         uart0: serial@ff180000 {
 325                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 326                 reg = <0x0 0xff180000 0x0 0x100>;
 327                 clock-frequency = <24000000>;
 328                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 329                 clock-names = "baudclk", "apb_pclk";
 330                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 331                 reg-shift = <2>;
 332                 reg-io-width = <4>;
 333                 status = "disabled";
 334         };
 335
 336         uart1: serial@ff190000 {
 337                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 338                 reg = <0x0 0xff190000 0x0 0x100>;
 339                 clock-frequency = <24000000>;
 340                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 341                 clock-names = "baudclk", "apb_pclk";
 342                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 343                 reg-shift = <2>;
 344                 reg-io-width = <4>;
 345                 status = "disabled";
 346         };
 347
 348         uart3: serial@ff1b0000 {
 349                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 350                 reg = <0x0 0xff1b0000 0x0 0x100>;
 351                 clock-frequency = <24000000>;
 352                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 353                 clock-names = "baudclk", "apb_pclk";
 354                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 355                 reg-shift = <2>;
 356                 reg-io-width = <4>;
 357                 status = "disabled";
 358         };
 359
 360         uart4: serial@ff1c0000 {
 361                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 362                 reg = <0x0 0xff1c0000 0x0 0x100>;
 363                 clock-frequency = <24000000>;
 364                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 365                 clock-names = "baudclk", "apb_pclk";
 366                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 367                 reg-shift = <2>;
 368                 reg-io-width = <4>;
 369                 status = "disabled";
 370         };
 371
 372         dmac_peri: dma-controller@ff250000 {
 373                 compatible = "arm,pl330", "arm,primecell";
 374                 reg = <0x0 0xff250000 0x0 0x4000>;
 375                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 376                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 377                 #dma-cells = <1>;
 378                 arm,pl330-broken-no-flushp;
 379                 arm,pl330-periph-burst;
 380                 clocks = <&cru ACLK_DMAC_PERI>;
 381                 clock-names = "apb_pclk";
 382         };
 383
 384         thermal-zones {
 385                 cpu_thermal: cpu-thermal {
 386                         polling-delay-passive = <100>; /* milliseconds */
 387                         polling-delay = <5000>; /* milliseconds */
 388
 389                         thermal-sensors = <&tsadc 0>;
 390
 391                         trips {
 392                                 cpu_alert0: cpu_alert0 {
 393                                         temperature = <75000>; /* millicelsius */
 394                                         hysteresis = <2000>; /* millicelsius */
 395                                         type = "passive";
 396                                 };
 397                                 cpu_alert1: cpu_alert1 {
 398                                         temperature = <80000>; /* millicelsius */
 399                                         hysteresis = <2000>; /* millicelsius */
 400                                         type = "passive";
 401                                 };
 402                                 cpu_crit: cpu_crit {
 403                                         temperature = <95000>; /* millicelsius */
 404                                         hysteresis = <2000>; /* millicelsius */
 405                                         type = "critical";
 406                                 };
 407                         };
 408
 409                         cooling-maps {
 410                                 map0 {
 411                                         trip = <&cpu_alert0>;
 412                                         cooling-device =
 413                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 414                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 415                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 416                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 417                                 };
 418                                 map1 {
 419                                         trip = <&cpu_alert1>;
 420                                         cooling-device =
 421                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 422                                         <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 423                                         <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 424                                         <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 425                                 };
 426                         };
 427                 };
 428
 429                 gpu_thermal: gpu-thermal {
 430                         polling-delay-passive = <100>; /* milliseconds */
 431                         polling-delay = <5000>; /* milliseconds */
 432
 433                         thermal-sensors = <&tsadc 1>;
 434
 435                         trips {
 436                                 gpu_alert0: gpu_alert0 {
 437                                         temperature = <80000>; /* millicelsius */
 438                                         hysteresis = <2000>; /* millicelsius */
 439                                         type = "passive";
 440                                 };
 441                                 gpu_crit: gpu_crit {
 442                                         temperature = <115000>; /* millicelsius */
 443                                         hysteresis = <2000>; /* millicelsius */
 444                                         type = "critical";
 445                                 };
 446                         };
 447
 448                         cooling-maps {
 449                                 map0 {
 450                                         trip = <&gpu_alert0>;
 451                                         cooling-device =
 452                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 453                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 454                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 455                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 456                                 };
 457                         };
 458                 };
 459         };
 460
 461         tsadc: tsadc@ff280000 {
 462                 compatible = "rockchip,rk3368-tsadc";
 463                 reg = <0x0 0xff280000 0x0 0x100>;
 464                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 466                 clock-names = "tsadc", "apb_pclk";
 467                 resets = <&cru SRST_TSADC>;
 468                 reset-names = "tsadc-apb";
 469                 pinctrl-names = "init", "default", "sleep";
 470                 pinctrl-0 = <&otp_pin>;
 471                 pinctrl-1 = <&otp_out>;
 472                 pinctrl-2 = <&otp_pin>;
 473                 #thermal-sensor-cells = <1>;
 474                 rockchip,hw-tshut-temp = <95000>;
 475                 status = "disabled";
 476         };
 477
 478         gmac: ethernet@ff290000 {
 479                 compatible = "rockchip,rk3368-gmac";
 480                 reg = <0x0 0xff290000 0x0 0x10000>;
 481                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 482                 interrupt-names = "macirq";
 483                 rockchip,grf = <&grf>;
 484                 clocks = <&cru SCLK_MAC>,
 485                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 486                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 487                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 488                 clock-names = "stmmaceth",
 489                         "mac_clk_rx", "mac_clk_tx",
 490                         "clk_mac_ref", "clk_mac_refout",
 491                         "aclk_mac", "pclk_mac";
 492                 status = "disabled";
 493         };
 494
 495         usb_host0_ehci: usb@ff500000 {
 496                 compatible = "generic-ehci";
 497                 reg = <0x0 0xff500000 0x0 0x100>;
 498                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&cru HCLK_HOST0>;
 500                 status = "disabled";
 501         };
 502
 503         usb_otg: usb@ff580000 {
 504                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 505                                 "snps,dwc2";
 506                 reg = <0x0 0xff580000 0x0 0x40000>;
 507                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&cru HCLK_OTG0>;
 509                 clock-names = "otg";
 510                 dr_mode = "otg";
 511                 g-np-tx-fifo-size = <16>;
 512                 g-rx-fifo-size = <275>;
 513                 g-tx-fifo-size = <256 128 128 64 64 32>;
 514                 status = "disabled";
 515         };
 516
 517         dmac_bus: dma-controller@ff600000 {
 518                 compatible = "arm,pl330", "arm,primecell";
 519                 reg = <0x0 0xff600000 0x0 0x4000>;
 520                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 521                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 522                 #dma-cells = <1>;
 523                 arm,pl330-broken-no-flushp;
 524                 arm,pl330-periph-burst;
 525                 clocks = <&cru ACLK_DMAC_BUS>;
 526                 clock-names = "apb_pclk";
 527         };
 528
 529         i2c0: i2c@ff650000 {
 530                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 531                 reg = <0x0 0xff650000 0x0 0x1000>;
 532                 clocks = <&cru PCLK_I2C0>;
 533                 clock-names = "i2c";
 534                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c0_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c1: i2c@ff660000 {
 543                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 544                 reg = <0x0 0xff660000 0x0 0x1000>;
 545                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 clock-names = "i2c";
 549                 clocks = <&cru PCLK_I2C1>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c1_xfer>;
 552                 status = "disabled";
 553         };
 554
 555         pwm0: pwm@ff680000 {
 556                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 557                 reg = <0x0 0xff680000 0x0 0x10>;
 558                 #pwm-cells = <3>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&pwm0_pin>;
 561                 clocks = <&cru PCLK_PWM1>;
 562                 status = "disabled";
 563         };
 564
 565         pwm1: pwm@ff680010 {
 566                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 567                 reg = <0x0 0xff680010 0x0 0x10>;
 568                 #pwm-cells = <3>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&pwm1_pin>;
 571                 clocks = <&cru PCLK_PWM1>;
 572                 status = "disabled";
 573         };
 574
 575         pwm2: pwm@ff680020 {
 576                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 577                 reg = <0x0 0xff680020 0x0 0x10>;
 578                 #pwm-cells = <3>;
 579                 clocks = <&cru PCLK_PWM1>;
 580                 status = "disabled";
 581         };
 582
 583         pwm3: pwm@ff680030 {
 584                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 585                 reg = <0x0 0xff680030 0x0 0x10>;
 586                 #pwm-cells = <3>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pwm3_pin>;
 589                 clocks = <&cru PCLK_PWM1>;
 590                 status = "disabled";
 591         };
 592
 593         uart2: serial@ff690000 {
 594                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 595                 reg = <0x0 0xff690000 0x0 0x100>;
 596                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 597                 clock-names = "baudclk", "apb_pclk";
 598                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&uart2_xfer>;
 601                 reg-shift = <2>;
 602                 reg-io-width = <4>;
 603                 status = "disabled";
 604         };
 605
 606         mbox: mbox@ff6b0000 {
 607                 compatible = "rockchip,rk3368-mailbox";
 608                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 609                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 610                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 611                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 612                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 613                 clocks = <&cru PCLK_MAILBOX>;
 614                 clock-names = "pclk_mailbox";
 615                 #mbox-cells = <1>;
 616                 status = "disabled";
 617         };
 618
 619         pmu: power-management@ff730000 {
 620                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 621                 reg = <0x0 0xff730000 0x0 0x1000>;
 622
 623                 power: power-controller {
 624                         compatible = "rockchip,rk3368-power-controller";
 625                         #power-domain-cells = <1>;
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628
 629                         /*
 630                          * Note: Although SCLK_* are the working clocks
 631                          * of device without including on the NOC, needed for
 632                          * synchronous reset.
 633                          *
 634                          * The clocks on the which NOC:
 635                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 636                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 637                          * ACLK_RGA is on ACLK_RGA_NIU.
 638                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 639                          *
 640                          * Which clock are device clocks:
 641                          *      clocks          devices
 642                          *      *_IEP           IEP:Image Enhancement Processor
 643                          *      *_ISP           ISP:Image Signal Processing
 644                          *      *_VIP           VIP:Video Input Processor
 645                          *      *_VOP*          VOP:Visual Output Processor
 646                          *      *_RGA           RGA
 647                          *      *_EDP*          EDP
 648                          *      *_DPHY*         LVDS
 649                          *      *_HDMI          HDMI
 650                          *      *_MIPI_*        MIPI
 651                          */
 652                         power-domain@RK3368_PD_VIO {
 653                                 reg = <RK3368_PD_VIO>;
 654                                 clocks = <&cru ACLK_IEP>,
 655                                          <&cru ACLK_ISP>,
 656                                          <&cru ACLK_VIP>,
 657                                          <&cru ACLK_RGA>,
 658                                          <&cru ACLK_VOP>,
 659                                          <&cru ACLK_VOP_IEP>,
 660                                          <&cru DCLK_VOP>,
 661                                          <&cru HCLK_IEP>,
 662                                          <&cru HCLK_ISP>,
 663                                          <&cru HCLK_RGA>,
 664                                          <&cru HCLK_VIP>,
 665                                          <&cru HCLK_VOP>,
 666                                          <&cru HCLK_VIO_HDCPMMU>,
 667                                          <&cru PCLK_EDP_CTRL>,
 668                                          <&cru PCLK_HDMI_CTRL>,
 669                                          <&cru PCLK_HDCP>,
 670                                          <&cru PCLK_ISP>,
 671                                          <&cru PCLK_VIP>,
 672                                          <&cru PCLK_DPHYRX>,
 673                                          <&cru PCLK_DPHYTX0>,
 674                                          <&cru PCLK_MIPI_CSI>,
 675                                          <&cru PCLK_MIPI_DSI0>,
 676                                          <&cru SCLK_VOP0_PWM>,
 677                                          <&cru SCLK_EDP_24M>,
 678                                          <&cru SCLK_EDP>,
 679                                          <&cru SCLK_HDCP>,
 680                                          <&cru SCLK_ISP>,
 681                                          <&cru SCLK_RGA>,
 682                                          <&cru SCLK_HDMI_CEC>,
 683                                          <&cru SCLK_HDMI_HDCP>;
 684                                 pm_qos = <&qos_iep>,
 685                                          <&qos_isp_r0>,
 686                                          <&qos_isp_r1>,
 687                                          <&qos_isp_w0>,
 688                                          <&qos_isp_w1>,
 689                                          <&qos_vip>,
 690                                          <&qos_vop>,
 691                                          <&qos_rga_r>,
 692                                          <&qos_rga_w>;
 693                                 #power-domain-cells = <0>;
 694                         };
 695
 696                         /*
 697                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 698                          * (video endecoder & decoder) clocks that on the
 699                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 700                          */
 701                         power-domain@RK3368_PD_VIDEO {
 702                                 reg = <RK3368_PD_VIDEO>;
 703                                 clocks = <&cru ACLK_VIDEO>,
 704                                          <&cru HCLK_VIDEO>,
 705                                          <&cru SCLK_HEVC_CABAC>,
 706                                          <&cru SCLK_HEVC_CORE>;
 707                                 pm_qos = <&qos_hevc_r>,
 708                                          <&qos_vpu_r>,
 709                                          <&qos_vpu_w>;
 710                                 #power-domain-cells = <0>;
 711                         };
 712
 713                         /*
 714                          * Note: ACLK_GPU is the GPU clock,
 715                          * and on the ACLK_GPU_NIU (NOC).
 716                          */
 717                         power-domain@RK3368_PD_GPU_1 {
 718                                 reg = <RK3368_PD_GPU_1>;
 719                                 clocks = <&cru ACLK_GPU_CFG>,
 720                                          <&cru ACLK_GPU_MEM>,
 721                                          <&cru SCLK_GPU_CORE>;
 722                                 pm_qos = <&qos_gpu>;
 723                                 #power-domain-cells = <0>;
 724                         };
 725                 };
 726         };
 727
 728         pmugrf: syscon@ff738000 {
 729                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 730                 reg = <0x0 0xff738000 0x0 0x1000>;
 731
 732                 pmu_io_domains: io-domains {
 733                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 734                         status = "disabled";
 735                 };
 736
 737                 reboot-mode {
 738                         compatible = "syscon-reboot-mode";
 739                         offset = <0x200>;
 740                         mode-normal = <BOOT_NORMAL>;
 741                         mode-recovery = <BOOT_RECOVERY>;
 742                         mode-bootloader = <BOOT_FASTBOOT>;
 743                         mode-loader = <BOOT_BL_DOWNLOAD>;
 744                 };
 745         };
 746
 747         cru: clock-controller@ff760000 {
 748                 compatible = "rockchip,rk3368-cru";
 749                 reg = <0x0 0xff760000 0x0 0x1000>;
 750                 rockchip,grf = <&grf>;
 751                 #clock-cells = <1>;
 752                 #reset-cells = <1>;
 753         };
 754
 755         grf: syscon@ff770000 {
 756                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 757                 reg = <0x0 0xff770000 0x0 0x1000>;
 758
 759                 io_domains: io-domains {
 760                         compatible = "rockchip,rk3368-io-voltage-domain";
 761                         status = "disabled";
 762                 };
 763         };
 764
 765         wdt: watchdog@ff800000 {
 766                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 767                 reg = <0x0 0xff800000 0x0 0x100>;
 768                 clocks = <&cru PCLK_WDT>;
 769                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 770                 status = "disabled";
 771         };
 772
 773         timer0: timer@ff810000 {
 774                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 775                 reg = <0x0 0xff810000 0x0 0x20>;
 776                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 777                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
 778                 clock-names = "pclk", "timer";
 779         };
 780
 781         spdif: spdif@ff880000 {
 782                 compatible = "rockchip,rk3368-spdif";
 783                 reg = <0x0 0xff880000 0x0 0x1000>;
 784                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 786                 clock-names = "mclk", "hclk";
 787                 dmas = <&dmac_bus 3>;
 788                 dma-names = "tx";
 789                 pinctrl-names = "default";
 790                 pinctrl-0 = <&spdif_tx>;
 791                 status = "disabled";
 792         };
 793
 794         i2s_2ch: i2s-2ch@ff890000 {
 795                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 796                 reg = <0x0 0xff890000 0x0 0x1000>;
 797                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 798                 clock-names = "i2s_clk", "i2s_hclk";
 799                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 800                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 801                 dma-names = "tx", "rx";
 802                 status = "disabled";
 803         };
 804
 805         i2s_8ch: i2s-8ch@ff898000 {
 806                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 807                 reg = <0x0 0xff898000 0x0 0x1000>;
 808                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 809                 clock-names = "i2s_clk", "i2s_hclk";
 810                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 811                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 812                 dma-names = "tx", "rx";
 813                 pinctrl-names = "default";
 814                 pinctrl-0 = <&i2s_8ch_bus>;
 815                 status = "disabled";
 816         };
 817
 818         iep_mmu: iommu@ff900800 {
 819                 compatible = "rockchip,iommu";
 820                 reg = <0x0 0xff900800 0x0 0x100>;
 821                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 823                 clock-names = "aclk", "iface";
 824                 power-domains = <&power RK3368_PD_VIO>;
 825                 #iommu-cells = <0>;
 826                 status = "disabled";
 827         };
 828
 829         isp_mmu: iommu@ff914000 {
 830                 compatible = "rockchip,iommu";
 831                 reg = <0x0 0xff914000 0x0 0x100>,
 832                       <0x0 0xff915000 0x0 0x100>;
 833                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 834                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
 835                 clock-names = "aclk", "iface";
 836                 #iommu-cells = <0>;
 837                 power-domains = <&power RK3368_PD_VIO>;
 838                 rockchip,disable-mmu-reset;
 839                 status = "disabled";
 840         };
 841
 842         vop_mmu: iommu@ff930300 {
 843                 compatible = "rockchip,iommu";
 844                 reg = <0x0 0xff930300 0x0 0x100>;
 845                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 846                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 847                 clock-names = "aclk", "iface";
 848                 power-domains = <&power RK3368_PD_VIO>;
 849                 #iommu-cells = <0>;
 850                 status = "disabled";
 851         };
 852
 853         hevc_mmu: iommu@ff9a0440 {
 854                 compatible = "rockchip,iommu";
 855                 reg = <0x0 0xff9a0440 0x0 0x40>,
 856                       <0x0 0xff9a0480 0x0 0x40>;
 857                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 859                 clock-names = "aclk", "iface";
 860                 #iommu-cells = <0>;
 861                 status = "disabled";
 862         };
 863
 864         vpu_mmu: iommu@ff9a0800 {
 865                 compatible = "rockchip,iommu";
 866                 reg = <0x0 0xff9a0800 0x0 0x100>;
 867                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 868                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 870                 clock-names = "aclk", "iface";
 871                 #iommu-cells = <0>;
 872                 status = "disabled";
 873         };
 874
 875         qos_iep: qos@ffad0000 {
 876                 compatible = "rockchip,rk3368-qos", "syscon";
 877                 reg = <0x0 0xffad0000 0x0 0x20>;
 878         };
 879
 880         qos_isp_r0: qos@ffad0080 {
 881                 compatible = "rockchip,rk3368-qos", "syscon";
 882                 reg = <0x0 0xffad0080 0x0 0x20>;
 883         };
 884
 885         qos_isp_r1: qos@ffad0100 {
 886                 compatible = "rockchip,rk3368-qos", "syscon";
 887                 reg = <0x0 0xffad0100 0x0 0x20>;
 888         };
 889
 890         qos_isp_w0: qos@ffad0180 {
 891                 compatible = "rockchip,rk3368-qos", "syscon";
 892                 reg = <0x0 0xffad0180 0x0 0x20>;
 893         };
 894
 895         qos_isp_w1: qos@ffad0200 {
 896                 compatible = "rockchip,rk3368-qos", "syscon";
 897                 reg = <0x0 0xffad0200 0x0 0x20>;
 898         };
 899
 900         qos_vip: qos@ffad0280 {
 901                 compatible = "rockchip,rk3368-qos", "syscon";
 902                 reg = <0x0 0xffad0280 0x0 0x20>;
 903         };
 904
 905         qos_vop: qos@ffad0300 {
 906                 compatible = "rockchip,rk3368-qos", "syscon";
 907                 reg = <0x0 0xffad0300 0x0 0x20>;
 908         };
 909
 910         qos_rga_r: qos@ffad0380 {
 911                 compatible = "rockchip,rk3368-qos", "syscon";
 912                 reg = <0x0 0xffad0380 0x0 0x20>;
 913         };
 914
 915         qos_rga_w: qos@ffad0400 {
 916                 compatible = "rockchip,rk3368-qos", "syscon";
 917                 reg = <0x0 0xffad0400 0x0 0x20>;
 918         };
 919
 920         qos_hevc_r: qos@ffae0000 {
 921                 compatible = "rockchip,rk3368-qos", "syscon";
 922                 reg = <0x0 0xffae0000 0x0 0x20>;
 923         };
 924
 925         qos_vpu_r: qos@ffae0100 {
 926                 compatible = "rockchip,rk3368-qos", "syscon";
 927                 reg = <0x0 0xffae0100 0x0 0x20>;
 928         };
 929
 930         qos_vpu_w: qos@ffae0180 {
 931                 compatible = "rockchip,rk3368-qos", "syscon";
 932                 reg = <0x0 0xffae0180 0x0 0x20>;
 933         };
 934
 935         qos_gpu: qos@ffaf0000 {
 936                 compatible = "rockchip,rk3368-qos", "syscon";
 937                 reg = <0x0 0xffaf0000 0x0 0x20>;
 938         };
 939
 940         efuse256: efuse@ffb00000 {
 941                 compatible = "rockchip,rk3368-efuse";
 942                 reg = <0x0 0xffb00000 0x0 0x20>;
 943                 #address-cells = <1>;
 944                 #size-cells = <1>;
 945                 clocks = <&cru PCLK_EFUSE256>;
 946                 clock-names = "pclk_efuse";
 947
 948                 cpu_leakage: cpu-leakage@17 {
 949                         reg = <0x17 0x1>;
 950                 };
 951                 temp_adjust: temp-adjust@1f {
 952                         reg = <0x1f 0x1>;
 953                 };
 954         };
 955
 956         gic: interrupt-controller@ffb71000 {
 957                 compatible = "arm,gic-400";
 958                 interrupt-controller;
 959                 #interrupt-cells = <3>;
 960                 #address-cells = <0>;
 961
 962                 reg = <0x0 0xffb71000 0x0 0x1000>,
 963                       <0x0 0xffb72000 0x0 0x2000>,
 964                       <0x0 0xffb74000 0x0 0x2000>,
 965                       <0x0 0xffb76000 0x0 0x2000>;
 966                 interrupts = <GIC_PPI 9
 967                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 968         };
 969
 970         pinctrl: pinctrl {
 971                 compatible = "rockchip,rk3368-pinctrl";
 972                 rockchip,grf = <&grf>;
 973                 rockchip,pmu = <&pmugrf>;
 974                 #address-cells = <0x2>;
 975                 #size-cells = <0x2>;
 976                 ranges;
 977
 978                 gpio0: gpio@ff750000 {
 979                         compatible = "rockchip,gpio-bank";
 980                         reg = <0x0 0xff750000 0x0 0x100>;
 981                         clocks = <&cru PCLK_GPIO0>;
 982                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 983
 984                         gpio-controller;
 985                         #gpio-cells = <0x2>;
 986
 987                         interrupt-controller;
 988                         #interrupt-cells = <0x2>;
 989                 };
 990
 991                 gpio1: gpio@ff780000 {
 992                         compatible = "rockchip,gpio-bank";
 993                         reg = <0x0 0xff780000 0x0 0x100>;
 994                         clocks = <&cru PCLK_GPIO1>;
 995                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 996
 997                         gpio-controller;
 998                         #gpio-cells = <0x2>;
 999
1000                         interrupt-controller;
1001                         #interrupt-cells = <0x2>;
1002                 };
1003
1004                 gpio2: gpio@ff790000 {
1005                         compatible = "rockchip,gpio-bank";
1006                         reg = <0x0 0xff790000 0x0 0x100>;
1007                         clocks = <&cru PCLK_GPIO2>;
1008                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1009
1010                         gpio-controller;
1011                         #gpio-cells = <0x2>;
1012
1013                         interrupt-controller;
1014                         #interrupt-cells = <0x2>;
1015                 };
1016
1017                 gpio3: gpio@ff7a0000 {
1018                         compatible = "rockchip,gpio-bank";
1019                         reg = <0x0 0xff7a0000 0x0 0x100>;
1020                         clocks = <&cru PCLK_GPIO3>;
1021                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1022
1023                         gpio-controller;
1024                         #gpio-cells = <0x2>;
1025
1026                         interrupt-controller;
1027                         #interrupt-cells = <0x2>;
1028                 };
1029
1030                 pcfg_pull_up: pcfg-pull-up {
1031                         bias-pull-up;
1032                 };
1033
1034                 pcfg_pull_down: pcfg-pull-down {
1035                         bias-pull-down;
1036                 };
1037
1038                 pcfg_pull_none: pcfg-pull-none {
1039                         bias-disable;
1040                 };
1041
1042                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1043                         bias-disable;
1044                         drive-strength = <12>;
1045                 };
1046
1047                 emmc {
1048                         emmc_clk: emmc-clk {
1049                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1050                         };
1051
1052                         emmc_cmd: emmc-cmd {
1053                                 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1054                         };
1055
1056                         emmc_pwr: emmc-pwr {
1057                                 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1058                         };
1059
1060                         emmc_bus1: emmc-bus1 {
1061                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1062                         };
1063
1064                         emmc_bus4: emmc-bus4 {
1065                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1066                                                 <1 RK_PC3 2 &pcfg_pull_up>,
1067                                                 <1 RK_PC4 2 &pcfg_pull_up>,
1068                                                 <1 RK_PC5 2 &pcfg_pull_up>;
1069                         };
1070
1071                         emmc_bus8: emmc-bus8 {
1072                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1073                                                 <1 RK_PC3 2 &pcfg_pull_up>,
1074                                                 <1 RK_PC4 2 &pcfg_pull_up>,
1075                                                 <1 RK_PC5 2 &pcfg_pull_up>,
1076                                                 <1 RK_PC6 2 &pcfg_pull_up>,
1077                                                 <1 RK_PC7 2 &pcfg_pull_up>,
1078                                                 <1 RK_PD0 2 &pcfg_pull_up>,
1079                                                 <1 RK_PD1 2 &pcfg_pull_up>;
1080                         };
1081                 };
1082
1083                 gmac {
1084                         rgmii_pins: rgmii-pins {
1085                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1086                                                 <3 RK_PD0 1 &pcfg_pull_none>,
1087                                                 <3 RK_PC3 1 &pcfg_pull_none>,
1088                                                 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1089                                                 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1090                                                 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1091                                                 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1092                                                 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1093                                                 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1094                                                 <3 RK_PB7 1 &pcfg_pull_none>,
1095                                                 <3 RK_PC0 1 &pcfg_pull_none>,
1096                                                 <3 RK_PC1 1 &pcfg_pull_none>,
1097                                                 <3 RK_PC2 1 &pcfg_pull_none>,
1098                                                 <3 RK_PD1 1 &pcfg_pull_none>,
1099                                                 <3 RK_PC4 1 &pcfg_pull_none>;
1100                         };
1101
1102                         rmii_pins: rmii-pins {
1103                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1104                                                 <3 RK_PD0 1 &pcfg_pull_none>,
1105                                                 <3 RK_PC3 1 &pcfg_pull_none>,
1106                                                 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1107                                                 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1108                                                 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1109                                                 <3 RK_PB7 1 &pcfg_pull_none>,
1110                                                 <3 RK_PC0 1 &pcfg_pull_none>,
1111                                                 <3 RK_PC4 1 &pcfg_pull_none>,
1112                                                 <3 RK_PC5 1 &pcfg_pull_none>;
1113                         };
1114                 };
1115
1116                 i2c0 {
1117                         i2c0_xfer: i2c0-xfer {
1118                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1119                                                 <0 RK_PA7 1 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 i2c1 {
1124                         i2c1_xfer: i2c1-xfer {
1125                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1126                                                 <2 RK_PC6 1 &pcfg_pull_none>;
1127                         };
1128                 };
1129
1130                 i2c2 {
1131                         i2c2_xfer: i2c2-xfer {
1132                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1133                                                 <3 RK_PD7 2 &pcfg_pull_none>;
1134                         };
1135                 };
1136
1137                 i2c3 {
1138                         i2c3_xfer: i2c3-xfer {
1139                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1140                                                 <1 RK_PC1 1 &pcfg_pull_none>;
1141                         };
1142                 };
1143
1144                 i2c4 {
1145                         i2c4_xfer: i2c4-xfer {
1146                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1147                                                 <3 RK_PD1 2 &pcfg_pull_none>;
1148                         };
1149                 };
1150
1151                 i2c5 {
1152                         i2c5_xfer: i2c5-xfer {
1153                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1154                                                 <3 RK_PD3 2 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 i2s {
1159                         i2s_8ch_bus: i2s-8ch-bus {
1160                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1161                                                 <2 RK_PB5 1 &pcfg_pull_none>,
1162                                                 <2 RK_PB6 1 &pcfg_pull_none>,
1163                                                 <2 RK_PB7 1 &pcfg_pull_none>,
1164                                                 <2 RK_PC0 1 &pcfg_pull_none>,
1165                                                 <2 RK_PC1 1 &pcfg_pull_none>,
1166                                                 <2 RK_PC2 1 &pcfg_pull_none>,
1167                                                 <2 RK_PC3 1 &pcfg_pull_none>,
1168                                                 <2 RK_PC4 1 &pcfg_pull_none>;
1169                         };
1170                 };
1171
1172                 pwm0 {
1173                         pwm0_pin: pwm0-pin {
1174                                 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1175                         };
1176                 };
1177
1178                 pwm1 {
1179                         pwm1_pin: pwm1-pin {
1180                                 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1181                         };
1182                 };
1183
1184                 pwm3 {
1185                         pwm3_pin: pwm3-pin {
1186                                 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1187                         };
1188                 };
1189
1190                 sdio0 {
1191                         sdio0_bus1: sdio0-bus1 {
1192                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1193                         };
1194
1195                         sdio0_bus4: sdio0-bus4 {
1196                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1197                                                 <2 RK_PD5 1 &pcfg_pull_up>,
1198                                                 <2 RK_PD6 1 &pcfg_pull_up>,
1199                                                 <2 RK_PD7 1 &pcfg_pull_up>;
1200                         };
1201
1202                         sdio0_cmd: sdio0-cmd {
1203                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1204                         };
1205
1206                         sdio0_clk: sdio0-clk {
1207                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1208                         };
1209
1210                         sdio0_cd: sdio0-cd {
1211                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1212                         };
1213
1214                         sdio0_wp: sdio0-wp {
1215                                 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1216                         };
1217
1218                         sdio0_pwr: sdio0-pwr {
1219                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1220                         };
1221
1222                         sdio0_bkpwr: sdio0-bkpwr {
1223                                 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1224                         };
1225
1226                         sdio0_int: sdio0-int {
1227                                 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1228                         };
1229                 };
1230
1231                 sdmmc {
1232                         sdmmc_clk: sdmmc-clk {
1233                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1234                         };
1235
1236                         sdmmc_cmd: sdmmc-cmd {
1237                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1238                         };
1239
1240                         sdmmc_cd: sdmmc-cd {
1241                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1242                         };
1243
1244                         sdmmc_bus1: sdmmc-bus1 {
1245                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1246                         };
1247
1248                         sdmmc_bus4: sdmmc-bus4 {
1249                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1250                                                 <2 RK_PA6 1 &pcfg_pull_up>,
1251                                                 <2 RK_PA7 1 &pcfg_pull_up>,
1252                                                 <2 RK_PB0 1 &pcfg_pull_up>;
1253                         };
1254                 };
1255
1256                 spdif {
1257                         spdif_tx: spdif-tx {
1258                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1259                         };
1260                 };
1261
1262                 spi0 {
1263                         spi0_clk: spi0-clk {
1264                                 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1265                         };
1266                         spi0_cs0: spi0-cs0 {
1267                                 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1268                         };
1269                         spi0_cs1: spi0-cs1 {
1270                                 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1271                         };
1272                         spi0_tx: spi0-tx {
1273                                 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1274                         };
1275                         spi0_rx: spi0-rx {
1276                                 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1277                         };
1278                 };
1279
1280                 spi1 {
1281                         spi1_clk: spi1-clk {
1282                                 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1283                         };
1284                         spi1_cs0: spi1-cs0 {
1285                                 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1286                         };
1287                         spi1_cs1: spi1-cs1 {
1288                                 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1289                         };
1290                         spi1_rx: spi1-rx {
1291                                 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1292                         };
1293                         spi1_tx: spi1-tx {
1294                                 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1295                         };
1296                 };
1297
1298                 spi2 {
1299                         spi2_clk: spi2-clk {
1300                                 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1301                         };
1302                         spi2_cs0: spi2-cs0 {
1303                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1304                         };
1305                         spi2_rx: spi2-rx {
1306                                 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1307                         };
1308                         spi2_tx: spi2-tx {
1309                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1310                         };
1311                 };
1312
1313                 tsadc {
1314                         otp_pin: otp-pin {
1315                                 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1316                         };
1317
1318                         otp_out: otp-out {
1319                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1320                         };
1321                 };
1322
1323                 uart0 {
1324                         uart0_xfer: uart0-xfer {
1325                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1326                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1327                         };
1328
1329                         uart0_cts: uart0-cts {
1330                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1331                         };
1332
1333                         uart0_rts: uart0-rts {
1334                                 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1335                         };
1336                 };
1337
1338                 uart1 {
1339                         uart1_xfer: uart1-xfer {
1340                                 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1341                                                 <0 RK_PC5 3 &pcfg_pull_none>;
1342                         };
1343
1344                         uart1_cts: uart1-cts {
1345                                 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1346                         };
1347
1348                         uart1_rts: uart1-rts {
1349                                 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1350                         };
1351                 };
1352
1353                 uart2 {
1354                         uart2_xfer: uart2-xfer {
1355                                 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1356                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1357                         };
1358                         /* no rts / cts for uart2 */
1359                 };
1360
1361                 uart3 {
1362                         uart3_xfer: uart3-xfer {
1363                                 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1364                                                 <3 RK_PD6 3 &pcfg_pull_none>;
1365                         };
1366
1367                         uart3_cts: uart3-cts {
1368                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1369                         };
1370
1371                         uart3_rts: uart3-rts {
1372                                 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1373                         };
1374                 };
1375
1376                 uart4 {
1377                         uart4_xfer: uart4-xfer {
1378                                 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1379                                                 <0 RK_PD2 3 &pcfg_pull_none>;
1380                         };
1381
1382                         uart4_cts: uart4-cts {
1383                                 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1384                         };
1385
1386                         uart4_rts: uart4-rts {
1387                                 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1388                         };
1389                 };
1390         };
1391 };