arch/arm64/boot/dts/rockchip/rk3308.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
   4  *
   5  */
   6
   7 #include <dt-bindings/clock/rk3308-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3308";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 serial4 = &uart4;
  32                 spi0 = &spi0;
  33                 spi1 = &spi1;
  34                 spi2 = &spi2;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a35";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         clocks = <&cru ARMCLK>;
  47                         #cooling-cells = <2>;
  48                         dynamic-power-coefficient = <90>;
  49                         operating-points-v2 = <&cpu0_opp_table>;
  50                         cpu-idle-states = <&CPU_SLEEP>;
  51                         next-level-cache = <&l2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP>;
  61                         next-level-cache = <&l2>;
  62                 };
  63
  64                 cpu2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a35";
  67                         reg = <0x0 0x2>;
  68                         enable-method = "psci";
  69                         operating-points-v2 = <&cpu0_opp_table>;
  70                         cpu-idle-states = <&CPU_SLEEP>;
  71                         next-level-cache = <&l2>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a35";
  77                         reg = <0x0 0x3>;
  78                         enable-method = "psci";
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         cpu-idle-states = <&CPU_SLEEP>;
  81                         next-level-cache = <&l2>;
  82                 };
  83
  84                 idle-states {
  85                         entry-method = "psci";
  86
  87                         CPU_SLEEP: cpu-sleep {
  88                                 compatible = "arm,idle-state";
  89                                 local-timer-stop;
  90                                 arm,psci-suspend-param = <0x0010000>;
  91                                 entry-latency-us = <120>;
  92                                 exit-latency-us = <250>;
  93                                 min-residency-us = <900>;
  94                         };
  95                 };
  96
  97                 l2: l2-cache {
  98                         compatible = "cache";
  99                 };
 100         };
 101
 102         cpu0_opp_table: cpu0-opp-table {
 103                 compatible = "operating-points-v2";
 104                 opp-shared;
 105
 106                 opp-408000000 {
 107                         opp-hz = /bits/ 64 <408000000>;
 108                         opp-microvolt = <950000 950000 1340000>;
 109                         clock-latency-ns = <40000>;
 110                         opp-suspend;
 111                 };
 112                 opp-600000000 {
 113                         opp-hz = /bits/ 64 <600000000>;
 114                         opp-microvolt = <950000 950000 1340000>;
 115                         clock-latency-ns = <40000>;
 116                 };
 117                 opp-816000000 {
 118                         opp-hz = /bits/ 64 <816000000>;
 119                         opp-microvolt = <1025000 1025000 1340000>;
 120                         clock-latency-ns = <40000>;
 121                 };
 122                 opp-1008000000 {
 123                         opp-hz = /bits/ 64 <1008000000>;
 124                         opp-microvolt = <1125000 1125000 1340000>;
 125                         clock-latency-ns = <40000>;
 126                 };
 127         };
 128
 129         arm-pmu {
 130                 compatible = "arm,cortex-a35-pmu";
 131                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 135                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 136         };
 137
 138         mac_clkin: external-mac-clock {
 139                 compatible = "fixed-clock";
 140                 clock-frequency = <50000000>;
 141                 clock-output-names = "mac_clkin";
 142                 #clock-cells = <0>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 153                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 154                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 156         };
 157
 158         xin24m: xin24m {
 159                 compatible = "fixed-clock";
 160                 #clock-cells = <0>;
 161                 clock-frequency = <24000000>;
 162                 clock-output-names = "xin24m";
 163         };
 164
 165         grf: grf@ff000000 {
 166                 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
 167                 reg = <0x0 0xff000000 0x0 0x10000>;
 168
 169                 reboot-mode {
 170                         compatible = "syscon-reboot-mode";
 171                         offset = <0x500>;
 172                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 173                         mode-loader = <BOOT_BL_DOWNLOAD>;
 174                         mode-normal = <BOOT_NORMAL>;
 175                         mode-recovery = <BOOT_RECOVERY>;
 176                         mode-fastboot = <BOOT_FASTBOOT>;
 177                 };
 178         };
 179
 180         detect_grf: syscon@ff00b000 {
 181                 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
 182                 reg = <0x0 0xff00b000 0x0 0x1000>;
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185         };
 186
 187         core_grf: syscon@ff00c000 {
 188                 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
 189                 reg = <0x0 0xff00c000 0x0 0x1000>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192         };
 193
 194         i2c0: i2c@ff040000 {
 195                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 196                 reg = <0x0 0xff040000 0x0 0x1000>;
 197                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 198                 clock-names = "i2c", "pclk";
 199                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&i2c0_xfer>;
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 status = "disabled";
 205         };
 206
 207         i2c1: i2c@ff050000 {
 208                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 209                 reg = <0x0 0xff050000 0x0 0x1000>;
 210                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 211                 clock-names = "i2c", "pclk";
 212                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&i2c1_xfer>;
 215                 #address-cells = <1>;
 216                 #size-cells = <0>;
 217                 status = "disabled";
 218         };
 219
 220         i2c2: i2c@ff060000 {
 221                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 222                 reg = <0x0 0xff060000 0x0 0x1000>;
 223                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 224                 clock-names = "i2c", "pclk";
 225                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&i2c2_xfer>;
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230                 status = "disabled";
 231         };
 232
 233         i2c3: i2c@ff070000 {
 234                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 235                 reg = <0x0 0xff070000 0x0 0x1000>;
 236                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 237                 clock-names = "i2c", "pclk";
 238                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&i2c3m0_xfer>;
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 status = "disabled";
 244         };
 245
 246         wdt: watchdog@ff080000 {
 247                 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
 248                 reg = <0x0 0xff080000 0x0 0x100>;
 249                 clocks = <&cru PCLK_WDT>;
 250                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 251                 status = "disabled";
 252         };
 253
 254         uart0: serial@ff0a0000 {
 255                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 256                 reg = <0x0 0xff0a0000 0x0 0x100>;
 257                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 259                 clock-names = "baudclk", "apb_pclk";
 260                 reg-shift = <2>;
 261                 reg-io-width = <4>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 264                 status = "disabled";
 265         };
 266
 267         uart1: serial@ff0b0000 {
 268                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 269                 reg = <0x0 0xff0b0000 0x0 0x100>;
 270                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 272                 clock-names = "baudclk", "apb_pclk";
 273                 reg-shift = <2>;
 274                 reg-io-width = <4>;
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 277                 status = "disabled";
 278         };
 279
 280         uart2: serial@ff0c0000 {
 281                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 282                 reg = <0x0 0xff0c0000 0x0 0x100>;
 283                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 285                 clock-names = "baudclk", "apb_pclk";
 286                 reg-shift = <2>;
 287                 reg-io-width = <4>;
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&uart2m0_xfer>;
 290                 status = "disabled";
 291         };
 292
 293         uart3: serial@ff0d0000 {
 294                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 295                 reg = <0x0 0xff0d0000 0x0 0x100>;
 296                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 298                 clock-names = "baudclk", "apb_pclk";
 299                 reg-shift = <2>;
 300                 reg-io-width = <4>;
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&uart3_xfer>;
 303                 status = "disabled";
 304         };
 305
 306         uart4: serial@ff0e0000 {
 307                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 308                 reg = <0x0 0xff0e0000 0x0 0x100>;
 309                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 311                 clock-names = "baudclk", "apb_pclk";
 312                 reg-shift = <2>;
 313                 reg-io-width = <4>;
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 316                 status = "disabled";
 317         };
 318
 319         spi0: spi@ff120000 {
 320                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 321                 reg = <0x0 0xff120000 0x0 0x1000>;
 322                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 326                 clock-names = "spiclk", "apb_pclk";
 327                 dmas = <&dmac0 0>, <&dmac0 1>;
 328                 dma-names = "tx", "rx";
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
 331                 status = "disabled";
 332         };
 333
 334         spi1: spi@ff130000 {
 335                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 336                 reg = <0x0 0xff130000 0x0 0x1000>;
 337                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 341                 clock-names = "spiclk", "apb_pclk";
 342                 dmas = <&dmac0 2>, <&dmac0 3>;
 343                 dma-names = "tx", "rx";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
 346                 status = "disabled";
 347         };
 348
 349         spi2: spi@ff140000 {
 350                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 351                 reg = <0x0 0xff140000 0x0 0x1000>;
 352                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 356                 clock-names = "spiclk", "apb_pclk";
 357                 dmas = <&dmac1 16>, <&dmac1 17>;
 358                 dma-names = "tx", "rx";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
 361                 status = "disabled";
 362         };
 363
 364         pwm8: pwm@ff160000 {
 365                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 366                 reg = <0x0 0xff160000 0x0 0x10>;
 367                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 368                 clock-names = "pwm", "pclk";
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&pwm8_pin>;
 371                 #pwm-cells = <3>;
 372                 status = "disabled";
 373         };
 374
 375         pwm9: pwm@ff160010 {
 376                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 377                 reg = <0x0 0xff160010 0x0 0x10>;
 378                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 379                 clock-names = "pwm", "pclk";
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&pwm9_pin>;
 382                 #pwm-cells = <3>;
 383                 status = "disabled";
 384         };
 385
 386         pwm10: pwm@ff160020 {
 387                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 388                 reg = <0x0 0xff160020 0x0 0x10>;
 389                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 390                 clock-names = "pwm", "pclk";
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&pwm10_pin>;
 393                 #pwm-cells = <3>;
 394                 status = "disabled";
 395         };
 396
 397         pwm11: pwm@ff160030 {
 398                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 399                 reg = <0x0 0xff160030 0x0 0x10>;
 400                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 401                 clock-names = "pwm", "pclk";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&pwm11_pin>;
 404                 #pwm-cells = <3>;
 405                 status = "disabled";
 406         };
 407
 408         pwm4: pwm@ff170000 {
 409                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 410                 reg = <0x0 0xff170000 0x0 0x10>;
 411                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 412                 clock-names = "pwm", "pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&pwm4_pin>;
 415                 #pwm-cells = <3>;
 416                 status = "disabled";
 417         };
 418
 419         pwm5: pwm@ff170010 {
 420                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 421                 reg = <0x0 0xff170010 0x0 0x10>;
 422                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 423                 clock-names = "pwm", "pclk";
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pwm5_pin>;
 426                 #pwm-cells = <3>;
 427                 status = "disabled";
 428         };
 429
 430         pwm6: pwm@ff170020 {
 431                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 432                 reg = <0x0 0xff170020 0x0 0x10>;
 433                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 434                 clock-names = "pwm", "pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&pwm6_pin>;
 437                 #pwm-cells = <3>;
 438                 status = "disabled";
 439         };
 440
 441         pwm7: pwm@ff170030 {
 442                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 443                 reg = <0x0 0xff170030 0x0 0x10>;
 444                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 445                 clock-names = "pwm", "pclk";
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&pwm7_pin>;
 448                 #pwm-cells = <3>;
 449                 status = "disabled";
 450         };
 451
 452         pwm0: pwm@ff180000 {
 453                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 454                 reg = <0x0 0xff180000 0x0 0x10>;
 455                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 456                 clock-names = "pwm", "pclk";
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&pwm0_pin>;
 459                 #pwm-cells = <3>;
 460                 status = "disabled";
 461         };
 462
 463         pwm1: pwm@ff180010 {
 464                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 465                 reg = <0x0 0xff180010 0x0 0x10>;
 466                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 467                 clock-names = "pwm", "pclk";
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&pwm1_pin>;
 470                 #pwm-cells = <3>;
 471                 status = "disabled";
 472         };
 473
 474         pwm2: pwm@ff180020 {
 475                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 476                 reg = <0x0 0xff180020 0x0 0x10>;
 477                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 478                 clock-names = "pwm", "pclk";
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&pwm2_pin>;
 481                 #pwm-cells = <3>;
 482                 status = "disabled";
 483         };
 484
 485         pwm3: pwm@ff180030 {
 486                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 487                 reg = <0x0 0xff180030 0x0 0x10>;
 488                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 489                 clock-names = "pwm", "pclk";
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&pwm3_pin>;
 492                 #pwm-cells = <3>;
 493                 status = "disabled";
 494         };
 495
 496         rktimer: rktimer@ff1a0000 {
 497                 compatible = "rockchip,rk3288-timer";
 498                 reg = <0x0 0xff1a0000 0x0 0x20>;
 499                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 500                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 501                 clock-names = "pclk", "timer";
 502         };
 503
 504         saradc: saradc@ff1e0000 {
 505                 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
 506                 reg = <0x0 0xff1e0000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 509                 clock-names = "saradc", "apb_pclk";
 510                 #io-channel-cells = <1>;
 511                 resets = <&cru SRST_SARADC_P>;
 512                 reset-names = "saradc-apb";
 513                 status = "disabled";
 514         };
 515
 516         dmac0: dma-controller@ff2c0000 {
 517                 compatible = "arm,pl330", "arm,primecell";
 518                 reg = <0x0 0xff2c0000 0x0 0x4000>;
 519                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 520                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 521                 arm,pl330-periph-burst;
 522                 clocks = <&cru ACLK_DMAC0>;
 523                 clock-names = "apb_pclk";
 524                 #dma-cells = <1>;
 525         };
 526
 527         dmac1: dma-controller@ff2d0000 {
 528                 compatible = "arm,pl330", "arm,primecell";
 529                 reg = <0x0 0xff2d0000 0x0 0x4000>;
 530                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 531                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 532                 arm,pl330-periph-burst;
 533                 clocks = <&cru ACLK_DMAC1>;
 534                 clock-names = "apb_pclk";
 535                 #dma-cells = <1>;
 536         };
 537
 538         i2s_2ch_0: i2s@ff350000 {
 539                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 540                 reg = <0x0 0xff350000 0x0 0x1000>;
 541                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 542                 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
 543                 clock-names = "i2s_clk", "i2s_hclk";
 544                 dmas = <&dmac1 8>, <&dmac1 9>;
 545                 dma-names = "tx", "rx";
 546                 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
 547                 reset-names = "reset-m", "reset-h";
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2s_2ch_0_sclk
 550                              &i2s_2ch_0_lrck
 551                              &i2s_2ch_0_sdi
 552                              &i2s_2ch_0_sdo>;
 553                 status = "disabled";
 554         };
 555
 556         i2s_2ch_1: i2s@ff360000 {
 557                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 558                 reg = <0x0 0xff360000 0x0 0x1000>;
 559                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 560                 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
 561                 clock-names = "i2s_clk", "i2s_hclk";
 562                 dmas = <&dmac1 11>;
 563                 dma-names = "rx";
 564                 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
 565                 reset-names = "reset-m", "reset-h";
 566                 status = "disabled";
 567         };
 568
 569         spdif_tx: spdif-tx@ff3a0000 {
 570                 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
 571                 reg = <0x0 0xff3a0000 0x0 0x1000>;
 572                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 573                 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
 574                 clock-names = "mclk", "hclk";
 575                 dmas = <&dmac1 13>;
 576                 dma-names = "tx";
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&spdif_out>;
 579                 status = "disabled";
 580         };
 581
 582         sdmmc: mmc@ff480000 {
 583                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 584                 reg = <0x0 0xff480000 0x0 0x4000>;
 585                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 586                 bus-width = <4>;
 587                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 588                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 589                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 590                 fifo-depth = <0x100>;
 591                 max-frequency = <150000000>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 594                 status = "disabled";
 595         };
 596
 597         emmc: mmc@ff490000 {
 598                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 599                 reg = <0x0 0xff490000 0x0 0x4000>;
 600                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 601                 bus-width = <8>;
 602                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 603                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 604                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 605                 fifo-depth = <0x100>;
 606                 max-frequency = <150000000>;
 607                 status = "disabled";
 608         };
 609
 610         sdio: mmc@ff4a0000 {
 611                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 612                 reg = <0x0 0xff4a0000 0x0 0x4000>;
 613                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 614                 bus-width = <4>;
 615                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 616                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 617                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 618                 fifo-depth = <0x100>;
 619                 max-frequency = <150000000>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 622                 status = "disabled";
 623         };
 624
 625         nfc: nand-controller@ff4b0000 {
 626                 compatible = "rockchip,rk3308-nfc",
 627                              "rockchip,rv1108-nfc";
 628                 reg = <0x0 0xff4b0000 0x0 0x4000>;
 629                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 631                 clock-names = "ahb", "nfc";
 632                 assigned-clocks = <&cru SCLK_NANDC>;
 633                 assigned-clock-rates = <150000000>;
 634                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 635                              &flash_rdn &flash_rdy &flash_wrn>;
 636                 pinctrl-names = "default";
 637                 status = "disabled";
 638         };
 639
 640         cru: clock-controller@ff500000 {
 641                 compatible = "rockchip,rk3308-cru";
 642                 reg = <0x0 0xff500000 0x0 0x1000>;
 643                 #clock-cells = <1>;
 644                 #reset-cells = <1>;
 645                 rockchip,grf = <&grf>;
 646
 647                 assigned-clocks = <&cru SCLK_RTC32K>;
 648                 assigned-clock-rates = <32768>;
 649         };
 650
 651         gic: interrupt-controller@ff580000 {
 652                 compatible = "arm,gic-400";
 653                 reg = <0x0 0xff581000 0x0 0x1000>,
 654                       <0x0 0xff582000 0x0 0x2000>,
 655                       <0x0 0xff584000 0x0 0x2000>,
 656                       <0x0 0xff586000 0x0 0x2000>;
 657                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 658                 #interrupt-cells = <3>;
 659                 interrupt-controller;
 660                 #address-cells = <0>;
 661         };
 662
 663         sram: sram@fff80000 {
 664                 compatible = "mmio-sram";
 665                 reg = <0x0 0xfff80000 0x0 0x40000>;
 666                 ranges = <0 0x0 0xfff80000 0x40000>;
 667                 #address-cells = <1>;
 668                 #size-cells = <1>;
 669
 670                 /* reserved for ddr dvfs and system suspend/resume */
 671                 ddr-sram@0 {
 672                         reg = <0x0 0x8000>;
 673                 };
 674
 675                 /* reserved for vad audio buffer */
 676                 vad_sram: vad-sram@8000 {
 677                         reg = <0x8000 0x38000>;
 678                 };
 679         };
 680
 681         pinctrl: pinctrl {
 682                 compatible = "rockchip,rk3308-pinctrl";
 683                 rockchip,grf = <&grf>;
 684                 #address-cells = <2>;
 685                 #size-cells = <2>;
 686                 ranges;
 687
 688                 gpio0: gpio0@ff220000 {
 689                         compatible = "rockchip,gpio-bank";
 690                         reg = <0x0 0xff220000 0x0 0x100>;
 691                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&cru PCLK_GPIO0>;
 693                         gpio-controller;
 694                         #gpio-cells = <2>;
 695                         interrupt-controller;
 696                         #interrupt-cells = <2>;
 697                 };
 698
 699                 gpio1: gpio1@ff230000 {
 700                         compatible = "rockchip,gpio-bank";
 701                         reg = <0x0 0xff230000 0x0 0x100>;
 702                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 703                         clocks = <&cru PCLK_GPIO1>;
 704                         gpio-controller;
 705                         #gpio-cells = <2>;
 706                         interrupt-controller;
 707                         #interrupt-cells = <2>;
 708                 };
 709
 710                 gpio2: gpio2@ff240000 {
 711                         compatible = "rockchip,gpio-bank";
 712                         reg = <0x0 0xff240000 0x0 0x100>;
 713                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 714                         clocks = <&cru PCLK_GPIO2>;
 715                         gpio-controller;
 716                         #gpio-cells = <2>;
 717                         interrupt-controller;
 718                         #interrupt-cells = <2>;
 719                 };
 720
 721                 gpio3: gpio3@ff250000 {
 722                         compatible = "rockchip,gpio-bank";
 723                         reg = <0x0 0xff250000 0x0 0x100>;
 724                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&cru PCLK_GPIO3>;
 726                         gpio-controller;
 727                         #gpio-cells = <2>;
 728                         interrupt-controller;
 729                         #interrupt-cells = <2>;
 730                 };
 731
 732                 gpio4: gpio4@ff260000 {
 733                         compatible = "rockchip,gpio-bank";
 734                         reg = <0x0 0xff260000 0x0 0x100>;
 735                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 736                         clocks = <&cru PCLK_GPIO4>;
 737                         gpio-controller;
 738                         #gpio-cells = <2>;
 739                         interrupt-controller;
 740                         #interrupt-cells = <2>;
 741                 };
 742
 743                 pcfg_pull_up: pcfg-pull-up {
 744                         bias-pull-up;
 745                 };
 746
 747                 pcfg_pull_down: pcfg-pull-down {
 748                         bias-pull-down;
 749                 };
 750
 751                 pcfg_pull_none: pcfg-pull-none {
 752                         bias-disable;
 753                 };
 754
 755                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 756                         bias-disable;
 757                         drive-strength = <2>;
 758                 };
 759
 760                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 761                         bias-pull-up;
 762                         drive-strength = <2>;
 763                 };
 764
 765                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 766                         bias-pull-up;
 767                         drive-strength = <4>;
 768                 };
 769
 770                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 771                         bias-disable;
 772                         drive-strength = <4>;
 773                 };
 774
 775                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 776                         bias-pull-down;
 777                         drive-strength = <4>;
 778                 };
 779
 780                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 781                         bias-disable;
 782                         drive-strength = <8>;
 783                 };
 784
 785                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 786                         bias-pull-up;
 787                         drive-strength = <8>;
 788                 };
 789
 790                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 791                         bias-disable;
 792                         drive-strength = <12>;
 793                 };
 794
 795                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 796                         bias-pull-up;
 797                         drive-strength = <12>;
 798                 };
 799
 800                 pcfg_pull_none_smt: pcfg-pull-none-smt {
 801                         bias-disable;
 802                         input-schmitt-enable;
 803                 };
 804
 805                 pcfg_output_high: pcfg-output-high {
 806                         output-high;
 807                 };
 808
 809                 pcfg_output_low: pcfg-output-low {
 810                         output-low;
 811                 };
 812
 813                 pcfg_input_high: pcfg-input-high {
 814                         bias-pull-up;
 815                         input-enable;
 816                 };
 817
 818                 pcfg_input: pcfg-input {
 819                         input-enable;
 820                 };
 821
 822                 emmc {
 823                         emmc_clk: emmc-clk {
 824                                 rockchip,pins =
 825                                         <3 RK_PB1 2 &pcfg_pull_none_8ma>;
 826                         };
 827
 828                         emmc_cmd: emmc-cmd {
 829                                 rockchip,pins =
 830                                         <3 RK_PB0 2 &pcfg_pull_up_8ma>;
 831                         };
 832
 833                         emmc_pwren: emmc-pwren {
 834                                 rockchip,pins =
 835                                         <3 RK_PB3 2 &pcfg_pull_none>;
 836                         };
 837
 838                         emmc_rstn: emmc-rstn {
 839                                 rockchip,pins =
 840                                         <3 RK_PB2 2 &pcfg_pull_none>;
 841                         };
 842
 843                         emmc_bus1: emmc-bus1 {
 844                                 rockchip,pins =
 845                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>;
 846                         };
 847
 848                         emmc_bus4: emmc-bus4 {
 849                                 rockchip,pins =
 850                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 851                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 852                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 853                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>;
 854                         };
 855
 856                         emmc_bus8: emmc-bus8 {
 857                                 rockchip,pins =
 858                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 859                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 860                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 861                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>,
 862                                         <3 RK_PA4 2 &pcfg_pull_up_8ma>,
 863                                         <3 RK_PA5 2 &pcfg_pull_up_8ma>,
 864                                         <3 RK_PA6 2 &pcfg_pull_up_8ma>,
 865                                         <3 RK_PA7 2 &pcfg_pull_up_8ma>;
 866                         };
 867                 };
 868
 869                 flash {
 870                         flash_csn0: flash-csn0 {
 871                                 rockchip,pins =
 872                                         <3 RK_PB5 1 &pcfg_pull_none>;
 873                         };
 874
 875                         flash_rdy: flash-rdy {
 876                                 rockchip,pins =
 877                                         <3 RK_PB4 1 &pcfg_pull_none>;
 878                         };
 879
 880                         flash_ale: flash-ale {
 881                                 rockchip,pins =
 882                                         <3 RK_PB3 1 &pcfg_pull_none>;
 883                         };
 884
 885                         flash_cle: flash-cle {
 886                                 rockchip,pins =
 887                                         <3 RK_PB1 1 &pcfg_pull_none>;
 888                         };
 889
 890                         flash_wrn: flash-wrn {
 891                                 rockchip,pins =
 892                                         <3 RK_PB0 1 &pcfg_pull_none>;
 893                         };
 894
 895                         flash_rdn: flash-rdn {
 896                                 rockchip,pins =
 897                                         <3 RK_PB2 1 &pcfg_pull_none>;
 898                         };
 899
 900                         flash_bus8: flash-bus8 {
 901                                 rockchip,pins =
 902                                         <3 RK_PA0 1 &pcfg_pull_up_12ma>,
 903                                         <3 RK_PA1 1 &pcfg_pull_up_12ma>,
 904                                         <3 RK_PA2 1 &pcfg_pull_up_12ma>,
 905                                         <3 RK_PA3 1 &pcfg_pull_up_12ma>,
 906                                         <3 RK_PA4 1 &pcfg_pull_up_12ma>,
 907                                         <3 RK_PA5 1 &pcfg_pull_up_12ma>,
 908                                         <3 RK_PA6 1 &pcfg_pull_up_12ma>,
 909                                         <3 RK_PA7 1 &pcfg_pull_up_12ma>;
 910                         };
 911                 };
 912
 913                 gmac {
 914                         rmii_pins: rmii-pins {
 915                                 rockchip,pins =
 916                                         /* mac_txen */
 917                                         <1 RK_PC1 3 &pcfg_pull_none_12ma>,
 918                                         /* mac_txd1 */
 919                                         <1 RK_PC3 3 &pcfg_pull_none_12ma>,
 920                                         /* mac_txd0 */
 921                                         <1 RK_PC2 3 &pcfg_pull_none_12ma>,
 922                                         /* mac_rxd0 */
 923                                         <1 RK_PC4 3 &pcfg_pull_none>,
 924                                         /* mac_rxd1 */
 925                                         <1 RK_PC5 3 &pcfg_pull_none>,
 926                                         /* mac_rxer */
 927                                         <1 RK_PB7 3 &pcfg_pull_none>,
 928                                         /* mac_rxdv */
 929                                         <1 RK_PC0 3 &pcfg_pull_none>,
 930                                         /* mac_mdio */
 931                                         <1 RK_PB6 3 &pcfg_pull_none>,
 932                                         /* mac_mdc */
 933                                         <1 RK_PB5 3 &pcfg_pull_none>;
 934                         };
 935
 936                         mac_refclk_12ma: mac-refclk-12ma {
 937                                 rockchip,pins =
 938                                         <1 RK_PB4 3 &pcfg_pull_none_12ma>;
 939                         };
 940
 941                         mac_refclk: mac-refclk {
 942                                 rockchip,pins =
 943                                         <1 RK_PB4 3 &pcfg_pull_none>;
 944                         };
 945                 };
 946
 947                 gmac-m1 {
 948                         rmiim1_pins: rmiim1-pins {
 949                                 rockchip,pins =
 950                                         /* mac_txen */
 951                                         <4 RK_PB7 2 &pcfg_pull_none_12ma>,
 952                                         /* mac_txd1 */
 953                                         <4 RK_PA5 2 &pcfg_pull_none_12ma>,
 954                                         /* mac_txd0 */
 955                                         <4 RK_PA4 2 &pcfg_pull_none_12ma>,
 956                                         /* mac_rxd0 */
 957                                         <4 RK_PA2 2 &pcfg_pull_none>,
 958                                         /* mac_rxd1 */
 959                                         <4 RK_PA3 2 &pcfg_pull_none>,
 960                                         /* mac_rxer */
 961                                         <4 RK_PA0 2 &pcfg_pull_none>,
 962                                         /* mac_rxdv */
 963                                         <4 RK_PA1 2 &pcfg_pull_none>,
 964                                         /* mac_mdio */
 965                                         <4 RK_PB6 2 &pcfg_pull_none>,
 966                                         /* mac_mdc */
 967                                         <4 RK_PB5 2 &pcfg_pull_none>;
 968                         };
 969
 970                         macm1_refclk_12ma: macm1-refclk-12ma {
 971                                 rockchip,pins =
 972                                         <4 RK_PB4 2 &pcfg_pull_none_12ma>;
 973                         };
 974
 975                         macm1_refclk: macm1-refclk {
 976                                 rockchip,pins =
 977                                         <4 RK_PB4 2 &pcfg_pull_none>;
 978                         };
 979                 };
 980
 981                 i2c0 {
 982                         i2c0_xfer: i2c0-xfer {
 983                                 rockchip,pins =
 984                                         <1 RK_PD0 2 &pcfg_pull_none_smt>,
 985                                         <1 RK_PD1 2 &pcfg_pull_none_smt>;
 986                         };
 987                 };
 988
 989                 i2c1 {
 990                         i2c1_xfer: i2c1-xfer {
 991                                 rockchip,pins =
 992                                         <0 RK_PB3 1 &pcfg_pull_none_smt>,
 993                                         <0 RK_PB4 1 &pcfg_pull_none_smt>;
 994                         };
 995                 };
 996
 997                 i2c2 {
 998                         i2c2_xfer: i2c2-xfer {
 999                                 rockchip,pins =
1000                                         <2 RK_PA2 3 &pcfg_pull_none_smt>,
1001                                         <2 RK_PA3 3 &pcfg_pull_none_smt>;
1002                         };
1003                 };
1004
1005                 i2c3-m0 {
1006                         i2c3m0_xfer: i2c3m0-xfer {
1007                                 rockchip,pins =
1008                                         <0 RK_PB7 2 &pcfg_pull_none_smt>,
1009                                         <0 RK_PC0 2 &pcfg_pull_none_smt>;
1010                         };
1011                 };
1012
1013                 i2c3-m1 {
1014                         i2c3m1_xfer: i2c3m1-xfer {
1015                                 rockchip,pins =
1016                                         <3 RK_PB4 2 &pcfg_pull_none_smt>,
1017                                         <3 RK_PB5 2 &pcfg_pull_none_smt>;
1018                         };
1019                 };
1020
1021                 i2c3-m2 {
1022                         i2c3m2_xfer: i2c3m2-xfer {
1023                                 rockchip,pins =
1024                                         <2 RK_PA1 3 &pcfg_pull_none_smt>,
1025                                         <2 RK_PA0 3 &pcfg_pull_none_smt>;
1026                         };
1027                 };
1028
1029                 i2s_2ch_0 {
1030                         i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1031                                 rockchip,pins =
1032                                         <4 RK_PB4 1 &pcfg_pull_none>;
1033                         };
1034
1035                         i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1036                                 rockchip,pins =
1037                                         <4 RK_PB5 1 &pcfg_pull_none>;
1038                         };
1039
1040                         i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1041                                 rockchip,pins =
1042                                         <4 RK_PB6 1 &pcfg_pull_none>;
1043                         };
1044
1045                         i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1046                                 rockchip,pins =
1047                                         <4 RK_PB7 1 &pcfg_pull_none>;
1048                         };
1049
1050                         i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1051                                 rockchip,pins =
1052                                         <4 RK_PC0 1 &pcfg_pull_none>;
1053                         };
1054                 };
1055
1056                 i2s_8ch_0 {
1057                         i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1058                                 rockchip,pins =
1059                                         <2 RK_PA4 1 &pcfg_pull_none>;
1060                         };
1061
1062                         i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1063                                 rockchip,pins =
1064                                         <2 RK_PA5 1 &pcfg_pull_none>;
1065                         };
1066
1067                         i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1068                                 rockchip,pins =
1069                                         <2 RK_PA6 1 &pcfg_pull_none>;
1070                         };
1071
1072                         i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1073                                 rockchip,pins =
1074                                         <2 RK_PA7 1 &pcfg_pull_none>;
1075                         };
1076
1077                         i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1078                                 rockchip,pins =
1079                                         <2 RK_PB0 1 &pcfg_pull_none>;
1080                         };
1081
1082                         i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1083                                 rockchip,pins =
1084                                         <2 RK_PB1 1 &pcfg_pull_none>;
1085                         };
1086
1087                         i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1088                                 rockchip,pins =
1089                                         <2 RK_PB2 1 &pcfg_pull_none>;
1090                         };
1091
1092                         i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1093                                 rockchip,pins =
1094                                         <2 RK_PB3 1 &pcfg_pull_none>;
1095                         };
1096
1097                         i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1098                                 rockchip,pins =
1099                                         <2 RK_PB4 1 &pcfg_pull_none>;
1100                         };
1101
1102                         i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1103                                 rockchip,pins =
1104                                         <2 RK_PB5 1 &pcfg_pull_none>;
1105                         };
1106
1107                         i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1108                                 rockchip,pins =
1109                                         <2 RK_PB6 1 &pcfg_pull_none>;
1110                         };
1111
1112                         i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1113                                 rockchip,pins =
1114                                         <2 RK_PB7 1 &pcfg_pull_none>;
1115                         };
1116
1117                         i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1118                                 rockchip,pins =
1119                                         <2 RK_PC0 1 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 i2s_8ch_1_m0 {
1124                         i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1125                                 rockchip,pins =
1126                                         <1 RK_PA2 2 &pcfg_pull_none>;
1127                         };
1128
1129                         i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1130                                 rockchip,pins =
1131                                         <1 RK_PA3 2 &pcfg_pull_none>;
1132                         };
1133
1134                         i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1135                                 rockchip,pins =
1136                                         <1 RK_PA4 2 &pcfg_pull_none>;
1137                         };
1138
1139                         i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1140                                 rockchip,pins =
1141                                         <1 RK_PA5 2 &pcfg_pull_none>;
1142                         };
1143
1144                         i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1145                                 rockchip,pins =
1146                                         <1 RK_PA6 2 &pcfg_pull_none>;
1147                         };
1148
1149                         i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1150                                 rockchip,pins =
1151                                         <1 RK_PA7 2 &pcfg_pull_none>;
1152                         };
1153
1154                         i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1155                                 rockchip,pins =
1156                                         <1 RK_PB0 2 &pcfg_pull_none>;
1157                         };
1158
1159                         i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1160                                 rockchip,pins =
1161                                         <1 RK_PB1 2 &pcfg_pull_none>;
1162                         };
1163
1164                         i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1165                                 rockchip,pins =
1166                                         <1 RK_PB2 2 &pcfg_pull_none>;
1167                         };
1168
1169                         i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1170                                 rockchip,pins =
1171                                         <1 RK_PB3 2 &pcfg_pull_none>;
1172                         };
1173                 };
1174
1175                 i2s_8ch_1_m1 {
1176                         i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1177                                 rockchip,pins =
1178                                         <1 RK_PB4 2 &pcfg_pull_none>;
1179                         };
1180
1181                         i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1182                                 rockchip,pins =
1183                                         <1 RK_PB5 2 &pcfg_pull_none>;
1184                         };
1185
1186                         i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1187                                 rockchip,pins =
1188                                         <1 RK_PB6 2 &pcfg_pull_none>;
1189                         };
1190
1191                         i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1192                                 rockchip,pins =
1193                                         <1 RK_PB7 2 &pcfg_pull_none>;
1194                         };
1195
1196                         i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1197                                 rockchip,pins =
1198                                         <1 RK_PC0 2 &pcfg_pull_none>;
1199                         };
1200
1201                         i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1202                                 rockchip,pins =
1203                                         <1 RK_PC1 2 &pcfg_pull_none>;
1204                         };
1205
1206                         i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1207                                 rockchip,pins =
1208                                         <1 RK_PC2 2 &pcfg_pull_none>;
1209                         };
1210
1211                         i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1212                                 rockchip,pins =
1213                                         <1 RK_PC3 2 &pcfg_pull_none>;
1214                         };
1215
1216                         i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1217                                 rockchip,pins =
1218                                         <1 RK_PC4 2 &pcfg_pull_none>;
1219                         };
1220
1221                         i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1222                                 rockchip,pins =
1223                                         <1 RK_PC5 2 &pcfg_pull_none>;
1224                         };
1225                 };
1226
1227                 pdm_m0 {
1228                         pdm_m0_clk: pdm-m0-clk {
1229                                 rockchip,pins =
1230                                         <1 RK_PA4 3 &pcfg_pull_none>;
1231                         };
1232
1233                         pdm_m0_sdi0: pdm-m0-sdi0 {
1234                                 rockchip,pins =
1235                                         <1 RK_PB3 3 &pcfg_pull_none>;
1236                         };
1237
1238                         pdm_m0_sdi1: pdm-m0-sdi1 {
1239                                 rockchip,pins =
1240                                         <1 RK_PB2 3 &pcfg_pull_none>;
1241                         };
1242
1243                         pdm_m0_sdi2: pdm-m0-sdi2 {
1244                                 rockchip,pins =
1245                                         <1 RK_PB1 3 &pcfg_pull_none>;
1246                         };
1247
1248                         pdm_m0_sdi3: pdm-m0-sdi3 {
1249                                 rockchip,pins =
1250                                         <1 RK_PB0 3 &pcfg_pull_none>;
1251                         };
1252                 };
1253
1254                 pdm_m1 {
1255                         pdm_m1_clk: pdm-m1-clk {
1256                                 rockchip,pins =
1257                                         <1 RK_PB6 4 &pcfg_pull_none>;
1258                         };
1259
1260                         pdm_m1_sdi0: pdm-m1-sdi0 {
1261                                 rockchip,pins =
1262                                         <1 RK_PC5 4 &pcfg_pull_none>;
1263                         };
1264
1265                         pdm_m1_sdi1: pdm-m1-sdi1 {
1266                                 rockchip,pins =
1267                                         <1 RK_PC4 4 &pcfg_pull_none>;
1268                         };
1269
1270                         pdm_m1_sdi2: pdm-m1-sdi2 {
1271                                 rockchip,pins =
1272                                         <1 RK_PC3 4 &pcfg_pull_none>;
1273                         };
1274
1275                         pdm_m1_sdi3: pdm-m1-sdi3 {
1276                                 rockchip,pins =
1277                                         <1 RK_PC2 4 &pcfg_pull_none>;
1278                         };
1279                 };
1280
1281                 pdm_m2 {
1282                         pdm_m2_clkm: pdm-m2-clkm {
1283                                 rockchip,pins =
1284                                         <2 RK_PA4 3 &pcfg_pull_none>;
1285                         };
1286
1287                         pdm_m2_clk: pdm-m2-clk {
1288                                 rockchip,pins =
1289                                         <2 RK_PA6 2 &pcfg_pull_none>;
1290                         };
1291
1292                         pdm_m2_sdi0: pdm-m2-sdi0 {
1293                                 rockchip,pins =
1294                                         <2 RK_PB5 2 &pcfg_pull_none>;
1295                         };
1296
1297                         pdm_m2_sdi1: pdm-m2-sdi1 {
1298                                 rockchip,pins =
1299                                         <2 RK_PB6 2 &pcfg_pull_none>;
1300                         };
1301
1302                         pdm_m2_sdi2: pdm-m2-sdi2 {
1303                                 rockchip,pins =
1304                                         <2 RK_PB7 2 &pcfg_pull_none>;
1305                         };
1306
1307                         pdm_m2_sdi3: pdm-m2-sdi3 {
1308                                 rockchip,pins =
1309                                         <2 RK_PC0 2 &pcfg_pull_none>;
1310                         };
1311                 };
1312
1313                 pwm0 {
1314                         pwm0_pin: pwm0-pin {
1315                                 rockchip,pins =
1316                                         <0 RK_PB5 1 &pcfg_pull_none>;
1317                         };
1318
1319                         pwm0_pin_pull_down: pwm0-pin-pull-down {
1320                                 rockchip,pins =
1321                                         <0 RK_PB5 1 &pcfg_pull_down>;
1322                         };
1323                 };
1324
1325                 pwm1 {
1326                         pwm1_pin: pwm1-pin {
1327                                 rockchip,pins =
1328                                         <0 RK_PB6 1 &pcfg_pull_none>;
1329                         };
1330
1331                         pwm1_pin_pull_down: pwm1-pin-pull-down {
1332                                 rockchip,pins =
1333                                         <0 RK_PB6 1 &pcfg_pull_down>;
1334                         };
1335                 };
1336
1337                 pwm2 {
1338                         pwm2_pin: pwm2-pin {
1339                                 rockchip,pins =
1340                                         <0 RK_PB7 1 &pcfg_pull_none>;
1341                         };
1342
1343                         pwm2_pin_pull_down: pwm2-pin-pull-down {
1344                                 rockchip,pins =
1345                                         <0 RK_PB7 1 &pcfg_pull_down>;
1346                         };
1347                 };
1348
1349                 pwm3 {
1350                         pwm3_pin: pwm3-pin {
1351                                 rockchip,pins =
1352                                         <0 RK_PC0 1 &pcfg_pull_none>;
1353                         };
1354
1355                         pwm3_pin_pull_down: pwm3-pin-pull-down {
1356                                 rockchip,pins =
1357                                         <0 RK_PC0 1 &pcfg_pull_down>;
1358                         };
1359                 };
1360
1361                 pwm4 {
1362                         pwm4_pin: pwm4-pin {
1363                                 rockchip,pins =
1364                                         <0 RK_PA1 2 &pcfg_pull_none>;
1365                         };
1366
1367                         pwm4_pin_pull_down: pwm4-pin-pull-down {
1368                                 rockchip,pins =
1369                                         <0 RK_PA1 2 &pcfg_pull_down>;
1370                         };
1371                 };
1372
1373                 pwm5 {
1374                         pwm5_pin: pwm5-pin {
1375                                 rockchip,pins =
1376                                         <0 RK_PC1 2 &pcfg_pull_none>;
1377                         };
1378
1379                         pwm5_pin_pull_down: pwm5-pin-pull-down {
1380                                 rockchip,pins =
1381                                         <0 RK_PC1 2 &pcfg_pull_down>;
1382                         };
1383                 };
1384
1385                 pwm6 {
1386                         pwm6_pin: pwm6-pin {
1387                                 rockchip,pins =
1388                                         <0 RK_PC2 2 &pcfg_pull_none>;
1389                         };
1390
1391                         pwm6_pin_pull_down: pwm6-pin-pull-down {
1392                                 rockchip,pins =
1393                                         <0 RK_PC2 2 &pcfg_pull_down>;
1394                         };
1395                 };
1396
1397                 pwm7 {
1398                         pwm7_pin: pwm7-pin {
1399                                 rockchip,pins =
1400                                         <2 RK_PB0 2 &pcfg_pull_none>;
1401                         };
1402
1403                         pwm7_pin_pull_down: pwm7-pin-pull-down {
1404                                 rockchip,pins =
1405                                         <2 RK_PB0 2 &pcfg_pull_down>;
1406                         };
1407                 };
1408
1409                 pwm8 {
1410                         pwm8_pin: pwm8-pin {
1411                                 rockchip,pins =
1412                                         <2 RK_PB2 2 &pcfg_pull_none>;
1413                         };
1414
1415                         pwm8_pin_pull_down: pwm8-pin-pull-down {
1416                                 rockchip,pins =
1417                                         <2 RK_PB2 2 &pcfg_pull_down>;
1418                         };
1419                 };
1420
1421                 pwm9 {
1422                         pwm9_pin: pwm9-pin {
1423                                 rockchip,pins =
1424                                         <2 RK_PB3 2 &pcfg_pull_none>;
1425                         };
1426
1427                         pwm9_pin_pull_down: pwm9-pin-pull-down {
1428                                 rockchip,pins =
1429                                         <2 RK_PB3 2 &pcfg_pull_down>;
1430                         };
1431                 };
1432
1433                 pwm10 {
1434                         pwm10_pin: pwm10-pin {
1435                                 rockchip,pins =
1436                                         <2 RK_PB4 2 &pcfg_pull_none>;
1437                         };
1438
1439                         pwm10_pin_pull_down: pwm10-pin-pull-down {
1440                                 rockchip,pins =
1441                                         <2 RK_PB4 2 &pcfg_pull_down>;
1442                         };
1443                 };
1444
1445                 pwm11 {
1446                         pwm11_pin: pwm11-pin {
1447                                 rockchip,pins =
1448                                         <2 RK_PC0 4 &pcfg_pull_none>;
1449                         };
1450
1451                         pwm11_pin_pull_down: pwm11-pin-pull-down {
1452                                 rockchip,pins =
1453                                         <2 RK_PC0 4 &pcfg_pull_down>;
1454                         };
1455                 };
1456
1457                 rtc {
1458                         rtc_32k: rtc-32k {
1459                                 rockchip,pins =
1460                                         <0 RK_PC3 1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 sdmmc {
1465                         sdmmc_clk: sdmmc-clk {
1466                                 rockchip,pins =
1467                                         <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1468                         };
1469
1470                         sdmmc_cmd: sdmmc-cmd {
1471                                 rockchip,pins =
1472                                         <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1473                         };
1474
1475                         sdmmc_det: sdmmc-det {
1476                                 rockchip,pins =
1477                                         <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1478                         };
1479
1480                         sdmmc_pwren: sdmmc-pwren {
1481                                 rockchip,pins =
1482                                         <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1483                         };
1484
1485                         sdmmc_bus1: sdmmc-bus1 {
1486                                 rockchip,pins =
1487                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1488                         };
1489
1490                         sdmmc_bus4: sdmmc-bus4 {
1491                                 rockchip,pins =
1492                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1493                                         <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1494                                         <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1495                                         <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1496                         };
1497                 };
1498
1499                 sdio {
1500                         sdio_clk: sdio-clk {
1501                                 rockchip,pins =
1502                                         <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1503                         };
1504
1505                         sdio_cmd: sdio-cmd {
1506                                 rockchip,pins =
1507                                         <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1508                         };
1509
1510                         sdio_pwren: sdio-pwren {
1511                                 rockchip,pins =
1512                                         <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1513                         };
1514
1515                         sdio_wrpt: sdio-wrpt {
1516                                 rockchip,pins =
1517                                         <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1518                         };
1519
1520                         sdio_intn: sdio-intn {
1521                                 rockchip,pins =
1522                                         <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1523                         };
1524
1525                         sdio_bus1: sdio-bus1 {
1526                                 rockchip,pins =
1527                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1528                         };
1529
1530                         sdio_bus4: sdio-bus4 {
1531                                 rockchip,pins =
1532                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1533                                         <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1534                                         <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1535                                         <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1536                         };
1537                 };
1538
1539                 spdif_in {
1540                         spdif_in: spdif-in {
1541                                 rockchip,pins =
1542                                         <0 RK_PC2 1 &pcfg_pull_none>;
1543                         };
1544                 };
1545
1546                 spdif_out {
1547                         spdif_out: spdif-out {
1548                                 rockchip,pins =
1549                                         <0 RK_PC1 1 &pcfg_pull_none>;
1550                         };
1551                 };
1552
1553                 spi0 {
1554                         spi0_clk: spi0-clk {
1555                                 rockchip,pins =
1556                                         <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1557                         };
1558
1559                         spi0_csn0: spi0-csn0 {
1560                                 rockchip,pins =
1561                                         <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1562                         };
1563
1564                         spi0_miso: spi0-miso {
1565                                 rockchip,pins =
1566                                         <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1567                         };
1568
1569                         spi0_mosi: spi0-mosi {
1570                                 rockchip,pins =
1571                                         <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1572                         };
1573                 };
1574
1575                 spi1 {
1576                         spi1_clk: spi1-clk {
1577                                 rockchip,pins =
1578                                         <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1579                         };
1580
1581                         spi1_csn0: spi1-csn0 {
1582                                 rockchip,pins =
1583                                         <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1584                         };
1585
1586                         spi1_miso: spi1-miso {
1587                                 rockchip,pins =
1588                                         <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1589                         };
1590
1591                         spi1_mosi: spi1-mosi {
1592                                 rockchip,pins =
1593                                         <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1594                         };
1595                 };
1596
1597                 spi1-m1 {
1598                         spi1m1_miso: spi1m1-miso {
1599                                 rockchip,pins =
1600                                         <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1601                         };
1602
1603                         spi1m1_mosi: spi1m1-mosi {
1604                                 rockchip,pins =
1605                                         <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1606                         };
1607
1608                         spi1m1_clk: spi1m1-clk {
1609                                 rockchip,pins =
1610                                         <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1611                         };
1612
1613                         spi1m1_csn0: spi1m1-csn0 {
1614                                 rockchip,pins =
1615                                         <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1616                         };
1617                 };
1618
1619                 spi2 {
1620                         spi2_clk: spi2-clk {
1621                                 rockchip,pins =
1622                                         <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1623                         };
1624
1625                         spi2_csn0: spi2-csn0 {
1626                                 rockchip,pins =
1627                                         <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1628                         };
1629
1630                         spi2_miso: spi2-miso {
1631                                 rockchip,pins =
1632                                         <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1633                         };
1634
1635                         spi2_mosi: spi2-mosi {
1636                                 rockchip,pins =
1637                                         <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1638                         };
1639                 };
1640
1641                 tsadc {
1642                         tsadc_otp_pin: tsadc-otp-pin {
1643                                 rockchip,pins =
1644                                         <0 RK_PB2 0 &pcfg_pull_none>;
1645                         };
1646
1647                         tsadc_otp_out: tsadc-otp-out {
1648                                 rockchip,pins =
1649                                         <0 RK_PB2 1 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 uart0 {
1654                         uart0_xfer: uart0-xfer {
1655                                 rockchip,pins =
1656                                         <2 RK_PA1 1 &pcfg_pull_up>,
1657                                         <2 RK_PA0 1 &pcfg_pull_up>;
1658                         };
1659
1660                         uart0_cts: uart0-cts {
1661                                 rockchip,pins =
1662                                         <2 RK_PA2 1 &pcfg_pull_none>;
1663                         };
1664
1665                         uart0_rts: uart0-rts {
1666                                 rockchip,pins =
1667                                         <2 RK_PA3 1 &pcfg_pull_none>;
1668                         };
1669
1670                         uart0_rts_pin: uart0-rts-pin {
1671                                 rockchip,pins =
1672                                         <2 RK_PA3 0 &pcfg_pull_none>;
1673                         };
1674                 };
1675
1676                 uart1 {
1677                         uart1_xfer: uart1-xfer {
1678                                 rockchip,pins =
1679                                         <1 RK_PD1 1 &pcfg_pull_up>,
1680                                         <1 RK_PD0 1 &pcfg_pull_up>;
1681                         };
1682
1683                         uart1_cts: uart1-cts {
1684                                 rockchip,pins =
1685                                         <1 RK_PC6 1 &pcfg_pull_none>;
1686                         };
1687
1688                         uart1_rts: uart1-rts {
1689                                 rockchip,pins =
1690                                         <1 RK_PC7 1 &pcfg_pull_none>;
1691                         };
1692                 };
1693
1694                 uart2-m0 {
1695                         uart2m0_xfer: uart2m0-xfer {
1696                                 rockchip,pins =
1697                                         <1 RK_PC7 2 &pcfg_pull_up>,
1698                                         <1 RK_PC6 2 &pcfg_pull_up>;
1699                         };
1700                 };
1701
1702                 uart2-m1 {
1703                         uart2m1_xfer: uart2m1-xfer {
1704                                 rockchip,pins =
1705                                         <4 RK_PD3 2 &pcfg_pull_up>,
1706                                         <4 RK_PD2 2 &pcfg_pull_up>;
1707                         };
1708                 };
1709
1710                 uart3 {
1711                         uart3_xfer: uart3-xfer {
1712                                 rockchip,pins =
1713                                         <3 RK_PB5 4 &pcfg_pull_up>,
1714                                         <3 RK_PB4 4 &pcfg_pull_up>;
1715                         };
1716                 };
1717
1718                 uart3-m1 {
1719                         uart3m1_xfer: uart3m1-xfer {
1720                                 rockchip,pins =
1721                                         <0 RK_PC2 3 &pcfg_pull_up>,
1722                                         <0 RK_PC1 3 &pcfg_pull_up>;
1723                         };
1724                 };
1725
1726                 uart4 {
1727                         uart4_xfer: uart4-xfer {
1728                                 rockchip,pins =
1729                                         <4 RK_PB1 1 &pcfg_pull_up>,
1730                                         <4 RK_PB0 1 &pcfg_pull_up>;
1731                         };
1732
1733                         uart4_cts: uart4-cts {
1734                                 rockchip,pins =
1735                                         <4 RK_PA6 1 &pcfg_pull_none>;
1736                         };
1737
1738                         uart4_rts: uart4-rts {
1739                                 rockchip,pins =
1740                                         <4 RK_PA7 1 &pcfg_pull_none>;
1741                         };
1742
1743                         uart4_rts_pin: uart4-rts-pin {
1744                                 rockchip,pins =
1745                                         <4 RK_PA7 0 &pcfg_pull_none>;
1746                         };
1747                 };
1748         };
1749 };