1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3308";
18 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
46 clocks = <&cru ARMCLK>;
48 dynamic-power-coefficient = <90>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 cpu-idle-states = <&CPU_SLEEP>;
51 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP>;
61 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a35";
68 enable-method = "psci";
69 operating-points-v2 = <&cpu0_opp_table>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 next-level-cache = <&l2>;
76 compatible = "arm,cortex-a35";
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cpu-idle-states = <&CPU_SLEEP>;
81 next-level-cache = <&l2>;
85 entry-method = "psci";
87 CPU_SLEEP: cpu-sleep {
88 compatible = "arm,idle-state";
90 arm,psci-suspend-param = <0x0010000>;
91 entry-latency-us = <120>;
92 exit-latency-us = <250>;
93 min-residency-us = <900>;
102 cpu0_opp_table: cpu0-opp-table {
103 compatible = "operating-points-v2";
107 opp-hz = /bits/ 64 <408000000>;
108 opp-microvolt = <950000 950000 1340000>;
109 clock-latency-ns = <40000>;
113 opp-hz = /bits/ 64 <600000000>;
114 opp-microvolt = <950000 950000 1340000>;
115 clock-latency-ns = <40000>;
118 opp-hz = /bits/ 64 <816000000>;
119 opp-microvolt = <1025000 1025000 1340000>;
120 clock-latency-ns = <40000>;
123 opp-hz = /bits/ 64 <1008000000>;
124 opp-microvolt = <1125000 1125000 1340000>;
125 clock-latency-ns = <40000>;
130 compatible = "arm,cortex-a35-pmu";
131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
138 mac_clkin: external-mac-clock {
139 compatible = "fixed-clock";
140 clock-frequency = <50000000>;
141 clock-output-names = "mac_clkin";
146 compatible = "arm,psci-1.0";
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
159 compatible = "fixed-clock";
161 clock-frequency = <24000000>;
162 clock-output-names = "xin24m";
166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
167 reg = <0x0 0xff000000 0x0 0x10000>;
170 compatible = "syscon-reboot-mode";
172 mode-bootloader = <BOOT_BL_DOWNLOAD>;
173 mode-loader = <BOOT_BL_DOWNLOAD>;
174 mode-normal = <BOOT_NORMAL>;
175 mode-recovery = <BOOT_RECOVERY>;
176 mode-fastboot = <BOOT_FASTBOOT>;
180 detect_grf: syscon@ff00b000 {
181 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
182 reg = <0x0 0xff00b000 0x0 0x1000>;
183 #address-cells = <1>;
187 core_grf: syscon@ff00c000 {
188 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
189 reg = <0x0 0xff00c000 0x0 0x1000>;
190 #address-cells = <1>;
195 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
196 reg = <0x0 0xff040000 0x0 0x1000>;
197 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
198 clock-names = "i2c", "pclk";
199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c0_xfer>;
202 #address-cells = <1>;
208 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
209 reg = <0x0 0xff050000 0x0 0x1000>;
210 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
211 clock-names = "i2c", "pclk";
212 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c1_xfer>;
215 #address-cells = <1>;
221 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
222 reg = <0x0 0xff060000 0x0 0x1000>;
223 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
224 clock-names = "i2c", "pclk";
225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c2_xfer>;
228 #address-cells = <1>;
234 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
235 reg = <0x0 0xff070000 0x0 0x1000>;
236 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
237 clock-names = "i2c", "pclk";
238 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&i2c3m0_xfer>;
241 #address-cells = <1>;
246 wdt: watchdog@ff080000 {
247 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
248 reg = <0x0 0xff080000 0x0 0x100>;
249 clocks = <&cru PCLK_WDT>;
250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
254 uart0: serial@ff0a0000 {
255 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
256 reg = <0x0 0xff0a0000 0x0 0x100>;
257 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
259 clock-names = "baudclk", "apb_pclk";
262 pinctrl-names = "default";
263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
267 uart1: serial@ff0b0000 {
268 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
269 reg = <0x0 0xff0b0000 0x0 0x100>;
270 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
272 clock-names = "baudclk", "apb_pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
280 uart2: serial@ff0c0000 {
281 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
282 reg = <0x0 0xff0c0000 0x0 0x100>;
283 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
285 clock-names = "baudclk", "apb_pclk";
288 pinctrl-names = "default";
289 pinctrl-0 = <&uart2m0_xfer>;
293 uart3: serial@ff0d0000 {
294 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
295 reg = <0x0 0xff0d0000 0x0 0x100>;
296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
298 clock-names = "baudclk", "apb_pclk";
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart3_xfer>;
306 uart4: serial@ff0e0000 {
307 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
308 reg = <0x0 0xff0e0000 0x0 0x100>;
309 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
311 clock-names = "baudclk", "apb_pclk";
314 pinctrl-names = "default";
315 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
320 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
321 reg = <0x0 0xff120000 0x0 0x1000>;
322 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
325 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
326 clock-names = "spiclk", "apb_pclk";
327 dmas = <&dmac0 0>, <&dmac0 1>;
328 dma-names = "tx", "rx";
329 pinctrl-names = "default";
330 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
335 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
336 reg = <0x0 0xff130000 0x0 0x1000>;
337 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
340 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
341 clock-names = "spiclk", "apb_pclk";
342 dmas = <&dmac0 2>, <&dmac0 3>;
343 dma-names = "tx", "rx";
344 pinctrl-names = "default";
345 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
350 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
351 reg = <0x0 0xff140000 0x0 0x1000>;
352 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
355 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
356 clock-names = "spiclk", "apb_pclk";
357 dmas = <&dmac1 16>, <&dmac1 17>;
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
365 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
366 reg = <0x0 0xff160000 0x0 0x10>;
367 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
368 clock-names = "pwm", "pclk";
369 pinctrl-names = "default";
370 pinctrl-0 = <&pwm8_pin>;
376 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
377 reg = <0x0 0xff160010 0x0 0x10>;
378 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
379 clock-names = "pwm", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm9_pin>;
386 pwm10: pwm@ff160020 {
387 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
388 reg = <0x0 0xff160020 0x0 0x10>;
389 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
390 clock-names = "pwm", "pclk";
391 pinctrl-names = "default";
392 pinctrl-0 = <&pwm10_pin>;
397 pwm11: pwm@ff160030 {
398 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
399 reg = <0x0 0xff160030 0x0 0x10>;
400 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
401 clock-names = "pwm", "pclk";
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm11_pin>;
409 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
410 reg = <0x0 0xff170000 0x0 0x10>;
411 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
412 clock-names = "pwm", "pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm4_pin>;
420 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
421 reg = <0x0 0xff170010 0x0 0x10>;
422 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
423 clock-names = "pwm", "pclk";
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm5_pin>;
431 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
432 reg = <0x0 0xff170020 0x0 0x10>;
433 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm6_pin>;
442 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
443 reg = <0x0 0xff170030 0x0 0x10>;
444 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
445 clock-names = "pwm", "pclk";
446 pinctrl-names = "default";
447 pinctrl-0 = <&pwm7_pin>;
453 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
454 reg = <0x0 0xff180000 0x0 0x10>;
455 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
456 clock-names = "pwm", "pclk";
457 pinctrl-names = "default";
458 pinctrl-0 = <&pwm0_pin>;
464 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
465 reg = <0x0 0xff180010 0x0 0x10>;
466 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
467 clock-names = "pwm", "pclk";
468 pinctrl-names = "default";
469 pinctrl-0 = <&pwm1_pin>;
475 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
476 reg = <0x0 0xff180020 0x0 0x10>;
477 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
478 clock-names = "pwm", "pclk";
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm2_pin>;
486 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
487 reg = <0x0 0xff180030 0x0 0x10>;
488 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
489 clock-names = "pwm", "pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwm3_pin>;
496 rktimer: rktimer@ff1a0000 {
497 compatible = "rockchip,rk3288-timer";
498 reg = <0x0 0xff1a0000 0x0 0x20>;
499 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
501 clock-names = "pclk", "timer";
504 saradc: saradc@ff1e0000 {
505 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
506 reg = <0x0 0xff1e0000 0x0 0x100>;
507 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
509 clock-names = "saradc", "apb_pclk";
510 #io-channel-cells = <1>;
511 resets = <&cru SRST_SARADC_P>;
512 reset-names = "saradc-apb";
516 dmac0: dma-controller@ff2c0000 {
517 compatible = "arm,pl330", "arm,primecell";
518 reg = <0x0 0xff2c0000 0x0 0x4000>;
519 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
521 arm,pl330-periph-burst;
522 clocks = <&cru ACLK_DMAC0>;
523 clock-names = "apb_pclk";
527 dmac1: dma-controller@ff2d0000 {
528 compatible = "arm,pl330", "arm,primecell";
529 reg = <0x0 0xff2d0000 0x0 0x4000>;
530 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
532 arm,pl330-periph-burst;
533 clocks = <&cru ACLK_DMAC1>;
534 clock-names = "apb_pclk";
538 i2s_2ch_0: i2s@ff350000 {
539 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
540 reg = <0x0 0xff350000 0x0 0x1000>;
541 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
543 clock-names = "i2s_clk", "i2s_hclk";
544 dmas = <&dmac1 8>, <&dmac1 9>;
545 dma-names = "tx", "rx";
546 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
547 reset-names = "reset-m", "reset-h";
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2s_2ch_0_sclk
556 i2s_2ch_1: i2s@ff360000 {
557 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
558 reg = <0x0 0xff360000 0x0 0x1000>;
559 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
561 clock-names = "i2s_clk", "i2s_hclk";
564 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
565 reset-names = "reset-m", "reset-h";
569 spdif_tx: spdif-tx@ff3a0000 {
570 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
571 reg = <0x0 0xff3a0000 0x0 0x1000>;
572 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
574 clock-names = "mclk", "hclk";
577 pinctrl-names = "default";
578 pinctrl-0 = <&spdif_out>;
582 sdmmc: mmc@ff480000 {
583 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
584 reg = <0x0 0xff480000 0x0 0x4000>;
585 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
588 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
589 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
590 fifo-depth = <0x100>;
591 max-frequency = <150000000>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
598 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
599 reg = <0x0 0xff490000 0x0 0x4000>;
600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
603 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
604 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
605 fifo-depth = <0x100>;
606 max-frequency = <150000000>;
611 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
612 reg = <0x0 0xff4a0000 0x0 0x4000>;
613 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
616 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
617 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
618 fifo-depth = <0x100>;
619 max-frequency = <150000000>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
625 nfc: nand-controller@ff4b0000 {
626 compatible = "rockchip,rk3308-nfc",
627 "rockchip,rv1108-nfc";
628 reg = <0x0 0xff4b0000 0x0 0x4000>;
629 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
631 clock-names = "ahb", "nfc";
632 assigned-clocks = <&cru SCLK_NANDC>;
633 assigned-clock-rates = <150000000>;
634 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
635 &flash_rdn &flash_rdy &flash_wrn>;
636 pinctrl-names = "default";
640 cru: clock-controller@ff500000 {
641 compatible = "rockchip,rk3308-cru";
642 reg = <0x0 0xff500000 0x0 0x1000>;
645 rockchip,grf = <&grf>;
647 assigned-clocks = <&cru SCLK_RTC32K>;
648 assigned-clock-rates = <32768>;
651 gic: interrupt-controller@ff580000 {
652 compatible = "arm,gic-400";
653 reg = <0x0 0xff581000 0x0 0x1000>,
654 <0x0 0xff582000 0x0 0x2000>,
655 <0x0 0xff584000 0x0 0x2000>,
656 <0x0 0xff586000 0x0 0x2000>;
657 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
658 #interrupt-cells = <3>;
659 interrupt-controller;
660 #address-cells = <0>;
663 sram: sram@fff80000 {
664 compatible = "mmio-sram";
665 reg = <0x0 0xfff80000 0x0 0x40000>;
666 ranges = <0 0x0 0xfff80000 0x40000>;
667 #address-cells = <1>;
670 /* reserved for ddr dvfs and system suspend/resume */
675 /* reserved for vad audio buffer */
676 vad_sram: vad-sram@8000 {
677 reg = <0x8000 0x38000>;
682 compatible = "rockchip,rk3308-pinctrl";
683 rockchip,grf = <&grf>;
684 #address-cells = <2>;
688 gpio0: gpio0@ff220000 {
689 compatible = "rockchip,gpio-bank";
690 reg = <0x0 0xff220000 0x0 0x100>;
691 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cru PCLK_GPIO0>;
695 interrupt-controller;
696 #interrupt-cells = <2>;
699 gpio1: gpio1@ff230000 {
700 compatible = "rockchip,gpio-bank";
701 reg = <0x0 0xff230000 0x0 0x100>;
702 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&cru PCLK_GPIO1>;
706 interrupt-controller;
707 #interrupt-cells = <2>;
710 gpio2: gpio2@ff240000 {
711 compatible = "rockchip,gpio-bank";
712 reg = <0x0 0xff240000 0x0 0x100>;
713 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cru PCLK_GPIO2>;
717 interrupt-controller;
718 #interrupt-cells = <2>;
721 gpio3: gpio3@ff250000 {
722 compatible = "rockchip,gpio-bank";
723 reg = <0x0 0xff250000 0x0 0x100>;
724 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cru PCLK_GPIO3>;
728 interrupt-controller;
729 #interrupt-cells = <2>;
732 gpio4: gpio4@ff260000 {
733 compatible = "rockchip,gpio-bank";
734 reg = <0x0 0xff260000 0x0 0x100>;
735 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&cru PCLK_GPIO4>;
739 interrupt-controller;
740 #interrupt-cells = <2>;
743 pcfg_pull_up: pcfg-pull-up {
747 pcfg_pull_down: pcfg-pull-down {
751 pcfg_pull_none: pcfg-pull-none {
755 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
757 drive-strength = <2>;
760 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
762 drive-strength = <2>;
765 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
767 drive-strength = <4>;
770 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
772 drive-strength = <4>;
775 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
777 drive-strength = <4>;
780 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
782 drive-strength = <8>;
785 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
787 drive-strength = <8>;
790 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
792 drive-strength = <12>;
795 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
797 drive-strength = <12>;
800 pcfg_pull_none_smt: pcfg-pull-none-smt {
802 input-schmitt-enable;
805 pcfg_output_high: pcfg-output-high {
809 pcfg_output_low: pcfg-output-low {
813 pcfg_input_high: pcfg-input-high {
818 pcfg_input: pcfg-input {
825 <3 RK_PB1 2 &pcfg_pull_none_8ma>;
830 <3 RK_PB0 2 &pcfg_pull_up_8ma>;
833 emmc_pwren: emmc-pwren {
835 <3 RK_PB3 2 &pcfg_pull_none>;
838 emmc_rstn: emmc-rstn {
840 <3 RK_PB2 2 &pcfg_pull_none>;
843 emmc_bus1: emmc-bus1 {
845 <3 RK_PA0 2 &pcfg_pull_up_8ma>;
848 emmc_bus4: emmc-bus4 {
850 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
851 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
852 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
853 <3 RK_PA3 2 &pcfg_pull_up_8ma>;
856 emmc_bus8: emmc-bus8 {
858 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
859 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
860 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
861 <3 RK_PA3 2 &pcfg_pull_up_8ma>,
862 <3 RK_PA4 2 &pcfg_pull_up_8ma>,
863 <3 RK_PA5 2 &pcfg_pull_up_8ma>,
864 <3 RK_PA6 2 &pcfg_pull_up_8ma>,
865 <3 RK_PA7 2 &pcfg_pull_up_8ma>;
870 flash_csn0: flash-csn0 {
872 <3 RK_PB5 1 &pcfg_pull_none>;
875 flash_rdy: flash-rdy {
877 <3 RK_PB4 1 &pcfg_pull_none>;
880 flash_ale: flash-ale {
882 <3 RK_PB3 1 &pcfg_pull_none>;
885 flash_cle: flash-cle {
887 <3 RK_PB1 1 &pcfg_pull_none>;
890 flash_wrn: flash-wrn {
892 <3 RK_PB0 1 &pcfg_pull_none>;
895 flash_rdn: flash-rdn {
897 <3 RK_PB2 1 &pcfg_pull_none>;
900 flash_bus8: flash-bus8 {
902 <3 RK_PA0 1 &pcfg_pull_up_12ma>,
903 <3 RK_PA1 1 &pcfg_pull_up_12ma>,
904 <3 RK_PA2 1 &pcfg_pull_up_12ma>,
905 <3 RK_PA3 1 &pcfg_pull_up_12ma>,
906 <3 RK_PA4 1 &pcfg_pull_up_12ma>,
907 <3 RK_PA5 1 &pcfg_pull_up_12ma>,
908 <3 RK_PA6 1 &pcfg_pull_up_12ma>,
909 <3 RK_PA7 1 &pcfg_pull_up_12ma>;
914 rmii_pins: rmii-pins {
917 <1 RK_PC1 3 &pcfg_pull_none_12ma>,
919 <1 RK_PC3 3 &pcfg_pull_none_12ma>,
921 <1 RK_PC2 3 &pcfg_pull_none_12ma>,
923 <1 RK_PC4 3 &pcfg_pull_none>,
925 <1 RK_PC5 3 &pcfg_pull_none>,
927 <1 RK_PB7 3 &pcfg_pull_none>,
929 <1 RK_PC0 3 &pcfg_pull_none>,
931 <1 RK_PB6 3 &pcfg_pull_none>,
933 <1 RK_PB5 3 &pcfg_pull_none>;
936 mac_refclk_12ma: mac-refclk-12ma {
938 <1 RK_PB4 3 &pcfg_pull_none_12ma>;
941 mac_refclk: mac-refclk {
943 <1 RK_PB4 3 &pcfg_pull_none>;
948 rmiim1_pins: rmiim1-pins {
951 <4 RK_PB7 2 &pcfg_pull_none_12ma>,
953 <4 RK_PA5 2 &pcfg_pull_none_12ma>,
955 <4 RK_PA4 2 &pcfg_pull_none_12ma>,
957 <4 RK_PA2 2 &pcfg_pull_none>,
959 <4 RK_PA3 2 &pcfg_pull_none>,
961 <4 RK_PA0 2 &pcfg_pull_none>,
963 <4 RK_PA1 2 &pcfg_pull_none>,
965 <4 RK_PB6 2 &pcfg_pull_none>,
967 <4 RK_PB5 2 &pcfg_pull_none>;
970 macm1_refclk_12ma: macm1-refclk-12ma {
972 <4 RK_PB4 2 &pcfg_pull_none_12ma>;
975 macm1_refclk: macm1-refclk {
977 <4 RK_PB4 2 &pcfg_pull_none>;
982 i2c0_xfer: i2c0-xfer {
984 <1 RK_PD0 2 &pcfg_pull_none_smt>,
985 <1 RK_PD1 2 &pcfg_pull_none_smt>;
990 i2c1_xfer: i2c1-xfer {
992 <0 RK_PB3 1 &pcfg_pull_none_smt>,
993 <0 RK_PB4 1 &pcfg_pull_none_smt>;
998 i2c2_xfer: i2c2-xfer {
1000 <2 RK_PA2 3 &pcfg_pull_none_smt>,
1001 <2 RK_PA3 3 &pcfg_pull_none_smt>;
1006 i2c3m0_xfer: i2c3m0-xfer {
1008 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1009 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1014 i2c3m1_xfer: i2c3m1-xfer {
1016 <3 RK_PB4 2 &pcfg_pull_none_smt>,
1017 <3 RK_PB5 2 &pcfg_pull_none_smt>;
1022 i2c3m2_xfer: i2c3m2-xfer {
1024 <2 RK_PA1 3 &pcfg_pull_none_smt>,
1025 <2 RK_PA0 3 &pcfg_pull_none_smt>;
1030 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1032 <4 RK_PB4 1 &pcfg_pull_none>;
1035 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1037 <4 RK_PB5 1 &pcfg_pull_none>;
1040 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1042 <4 RK_PB6 1 &pcfg_pull_none>;
1045 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1047 <4 RK_PB7 1 &pcfg_pull_none>;
1050 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1052 <4 RK_PC0 1 &pcfg_pull_none>;
1057 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1059 <2 RK_PA4 1 &pcfg_pull_none>;
1062 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1064 <2 RK_PA5 1 &pcfg_pull_none>;
1067 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1069 <2 RK_PA6 1 &pcfg_pull_none>;
1072 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1074 <2 RK_PA7 1 &pcfg_pull_none>;
1077 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1079 <2 RK_PB0 1 &pcfg_pull_none>;
1082 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1084 <2 RK_PB1 1 &pcfg_pull_none>;
1087 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1089 <2 RK_PB2 1 &pcfg_pull_none>;
1092 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1094 <2 RK_PB3 1 &pcfg_pull_none>;
1097 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1099 <2 RK_PB4 1 &pcfg_pull_none>;
1102 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1104 <2 RK_PB5 1 &pcfg_pull_none>;
1107 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1109 <2 RK_PB6 1 &pcfg_pull_none>;
1112 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1114 <2 RK_PB7 1 &pcfg_pull_none>;
1117 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1119 <2 RK_PC0 1 &pcfg_pull_none>;
1124 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1126 <1 RK_PA2 2 &pcfg_pull_none>;
1129 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1131 <1 RK_PA3 2 &pcfg_pull_none>;
1134 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1136 <1 RK_PA4 2 &pcfg_pull_none>;
1139 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1141 <1 RK_PA5 2 &pcfg_pull_none>;
1144 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1146 <1 RK_PA6 2 &pcfg_pull_none>;
1149 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1151 <1 RK_PA7 2 &pcfg_pull_none>;
1154 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1156 <1 RK_PB0 2 &pcfg_pull_none>;
1159 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1161 <1 RK_PB1 2 &pcfg_pull_none>;
1164 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1166 <1 RK_PB2 2 &pcfg_pull_none>;
1169 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1171 <1 RK_PB3 2 &pcfg_pull_none>;
1176 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1178 <1 RK_PB4 2 &pcfg_pull_none>;
1181 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1183 <1 RK_PB5 2 &pcfg_pull_none>;
1186 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1188 <1 RK_PB6 2 &pcfg_pull_none>;
1191 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1193 <1 RK_PB7 2 &pcfg_pull_none>;
1196 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1198 <1 RK_PC0 2 &pcfg_pull_none>;
1201 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1203 <1 RK_PC1 2 &pcfg_pull_none>;
1206 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1208 <1 RK_PC2 2 &pcfg_pull_none>;
1211 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1213 <1 RK_PC3 2 &pcfg_pull_none>;
1216 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1218 <1 RK_PC4 2 &pcfg_pull_none>;
1221 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1223 <1 RK_PC5 2 &pcfg_pull_none>;
1228 pdm_m0_clk: pdm-m0-clk {
1230 <1 RK_PA4 3 &pcfg_pull_none>;
1233 pdm_m0_sdi0: pdm-m0-sdi0 {
1235 <1 RK_PB3 3 &pcfg_pull_none>;
1238 pdm_m0_sdi1: pdm-m0-sdi1 {
1240 <1 RK_PB2 3 &pcfg_pull_none>;
1243 pdm_m0_sdi2: pdm-m0-sdi2 {
1245 <1 RK_PB1 3 &pcfg_pull_none>;
1248 pdm_m0_sdi3: pdm-m0-sdi3 {
1250 <1 RK_PB0 3 &pcfg_pull_none>;
1255 pdm_m1_clk: pdm-m1-clk {
1257 <1 RK_PB6 4 &pcfg_pull_none>;
1260 pdm_m1_sdi0: pdm-m1-sdi0 {
1262 <1 RK_PC5 4 &pcfg_pull_none>;
1265 pdm_m1_sdi1: pdm-m1-sdi1 {
1267 <1 RK_PC4 4 &pcfg_pull_none>;
1270 pdm_m1_sdi2: pdm-m1-sdi2 {
1272 <1 RK_PC3 4 &pcfg_pull_none>;
1275 pdm_m1_sdi3: pdm-m1-sdi3 {
1277 <1 RK_PC2 4 &pcfg_pull_none>;
1282 pdm_m2_clkm: pdm-m2-clkm {
1284 <2 RK_PA4 3 &pcfg_pull_none>;
1287 pdm_m2_clk: pdm-m2-clk {
1289 <2 RK_PA6 2 &pcfg_pull_none>;
1292 pdm_m2_sdi0: pdm-m2-sdi0 {
1294 <2 RK_PB5 2 &pcfg_pull_none>;
1297 pdm_m2_sdi1: pdm-m2-sdi1 {
1299 <2 RK_PB6 2 &pcfg_pull_none>;
1302 pdm_m2_sdi2: pdm-m2-sdi2 {
1304 <2 RK_PB7 2 &pcfg_pull_none>;
1307 pdm_m2_sdi3: pdm-m2-sdi3 {
1309 <2 RK_PC0 2 &pcfg_pull_none>;
1314 pwm0_pin: pwm0-pin {
1316 <0 RK_PB5 1 &pcfg_pull_none>;
1319 pwm0_pin_pull_down: pwm0-pin-pull-down {
1321 <0 RK_PB5 1 &pcfg_pull_down>;
1326 pwm1_pin: pwm1-pin {
1328 <0 RK_PB6 1 &pcfg_pull_none>;
1331 pwm1_pin_pull_down: pwm1-pin-pull-down {
1333 <0 RK_PB6 1 &pcfg_pull_down>;
1338 pwm2_pin: pwm2-pin {
1340 <0 RK_PB7 1 &pcfg_pull_none>;
1343 pwm2_pin_pull_down: pwm2-pin-pull-down {
1345 <0 RK_PB7 1 &pcfg_pull_down>;
1350 pwm3_pin: pwm3-pin {
1352 <0 RK_PC0 1 &pcfg_pull_none>;
1355 pwm3_pin_pull_down: pwm3-pin-pull-down {
1357 <0 RK_PC0 1 &pcfg_pull_down>;
1362 pwm4_pin: pwm4-pin {
1364 <0 RK_PA1 2 &pcfg_pull_none>;
1367 pwm4_pin_pull_down: pwm4-pin-pull-down {
1369 <0 RK_PA1 2 &pcfg_pull_down>;
1374 pwm5_pin: pwm5-pin {
1376 <0 RK_PC1 2 &pcfg_pull_none>;
1379 pwm5_pin_pull_down: pwm5-pin-pull-down {
1381 <0 RK_PC1 2 &pcfg_pull_down>;
1386 pwm6_pin: pwm6-pin {
1388 <0 RK_PC2 2 &pcfg_pull_none>;
1391 pwm6_pin_pull_down: pwm6-pin-pull-down {
1393 <0 RK_PC2 2 &pcfg_pull_down>;
1398 pwm7_pin: pwm7-pin {
1400 <2 RK_PB0 2 &pcfg_pull_none>;
1403 pwm7_pin_pull_down: pwm7-pin-pull-down {
1405 <2 RK_PB0 2 &pcfg_pull_down>;
1410 pwm8_pin: pwm8-pin {
1412 <2 RK_PB2 2 &pcfg_pull_none>;
1415 pwm8_pin_pull_down: pwm8-pin-pull-down {
1417 <2 RK_PB2 2 &pcfg_pull_down>;
1422 pwm9_pin: pwm9-pin {
1424 <2 RK_PB3 2 &pcfg_pull_none>;
1427 pwm9_pin_pull_down: pwm9-pin-pull-down {
1429 <2 RK_PB3 2 &pcfg_pull_down>;
1434 pwm10_pin: pwm10-pin {
1436 <2 RK_PB4 2 &pcfg_pull_none>;
1439 pwm10_pin_pull_down: pwm10-pin-pull-down {
1441 <2 RK_PB4 2 &pcfg_pull_down>;
1446 pwm11_pin: pwm11-pin {
1448 <2 RK_PC0 4 &pcfg_pull_none>;
1451 pwm11_pin_pull_down: pwm11-pin-pull-down {
1453 <2 RK_PC0 4 &pcfg_pull_down>;
1460 <0 RK_PC3 1 &pcfg_pull_none>;
1465 sdmmc_clk: sdmmc-clk {
1467 <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1470 sdmmc_cmd: sdmmc-cmd {
1472 <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1475 sdmmc_det: sdmmc-det {
1477 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1480 sdmmc_pwren: sdmmc-pwren {
1482 <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1485 sdmmc_bus1: sdmmc-bus1 {
1487 <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1490 sdmmc_bus4: sdmmc-bus4 {
1492 <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1493 <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1494 <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1495 <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1500 sdio_clk: sdio-clk {
1502 <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1505 sdio_cmd: sdio-cmd {
1507 <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1510 sdio_pwren: sdio-pwren {
1512 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1515 sdio_wrpt: sdio-wrpt {
1517 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1520 sdio_intn: sdio-intn {
1522 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1525 sdio_bus1: sdio-bus1 {
1527 <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1530 sdio_bus4: sdio-bus4 {
1532 <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1533 <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1534 <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1535 <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1540 spdif_in: spdif-in {
1542 <0 RK_PC2 1 &pcfg_pull_none>;
1547 spdif_out: spdif-out {
1549 <0 RK_PC1 1 &pcfg_pull_none>;
1554 spi0_clk: spi0-clk {
1556 <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1559 spi0_csn0: spi0-csn0 {
1561 <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1564 spi0_miso: spi0-miso {
1566 <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1569 spi0_mosi: spi0-mosi {
1571 <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1576 spi1_clk: spi1-clk {
1578 <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1581 spi1_csn0: spi1-csn0 {
1583 <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1586 spi1_miso: spi1-miso {
1588 <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1591 spi1_mosi: spi1-mosi {
1593 <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1598 spi1m1_miso: spi1m1-miso {
1600 <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1603 spi1m1_mosi: spi1m1-mosi {
1605 <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1608 spi1m1_clk: spi1m1-clk {
1610 <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1613 spi1m1_csn0: spi1m1-csn0 {
1615 <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1620 spi2_clk: spi2-clk {
1622 <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1625 spi2_csn0: spi2-csn0 {
1627 <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1630 spi2_miso: spi2-miso {
1632 <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1635 spi2_mosi: spi2-mosi {
1637 <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1642 tsadc_otp_pin: tsadc-otp-pin {
1644 <0 RK_PB2 0 &pcfg_pull_none>;
1647 tsadc_otp_out: tsadc-otp-out {
1649 <0 RK_PB2 1 &pcfg_pull_none>;
1654 uart0_xfer: uart0-xfer {
1656 <2 RK_PA1 1 &pcfg_pull_up>,
1657 <2 RK_PA0 1 &pcfg_pull_up>;
1660 uart0_cts: uart0-cts {
1662 <2 RK_PA2 1 &pcfg_pull_none>;
1665 uart0_rts: uart0-rts {
1667 <2 RK_PA3 1 &pcfg_pull_none>;
1670 uart0_rts_pin: uart0-rts-pin {
1672 <2 RK_PA3 0 &pcfg_pull_none>;
1677 uart1_xfer: uart1-xfer {
1679 <1 RK_PD1 1 &pcfg_pull_up>,
1680 <1 RK_PD0 1 &pcfg_pull_up>;
1683 uart1_cts: uart1-cts {
1685 <1 RK_PC6 1 &pcfg_pull_none>;
1688 uart1_rts: uart1-rts {
1690 <1 RK_PC7 1 &pcfg_pull_none>;
1695 uart2m0_xfer: uart2m0-xfer {
1697 <1 RK_PC7 2 &pcfg_pull_up>,
1698 <1 RK_PC6 2 &pcfg_pull_up>;
1703 uart2m1_xfer: uart2m1-xfer {
1705 <4 RK_PD3 2 &pcfg_pull_up>,
1706 <4 RK_PD2 2 &pcfg_pull_up>;
1711 uart3_xfer: uart3-xfer {
1713 <3 RK_PB5 4 &pcfg_pull_up>,
1714 <3 RK_PB4 4 &pcfg_pull_up>;
1719 uart3m1_xfer: uart3m1-xfer {
1721 <0 RK_PC2 3 &pcfg_pull_up>,
1722 <0 RK_PC1 3 &pcfg_pull_up>;
1727 uart4_xfer: uart4-xfer {
1729 <4 RK_PB1 1 &pcfg_pull_up>,
1730 <4 RK_PB0 1 &pcfg_pull_up>;
1733 uart4_cts: uart4-cts {
1735 <4 RK_PA6 1 &pcfg_pull_none>;
1738 uart4_rts: uart4-rts {
1740 <4 RK_PA7 1 &pcfg_pull_none>;
1743 uart4_rts_pin: uart4-rts-pin {
1745 <4 RK_PA7 0 &pcfg_pull_none>;