arch/arm64/boot/dts/rockchip/rk3308.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
   4  *
   5  */
   6
   7 #include <dt-bindings/clock/rk3308-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3308";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26                 gpio3 = &gpio3;
  27                 gpio4 = &gpio4;
  28                 i2c0 = &i2c0;
  29                 i2c1 = &i2c1;
  30                 i2c2 = &i2c2;
  31                 i2c3 = &i2c3;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 spi0 = &spi0;
  38                 spi1 = &spi1;
  39                 spi2 = &spi2;
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a35";
  49                         reg = <0x0 0x0>;
  50                         enable-method = "psci";
  51                         clocks = <&cru ARMCLK>;
  52                         #cooling-cells = <2>;
  53                         dynamic-power-coefficient = <90>;
  54                         operating-points-v2 = <&cpu0_opp_table>;
  55                         cpu-idle-states = <&CPU_SLEEP>;
  56                         next-level-cache = <&l2>;
  57                 };
  58
  59                 cpu1: cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a35";
  62                         reg = <0x0 0x1>;
  63                         enable-method = "psci";
  64                         operating-points-v2 = <&cpu0_opp_table>;
  65                         cpu-idle-states = <&CPU_SLEEP>;
  66                         next-level-cache = <&l2>;
  67                 };
  68
  69                 cpu2: cpu@2 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a35";
  72                         reg = <0x0 0x2>;
  73                         enable-method = "psci";
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                         cpu-idle-states = <&CPU_SLEEP>;
  76                         next-level-cache = <&l2>;
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a35";
  82                         reg = <0x0 0x3>;
  83                         enable-method = "psci";
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85                         cpu-idle-states = <&CPU_SLEEP>;
  86                         next-level-cache = <&l2>;
  87                 };
  88
  89                 idle-states {
  90                         entry-method = "psci";
  91
  92                         CPU_SLEEP: cpu-sleep {
  93                                 compatible = "arm,idle-state";
  94                                 local-timer-stop;
  95                                 arm,psci-suspend-param = <0x0010000>;
  96                                 entry-latency-us = <120>;
  97                                 exit-latency-us = <250>;
  98                                 min-residency-us = <900>;
  99                         };
 100                 };
 101
 102                 l2: l2-cache {
 103                         compatible = "cache";
 104                         cache-level = <2>;
 105                         cache-unified;
 106                 };
 107         };
 108
 109         cpu0_opp_table: opp-table-0 {
 110                 compatible = "operating-points-v2";
 111                 opp-shared;
 112
 113                 opp-408000000 {
 114                         opp-hz = /bits/ 64 <408000000>;
 115                         opp-microvolt = <950000 950000 1340000>;
 116                         clock-latency-ns = <40000>;
 117                         opp-suspend;
 118                 };
 119                 opp-600000000 {
 120                         opp-hz = /bits/ 64 <600000000>;
 121                         opp-microvolt = <950000 950000 1340000>;
 122                         clock-latency-ns = <40000>;
 123                 };
 124                 opp-816000000 {
 125                         opp-hz = /bits/ 64 <816000000>;
 126                         opp-microvolt = <1025000 1025000 1340000>;
 127                         clock-latency-ns = <40000>;
 128                 };
 129                 opp-1008000000 {
 130                         opp-hz = /bits/ 64 <1008000000>;
 131                         opp-microvolt = <1125000 1125000 1340000>;
 132                         clock-latency-ns = <40000>;
 133                 };
 134         };
 135
 136         arm-pmu {
 137                 compatible = "arm,cortex-a35-pmu";
 138                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 142                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 143         };
 144
 145         mac_clkin: external-mac-clock {
 146                 compatible = "fixed-clock";
 147                 clock-frequency = <50000000>;
 148                 clock-output-names = "mac_clkin";
 149                 #clock-cells = <0>;
 150         };
 151
 152         psci {
 153                 compatible = "arm,psci-1.0";
 154                 method = "smc";
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 160                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 161                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 162                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 163         };
 164
 165         xin24m: xin24m {
 166                 compatible = "fixed-clock";
 167                 #clock-cells = <0>;
 168                 clock-frequency = <24000000>;
 169                 clock-output-names = "xin24m";
 170         };
 171
 172         grf: grf@ff000000 {
 173                 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
 174                 reg = <0x0 0xff000000 0x0 0x08000>;
 175
 176                 reboot-mode {
 177                         compatible = "syscon-reboot-mode";
 178                         offset = <0x500>;
 179                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 180                         mode-loader = <BOOT_BL_DOWNLOAD>;
 181                         mode-normal = <BOOT_NORMAL>;
 182                         mode-recovery = <BOOT_RECOVERY>;
 183                         mode-fastboot = <BOOT_FASTBOOT>;
 184                 };
 185         };
 186
 187         usb2phy_grf: syscon@ff008000 {
 188                 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
 189                 reg = <0x0 0xff008000 0x0 0x4000>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192
 193                 u2phy: usb2phy@100 {
 194                         compatible = "rockchip,rk3308-usb2phy";
 195                         reg = <0x100 0x10>;
 196                         assigned-clocks = <&cru USB480M>;
 197                         assigned-clock-parents = <&u2phy>;
 198                         clocks = <&cru SCLK_USBPHY_REF>;
 199                         clock-names = "phyclk";
 200                         clock-output-names = "usb480m_phy";
 201                         #clock-cells = <0>;
 202                         status = "disabled";
 203
 204                         u2phy_otg: otg-port {
 205                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 206                                              <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 207                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 208                                 interrupt-names = "otg-bvalid", "otg-id",
 209                                                   "linestate";
 210                                 #phy-cells = <0>;
 211                                 status = "disabled";
 212                         };
 213
 214                         u2phy_host: host-port {
 215                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 216                                 interrupt-names = "linestate";
 217                                 #phy-cells = <0>;
 218                                 status = "disabled";
 219                         };
 220                 };
 221         };
 222
 223         detect_grf: syscon@ff00b000 {
 224                 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
 225                 reg = <0x0 0xff00b000 0x0 0x1000>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228         };
 229
 230         core_grf: syscon@ff00c000 {
 231                 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
 232                 reg = <0x0 0xff00c000 0x0 0x1000>;
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235         };
 236
 237         i2c0: i2c@ff040000 {
 238                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 239                 reg = <0x0 0xff040000 0x0 0x1000>;
 240                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 241                 clock-names = "i2c", "pclk";
 242                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 243                 pinctrl-names = "default";
 244                 pinctrl-0 = <&i2c0_xfer>;
 245                 #address-cells = <1>;
 246                 #size-cells = <0>;
 247                 status = "disabled";
 248         };
 249
 250         i2c1: i2c@ff050000 {
 251                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 252                 reg = <0x0 0xff050000 0x0 0x1000>;
 253                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 254                 clock-names = "i2c", "pclk";
 255                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&i2c1_xfer>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 status = "disabled";
 261         };
 262
 263         i2c2: i2c@ff060000 {
 264                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 265                 reg = <0x0 0xff060000 0x0 0x1000>;
 266                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 267                 clock-names = "i2c", "pclk";
 268                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 269                 pinctrl-names = "default";
 270                 pinctrl-0 = <&i2c2_xfer>;
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 status = "disabled";
 274         };
 275
 276         i2c3: i2c@ff070000 {
 277                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 278                 reg = <0x0 0xff070000 0x0 0x1000>;
 279                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 280                 clock-names = "i2c", "pclk";
 281                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&i2c3m0_xfer>;
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 status = "disabled";
 287         };
 288
 289         wdt: watchdog@ff080000 {
 290                 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
 291                 reg = <0x0 0xff080000 0x0 0x100>;
 292                 clocks = <&cru PCLK_WDT>;
 293                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 294                 status = "disabled";
 295         };
 296
 297         uart0: serial@ff0a0000 {
 298                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 299                 reg = <0x0 0xff0a0000 0x0 0x100>;
 300                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 301                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 302                 clock-names = "baudclk", "apb_pclk";
 303                 reg-shift = <2>;
 304                 reg-io-width = <4>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 307                 status = "disabled";
 308         };
 309
 310         uart1: serial@ff0b0000 {
 311                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 312                 reg = <0x0 0xff0b0000 0x0 0x100>;
 313                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 315                 clock-names = "baudclk", "apb_pclk";
 316                 reg-shift = <2>;
 317                 reg-io-width = <4>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 320                 status = "disabled";
 321         };
 322
 323         uart2: serial@ff0c0000 {
 324                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 325                 reg = <0x0 0xff0c0000 0x0 0x100>;
 326                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 reg-shift = <2>;
 330                 reg-io-width = <4>;
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&uart2m0_xfer>;
 333                 status = "disabled";
 334         };
 335
 336         uart3: serial@ff0d0000 {
 337                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 338                 reg = <0x0 0xff0d0000 0x0 0x100>;
 339                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 341                 clock-names = "baudclk", "apb_pclk";
 342                 reg-shift = <2>;
 343                 reg-io-width = <4>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&uart3_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         uart4: serial@ff0e0000 {
 350                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 351                 reg = <0x0 0xff0e0000 0x0 0x100>;
 352                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 354                 clock-names = "baudclk", "apb_pclk";
 355                 reg-shift = <2>;
 356                 reg-io-width = <4>;
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 359                 status = "disabled";
 360         };
 361
 362         spi0: spi@ff120000 {
 363                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 364                 reg = <0x0 0xff120000 0x0 0x1000>;
 365                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 369                 clock-names = "spiclk", "apb_pclk";
 370                 dmas = <&dmac0 0>, <&dmac0 1>;
 371                 dma-names = "tx", "rx";
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
 374                 status = "disabled";
 375         };
 376
 377         spi1: spi@ff130000 {
 378                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 379                 reg = <0x0 0xff130000 0x0 0x1000>;
 380                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 384                 clock-names = "spiclk", "apb_pclk";
 385                 dmas = <&dmac0 2>, <&dmac0 3>;
 386                 dma-names = "tx", "rx";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
 389                 status = "disabled";
 390         };
 391
 392         spi2: spi@ff140000 {
 393                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 394                 reg = <0x0 0xff140000 0x0 0x1000>;
 395                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 dmas = <&dmac1 16>, <&dmac1 17>;
 401                 dma-names = "tx", "rx";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
 404                 status = "disabled";
 405         };
 406
 407         pwm8: pwm@ff160000 {
 408                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 409                 reg = <0x0 0xff160000 0x0 0x10>;
 410                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 411                 clock-names = "pwm", "pclk";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&pwm8_pin>;
 414                 #pwm-cells = <3>;
 415                 status = "disabled";
 416         };
 417
 418         pwm9: pwm@ff160010 {
 419                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 420                 reg = <0x0 0xff160010 0x0 0x10>;
 421                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 422                 clock-names = "pwm", "pclk";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&pwm9_pin>;
 425                 #pwm-cells = <3>;
 426                 status = "disabled";
 427         };
 428
 429         pwm10: pwm@ff160020 {
 430                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 431                 reg = <0x0 0xff160020 0x0 0x10>;
 432                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 433                 clock-names = "pwm", "pclk";
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&pwm10_pin>;
 436                 #pwm-cells = <3>;
 437                 status = "disabled";
 438         };
 439
 440         pwm11: pwm@ff160030 {
 441                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 442                 reg = <0x0 0xff160030 0x0 0x10>;
 443                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 444                 clock-names = "pwm", "pclk";
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&pwm11_pin>;
 447                 #pwm-cells = <3>;
 448                 status = "disabled";
 449         };
 450
 451         pwm4: pwm@ff170000 {
 452                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 453                 reg = <0x0 0xff170000 0x0 0x10>;
 454                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 455                 clock-names = "pwm", "pclk";
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&pwm4_pin>;
 458                 #pwm-cells = <3>;
 459                 status = "disabled";
 460         };
 461
 462         pwm5: pwm@ff170010 {
 463                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 464                 reg = <0x0 0xff170010 0x0 0x10>;
 465                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 466                 clock-names = "pwm", "pclk";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&pwm5_pin>;
 469                 #pwm-cells = <3>;
 470                 status = "disabled";
 471         };
 472
 473         pwm6: pwm@ff170020 {
 474                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 475                 reg = <0x0 0xff170020 0x0 0x10>;
 476                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 477                 clock-names = "pwm", "pclk";
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&pwm6_pin>;
 480                 #pwm-cells = <3>;
 481                 status = "disabled";
 482         };
 483
 484         pwm7: pwm@ff170030 {
 485                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 486                 reg = <0x0 0xff170030 0x0 0x10>;
 487                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 488                 clock-names = "pwm", "pclk";
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&pwm7_pin>;
 491                 #pwm-cells = <3>;
 492                 status = "disabled";
 493         };
 494
 495         pwm0: pwm@ff180000 {
 496                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 497                 reg = <0x0 0xff180000 0x0 0x10>;
 498                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 499                 clock-names = "pwm", "pclk";
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&pwm0_pin>;
 502                 #pwm-cells = <3>;
 503                 status = "disabled";
 504         };
 505
 506         pwm1: pwm@ff180010 {
 507                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 508                 reg = <0x0 0xff180010 0x0 0x10>;
 509                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 510                 clock-names = "pwm", "pclk";
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&pwm1_pin>;
 513                 #pwm-cells = <3>;
 514                 status = "disabled";
 515         };
 516
 517         pwm2: pwm@ff180020 {
 518                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 519                 reg = <0x0 0xff180020 0x0 0x10>;
 520                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 521                 clock-names = "pwm", "pclk";
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&pwm2_pin>;
 524                 #pwm-cells = <3>;
 525                 status = "disabled";
 526         };
 527
 528         pwm3: pwm@ff180030 {
 529                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 530                 reg = <0x0 0xff180030 0x0 0x10>;
 531                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 532                 clock-names = "pwm", "pclk";
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&pwm3_pin>;
 535                 #pwm-cells = <3>;
 536                 status = "disabled";
 537         };
 538
 539         rktimer: rktimer@ff1a0000 {
 540                 compatible = "rockchip,rk3288-timer";
 541                 reg = <0x0 0xff1a0000 0x0 0x20>;
 542                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 544                 clock-names = "pclk", "timer";
 545         };
 546
 547         saradc: saradc@ff1e0000 {
 548                 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
 549                 reg = <0x0 0xff1e0000 0x0 0x100>;
 550                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 552                 clock-names = "saradc", "apb_pclk";
 553                 #io-channel-cells = <1>;
 554                 resets = <&cru SRST_SARADC_P>;
 555                 reset-names = "saradc-apb";
 556                 status = "disabled";
 557         };
 558
 559         dmac0: dma-controller@ff2c0000 {
 560                 compatible = "arm,pl330", "arm,primecell";
 561                 reg = <0x0 0xff2c0000 0x0 0x4000>;
 562                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 563                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 564                 arm,pl330-periph-burst;
 565                 clocks = <&cru ACLK_DMAC0>;
 566                 clock-names = "apb_pclk";
 567                 #dma-cells = <1>;
 568         };
 569
 570         dmac1: dma-controller@ff2d0000 {
 571                 compatible = "arm,pl330", "arm,primecell";
 572                 reg = <0x0 0xff2d0000 0x0 0x4000>;
 573                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 574                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 575                 arm,pl330-periph-burst;
 576                 clocks = <&cru ACLK_DMAC1>;
 577                 clock-names = "apb_pclk";
 578                 #dma-cells = <1>;
 579         };
 580
 581         i2s_2ch_0: i2s@ff350000 {
 582                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 583                 reg = <0x0 0xff350000 0x0 0x1000>;
 584                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 585                 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
 586                 clock-names = "i2s_clk", "i2s_hclk";
 587                 dmas = <&dmac1 8>, <&dmac1 9>;
 588                 dma-names = "tx", "rx";
 589                 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
 590                 reset-names = "reset-m", "reset-h";
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2s_2ch_0_sclk
 593                              &i2s_2ch_0_lrck
 594                              &i2s_2ch_0_sdi
 595                              &i2s_2ch_0_sdo>;
 596                 status = "disabled";
 597         };
 598
 599         i2s_2ch_1: i2s@ff360000 {
 600                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 601                 reg = <0x0 0xff360000 0x0 0x1000>;
 602                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
 604                 clock-names = "i2s_clk", "i2s_hclk";
 605                 dmas = <&dmac1 11>;
 606                 dma-names = "rx";
 607                 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
 608                 reset-names = "reset-m", "reset-h";
 609                 status = "disabled";
 610         };
 611
 612         spdif_tx: spdif-tx@ff3a0000 {
 613                 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
 614                 reg = <0x0 0xff3a0000 0x0 0x1000>;
 615                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 616                 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
 617                 clock-names = "mclk", "hclk";
 618                 dmas = <&dmac1 13>;
 619                 dma-names = "tx";
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&spdif_out>;
 622                 status = "disabled";
 623         };
 624
 625         usb20_otg: usb@ff400000 {
 626                 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
 627                              "snps,dwc2";
 628                 reg = <0x0 0xff400000 0x0 0x40000>;
 629                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&cru HCLK_OTG>;
 631                 clock-names = "otg";
 632                 dr_mode = "otg";
 633                 g-np-tx-fifo-size = <16>;
 634                 g-rx-fifo-size = <280>;
 635                 g-tx-fifo-size = <256 128 128 64 32 16>;
 636                 phys = <&u2phy_otg>;
 637                 phy-names = "usb2-phy";
 638                 status = "disabled";
 639         };
 640
 641         usb_host_ehci: usb@ff440000 {
 642                 compatible = "generic-ehci";
 643                 reg = <0x0 0xff440000 0x0 0x10000>;
 644                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
 646                 phys = <&u2phy_host>;
 647                 phy-names = "usb";
 648                 status = "disabled";
 649         };
 650
 651         usb_host_ohci: usb@ff450000 {
 652                 compatible = "generic-ohci";
 653                 reg = <0x0 0xff450000 0x0 0x10000>;
 654                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
 656                 phys = <&u2phy_host>;
 657                 phy-names = "usb";
 658                 status = "disabled";
 659         };
 660
 661         sdmmc: mmc@ff480000 {
 662                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 663                 reg = <0x0 0xff480000 0x0 0x4000>;
 664                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 665                 bus-width = <4>;
 666                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 667                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 668                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 669                 fifo-depth = <0x100>;
 670                 max-frequency = <150000000>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 673                 status = "disabled";
 674         };
 675
 676         emmc: mmc@ff490000 {
 677                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 678                 reg = <0x0 0xff490000 0x0 0x4000>;
 679                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 680                 bus-width = <8>;
 681                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 682                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 683                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 684                 fifo-depth = <0x100>;
 685                 max-frequency = <150000000>;
 686                 status = "disabled";
 687         };
 688
 689         sdio: mmc@ff4a0000 {
 690                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 691                 reg = <0x0 0xff4a0000 0x0 0x4000>;
 692                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 693                 bus-width = <4>;
 694                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 695                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 696                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 697                 fifo-depth = <0x100>;
 698                 max-frequency = <150000000>;
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 701                 status = "disabled";
 702         };
 703
 704         nfc: nand-controller@ff4b0000 {
 705                 compatible = "rockchip,rk3308-nfc",
 706                              "rockchip,rv1108-nfc";
 707                 reg = <0x0 0xff4b0000 0x0 0x4000>;
 708                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 710                 clock-names = "ahb", "nfc";
 711                 assigned-clocks = <&cru SCLK_NANDC>;
 712                 assigned-clock-rates = <150000000>;
 713                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 714                              &flash_rdn &flash_rdy &flash_wrn>;
 715                 pinctrl-names = "default";
 716                 status = "disabled";
 717         };
 718
 719         gmac: ethernet@ff4e0000 {
 720                 compatible = "rockchip,rk3308-gmac";
 721                 reg = <0x0 0xff4e0000 0x0 0x10000>;
 722                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 723                 interrupt-names = "macirq";
 724                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
 725                          <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
 726                          <&cru SCLK_MAC>, <&cru ACLK_MAC>,
 727                          <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
 728                 clock-names = "stmmaceth", "mac_clk_rx",
 729                               "mac_clk_tx", "clk_mac_ref",
 730                               "clk_mac_refout", "aclk_mac",
 731                               "pclk_mac", "clk_mac_speed";
 732                 phy-mode = "rmii";
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 735                 resets = <&cru SRST_MAC_A>;
 736                 reset-names = "stmmaceth";
 737                 rockchip,grf = <&grf>;
 738                 status = "disabled";
 739         };
 740
 741         sfc: spi@ff4c0000 {
 742                 compatible = "rockchip,sfc";
 743                 reg = <0x0 0xff4c0000 0x0 0x4000>;
 744                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 745                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 746                 clock-names = "clk_sfc", "hclk_sfc";
 747                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
 748                 pinctrl-names = "default";
 749                 status = "disabled";
 750         };
 751
 752         cru: clock-controller@ff500000 {
 753                 compatible = "rockchip,rk3308-cru";
 754                 reg = <0x0 0xff500000 0x0 0x1000>;
 755                 clocks = <&xin24m>;
 756                 clock-names = "xin24m";
 757                 rockchip,grf = <&grf>;
 758                 #clock-cells = <1>;
 759                 #reset-cells = <1>;
 760                 assigned-clocks = <&cru SCLK_RTC32K>;
 761                 assigned-clock-rates = <32768>;
 762         };
 763
 764         gic: interrupt-controller@ff580000 {
 765                 compatible = "arm,gic-400";
 766                 reg = <0x0 0xff581000 0x0 0x1000>,
 767                       <0x0 0xff582000 0x0 0x2000>,
 768                       <0x0 0xff584000 0x0 0x2000>,
 769                       <0x0 0xff586000 0x0 0x2000>;
 770                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 771                 #interrupt-cells = <3>;
 772                 interrupt-controller;
 773                 #address-cells = <0>;
 774         };
 775
 776         sram: sram@fff80000 {
 777                 compatible = "mmio-sram";
 778                 reg = <0x0 0xfff80000 0x0 0x40000>;
 779                 ranges = <0 0x0 0xfff80000 0x40000>;
 780                 #address-cells = <1>;
 781                 #size-cells = <1>;
 782
 783                 /* reserved for ddr dvfs and system suspend/resume */
 784                 ddr-sram@0 {
 785                         reg = <0x0 0x8000>;
 786                 };
 787
 788                 /* reserved for vad audio buffer */
 789                 vad_sram: vad-sram@8000 {
 790                         reg = <0x8000 0x38000>;
 791                 };
 792         };
 793
 794         pinctrl: pinctrl {
 795                 compatible = "rockchip,rk3308-pinctrl";
 796                 rockchip,grf = <&grf>;
 797                 #address-cells = <2>;
 798                 #size-cells = <2>;
 799                 ranges;
 800
 801                 gpio0: gpio@ff220000 {
 802                         compatible = "rockchip,gpio-bank";
 803                         reg = <0x0 0xff220000 0x0 0x100>;
 804                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 805                         clocks = <&cru PCLK_GPIO0>;
 806                         gpio-controller;
 807                         #gpio-cells = <2>;
 808                         interrupt-controller;
 809                         #interrupt-cells = <2>;
 810                 };
 811
 812                 gpio1: gpio@ff230000 {
 813                         compatible = "rockchip,gpio-bank";
 814                         reg = <0x0 0xff230000 0x0 0x100>;
 815                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&cru PCLK_GPIO1>;
 817                         gpio-controller;
 818                         #gpio-cells = <2>;
 819                         interrupt-controller;
 820                         #interrupt-cells = <2>;
 821                 };
 822
 823                 gpio2: gpio@ff240000 {
 824                         compatible = "rockchip,gpio-bank";
 825                         reg = <0x0 0xff240000 0x0 0x100>;
 826                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 827                         clocks = <&cru PCLK_GPIO2>;
 828                         gpio-controller;
 829                         #gpio-cells = <2>;
 830                         interrupt-controller;
 831                         #interrupt-cells = <2>;
 832                 };
 833
 834                 gpio3: gpio@ff250000 {
 835                         compatible = "rockchip,gpio-bank";
 836                         reg = <0x0 0xff250000 0x0 0x100>;
 837                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&cru PCLK_GPIO3>;
 839                         gpio-controller;
 840                         #gpio-cells = <2>;
 841                         interrupt-controller;
 842                         #interrupt-cells = <2>;
 843                 };
 844
 845                 gpio4: gpio@ff260000 {
 846                         compatible = "rockchip,gpio-bank";
 847                         reg = <0x0 0xff260000 0x0 0x100>;
 848                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 849                         clocks = <&cru PCLK_GPIO4>;
 850                         gpio-controller;
 851                         #gpio-cells = <2>;
 852                         interrupt-controller;
 853                         #interrupt-cells = <2>;
 854                 };
 855
 856                 pcfg_pull_up: pcfg-pull-up {
 857                         bias-pull-up;
 858                 };
 859
 860                 pcfg_pull_down: pcfg-pull-down {
 861                         bias-pull-down;
 862                 };
 863
 864                 pcfg_pull_none: pcfg-pull-none {
 865                         bias-disable;
 866                 };
 867
 868                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 869                         bias-disable;
 870                         drive-strength = <2>;
 871                 };
 872
 873                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 874                         bias-pull-up;
 875                         drive-strength = <2>;
 876                 };
 877
 878                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 879                         bias-pull-up;
 880                         drive-strength = <4>;
 881                 };
 882
 883                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 884                         bias-disable;
 885                         drive-strength = <4>;
 886                 };
 887
 888                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 889                         bias-pull-down;
 890                         drive-strength = <4>;
 891                 };
 892
 893                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 894                         bias-disable;
 895                         drive-strength = <8>;
 896                 };
 897
 898                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 899                         bias-pull-up;
 900                         drive-strength = <8>;
 901                 };
 902
 903                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 904                         bias-disable;
 905                         drive-strength = <12>;
 906                 };
 907
 908                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 909                         bias-pull-up;
 910                         drive-strength = <12>;
 911                 };
 912
 913                 pcfg_pull_none_smt: pcfg-pull-none-smt {
 914                         bias-disable;
 915                         input-schmitt-enable;
 916                 };
 917
 918                 pcfg_output_high: pcfg-output-high {
 919                         output-high;
 920                 };
 921
 922                 pcfg_output_low: pcfg-output-low {
 923                         output-low;
 924                 };
 925
 926                 pcfg_input_high: pcfg-input-high {
 927                         bias-pull-up;
 928                         input-enable;
 929                 };
 930
 931                 pcfg_input: pcfg-input {
 932                         input-enable;
 933                 };
 934
 935                 emmc {
 936                         emmc_clk: emmc-clk {
 937                                 rockchip,pins =
 938                                         <3 RK_PB1 2 &pcfg_pull_none_8ma>;
 939                         };
 940
 941                         emmc_cmd: emmc-cmd {
 942                                 rockchip,pins =
 943                                         <3 RK_PB0 2 &pcfg_pull_up_8ma>;
 944                         };
 945
 946                         emmc_pwren: emmc-pwren {
 947                                 rockchip,pins =
 948                                         <3 RK_PB3 2 &pcfg_pull_none>;
 949                         };
 950
 951                         emmc_rstn: emmc-rstn {
 952                                 rockchip,pins =
 953                                         <3 RK_PB2 2 &pcfg_pull_none>;
 954                         };
 955
 956                         emmc_bus1: emmc-bus1 {
 957                                 rockchip,pins =
 958                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>;
 959                         };
 960
 961                         emmc_bus4: emmc-bus4 {
 962                                 rockchip,pins =
 963                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 964                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 965                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 966                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>;
 967                         };
 968
 969                         emmc_bus8: emmc-bus8 {
 970                                 rockchip,pins =
 971                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 972                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 973                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 974                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>,
 975                                         <3 RK_PA4 2 &pcfg_pull_up_8ma>,
 976                                         <3 RK_PA5 2 &pcfg_pull_up_8ma>,
 977                                         <3 RK_PA6 2 &pcfg_pull_up_8ma>,
 978                                         <3 RK_PA7 2 &pcfg_pull_up_8ma>;
 979                         };
 980                 };
 981
 982                 flash {
 983                         flash_csn0: flash-csn0 {
 984                                 rockchip,pins =
 985                                         <3 RK_PB5 1 &pcfg_pull_none>;
 986                         };
 987
 988                         flash_rdy: flash-rdy {
 989                                 rockchip,pins =
 990                                         <3 RK_PB4 1 &pcfg_pull_none>;
 991                         };
 992
 993                         flash_ale: flash-ale {
 994                                 rockchip,pins =
 995                                         <3 RK_PB3 1 &pcfg_pull_none>;
 996                         };
 997
 998                         flash_cle: flash-cle {
 999                                 rockchip,pins =
1000                                         <3 RK_PB1 1 &pcfg_pull_none>;
1001                         };
1002
1003                         flash_wrn: flash-wrn {
1004                                 rockchip,pins =
1005                                         <3 RK_PB0 1 &pcfg_pull_none>;
1006                         };
1007
1008                         flash_rdn: flash-rdn {
1009                                 rockchip,pins =
1010                                         <3 RK_PB2 1 &pcfg_pull_none>;
1011                         };
1012
1013                         flash_bus8: flash-bus8 {
1014                                 rockchip,pins =
1015                                         <3 RK_PA0 1 &pcfg_pull_up_12ma>,
1016                                         <3 RK_PA1 1 &pcfg_pull_up_12ma>,
1017                                         <3 RK_PA2 1 &pcfg_pull_up_12ma>,
1018                                         <3 RK_PA3 1 &pcfg_pull_up_12ma>,
1019                                         <3 RK_PA4 1 &pcfg_pull_up_12ma>,
1020                                         <3 RK_PA5 1 &pcfg_pull_up_12ma>,
1021                                         <3 RK_PA6 1 &pcfg_pull_up_12ma>,
1022                                         <3 RK_PA7 1 &pcfg_pull_up_12ma>;
1023                         };
1024                 };
1025
1026                 sfc {
1027                         sfc_bus4: sfc-bus4 {
1028                                 rockchip,pins =
1029                                         <3 RK_PA0 3 &pcfg_pull_none>,
1030                                         <3 RK_PA1 3 &pcfg_pull_none>,
1031                                         <3 RK_PA2 3 &pcfg_pull_none>,
1032                                         <3 RK_PA3 3 &pcfg_pull_none>;
1033                         };
1034
1035                         sfc_bus2: sfc-bus2 {
1036                                 rockchip,pins =
1037                                         <3 RK_PA0 3 &pcfg_pull_none>,
1038                                         <3 RK_PA1 3 &pcfg_pull_none>;
1039                         };
1040
1041                         sfc_cs0: sfc-cs0 {
1042                                 rockchip,pins =
1043                                         <3 RK_PA4 3 &pcfg_pull_none>;
1044                         };
1045
1046                         sfc_clk: sfc-clk {
1047                                 rockchip,pins =
1048                                         <3 RK_PA5 3 &pcfg_pull_none>;
1049                         };
1050                 };
1051
1052                 gmac {
1053                         rmii_pins: rmii-pins {
1054                                 rockchip,pins =
1055                                         /* mac_txen */
1056                                         <1 RK_PC1 3 &pcfg_pull_none_12ma>,
1057                                         /* mac_txd1 */
1058                                         <1 RK_PC3 3 &pcfg_pull_none_12ma>,
1059                                         /* mac_txd0 */
1060                                         <1 RK_PC2 3 &pcfg_pull_none_12ma>,
1061                                         /* mac_rxd0 */
1062                                         <1 RK_PC4 3 &pcfg_pull_none>,
1063                                         /* mac_rxd1 */
1064                                         <1 RK_PC5 3 &pcfg_pull_none>,
1065                                         /* mac_rxer */
1066                                         <1 RK_PB7 3 &pcfg_pull_none>,
1067                                         /* mac_rxdv */
1068                                         <1 RK_PC0 3 &pcfg_pull_none>,
1069                                         /* mac_mdio */
1070                                         <1 RK_PB6 3 &pcfg_pull_none>,
1071                                         /* mac_mdc */
1072                                         <1 RK_PB5 3 &pcfg_pull_none>;
1073                         };
1074
1075                         mac_refclk_12ma: mac-refclk-12ma {
1076                                 rockchip,pins =
1077                                         <1 RK_PB4 3 &pcfg_pull_none_12ma>;
1078                         };
1079
1080                         mac_refclk: mac-refclk {
1081                                 rockchip,pins =
1082                                         <1 RK_PB4 3 &pcfg_pull_none>;
1083                         };
1084                 };
1085
1086                 gmac-m1 {
1087                         rmiim1_pins: rmiim1-pins {
1088                                 rockchip,pins =
1089                                         /* mac_txen */
1090                                         <4 RK_PB7 2 &pcfg_pull_none_12ma>,
1091                                         /* mac_txd1 */
1092                                         <4 RK_PA5 2 &pcfg_pull_none_12ma>,
1093                                         /* mac_txd0 */
1094                                         <4 RK_PA4 2 &pcfg_pull_none_12ma>,
1095                                         /* mac_rxd0 */
1096                                         <4 RK_PA2 2 &pcfg_pull_none>,
1097                                         /* mac_rxd1 */
1098                                         <4 RK_PA3 2 &pcfg_pull_none>,
1099                                         /* mac_rxer */
1100                                         <4 RK_PA0 2 &pcfg_pull_none>,
1101                                         /* mac_rxdv */
1102                                         <4 RK_PA1 2 &pcfg_pull_none>,
1103                                         /* mac_mdio */
1104                                         <4 RK_PB6 2 &pcfg_pull_none>,
1105                                         /* mac_mdc */
1106                                         <4 RK_PB5 2 &pcfg_pull_none>;
1107                         };
1108
1109                         macm1_refclk_12ma: macm1-refclk-12ma {
1110                                 rockchip,pins =
1111                                         <4 RK_PB4 2 &pcfg_pull_none_12ma>;
1112                         };
1113
1114                         macm1_refclk: macm1-refclk {
1115                                 rockchip,pins =
1116                                         <4 RK_PB4 2 &pcfg_pull_none>;
1117                         };
1118                 };
1119
1120                 i2c0 {
1121                         i2c0_xfer: i2c0-xfer {
1122                                 rockchip,pins =
1123                                         <1 RK_PD0 2 &pcfg_pull_none_smt>,
1124                                         <1 RK_PD1 2 &pcfg_pull_none_smt>;
1125                         };
1126                 };
1127
1128                 i2c1 {
1129                         i2c1_xfer: i2c1-xfer {
1130                                 rockchip,pins =
1131                                         <0 RK_PB3 1 &pcfg_pull_none_smt>,
1132                                         <0 RK_PB4 1 &pcfg_pull_none_smt>;
1133                         };
1134                 };
1135
1136                 i2c2 {
1137                         i2c2_xfer: i2c2-xfer {
1138                                 rockchip,pins =
1139                                         <2 RK_PA2 3 &pcfg_pull_none_smt>,
1140                                         <2 RK_PA3 3 &pcfg_pull_none_smt>;
1141                         };
1142                 };
1143
1144                 i2c3-m0 {
1145                         i2c3m0_xfer: i2c3m0-xfer {
1146                                 rockchip,pins =
1147                                         <0 RK_PB7 2 &pcfg_pull_none_smt>,
1148                                         <0 RK_PC0 2 &pcfg_pull_none_smt>;
1149                         };
1150                 };
1151
1152                 i2c3-m1 {
1153                         i2c3m1_xfer: i2c3m1-xfer {
1154                                 rockchip,pins =
1155                                         <3 RK_PB4 2 &pcfg_pull_none_smt>,
1156                                         <3 RK_PB5 2 &pcfg_pull_none_smt>;
1157                         };
1158                 };
1159
1160                 i2c3-m2 {
1161                         i2c3m2_xfer: i2c3m2-xfer {
1162                                 rockchip,pins =
1163                                         <2 RK_PA1 3 &pcfg_pull_none_smt>,
1164                                         <2 RK_PA0 3 &pcfg_pull_none_smt>;
1165                         };
1166                 };
1167
1168                 i2s_2ch_0 {
1169                         i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1170                                 rockchip,pins =
1171                                         <4 RK_PB4 1 &pcfg_pull_none>;
1172                         };
1173
1174                         i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1175                                 rockchip,pins =
1176                                         <4 RK_PB5 1 &pcfg_pull_none>;
1177                         };
1178
1179                         i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1180                                 rockchip,pins =
1181                                         <4 RK_PB6 1 &pcfg_pull_none>;
1182                         };
1183
1184                         i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1185                                 rockchip,pins =
1186                                         <4 RK_PB7 1 &pcfg_pull_none>;
1187                         };
1188
1189                         i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1190                                 rockchip,pins =
1191                                         <4 RK_PC0 1 &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 i2s_8ch_0 {
1196                         i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1197                                 rockchip,pins =
1198                                         <2 RK_PA4 1 &pcfg_pull_none>;
1199                         };
1200
1201                         i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1202                                 rockchip,pins =
1203                                         <2 RK_PA5 1 &pcfg_pull_none>;
1204                         };
1205
1206                         i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1207                                 rockchip,pins =
1208                                         <2 RK_PA6 1 &pcfg_pull_none>;
1209                         };
1210
1211                         i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1212                                 rockchip,pins =
1213                                         <2 RK_PA7 1 &pcfg_pull_none>;
1214                         };
1215
1216                         i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1217                                 rockchip,pins =
1218                                         <2 RK_PB0 1 &pcfg_pull_none>;
1219                         };
1220
1221                         i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1222                                 rockchip,pins =
1223                                         <2 RK_PB1 1 &pcfg_pull_none>;
1224                         };
1225
1226                         i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1227                                 rockchip,pins =
1228                                         <2 RK_PB2 1 &pcfg_pull_none>;
1229                         };
1230
1231                         i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1232                                 rockchip,pins =
1233                                         <2 RK_PB3 1 &pcfg_pull_none>;
1234                         };
1235
1236                         i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1237                                 rockchip,pins =
1238                                         <2 RK_PB4 1 &pcfg_pull_none>;
1239                         };
1240
1241                         i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1242                                 rockchip,pins =
1243                                         <2 RK_PB5 1 &pcfg_pull_none>;
1244                         };
1245
1246                         i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1247                                 rockchip,pins =
1248                                         <2 RK_PB6 1 &pcfg_pull_none>;
1249                         };
1250
1251                         i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1252                                 rockchip,pins =
1253                                         <2 RK_PB7 1 &pcfg_pull_none>;
1254                         };
1255
1256                         i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1257                                 rockchip,pins =
1258                                         <2 RK_PC0 1 &pcfg_pull_none>;
1259                         };
1260                 };
1261
1262                 i2s_8ch_1_m0 {
1263                         i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1264                                 rockchip,pins =
1265                                         <1 RK_PA2 2 &pcfg_pull_none>;
1266                         };
1267
1268                         i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1269                                 rockchip,pins =
1270                                         <1 RK_PA3 2 &pcfg_pull_none>;
1271                         };
1272
1273                         i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1274                                 rockchip,pins =
1275                                         <1 RK_PA4 2 &pcfg_pull_none>;
1276                         };
1277
1278                         i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1279                                 rockchip,pins =
1280                                         <1 RK_PA5 2 &pcfg_pull_none>;
1281                         };
1282
1283                         i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1284                                 rockchip,pins =
1285                                         <1 RK_PA6 2 &pcfg_pull_none>;
1286                         };
1287
1288                         i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1289                                 rockchip,pins =
1290                                         <1 RK_PA7 2 &pcfg_pull_none>;
1291                         };
1292
1293                         i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1294                                 rockchip,pins =
1295                                         <1 RK_PB0 2 &pcfg_pull_none>;
1296                         };
1297
1298                         i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1299                                 rockchip,pins =
1300                                         <1 RK_PB1 2 &pcfg_pull_none>;
1301                         };
1302
1303                         i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1304                                 rockchip,pins =
1305                                         <1 RK_PB2 2 &pcfg_pull_none>;
1306                         };
1307
1308                         i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1309                                 rockchip,pins =
1310                                         <1 RK_PB3 2 &pcfg_pull_none>;
1311                         };
1312                 };
1313
1314                 i2s_8ch_1_m1 {
1315                         i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1316                                 rockchip,pins =
1317                                         <1 RK_PB4 2 &pcfg_pull_none>;
1318                         };
1319
1320                         i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1321                                 rockchip,pins =
1322                                         <1 RK_PB5 2 &pcfg_pull_none>;
1323                         };
1324
1325                         i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1326                                 rockchip,pins =
1327                                         <1 RK_PB6 2 &pcfg_pull_none>;
1328                         };
1329
1330                         i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1331                                 rockchip,pins =
1332                                         <1 RK_PB7 2 &pcfg_pull_none>;
1333                         };
1334
1335                         i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1336                                 rockchip,pins =
1337                                         <1 RK_PC0 2 &pcfg_pull_none>;
1338                         };
1339
1340                         i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1341                                 rockchip,pins =
1342                                         <1 RK_PC1 2 &pcfg_pull_none>;
1343                         };
1344
1345                         i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1346                                 rockchip,pins =
1347                                         <1 RK_PC2 2 &pcfg_pull_none>;
1348                         };
1349
1350                         i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1351                                 rockchip,pins =
1352                                         <1 RK_PC3 2 &pcfg_pull_none>;
1353                         };
1354
1355                         i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1356                                 rockchip,pins =
1357                                         <1 RK_PC4 2 &pcfg_pull_none>;
1358                         };
1359
1360                         i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1361                                 rockchip,pins =
1362                                         <1 RK_PC5 2 &pcfg_pull_none>;
1363                         };
1364                 };
1365
1366                 pdm_m0 {
1367                         pdm_m0_clk: pdm-m0-clk {
1368                                 rockchip,pins =
1369                                         <1 RK_PA4 3 &pcfg_pull_none>;
1370                         };
1371
1372                         pdm_m0_sdi0: pdm-m0-sdi0 {
1373                                 rockchip,pins =
1374                                         <1 RK_PB3 3 &pcfg_pull_none>;
1375                         };
1376
1377                         pdm_m0_sdi1: pdm-m0-sdi1 {
1378                                 rockchip,pins =
1379                                         <1 RK_PB2 3 &pcfg_pull_none>;
1380                         };
1381
1382                         pdm_m0_sdi2: pdm-m0-sdi2 {
1383                                 rockchip,pins =
1384                                         <1 RK_PB1 3 &pcfg_pull_none>;
1385                         };
1386
1387                         pdm_m0_sdi3: pdm-m0-sdi3 {
1388                                 rockchip,pins =
1389                                         <1 RK_PB0 3 &pcfg_pull_none>;
1390                         };
1391                 };
1392
1393                 pdm_m1 {
1394                         pdm_m1_clk: pdm-m1-clk {
1395                                 rockchip,pins =
1396                                         <1 RK_PB6 4 &pcfg_pull_none>;
1397                         };
1398
1399                         pdm_m1_sdi0: pdm-m1-sdi0 {
1400                                 rockchip,pins =
1401                                         <1 RK_PC5 4 &pcfg_pull_none>;
1402                         };
1403
1404                         pdm_m1_sdi1: pdm-m1-sdi1 {
1405                                 rockchip,pins =
1406                                         <1 RK_PC4 4 &pcfg_pull_none>;
1407                         };
1408
1409                         pdm_m1_sdi2: pdm-m1-sdi2 {
1410                                 rockchip,pins =
1411                                         <1 RK_PC3 4 &pcfg_pull_none>;
1412                         };
1413
1414                         pdm_m1_sdi3: pdm-m1-sdi3 {
1415                                 rockchip,pins =
1416                                         <1 RK_PC2 4 &pcfg_pull_none>;
1417                         };
1418                 };
1419
1420                 pdm_m2 {
1421                         pdm_m2_clkm: pdm-m2-clkm {
1422                                 rockchip,pins =
1423                                         <2 RK_PA4 3 &pcfg_pull_none>;
1424                         };
1425
1426                         pdm_m2_clk: pdm-m2-clk {
1427                                 rockchip,pins =
1428                                         <2 RK_PA6 2 &pcfg_pull_none>;
1429                         };
1430
1431                         pdm_m2_sdi0: pdm-m2-sdi0 {
1432                                 rockchip,pins =
1433                                         <2 RK_PB5 2 &pcfg_pull_none>;
1434                         };
1435
1436                         pdm_m2_sdi1: pdm-m2-sdi1 {
1437                                 rockchip,pins =
1438                                         <2 RK_PB6 2 &pcfg_pull_none>;
1439                         };
1440
1441                         pdm_m2_sdi2: pdm-m2-sdi2 {
1442                                 rockchip,pins =
1443                                         <2 RK_PB7 2 &pcfg_pull_none>;
1444                         };
1445
1446                         pdm_m2_sdi3: pdm-m2-sdi3 {
1447                                 rockchip,pins =
1448                                         <2 RK_PC0 2 &pcfg_pull_none>;
1449                         };
1450                 };
1451
1452                 pwm0 {
1453                         pwm0_pin: pwm0-pin {
1454                                 rockchip,pins =
1455                                         <0 RK_PB5 1 &pcfg_pull_none>;
1456                         };
1457
1458                         pwm0_pin_pull_down: pwm0-pin-pull-down {
1459                                 rockchip,pins =
1460                                         <0 RK_PB5 1 &pcfg_pull_down>;
1461                         };
1462                 };
1463
1464                 pwm1 {
1465                         pwm1_pin: pwm1-pin {
1466                                 rockchip,pins =
1467                                         <0 RK_PB6 1 &pcfg_pull_none>;
1468                         };
1469
1470                         pwm1_pin_pull_down: pwm1-pin-pull-down {
1471                                 rockchip,pins =
1472                                         <0 RK_PB6 1 &pcfg_pull_down>;
1473                         };
1474                 };
1475
1476                 pwm2 {
1477                         pwm2_pin: pwm2-pin {
1478                                 rockchip,pins =
1479                                         <0 RK_PB7 1 &pcfg_pull_none>;
1480                         };
1481
1482                         pwm2_pin_pull_down: pwm2-pin-pull-down {
1483                                 rockchip,pins =
1484                                         <0 RK_PB7 1 &pcfg_pull_down>;
1485                         };
1486                 };
1487
1488                 pwm3 {
1489                         pwm3_pin: pwm3-pin {
1490                                 rockchip,pins =
1491                                         <0 RK_PC0 1 &pcfg_pull_none>;
1492                         };
1493
1494                         pwm3_pin_pull_down: pwm3-pin-pull-down {
1495                                 rockchip,pins =
1496                                         <0 RK_PC0 1 &pcfg_pull_down>;
1497                         };
1498                 };
1499
1500                 pwm4 {
1501                         pwm4_pin: pwm4-pin {
1502                                 rockchip,pins =
1503                                         <0 RK_PA1 2 &pcfg_pull_none>;
1504                         };
1505
1506                         pwm4_pin_pull_down: pwm4-pin-pull-down {
1507                                 rockchip,pins =
1508                                         <0 RK_PA1 2 &pcfg_pull_down>;
1509                         };
1510                 };
1511
1512                 pwm5 {
1513                         pwm5_pin: pwm5-pin {
1514                                 rockchip,pins =
1515                                         <0 RK_PC1 2 &pcfg_pull_none>;
1516                         };
1517
1518                         pwm5_pin_pull_down: pwm5-pin-pull-down {
1519                                 rockchip,pins =
1520                                         <0 RK_PC1 2 &pcfg_pull_down>;
1521                         };
1522                 };
1523
1524                 pwm6 {
1525                         pwm6_pin: pwm6-pin {
1526                                 rockchip,pins =
1527                                         <0 RK_PC2 2 &pcfg_pull_none>;
1528                         };
1529
1530                         pwm6_pin_pull_down: pwm6-pin-pull-down {
1531                                 rockchip,pins =
1532                                         <0 RK_PC2 2 &pcfg_pull_down>;
1533                         };
1534                 };
1535
1536                 pwm7 {
1537                         pwm7_pin: pwm7-pin {
1538                                 rockchip,pins =
1539                                         <2 RK_PB0 2 &pcfg_pull_none>;
1540                         };
1541
1542                         pwm7_pin_pull_down: pwm7-pin-pull-down {
1543                                 rockchip,pins =
1544                                         <2 RK_PB0 2 &pcfg_pull_down>;
1545                         };
1546                 };
1547
1548                 pwm8 {
1549                         pwm8_pin: pwm8-pin {
1550                                 rockchip,pins =
1551                                         <2 RK_PB2 2 &pcfg_pull_none>;
1552                         };
1553
1554                         pwm8_pin_pull_down: pwm8-pin-pull-down {
1555                                 rockchip,pins =
1556                                         <2 RK_PB2 2 &pcfg_pull_down>;
1557                         };
1558                 };
1559
1560                 pwm9 {
1561                         pwm9_pin: pwm9-pin {
1562                                 rockchip,pins =
1563                                         <2 RK_PB3 2 &pcfg_pull_none>;
1564                         };
1565
1566                         pwm9_pin_pull_down: pwm9-pin-pull-down {
1567                                 rockchip,pins =
1568                                         <2 RK_PB3 2 &pcfg_pull_down>;
1569                         };
1570                 };
1571
1572                 pwm10 {
1573                         pwm10_pin: pwm10-pin {
1574                                 rockchip,pins =
1575                                         <2 RK_PB4 2 &pcfg_pull_none>;
1576                         };
1577
1578                         pwm10_pin_pull_down: pwm10-pin-pull-down {
1579                                 rockchip,pins =
1580                                         <2 RK_PB4 2 &pcfg_pull_down>;
1581                         };
1582                 };
1583
1584                 pwm11 {
1585                         pwm11_pin: pwm11-pin {
1586                                 rockchip,pins =
1587                                         <2 RK_PC0 4 &pcfg_pull_none>;
1588                         };
1589
1590                         pwm11_pin_pull_down: pwm11-pin-pull-down {
1591                                 rockchip,pins =
1592                                         <2 RK_PC0 4 &pcfg_pull_down>;
1593                         };
1594                 };
1595
1596                 rtc {
1597                         rtc_32k: rtc-32k {
1598                                 rockchip,pins =
1599                                         <0 RK_PC3 1 &pcfg_pull_none>;
1600                         };
1601                 };
1602
1603                 sdmmc {
1604                         sdmmc_clk: sdmmc-clk {
1605                                 rockchip,pins =
1606                                         <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1607                         };
1608
1609                         sdmmc_cmd: sdmmc-cmd {
1610                                 rockchip,pins =
1611                                         <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1612                         };
1613
1614                         sdmmc_det: sdmmc-det {
1615                                 rockchip,pins =
1616                                         <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1617                         };
1618
1619                         sdmmc_pwren: sdmmc-pwren {
1620                                 rockchip,pins =
1621                                         <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1622                         };
1623
1624                         sdmmc_bus1: sdmmc-bus1 {
1625                                 rockchip,pins =
1626                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1627                         };
1628
1629                         sdmmc_bus4: sdmmc-bus4 {
1630                                 rockchip,pins =
1631                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1632                                         <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1633                                         <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1634                                         <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1635                         };
1636                 };
1637
1638                 sdio {
1639                         sdio_clk: sdio-clk {
1640                                 rockchip,pins =
1641                                         <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1642                         };
1643
1644                         sdio_cmd: sdio-cmd {
1645                                 rockchip,pins =
1646                                         <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1647                         };
1648
1649                         sdio_pwren: sdio-pwren {
1650                                 rockchip,pins =
1651                                         <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1652                         };
1653
1654                         sdio_wrpt: sdio-wrpt {
1655                                 rockchip,pins =
1656                                         <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1657                         };
1658
1659                         sdio_intn: sdio-intn {
1660                                 rockchip,pins =
1661                                         <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1662                         };
1663
1664                         sdio_bus1: sdio-bus1 {
1665                                 rockchip,pins =
1666                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1667                         };
1668
1669                         sdio_bus4: sdio-bus4 {
1670                                 rockchip,pins =
1671                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1672                                         <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1673                                         <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1674                                         <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1675                         };
1676                 };
1677
1678                 spdif_in {
1679                         spdif_in: spdif-in {
1680                                 rockchip,pins =
1681                                         <0 RK_PC2 1 &pcfg_pull_none>;
1682                         };
1683                 };
1684
1685                 spdif_out {
1686                         spdif_out: spdif-out {
1687                                 rockchip,pins =
1688                                         <0 RK_PC1 1 &pcfg_pull_none>;
1689                         };
1690                 };
1691
1692                 spi0 {
1693                         spi0_clk: spi0-clk {
1694                                 rockchip,pins =
1695                                         <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1696                         };
1697
1698                         spi0_csn0: spi0-csn0 {
1699                                 rockchip,pins =
1700                                         <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1701                         };
1702
1703                         spi0_miso: spi0-miso {
1704                                 rockchip,pins =
1705                                         <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1706                         };
1707
1708                         spi0_mosi: spi0-mosi {
1709                                 rockchip,pins =
1710                                         <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1711                         };
1712                 };
1713
1714                 spi1 {
1715                         spi1_clk: spi1-clk {
1716                                 rockchip,pins =
1717                                         <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1718                         };
1719
1720                         spi1_csn0: spi1-csn0 {
1721                                 rockchip,pins =
1722                                         <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1723                         };
1724
1725                         spi1_miso: spi1-miso {
1726                                 rockchip,pins =
1727                                         <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1728                         };
1729
1730                         spi1_mosi: spi1-mosi {
1731                                 rockchip,pins =
1732                                         <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1733                         };
1734                 };
1735
1736                 spi1-m1 {
1737                         spi1m1_miso: spi1m1-miso {
1738                                 rockchip,pins =
1739                                         <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1740                         };
1741
1742                         spi1m1_mosi: spi1m1-mosi {
1743                                 rockchip,pins =
1744                                         <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1745                         };
1746
1747                         spi1m1_clk: spi1m1-clk {
1748                                 rockchip,pins =
1749                                         <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1750                         };
1751
1752                         spi1m1_csn0: spi1m1-csn0 {
1753                                 rockchip,pins =
1754                                         <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1755                         };
1756                 };
1757
1758                 spi2 {
1759                         spi2_clk: spi2-clk {
1760                                 rockchip,pins =
1761                                         <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1762                         };
1763
1764                         spi2_csn0: spi2-csn0 {
1765                                 rockchip,pins =
1766                                         <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1767                         };
1768
1769                         spi2_miso: spi2-miso {
1770                                 rockchip,pins =
1771                                         <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1772                         };
1773
1774                         spi2_mosi: spi2-mosi {
1775                                 rockchip,pins =
1776                                         <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1777                         };
1778                 };
1779
1780                 tsadc {
1781                         tsadc_otp_pin: tsadc-otp-pin {
1782                                 rockchip,pins =
1783                                         <0 RK_PB2 0 &pcfg_pull_none>;
1784                         };
1785
1786                         tsadc_otp_out: tsadc-otp-out {
1787                                 rockchip,pins =
1788                                         <0 RK_PB2 1 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 uart0 {
1793                         uart0_xfer: uart0-xfer {
1794                                 rockchip,pins =
1795                                         <2 RK_PA1 1 &pcfg_pull_up>,
1796                                         <2 RK_PA0 1 &pcfg_pull_up>;
1797                         };
1798
1799                         uart0_cts: uart0-cts {
1800                                 rockchip,pins =
1801                                         <2 RK_PA2 1 &pcfg_pull_none>;
1802                         };
1803
1804                         uart0_rts: uart0-rts {
1805                                 rockchip,pins =
1806                                         <2 RK_PA3 1 &pcfg_pull_none>;
1807                         };
1808
1809                         uart0_rts_pin: uart0-rts-pin {
1810                                 rockchip,pins =
1811                                         <2 RK_PA3 0 &pcfg_pull_none>;
1812                         };
1813                 };
1814
1815                 uart1 {
1816                         uart1_xfer: uart1-xfer {
1817                                 rockchip,pins =
1818                                         <1 RK_PD1 1 &pcfg_pull_up>,
1819                                         <1 RK_PD0 1 &pcfg_pull_up>;
1820                         };
1821
1822                         uart1_cts: uart1-cts {
1823                                 rockchip,pins =
1824                                         <1 RK_PC6 1 &pcfg_pull_none>;
1825                         };
1826
1827                         uart1_rts: uart1-rts {
1828                                 rockchip,pins =
1829                                         <1 RK_PC7 1 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 uart2-m0 {
1834                         uart2m0_xfer: uart2m0-xfer {
1835                                 rockchip,pins =
1836                                         <1 RK_PC7 2 &pcfg_pull_up>,
1837                                         <1 RK_PC6 2 &pcfg_pull_up>;
1838                         };
1839                 };
1840
1841                 uart2-m1 {
1842                         uart2m1_xfer: uart2m1-xfer {
1843                                 rockchip,pins =
1844                                         <4 RK_PD3 2 &pcfg_pull_up>,
1845                                         <4 RK_PD2 2 &pcfg_pull_up>;
1846                         };
1847                 };
1848
1849                 uart3 {
1850                         uart3_xfer: uart3-xfer {
1851                                 rockchip,pins =
1852                                         <3 RK_PB5 4 &pcfg_pull_up>,
1853                                         <3 RK_PB4 4 &pcfg_pull_up>;
1854                         };
1855                 };
1856
1857                 uart3-m1 {
1858                         uart3m1_xfer: uart3m1-xfer {
1859                                 rockchip,pins =
1860                                         <0 RK_PC2 3 &pcfg_pull_up>,
1861                                         <0 RK_PC1 3 &pcfg_pull_up>;
1862                         };
1863                 };
1864
1865                 uart4 {
1866                         uart4_xfer: uart4-xfer {
1867                                 rockchip,pins =
1868                                         <4 RK_PB1 1 &pcfg_pull_up>,
1869                                         <4 RK_PB0 1 &pcfg_pull_up>;
1870                         };
1871
1872                         uart4_cts: uart4-cts {
1873                                 rockchip,pins =
1874                                         <4 RK_PA6 1 &pcfg_pull_none>;
1875                         };
1876
1877                         uart4_rts: uart4-rts {
1878                                 rockchip,pins =
1879                                         <4 RK_PA7 1 &pcfg_pull_none>;
1880                         };
1881
1882                         uart4_rts_pin: uart4-rts-pin {
1883                                 rockchip,pins =
1884                                         <4 RK_PA7 0 &pcfg_pull_none>;
1885                         };
1886                 };
1887         };
1888 };