1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3308";
18 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a35";
50 enable-method = "psci";
51 clocks = <&cru ARMCLK>;
53 dynamic-power-coefficient = <90>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 cpu-idle-states = <&CPU_SLEEP>;
56 next-level-cache = <&l2>;
61 compatible = "arm,cortex-a35";
63 enable-method = "psci";
64 operating-points-v2 = <&cpu0_opp_table>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 next-level-cache = <&l2>;
71 compatible = "arm,cortex-a35";
73 enable-method = "psci";
74 operating-points-v2 = <&cpu0_opp_table>;
75 cpu-idle-states = <&CPU_SLEEP>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a35";
83 enable-method = "psci";
84 operating-points-v2 = <&cpu0_opp_table>;
85 cpu-idle-states = <&CPU_SLEEP>;
86 next-level-cache = <&l2>;
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
103 compatible = "cache";
109 cpu0_opp_table: opp-table-0 {
110 compatible = "operating-points-v2";
114 opp-hz = /bits/ 64 <408000000>;
115 opp-microvolt = <950000 950000 1340000>;
116 clock-latency-ns = <40000>;
120 opp-hz = /bits/ 64 <600000000>;
121 opp-microvolt = <950000 950000 1340000>;
122 clock-latency-ns = <40000>;
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1025000 1025000 1340000>;
127 clock-latency-ns = <40000>;
130 opp-hz = /bits/ 64 <1008000000>;
131 opp-microvolt = <1125000 1125000 1340000>;
132 clock-latency-ns = <40000>;
137 compatible = "arm,cortex-a35-pmu";
138 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
145 mac_clkin: external-mac-clock {
146 compatible = "fixed-clock";
147 clock-frequency = <50000000>;
148 clock-output-names = "mac_clkin";
153 compatible = "arm,psci-1.0";
158 compatible = "arm,armv8-timer";
159 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
160 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
162 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
166 compatible = "fixed-clock";
168 clock-frequency = <24000000>;
169 clock-output-names = "xin24m";
173 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
174 reg = <0x0 0xff000000 0x0 0x08000>;
177 compatible = "syscon-reboot-mode";
179 mode-bootloader = <BOOT_BL_DOWNLOAD>;
180 mode-loader = <BOOT_BL_DOWNLOAD>;
181 mode-normal = <BOOT_NORMAL>;
182 mode-recovery = <BOOT_RECOVERY>;
183 mode-fastboot = <BOOT_FASTBOOT>;
187 usb2phy_grf: syscon@ff008000 {
188 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
189 reg = <0x0 0xff008000 0x0 0x4000>;
190 #address-cells = <1>;
194 compatible = "rockchip,rk3308-usb2phy";
196 assigned-clocks = <&cru USB480M>;
197 assigned-clock-parents = <&u2phy>;
198 clocks = <&cru SCLK_USBPHY_REF>;
199 clock-names = "phyclk";
200 clock-output-names = "usb480m_phy";
204 u2phy_otg: otg-port {
205 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-names = "otg-bvalid", "otg-id",
214 u2phy_host: host-port {
215 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
216 interrupt-names = "linestate";
223 detect_grf: syscon@ff00b000 {
224 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
225 reg = <0x0 0xff00b000 0x0 0x1000>;
226 #address-cells = <1>;
230 core_grf: syscon@ff00c000 {
231 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
232 reg = <0x0 0xff00c000 0x0 0x1000>;
233 #address-cells = <1>;
238 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
239 reg = <0x0 0xff040000 0x0 0x1000>;
240 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
241 clock-names = "i2c", "pclk";
242 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&i2c0_xfer>;
245 #address-cells = <1>;
251 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
252 reg = <0x0 0xff050000 0x0 0x1000>;
253 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
254 clock-names = "i2c", "pclk";
255 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&i2c1_xfer>;
258 #address-cells = <1>;
264 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
265 reg = <0x0 0xff060000 0x0 0x1000>;
266 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
267 clock-names = "i2c", "pclk";
268 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&i2c2_xfer>;
271 #address-cells = <1>;
277 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
278 reg = <0x0 0xff070000 0x0 0x1000>;
279 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
280 clock-names = "i2c", "pclk";
281 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&i2c3m0_xfer>;
284 #address-cells = <1>;
289 wdt: watchdog@ff080000 {
290 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
291 reg = <0x0 0xff080000 0x0 0x100>;
292 clocks = <&cru PCLK_WDT>;
293 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
297 uart0: serial@ff0a0000 {
298 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
299 reg = <0x0 0xff0a0000 0x0 0x100>;
300 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
302 clock-names = "baudclk", "apb_pclk";
305 pinctrl-names = "default";
306 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
310 uart1: serial@ff0b0000 {
311 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
312 reg = <0x0 0xff0b0000 0x0 0x100>;
313 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
315 clock-names = "baudclk", "apb_pclk";
318 pinctrl-names = "default";
319 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
323 uart2: serial@ff0c0000 {
324 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
325 reg = <0x0 0xff0c0000 0x0 0x100>;
326 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
328 clock-names = "baudclk", "apb_pclk";
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart2m0_xfer>;
336 uart3: serial@ff0d0000 {
337 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
338 reg = <0x0 0xff0d0000 0x0 0x100>;
339 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
341 clock-names = "baudclk", "apb_pclk";
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart3_xfer>;
349 uart4: serial@ff0e0000 {
350 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
351 reg = <0x0 0xff0e0000 0x0 0x100>;
352 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
354 clock-names = "baudclk", "apb_pclk";
357 pinctrl-names = "default";
358 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
363 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
364 reg = <0x0 0xff120000 0x0 0x1000>;
365 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>;
368 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
369 clock-names = "spiclk", "apb_pclk";
370 dmas = <&dmac0 0>, <&dmac0 1>;
371 dma-names = "tx", "rx";
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
378 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
379 reg = <0x0 0xff130000 0x0 0x1000>;
380 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
381 #address-cells = <1>;
383 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
384 clock-names = "spiclk", "apb_pclk";
385 dmas = <&dmac0 2>, <&dmac0 3>;
386 dma-names = "tx", "rx";
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
393 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
394 reg = <0x0 0xff140000 0x0 0x1000>;
395 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
398 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
399 clock-names = "spiclk", "apb_pclk";
400 dmas = <&dmac1 16>, <&dmac1 17>;
401 dma-names = "tx", "rx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
408 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
409 reg = <0x0 0xff160000 0x0 0x10>;
410 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
411 clock-names = "pwm", "pclk";
412 pinctrl-names = "default";
413 pinctrl-0 = <&pwm8_pin>;
419 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
420 reg = <0x0 0xff160010 0x0 0x10>;
421 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
422 clock-names = "pwm", "pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm9_pin>;
429 pwm10: pwm@ff160020 {
430 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
431 reg = <0x0 0xff160020 0x0 0x10>;
432 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
433 clock-names = "pwm", "pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&pwm10_pin>;
440 pwm11: pwm@ff160030 {
441 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
442 reg = <0x0 0xff160030 0x0 0x10>;
443 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
444 clock-names = "pwm", "pclk";
445 pinctrl-names = "default";
446 pinctrl-0 = <&pwm11_pin>;
452 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
453 reg = <0x0 0xff170000 0x0 0x10>;
454 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
455 clock-names = "pwm", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&pwm4_pin>;
463 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
464 reg = <0x0 0xff170010 0x0 0x10>;
465 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
466 clock-names = "pwm", "pclk";
467 pinctrl-names = "default";
468 pinctrl-0 = <&pwm5_pin>;
474 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
475 reg = <0x0 0xff170020 0x0 0x10>;
476 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
477 clock-names = "pwm", "pclk";
478 pinctrl-names = "default";
479 pinctrl-0 = <&pwm6_pin>;
485 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
486 reg = <0x0 0xff170030 0x0 0x10>;
487 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
488 clock-names = "pwm", "pclk";
489 pinctrl-names = "default";
490 pinctrl-0 = <&pwm7_pin>;
496 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
497 reg = <0x0 0xff180000 0x0 0x10>;
498 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
499 clock-names = "pwm", "pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&pwm0_pin>;
507 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
508 reg = <0x0 0xff180010 0x0 0x10>;
509 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
510 clock-names = "pwm", "pclk";
511 pinctrl-names = "default";
512 pinctrl-0 = <&pwm1_pin>;
518 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
519 reg = <0x0 0xff180020 0x0 0x10>;
520 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
521 clock-names = "pwm", "pclk";
522 pinctrl-names = "default";
523 pinctrl-0 = <&pwm2_pin>;
529 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
530 reg = <0x0 0xff180030 0x0 0x10>;
531 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
532 clock-names = "pwm", "pclk";
533 pinctrl-names = "default";
534 pinctrl-0 = <&pwm3_pin>;
539 rktimer: rktimer@ff1a0000 {
540 compatible = "rockchip,rk3288-timer";
541 reg = <0x0 0xff1a0000 0x0 0x20>;
542 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
544 clock-names = "pclk", "timer";
547 saradc: saradc@ff1e0000 {
548 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
549 reg = <0x0 0xff1e0000 0x0 0x100>;
550 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
552 clock-names = "saradc", "apb_pclk";
553 #io-channel-cells = <1>;
554 resets = <&cru SRST_SARADC_P>;
555 reset-names = "saradc-apb";
559 dmac0: dma-controller@ff2c0000 {
560 compatible = "arm,pl330", "arm,primecell";
561 reg = <0x0 0xff2c0000 0x0 0x4000>;
562 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
564 arm,pl330-periph-burst;
565 clocks = <&cru ACLK_DMAC0>;
566 clock-names = "apb_pclk";
570 dmac1: dma-controller@ff2d0000 {
571 compatible = "arm,pl330", "arm,primecell";
572 reg = <0x0 0xff2d0000 0x0 0x4000>;
573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
575 arm,pl330-periph-burst;
576 clocks = <&cru ACLK_DMAC1>;
577 clock-names = "apb_pclk";
581 i2s_2ch_0: i2s@ff350000 {
582 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
583 reg = <0x0 0xff350000 0x0 0x1000>;
584 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
586 clock-names = "i2s_clk", "i2s_hclk";
587 dmas = <&dmac1 8>, <&dmac1 9>;
588 dma-names = "tx", "rx";
589 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
590 reset-names = "reset-m", "reset-h";
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2s_2ch_0_sclk
599 i2s_2ch_1: i2s@ff360000 {
600 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
601 reg = <0x0 0xff360000 0x0 0x1000>;
602 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
604 clock-names = "i2s_clk", "i2s_hclk";
607 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
608 reset-names = "reset-m", "reset-h";
612 spdif_tx: spdif-tx@ff3a0000 {
613 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
614 reg = <0x0 0xff3a0000 0x0 0x1000>;
615 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
617 clock-names = "mclk", "hclk";
620 pinctrl-names = "default";
621 pinctrl-0 = <&spdif_out>;
625 usb20_otg: usb@ff400000 {
626 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
628 reg = <0x0 0xff400000 0x0 0x40000>;
629 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru HCLK_OTG>;
633 g-np-tx-fifo-size = <16>;
634 g-rx-fifo-size = <280>;
635 g-tx-fifo-size = <256 128 128 64 32 16>;
637 phy-names = "usb2-phy";
641 usb_host_ehci: usb@ff440000 {
642 compatible = "generic-ehci";
643 reg = <0x0 0xff440000 0x0 0x10000>;
644 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
646 phys = <&u2phy_host>;
651 usb_host_ohci: usb@ff450000 {
652 compatible = "generic-ohci";
653 reg = <0x0 0xff450000 0x0 0x10000>;
654 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
656 phys = <&u2phy_host>;
661 sdmmc: mmc@ff480000 {
662 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
663 reg = <0x0 0xff480000 0x0 0x4000>;
664 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
667 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
668 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
669 fifo-depth = <0x100>;
670 max-frequency = <150000000>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
677 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
678 reg = <0x0 0xff490000 0x0 0x4000>;
679 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
682 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
683 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
684 fifo-depth = <0x100>;
685 max-frequency = <150000000>;
690 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
691 reg = <0x0 0xff4a0000 0x0 0x4000>;
692 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
695 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
696 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
697 fifo-depth = <0x100>;
698 max-frequency = <150000000>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
704 nfc: nand-controller@ff4b0000 {
705 compatible = "rockchip,rk3308-nfc",
706 "rockchip,rv1108-nfc";
707 reg = <0x0 0xff4b0000 0x0 0x4000>;
708 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
710 clock-names = "ahb", "nfc";
711 assigned-clocks = <&cru SCLK_NANDC>;
712 assigned-clock-rates = <150000000>;
713 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
714 &flash_rdn &flash_rdy &flash_wrn>;
715 pinctrl-names = "default";
719 gmac: ethernet@ff4e0000 {
720 compatible = "rockchip,rk3308-gmac";
721 reg = <0x0 0xff4e0000 0x0 0x10000>;
722 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "macirq";
724 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
725 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
726 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
727 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
728 clock-names = "stmmaceth", "mac_clk_rx",
729 "mac_clk_tx", "clk_mac_ref",
730 "clk_mac_refout", "aclk_mac",
731 "pclk_mac", "clk_mac_speed";
733 pinctrl-names = "default";
734 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
735 resets = <&cru SRST_MAC_A>;
736 reset-names = "stmmaceth";
737 rockchip,grf = <&grf>;
742 compatible = "rockchip,sfc";
743 reg = <0x0 0xff4c0000 0x0 0x4000>;
744 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
746 clock-names = "clk_sfc", "hclk_sfc";
747 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
748 pinctrl-names = "default";
752 cru: clock-controller@ff500000 {
753 compatible = "rockchip,rk3308-cru";
754 reg = <0x0 0xff500000 0x0 0x1000>;
756 clock-names = "xin24m";
757 rockchip,grf = <&grf>;
760 assigned-clocks = <&cru SCLK_RTC32K>;
761 assigned-clock-rates = <32768>;
764 gic: interrupt-controller@ff580000 {
765 compatible = "arm,gic-400";
766 reg = <0x0 0xff581000 0x0 0x1000>,
767 <0x0 0xff582000 0x0 0x2000>,
768 <0x0 0xff584000 0x0 0x2000>,
769 <0x0 0xff586000 0x0 0x2000>;
770 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
771 #interrupt-cells = <3>;
772 interrupt-controller;
773 #address-cells = <0>;
776 sram: sram@fff80000 {
777 compatible = "mmio-sram";
778 reg = <0x0 0xfff80000 0x0 0x40000>;
779 ranges = <0 0x0 0xfff80000 0x40000>;
780 #address-cells = <1>;
783 /* reserved for ddr dvfs and system suspend/resume */
788 /* reserved for vad audio buffer */
789 vad_sram: vad-sram@8000 {
790 reg = <0x8000 0x38000>;
795 compatible = "rockchip,rk3308-pinctrl";
796 rockchip,grf = <&grf>;
797 #address-cells = <2>;
801 gpio0: gpio@ff220000 {
802 compatible = "rockchip,gpio-bank";
803 reg = <0x0 0xff220000 0x0 0x100>;
804 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&cru PCLK_GPIO0>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
812 gpio1: gpio@ff230000 {
813 compatible = "rockchip,gpio-bank";
814 reg = <0x0 0xff230000 0x0 0x100>;
815 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&cru PCLK_GPIO1>;
819 interrupt-controller;
820 #interrupt-cells = <2>;
823 gpio2: gpio@ff240000 {
824 compatible = "rockchip,gpio-bank";
825 reg = <0x0 0xff240000 0x0 0x100>;
826 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&cru PCLK_GPIO2>;
830 interrupt-controller;
831 #interrupt-cells = <2>;
834 gpio3: gpio@ff250000 {
835 compatible = "rockchip,gpio-bank";
836 reg = <0x0 0xff250000 0x0 0x100>;
837 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cru PCLK_GPIO3>;
841 interrupt-controller;
842 #interrupt-cells = <2>;
845 gpio4: gpio@ff260000 {
846 compatible = "rockchip,gpio-bank";
847 reg = <0x0 0xff260000 0x0 0x100>;
848 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cru PCLK_GPIO4>;
852 interrupt-controller;
853 #interrupt-cells = <2>;
856 pcfg_pull_up: pcfg-pull-up {
860 pcfg_pull_down: pcfg-pull-down {
864 pcfg_pull_none: pcfg-pull-none {
868 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
870 drive-strength = <2>;
873 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
875 drive-strength = <2>;
878 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
880 drive-strength = <4>;
883 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
885 drive-strength = <4>;
888 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
890 drive-strength = <4>;
893 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
895 drive-strength = <8>;
898 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
900 drive-strength = <8>;
903 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
905 drive-strength = <12>;
908 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
910 drive-strength = <12>;
913 pcfg_pull_none_smt: pcfg-pull-none-smt {
915 input-schmitt-enable;
918 pcfg_output_high: pcfg-output-high {
922 pcfg_output_low: pcfg-output-low {
926 pcfg_input_high: pcfg-input-high {
931 pcfg_input: pcfg-input {
938 <3 RK_PB1 2 &pcfg_pull_none_8ma>;
943 <3 RK_PB0 2 &pcfg_pull_up_8ma>;
946 emmc_pwren: emmc-pwren {
948 <3 RK_PB3 2 &pcfg_pull_none>;
951 emmc_rstn: emmc-rstn {
953 <3 RK_PB2 2 &pcfg_pull_none>;
956 emmc_bus1: emmc-bus1 {
958 <3 RK_PA0 2 &pcfg_pull_up_8ma>;
961 emmc_bus4: emmc-bus4 {
963 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
964 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
965 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
966 <3 RK_PA3 2 &pcfg_pull_up_8ma>;
969 emmc_bus8: emmc-bus8 {
971 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
972 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
973 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
974 <3 RK_PA3 2 &pcfg_pull_up_8ma>,
975 <3 RK_PA4 2 &pcfg_pull_up_8ma>,
976 <3 RK_PA5 2 &pcfg_pull_up_8ma>,
977 <3 RK_PA6 2 &pcfg_pull_up_8ma>,
978 <3 RK_PA7 2 &pcfg_pull_up_8ma>;
983 flash_csn0: flash-csn0 {
985 <3 RK_PB5 1 &pcfg_pull_none>;
988 flash_rdy: flash-rdy {
990 <3 RK_PB4 1 &pcfg_pull_none>;
993 flash_ale: flash-ale {
995 <3 RK_PB3 1 &pcfg_pull_none>;
998 flash_cle: flash-cle {
1000 <3 RK_PB1 1 &pcfg_pull_none>;
1003 flash_wrn: flash-wrn {
1005 <3 RK_PB0 1 &pcfg_pull_none>;
1008 flash_rdn: flash-rdn {
1010 <3 RK_PB2 1 &pcfg_pull_none>;
1013 flash_bus8: flash-bus8 {
1015 <3 RK_PA0 1 &pcfg_pull_up_12ma>,
1016 <3 RK_PA1 1 &pcfg_pull_up_12ma>,
1017 <3 RK_PA2 1 &pcfg_pull_up_12ma>,
1018 <3 RK_PA3 1 &pcfg_pull_up_12ma>,
1019 <3 RK_PA4 1 &pcfg_pull_up_12ma>,
1020 <3 RK_PA5 1 &pcfg_pull_up_12ma>,
1021 <3 RK_PA6 1 &pcfg_pull_up_12ma>,
1022 <3 RK_PA7 1 &pcfg_pull_up_12ma>;
1027 sfc_bus4: sfc-bus4 {
1029 <3 RK_PA0 3 &pcfg_pull_none>,
1030 <3 RK_PA1 3 &pcfg_pull_none>,
1031 <3 RK_PA2 3 &pcfg_pull_none>,
1032 <3 RK_PA3 3 &pcfg_pull_none>;
1035 sfc_bus2: sfc-bus2 {
1037 <3 RK_PA0 3 &pcfg_pull_none>,
1038 <3 RK_PA1 3 &pcfg_pull_none>;
1043 <3 RK_PA4 3 &pcfg_pull_none>;
1048 <3 RK_PA5 3 &pcfg_pull_none>;
1053 rmii_pins: rmii-pins {
1056 <1 RK_PC1 3 &pcfg_pull_none_12ma>,
1058 <1 RK_PC3 3 &pcfg_pull_none_12ma>,
1060 <1 RK_PC2 3 &pcfg_pull_none_12ma>,
1062 <1 RK_PC4 3 &pcfg_pull_none>,
1064 <1 RK_PC5 3 &pcfg_pull_none>,
1066 <1 RK_PB7 3 &pcfg_pull_none>,
1068 <1 RK_PC0 3 &pcfg_pull_none>,
1070 <1 RK_PB6 3 &pcfg_pull_none>,
1072 <1 RK_PB5 3 &pcfg_pull_none>;
1075 mac_refclk_12ma: mac-refclk-12ma {
1077 <1 RK_PB4 3 &pcfg_pull_none_12ma>;
1080 mac_refclk: mac-refclk {
1082 <1 RK_PB4 3 &pcfg_pull_none>;
1087 rmiim1_pins: rmiim1-pins {
1090 <4 RK_PB7 2 &pcfg_pull_none_12ma>,
1092 <4 RK_PA5 2 &pcfg_pull_none_12ma>,
1094 <4 RK_PA4 2 &pcfg_pull_none_12ma>,
1096 <4 RK_PA2 2 &pcfg_pull_none>,
1098 <4 RK_PA3 2 &pcfg_pull_none>,
1100 <4 RK_PA0 2 &pcfg_pull_none>,
1102 <4 RK_PA1 2 &pcfg_pull_none>,
1104 <4 RK_PB6 2 &pcfg_pull_none>,
1106 <4 RK_PB5 2 &pcfg_pull_none>;
1109 macm1_refclk_12ma: macm1-refclk-12ma {
1111 <4 RK_PB4 2 &pcfg_pull_none_12ma>;
1114 macm1_refclk: macm1-refclk {
1116 <4 RK_PB4 2 &pcfg_pull_none>;
1121 i2c0_xfer: i2c0-xfer {
1123 <1 RK_PD0 2 &pcfg_pull_none_smt>,
1124 <1 RK_PD1 2 &pcfg_pull_none_smt>;
1129 i2c1_xfer: i2c1-xfer {
1131 <0 RK_PB3 1 &pcfg_pull_none_smt>,
1132 <0 RK_PB4 1 &pcfg_pull_none_smt>;
1137 i2c2_xfer: i2c2-xfer {
1139 <2 RK_PA2 3 &pcfg_pull_none_smt>,
1140 <2 RK_PA3 3 &pcfg_pull_none_smt>;
1145 i2c3m0_xfer: i2c3m0-xfer {
1147 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1148 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1153 i2c3m1_xfer: i2c3m1-xfer {
1155 <3 RK_PB4 2 &pcfg_pull_none_smt>,
1156 <3 RK_PB5 2 &pcfg_pull_none_smt>;
1161 i2c3m2_xfer: i2c3m2-xfer {
1163 <2 RK_PA1 3 &pcfg_pull_none_smt>,
1164 <2 RK_PA0 3 &pcfg_pull_none_smt>;
1169 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1171 <4 RK_PB4 1 &pcfg_pull_none>;
1174 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1176 <4 RK_PB5 1 &pcfg_pull_none>;
1179 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1181 <4 RK_PB6 1 &pcfg_pull_none>;
1184 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1186 <4 RK_PB7 1 &pcfg_pull_none>;
1189 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1191 <4 RK_PC0 1 &pcfg_pull_none>;
1196 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1198 <2 RK_PA4 1 &pcfg_pull_none>;
1201 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1203 <2 RK_PA5 1 &pcfg_pull_none>;
1206 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1208 <2 RK_PA6 1 &pcfg_pull_none>;
1211 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1213 <2 RK_PA7 1 &pcfg_pull_none>;
1216 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1218 <2 RK_PB0 1 &pcfg_pull_none>;
1221 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1223 <2 RK_PB1 1 &pcfg_pull_none>;
1226 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1228 <2 RK_PB2 1 &pcfg_pull_none>;
1231 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1233 <2 RK_PB3 1 &pcfg_pull_none>;
1236 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1238 <2 RK_PB4 1 &pcfg_pull_none>;
1241 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1243 <2 RK_PB5 1 &pcfg_pull_none>;
1246 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1248 <2 RK_PB6 1 &pcfg_pull_none>;
1251 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1253 <2 RK_PB7 1 &pcfg_pull_none>;
1256 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1258 <2 RK_PC0 1 &pcfg_pull_none>;
1263 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1265 <1 RK_PA2 2 &pcfg_pull_none>;
1268 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1270 <1 RK_PA3 2 &pcfg_pull_none>;
1273 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1275 <1 RK_PA4 2 &pcfg_pull_none>;
1278 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1280 <1 RK_PA5 2 &pcfg_pull_none>;
1283 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1285 <1 RK_PA6 2 &pcfg_pull_none>;
1288 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1290 <1 RK_PA7 2 &pcfg_pull_none>;
1293 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1295 <1 RK_PB0 2 &pcfg_pull_none>;
1298 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1300 <1 RK_PB1 2 &pcfg_pull_none>;
1303 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1305 <1 RK_PB2 2 &pcfg_pull_none>;
1308 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1310 <1 RK_PB3 2 &pcfg_pull_none>;
1315 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1317 <1 RK_PB4 2 &pcfg_pull_none>;
1320 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1322 <1 RK_PB5 2 &pcfg_pull_none>;
1325 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1327 <1 RK_PB6 2 &pcfg_pull_none>;
1330 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1332 <1 RK_PB7 2 &pcfg_pull_none>;
1335 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1337 <1 RK_PC0 2 &pcfg_pull_none>;
1340 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1342 <1 RK_PC1 2 &pcfg_pull_none>;
1345 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1347 <1 RK_PC2 2 &pcfg_pull_none>;
1350 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1352 <1 RK_PC3 2 &pcfg_pull_none>;
1355 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1357 <1 RK_PC4 2 &pcfg_pull_none>;
1360 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1362 <1 RK_PC5 2 &pcfg_pull_none>;
1367 pdm_m0_clk: pdm-m0-clk {
1369 <1 RK_PA4 3 &pcfg_pull_none>;
1372 pdm_m0_sdi0: pdm-m0-sdi0 {
1374 <1 RK_PB3 3 &pcfg_pull_none>;
1377 pdm_m0_sdi1: pdm-m0-sdi1 {
1379 <1 RK_PB2 3 &pcfg_pull_none>;
1382 pdm_m0_sdi2: pdm-m0-sdi2 {
1384 <1 RK_PB1 3 &pcfg_pull_none>;
1387 pdm_m0_sdi3: pdm-m0-sdi3 {
1389 <1 RK_PB0 3 &pcfg_pull_none>;
1394 pdm_m1_clk: pdm-m1-clk {
1396 <1 RK_PB6 4 &pcfg_pull_none>;
1399 pdm_m1_sdi0: pdm-m1-sdi0 {
1401 <1 RK_PC5 4 &pcfg_pull_none>;
1404 pdm_m1_sdi1: pdm-m1-sdi1 {
1406 <1 RK_PC4 4 &pcfg_pull_none>;
1409 pdm_m1_sdi2: pdm-m1-sdi2 {
1411 <1 RK_PC3 4 &pcfg_pull_none>;
1414 pdm_m1_sdi3: pdm-m1-sdi3 {
1416 <1 RK_PC2 4 &pcfg_pull_none>;
1421 pdm_m2_clkm: pdm-m2-clkm {
1423 <2 RK_PA4 3 &pcfg_pull_none>;
1426 pdm_m2_clk: pdm-m2-clk {
1428 <2 RK_PA6 2 &pcfg_pull_none>;
1431 pdm_m2_sdi0: pdm-m2-sdi0 {
1433 <2 RK_PB5 2 &pcfg_pull_none>;
1436 pdm_m2_sdi1: pdm-m2-sdi1 {
1438 <2 RK_PB6 2 &pcfg_pull_none>;
1441 pdm_m2_sdi2: pdm-m2-sdi2 {
1443 <2 RK_PB7 2 &pcfg_pull_none>;
1446 pdm_m2_sdi3: pdm-m2-sdi3 {
1448 <2 RK_PC0 2 &pcfg_pull_none>;
1453 pwm0_pin: pwm0-pin {
1455 <0 RK_PB5 1 &pcfg_pull_none>;
1458 pwm0_pin_pull_down: pwm0-pin-pull-down {
1460 <0 RK_PB5 1 &pcfg_pull_down>;
1465 pwm1_pin: pwm1-pin {
1467 <0 RK_PB6 1 &pcfg_pull_none>;
1470 pwm1_pin_pull_down: pwm1-pin-pull-down {
1472 <0 RK_PB6 1 &pcfg_pull_down>;
1477 pwm2_pin: pwm2-pin {
1479 <0 RK_PB7 1 &pcfg_pull_none>;
1482 pwm2_pin_pull_down: pwm2-pin-pull-down {
1484 <0 RK_PB7 1 &pcfg_pull_down>;
1489 pwm3_pin: pwm3-pin {
1491 <0 RK_PC0 1 &pcfg_pull_none>;
1494 pwm3_pin_pull_down: pwm3-pin-pull-down {
1496 <0 RK_PC0 1 &pcfg_pull_down>;
1501 pwm4_pin: pwm4-pin {
1503 <0 RK_PA1 2 &pcfg_pull_none>;
1506 pwm4_pin_pull_down: pwm4-pin-pull-down {
1508 <0 RK_PA1 2 &pcfg_pull_down>;
1513 pwm5_pin: pwm5-pin {
1515 <0 RK_PC1 2 &pcfg_pull_none>;
1518 pwm5_pin_pull_down: pwm5-pin-pull-down {
1520 <0 RK_PC1 2 &pcfg_pull_down>;
1525 pwm6_pin: pwm6-pin {
1527 <0 RK_PC2 2 &pcfg_pull_none>;
1530 pwm6_pin_pull_down: pwm6-pin-pull-down {
1532 <0 RK_PC2 2 &pcfg_pull_down>;
1537 pwm7_pin: pwm7-pin {
1539 <2 RK_PB0 2 &pcfg_pull_none>;
1542 pwm7_pin_pull_down: pwm7-pin-pull-down {
1544 <2 RK_PB0 2 &pcfg_pull_down>;
1549 pwm8_pin: pwm8-pin {
1551 <2 RK_PB2 2 &pcfg_pull_none>;
1554 pwm8_pin_pull_down: pwm8-pin-pull-down {
1556 <2 RK_PB2 2 &pcfg_pull_down>;
1561 pwm9_pin: pwm9-pin {
1563 <2 RK_PB3 2 &pcfg_pull_none>;
1566 pwm9_pin_pull_down: pwm9-pin-pull-down {
1568 <2 RK_PB3 2 &pcfg_pull_down>;
1573 pwm10_pin: pwm10-pin {
1575 <2 RK_PB4 2 &pcfg_pull_none>;
1578 pwm10_pin_pull_down: pwm10-pin-pull-down {
1580 <2 RK_PB4 2 &pcfg_pull_down>;
1585 pwm11_pin: pwm11-pin {
1587 <2 RK_PC0 4 &pcfg_pull_none>;
1590 pwm11_pin_pull_down: pwm11-pin-pull-down {
1592 <2 RK_PC0 4 &pcfg_pull_down>;
1599 <0 RK_PC3 1 &pcfg_pull_none>;
1604 sdmmc_clk: sdmmc-clk {
1606 <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1609 sdmmc_cmd: sdmmc-cmd {
1611 <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1614 sdmmc_det: sdmmc-det {
1616 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1619 sdmmc_pwren: sdmmc-pwren {
1621 <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1624 sdmmc_bus1: sdmmc-bus1 {
1626 <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1629 sdmmc_bus4: sdmmc-bus4 {
1631 <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1632 <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1633 <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1634 <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1639 sdio_clk: sdio-clk {
1641 <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1644 sdio_cmd: sdio-cmd {
1646 <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1649 sdio_pwren: sdio-pwren {
1651 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1654 sdio_wrpt: sdio-wrpt {
1656 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1659 sdio_intn: sdio-intn {
1661 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1664 sdio_bus1: sdio-bus1 {
1666 <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1669 sdio_bus4: sdio-bus4 {
1671 <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1672 <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1673 <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1674 <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1679 spdif_in: spdif-in {
1681 <0 RK_PC2 1 &pcfg_pull_none>;
1686 spdif_out: spdif-out {
1688 <0 RK_PC1 1 &pcfg_pull_none>;
1693 spi0_clk: spi0-clk {
1695 <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1698 spi0_csn0: spi0-csn0 {
1700 <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1703 spi0_miso: spi0-miso {
1705 <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1708 spi0_mosi: spi0-mosi {
1710 <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1715 spi1_clk: spi1-clk {
1717 <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1720 spi1_csn0: spi1-csn0 {
1722 <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1725 spi1_miso: spi1-miso {
1727 <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1730 spi1_mosi: spi1-mosi {
1732 <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1737 spi1m1_miso: spi1m1-miso {
1739 <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1742 spi1m1_mosi: spi1m1-mosi {
1744 <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1747 spi1m1_clk: spi1m1-clk {
1749 <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1752 spi1m1_csn0: spi1m1-csn0 {
1754 <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1759 spi2_clk: spi2-clk {
1761 <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1764 spi2_csn0: spi2-csn0 {
1766 <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1769 spi2_miso: spi2-miso {
1771 <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1774 spi2_mosi: spi2-mosi {
1776 <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1781 tsadc_otp_pin: tsadc-otp-pin {
1783 <0 RK_PB2 0 &pcfg_pull_none>;
1786 tsadc_otp_out: tsadc-otp-out {
1788 <0 RK_PB2 1 &pcfg_pull_none>;
1793 uart0_xfer: uart0-xfer {
1795 <2 RK_PA1 1 &pcfg_pull_up>,
1796 <2 RK_PA0 1 &pcfg_pull_up>;
1799 uart0_cts: uart0-cts {
1801 <2 RK_PA2 1 &pcfg_pull_none>;
1804 uart0_rts: uart0-rts {
1806 <2 RK_PA3 1 &pcfg_pull_none>;
1809 uart0_rts_pin: uart0-rts-pin {
1811 <2 RK_PA3 0 &pcfg_pull_none>;
1816 uart1_xfer: uart1-xfer {
1818 <1 RK_PD1 1 &pcfg_pull_up>,
1819 <1 RK_PD0 1 &pcfg_pull_up>;
1822 uart1_cts: uart1-cts {
1824 <1 RK_PC6 1 &pcfg_pull_none>;
1827 uart1_rts: uart1-rts {
1829 <1 RK_PC7 1 &pcfg_pull_none>;
1834 uart2m0_xfer: uart2m0-xfer {
1836 <1 RK_PC7 2 &pcfg_pull_up>,
1837 <1 RK_PC6 2 &pcfg_pull_up>;
1842 uart2m1_xfer: uart2m1-xfer {
1844 <4 RK_PD3 2 &pcfg_pull_up>,
1845 <4 RK_PD2 2 &pcfg_pull_up>;
1850 uart3_xfer: uart3-xfer {
1852 <3 RK_PB5 4 &pcfg_pull_up>,
1853 <3 RK_PB4 4 &pcfg_pull_up>;
1858 uart3m1_xfer: uart3m1-xfer {
1860 <0 RK_PC2 3 &pcfg_pull_up>,
1861 <0 RK_PC1 3 &pcfg_pull_up>;
1866 uart4_xfer: uart4-xfer {
1868 <4 RK_PB1 1 &pcfg_pull_up>,
1869 <4 RK_PB0 1 &pcfg_pull_up>;
1872 uart4_cts: uart4-cts {
1874 <4 RK_PA6 1 &pcfg_pull_none>;
1877 uart4_rts: uart4-rts {
1879 <4 RK_PA7 1 &pcfg_pull_none>;
1882 uart4_rts_pin: uart4-rts-pin {
1884 <4 RK_PA7 0 &pcfg_pull_none>;