arch/arm64/boot/dts/rockchip/px30.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/px30-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/px30-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,px30";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 ethernet0 = &gmac;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &uart2;
  31                 serial3 = &uart3;
  32                 serial4 = &uart4;
  33                 serial5 = &uart5;
  34                 spi0 = &spi0;
  35                 spi1 = &spi1;
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a35";
  45                         reg = <0x0 0x0>;
  46                         enable-method = "psci";
  47                         clocks = <&cru ARMCLK>;
  48                         #cooling-cells = <2>;
  49                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  50                         dynamic-power-coefficient = <90>;
  51                         operating-points-v2 = <&cpu0_opp_table>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         clocks = <&cru ARMCLK>;
  60                         #cooling-cells = <2>;
  61                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  62                         dynamic-power-coefficient = <90>;
  63                         operating-points-v2 = <&cpu0_opp_table>;
  64                 };
  65
  66                 cpu2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a35";
  69                         reg = <0x0 0x2>;
  70                         enable-method = "psci";
  71                         clocks = <&cru ARMCLK>;
  72                         #cooling-cells = <2>;
  73                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  74                         dynamic-power-coefficient = <90>;
  75                         operating-points-v2 = <&cpu0_opp_table>;
  76                 };
  77
  78                 cpu3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a35";
  81                         reg = <0x0 0x3>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         #cooling-cells = <2>;
  85                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  86                         dynamic-power-coefficient = <90>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 idle-states {
  91                         entry-method = "psci";
  92
  93                         CPU_SLEEP: cpu-sleep {
  94                                 compatible = "arm,idle-state";
  95                                 local-timer-stop;
  96                                 arm,psci-suspend-param = <0x0010000>;
  97                                 entry-latency-us = <120>;
  98                                 exit-latency-us = <250>;
  99                                 min-residency-us = <900>;
 100                         };
 101
 102                         CLUSTER_SLEEP: cluster-sleep {
 103                                 compatible = "arm,idle-state";
 104                                 local-timer-stop;
 105                                 arm,psci-suspend-param = <0x1010000>;
 106                                 entry-latency-us = <400>;
 107                                 exit-latency-us = <500>;
 108                                 min-residency-us = <2000>;
 109                         };
 110                 };
 111         };
 112
 113         cpu0_opp_table: cpu0-opp-table {
 114                 compatible = "operating-points-v2";
 115                 opp-shared;
 116
 117                 opp-600000000 {
 118                         opp-hz = /bits/ 64 <600000000>;
 119                         opp-microvolt = <950000 950000 1350000>;
 120                         clock-latency-ns = <40000>;
 121                         opp-suspend;
 122                 };
 123                 opp-816000000 {
 124                         opp-hz = /bits/ 64 <816000000>;
 125                         opp-microvolt = <1050000 1050000 1350000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128                 opp-1008000000 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1175000 1175000 1350000>;
 131                         clock-latency-ns = <40000>;
 132                 };
 133                 opp-1200000000 {
 134                         opp-hz = /bits/ 64 <1200000000>;
 135                         opp-microvolt = <1300000 1300000 1350000>;
 136                         clock-latency-ns = <40000>;
 137                 };
 138                 opp-1296000000 {
 139                         opp-hz = /bits/ 64 <1296000000>;
 140                         opp-microvolt = <1350000 1350000 1350000>;
 141                         clock-latency-ns = <40000>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         display_subsystem: display-subsystem {
 155                 compatible = "rockchip,display-subsystem";
 156                 ports = <&vopb_out>, <&vopl_out>;
 157                 status = "disabled";
 158         };
 159
 160         gmac_clkin: external-gmac-clock {
 161                 compatible = "fixed-clock";
 162                 clock-frequency = <50000000>;
 163                 clock-output-names = "gmac_clkin";
 164                 #clock-cells = <0>;
 165         };
 166
 167         psci {
 168                 compatible = "arm,psci-1.0";
 169                 method = "smc";
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv8-timer";
 174                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 175                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 176                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 177                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 178         };
 179
 180         thermal_zones: thermal-zones {
 181                 soc_thermal: soc-thermal {
 182                         polling-delay-passive = <20>;
 183                         polling-delay = <1000>;
 184                         sustainable-power = <750>;
 185                         thermal-sensors = <&tsadc 0>;
 186
 187                         trips {
 188                                 threshold: trip-point-0 {
 189                                         temperature = <70000>;
 190                                         hysteresis = <2000>;
 191                                         type = "passive";
 192                                 };
 193
 194                                 target: trip-point-1 {
 195                                         temperature = <85000>;
 196                                         hysteresis = <2000>;
 197                                         type = "passive";
 198                                 };
 199
 200                                 soc_crit: soc-crit {
 201                                         temperature = <115000>;
 202                                         hysteresis = <2000>;
 203                                         type = "critical";
 204                                 };
 205                         };
 206
 207                         cooling-maps {
 208                                 map0 {
 209                                         trip = <&target>;
 210                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 211                                         contribution = <4096>;
 212                                 };
 213                         };
 214                 };
 215
 216                 gpu_thermal: gpu-thermal {
 217                         polling-delay-passive = <100>; /* milliseconds */
 218                         polling-delay = <1000>; /* milliseconds */
 219                         thermal-sensors = <&tsadc 1>;
 220                 };
 221         };
 222
 223         xin24m: xin24m {
 224                 compatible = "fixed-clock";
 225                 #clock-cells = <0>;
 226                 clock-frequency = <24000000>;
 227                 clock-output-names = "xin24m";
 228         };
 229
 230         pmu: power-management@ff000000 {
 231                 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
 232                 reg = <0x0 0xff000000 0x0 0x1000>;
 233
 234                 power: power-controller {
 235                         compatible = "rockchip,px30-power-controller";
 236                         #power-domain-cells = <1>;
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239
 240                         /* These power domains are grouped by VD_LOGIC */
 241                         pd_usb@PX30_PD_USB {
 242                                 reg = <PX30_PD_USB>;
 243                                 clocks = <&cru HCLK_HOST>,
 244                                          <&cru HCLK_OTG>,
 245                                          <&cru SCLK_OTG_ADP>;
 246                                 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
 247                         };
 248                         pd_sdcard@PX30_PD_SDCARD {
 249                                 reg = <PX30_PD_SDCARD>;
 250                                 clocks = <&cru HCLK_SDMMC>,
 251                                          <&cru SCLK_SDMMC>;
 252                                 pm_qos = <&qos_sdmmc>;
 253                         };
 254                         pd_gmac@PX30_PD_GMAC {
 255                                 reg = <PX30_PD_GMAC>;
 256                                 clocks = <&cru ACLK_GMAC>,
 257                                          <&cru PCLK_GMAC>,
 258                                          <&cru SCLK_MAC_REF>,
 259                                          <&cru SCLK_GMAC_RX_TX>;
 260                                 pm_qos = <&qos_gmac>;
 261                         };
 262                         pd_mmc_nand@PX30_PD_MMC_NAND {
 263                                 reg = <PX30_PD_MMC_NAND>;
 264                                 clocks =  <&cru HCLK_NANDC>,
 265                                           <&cru HCLK_EMMC>,
 266                                           <&cru HCLK_SDIO>,
 267                                           <&cru HCLK_SFC>,
 268                                           <&cru SCLK_EMMC>,
 269                                           <&cru SCLK_NANDC>,
 270                                           <&cru SCLK_SDIO>,
 271                                           <&cru SCLK_SFC>;
 272                                 pm_qos = <&qos_emmc>, <&qos_nand>,
 273                                          <&qos_sdio>, <&qos_sfc>;
 274                         };
 275                         pd_vpu@PX30_PD_VPU {
 276                                 reg = <PX30_PD_VPU>;
 277                                 clocks = <&cru ACLK_VPU>,
 278                                          <&cru HCLK_VPU>,
 279                                          <&cru SCLK_CORE_VPU>;
 280                                 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
 281                         };
 282                         pd_vo@PX30_PD_VO {
 283                                 reg = <PX30_PD_VO>;
 284                                 clocks = <&cru ACLK_RGA>,
 285                                          <&cru ACLK_VOPB>,
 286                                          <&cru ACLK_VOPL>,
 287                                          <&cru DCLK_VOPB>,
 288                                          <&cru DCLK_VOPL>,
 289                                          <&cru HCLK_RGA>,
 290                                          <&cru HCLK_VOPB>,
 291                                          <&cru HCLK_VOPL>,
 292                                          <&cru PCLK_MIPI_DSI>,
 293                                          <&cru SCLK_RGA_CORE>,
 294                                          <&cru SCLK_VOPB_PWM>;
 295                                 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 296                                          <&qos_vop_m0>, <&qos_vop_m1>;
 297                         };
 298                         pd_vi@PX30_PD_VI {
 299                                 reg = <PX30_PD_VI>;
 300                                 clocks = <&cru ACLK_CIF>,
 301                                          <&cru ACLK_ISP>,
 302                                          <&cru HCLK_CIF>,
 303                                          <&cru HCLK_ISP>,
 304                                          <&cru SCLK_ISP>;
 305                                 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 306                                          <&qos_isp_wr>, <&qos_isp_m1>,
 307                                          <&qos_vip>;
 308                         };
 309                         pd_gpu@PX30_PD_GPU {
 310                                 reg = <PX30_PD_GPU>;
 311                                 clocks = <&cru SCLK_GPU>;
 312                                 pm_qos = <&qos_gpu>;
 313                         };
 314                 };
 315         };
 316
 317         pmugrf: syscon@ff010000 {
 318                 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
 319                 reg = <0x0 0xff010000 0x0 0x1000>;
 320                 #address-cells = <1>;
 321                 #size-cells = <1>;
 322
 323                 pmu_io_domains: io-domains {
 324                         compatible = "rockchip,px30-pmu-io-voltage-domain";
 325                         status = "disabled";
 326                 };
 327
 328                 reboot-mode {
 329                         compatible = "syscon-reboot-mode";
 330                         offset = <0x200>;
 331                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 332                         mode-fastboot = <BOOT_FASTBOOT>;
 333                         mode-loader = <BOOT_BL_DOWNLOAD>;
 334                         mode-normal = <BOOT_NORMAL>;
 335                         mode-recovery = <BOOT_RECOVERY>;
 336                 };
 337         };
 338
 339         uart0: serial@ff030000 {
 340                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 341                 reg = <0x0 0xff030000 0x0 0x100>;
 342                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 344                 clock-names = "baudclk", "apb_pclk";
 345                 dmas = <&dmac 0>, <&dmac 1>;
 346                 dma-names = "tx", "rx";
 347                 reg-shift = <2>;
 348                 reg-io-width = <4>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 351                 status = "disabled";
 352         };
 353
 354         i2s1_2ch: i2s@ff070000 {
 355                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 356                 reg = <0x0 0xff070000 0x0 0x1000>;
 357                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 359                 clock-names = "i2s_clk", "i2s_hclk";
 360                 dmas = <&dmac 18>, <&dmac 19>;
 361                 dma-names = "tx", "rx";
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
 364                              &i2s1_2ch_sdi &i2s1_2ch_sdo>;
 365                 #sound-dai-cells = <0>;
 366                 status = "disabled";
 367         };
 368
 369         i2s2_2ch: i2s@ff080000 {
 370                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 371                 reg = <0x0 0xff080000 0x0 0x1000>;
 372                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 374                 clock-names = "i2s_clk", "i2s_hclk";
 375                 dmas = <&dmac 20>, <&dmac 21>;
 376                 dma-names = "tx", "rx";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
 379                              &i2s2_2ch_sdi &i2s2_2ch_sdo>;
 380                 #sound-dai-cells = <0>;
 381                 status = "disabled";
 382         };
 383
 384         gic: interrupt-controller@ff131000 {
 385                 compatible = "arm,gic-400";
 386                 #interrupt-cells = <3>;
 387                 #address-cells = <0>;
 388                 interrupt-controller;
 389                 reg = <0x0 0xff131000 0 0x1000>,
 390                       <0x0 0xff132000 0 0x2000>,
 391                       <0x0 0xff134000 0 0x2000>,
 392                       <0x0 0xff136000 0 0x2000>;
 393                 interrupts = <GIC_PPI 9
 394                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 395         };
 396
 397         grf: syscon@ff140000 {
 398                 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
 399                 reg = <0x0 0xff140000 0x0 0x1000>;
 400                 #address-cells = <1>;
 401                 #size-cells = <1>;
 402
 403                 io_domains: io-domains {
 404                         compatible = "rockchip,px30-io-voltage-domain";
 405                         status = "disabled";
 406                 };
 407         };
 408
 409         uart1: serial@ff158000 {
 410                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 411                 reg = <0x0 0xff158000 0x0 0x100>;
 412                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 414                 clock-names = "baudclk", "apb_pclk";
 415                 dmas = <&dmac 2>, <&dmac 3>;
 416                 dma-names = "tx", "rx";
 417                 reg-shift = <2>;
 418                 reg-io-width = <4>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 421                 status = "disabled";
 422         };
 423
 424         uart2: serial@ff160000 {
 425                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 426                 reg = <0x0 0xff160000 0x0 0x100>;
 427                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 429                 clock-names = "baudclk", "apb_pclk";
 430                 dmas = <&dmac 4>, <&dmac 5>;
 431                 dma-names = "tx", "rx";
 432                 reg-shift = <2>;
 433                 reg-io-width = <4>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&uart2m0_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         uart3: serial@ff168000 {
 440                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 441                 reg = <0x0 0xff168000 0x0 0x100>;
 442                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 444                 clock-names = "baudclk", "apb_pclk";
 445                 dmas = <&dmac 6>, <&dmac 7>;
 446                 dma-names = "tx", "rx";
 447                 reg-shift = <2>;
 448                 reg-io-width = <4>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
 451                 status = "disabled";
 452         };
 453
 454         uart4: serial@ff170000 {
 455                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 456                 reg = <0x0 0xff170000 0x0 0x100>;
 457                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 459                 clock-names = "baudclk", "apb_pclk";
 460                 dmas = <&dmac 8>, <&dmac 9>;
 461                 dma-names = "tx", "rx";
 462                 reg-shift = <2>;
 463                 reg-io-width = <4>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 466                 status = "disabled";
 467         };
 468
 469         uart5: serial@ff178000 {
 470                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 471                 reg = <0x0 0xff178000 0x0 0x100>;
 472                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 dmas = <&dmac 10>, <&dmac 11>;
 476                 dma-names = "tx", "rx";
 477                 reg-shift = <2>;
 478                 reg-io-width = <4>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
 481                 status = "disabled";
 482         };
 483
 484         i2c0: i2c@ff180000 {
 485                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 486                 reg = <0x0 0xff180000 0x0 0x1000>;
 487                 clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 488                 clock-names = "i2c", "pclk";
 489                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c0_xfer>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 status = "disabled";
 495         };
 496
 497         i2c1: i2c@ff190000 {
 498                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 499                 reg = <0x0 0xff190000 0x0 0x1000>;
 500                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 501                 clock-names = "i2c", "pclk";
 502                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c1_xfer>;
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 status = "disabled";
 508         };
 509
 510         i2c2: i2c@ff1a0000 {
 511                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 512                 reg = <0x0 0xff1a0000 0x0 0x1000>;
 513                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 514                 clock-names = "i2c", "pclk";
 515                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&i2c2_xfer>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 status = "disabled";
 521         };
 522
 523         i2c3: i2c@ff1b0000 {
 524                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 525                 reg = <0x0 0xff1b0000 0x0 0x1000>;
 526                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 527                 clock-names = "i2c", "pclk";
 528                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2c3_xfer>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 status = "disabled";
 534         };
 535
 536         spi0: spi@ff1d0000 {
 537                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 538                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 539                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 541                 clock-names = "spiclk", "apb_pclk";
 542                 dmas = <&dmac 12>, <&dmac 13>;
 543                 dma-names = "tx", "rx";
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         spi1: spi@ff1d8000 {
 552                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 553                 reg = <0x0 0xff1d8000 0x0 0x1000>;
 554                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 555                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 556                 clock-names = "spiclk", "apb_pclk";
 557                 dmas = <&dmac 14>, <&dmac 15>;
 558                 dma-names = "tx", "rx";
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         wdt: watchdog@ff1e0000 {
 567                 compatible = "snps,dw-wdt";
 568                 reg = <0x0 0xff1e0000 0x0 0x100>;
 569                 clocks = <&cru PCLK_WDT_NS>;
 570                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 571                 status = "disabled";
 572         };
 573
 574         pwm0: pwm@ff200000 {
 575                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 576                 reg = <0x0 0xff200000 0x0 0x10>;
 577                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 578                 clock-names = "pwm", "pclk";
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&pwm0_pin>;
 581                 #pwm-cells = <3>;
 582                 status = "disabled";
 583         };
 584
 585         pwm1: pwm@ff200010 {
 586                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 587                 reg = <0x0 0xff200010 0x0 0x10>;
 588                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 589                 clock-names = "pwm", "pclk";
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&pwm1_pin>;
 592                 #pwm-cells = <3>;
 593                 status = "disabled";
 594         };
 595
 596         pwm2: pwm@ff200020 {
 597                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 598                 reg = <0x0 0xff200020 0x0 0x10>;
 599                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 600                 clock-names = "pwm", "pclk";
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&pwm2_pin>;
 603                 #pwm-cells = <3>;
 604                 status = "disabled";
 605         };
 606
 607         pwm3: pwm@ff200030 {
 608                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 609                 reg = <0x0 0xff200030 0x0 0x10>;
 610                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 611                 clock-names = "pwm", "pclk";
 612                 pinctrl-names = "default";
 613                 pinctrl-0 = <&pwm3_pin>;
 614                 #pwm-cells = <3>;
 615                 status = "disabled";
 616         };
 617
 618         pwm4: pwm@ff208000 {
 619                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 620                 reg = <0x0 0xff208000 0x0 0x10>;
 621                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 622                 clock-names = "pwm", "pclk";
 623                 pinctrl-names = "default";
 624                 pinctrl-0 = <&pwm4_pin>;
 625                 #pwm-cells = <3>;
 626                 status = "disabled";
 627         };
 628
 629         pwm5: pwm@ff208010 {
 630                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 631                 reg = <0x0 0xff208010 0x0 0x10>;
 632                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 633                 clock-names = "pwm", "pclk";
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&pwm5_pin>;
 636                 #pwm-cells = <3>;
 637                 status = "disabled";
 638         };
 639
 640         pwm6: pwm@ff208020 {
 641                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 642                 reg = <0x0 0xff208020 0x0 0x10>;
 643                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 644                 clock-names = "pwm", "pclk";
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&pwm6_pin>;
 647                 #pwm-cells = <3>;
 648                 status = "disabled";
 649         };
 650
 651         pwm7: pwm@ff208030 {
 652                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 653                 reg = <0x0 0xff208030 0x0 0x10>;
 654                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 655                 clock-names = "pwm", "pclk";
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&pwm7_pin>;
 658                 #pwm-cells = <3>;
 659                 status = "disabled";
 660         };
 661
 662         rktimer: timer@ff210000 {
 663                 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
 664                 reg = <0x0 0xff210000 0x0 0x1000>;
 665                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 667                 clock-names = "pclk", "timer";
 668         };
 669
 670         amba {
 671                 compatible = "simple-bus";
 672                 #address-cells = <2>;
 673                 #size-cells = <2>;
 674                 ranges;
 675
 676                 dmac: dmac@ff240000 {
 677                         compatible = "arm,pl330", "arm,primecell";
 678                         reg = <0x0 0xff240000 0x0 0x4000>;
 679                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&cru ACLK_DMAC>;
 682                         clock-names = "apb_pclk";
 683                         #dma-cells = <1>;
 684                 };
 685         };
 686
 687         tsadc: tsadc@ff280000 {
 688                 compatible = "rockchip,px30-tsadc";
 689                 reg = <0x0 0xff280000 0x0 0x100>;
 690                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 691                 assigned-clocks = <&cru SCLK_TSADC>;
 692                 assigned-clock-rates = <50000>;
 693                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 694                 clock-names = "tsadc", "apb_pclk";
 695                 resets = <&cru SRST_TSADC>;
 696                 reset-names = "tsadc-apb";
 697                 rockchip,grf = <&grf>;
 698                 rockchip,hw-tshut-temp = <120000>;
 699                 pinctrl-names = "init", "default", "sleep";
 700                 pinctrl-0 = <&tsadc_otp_gpio>;
 701                 pinctrl-1 = <&tsadc_otp_out>;
 702                 pinctrl-2 = <&tsadc_otp_gpio>;
 703                 #thermal-sensor-cells = <1>;
 704                 status = "disabled";
 705         };
 706
 707         saradc: saradc@ff288000 {
 708                 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
 709                 reg = <0x0 0xff288000 0x0 0x100>;
 710                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 711                 #io-channel-cells = <1>;
 712                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 713                 clock-names = "saradc", "apb_pclk";
 714                 resets = <&cru SRST_SARADC_P>;
 715                 reset-names = "saradc-apb";
 716                 status = "disabled";
 717         };
 718
 719         otp: nvmem@ff290000 {
 720                 compatible = "rockchip,px30-otp";
 721                 reg = <0x0 0xff290000 0x0 0x4000>;
 722                 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
 723                          <&cru PCLK_OTP_PHY>;
 724                 clock-names = "otp", "apb_pclk", "phy";
 725                 resets = <&cru SRST_OTP_PHY>;
 726                 reset-names = "phy";
 727                 #address-cells = <1>;
 728                 #size-cells = <1>;
 729
 730                 /* Data cells */
 731                 cpu_id: id@7 {
 732                         reg = <0x07 0x10>;
 733                 };
 734                 cpu_leakage: cpu-leakage@17 {
 735                         reg = <0x17 0x1>;
 736                 };
 737                 performance: performance@1e {
 738                         reg = <0x1e 0x1>;
 739                         bits = <4 3>;
 740                 };
 741         };
 742
 743         cru: clock-controller@ff2b0000 {
 744                 compatible = "rockchip,px30-cru";
 745                 reg = <0x0 0xff2b0000 0x0 0x1000>;
 746                 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
 747                 clock-names = "xin24m", "gpll";
 748                 rockchip,grf = <&grf>;
 749                 #clock-cells = <1>;
 750                 #reset-cells = <1>;
 751
 752                 assigned-clocks = <&cru PLL_NPLL>,
 753                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 754                         <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
 755                         <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
 756
 757                 assigned-clock-rates = <1188000000>,
 758                         <200000000>, <200000000>,
 759                         <150000000>, <150000000>,
 760                         <100000000>, <200000000>;
 761         };
 762
 763         pmucru: clock-controller@ff2bc000 {
 764                 compatible = "rockchip,px30-pmucru";
 765                 reg = <0x0 0xff2bc000 0x0 0x1000>;
 766                 clocks = <&xin24m>;
 767                 clock-names = "xin24m";
 768                 rockchip,grf = <&grf>;
 769                 #clock-cells = <1>;
 770                 #reset-cells = <1>;
 771
 772                 assigned-clocks =
 773                         <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
 774                         <&pmucru SCLK_WIFI_PMU>;
 775                 assigned-clock-rates =
 776                         <1200000000>, <100000000>,
 777                         <26000000>;
 778         };
 779
 780         usb2phy_grf: syscon@ff2c0000 {
 781                 compatible = "rockchip,px30-usb2phy-grf", "syscon",
 782                              "simple-mfd";
 783                 reg = <0x0 0xff2c0000 0x0 0x10000>;
 784                 #address-cells = <1>;
 785                 #size-cells = <1>;
 786
 787                 u2phy: usb2-phy@100 {
 788                         compatible = "rockchip,px30-usb2phy";
 789                         reg = <0x100 0x20>;
 790                         clocks = <&pmucru SCLK_USBPHY_REF>;
 791                         clock-names = "phyclk";
 792                         #clock-cells = <0>;
 793                         assigned-clocks = <&cru USB480M>;
 794                         assigned-clock-parents = <&u2phy>;
 795                         clock-output-names = "usb480m_phy";
 796                         status = "disabled";
 797
 798                         u2phy_host: host-port {
 799                                 #phy-cells = <0>;
 800                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 801                                 interrupt-names = "linestate";
 802                                 status = "disabled";
 803                         };
 804
 805                         u2phy_otg: otg-port {
 806                                 #phy-cells = <0>;
 807                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 808                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 809                                              <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 810                                 interrupt-names = "otg-bvalid", "otg-id",
 811                                                   "linestate";
 812                                 status = "disabled";
 813                         };
 814                 };
 815         };
 816
 817         usb20_otg: usb@ff300000 {
 818                 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 819                              "snps,dwc2";
 820                 reg = <0x0 0xff300000 0x0 0x40000>;
 821                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&cru HCLK_OTG>;
 823                 clock-names = "otg";
 824                 dr_mode = "otg";
 825                 g-np-tx-fifo-size = <16>;
 826                 g-rx-fifo-size = <280>;
 827                 g-tx-fifo-size = <256 128 128 64 32 16>;
 828                 g-use-dma;
 829                 phys = <&u2phy_otg>;
 830                 phy-names = "usb2-phy";
 831                 power-domains = <&power PX30_PD_USB>;
 832                 status = "disabled";
 833         };
 834
 835         usb_host0_ehci: usb@ff340000 {
 836                 compatible = "generic-ehci";
 837                 reg = <0x0 0xff340000 0x0 0x10000>;
 838                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&cru HCLK_HOST>;
 840                 clock-names = "usbhost";
 841                 phys = <&u2phy_host>;
 842                 phy-names = "usb";
 843                 power-domains = <&power PX30_PD_USB>;
 844                 status = "disabled";
 845         };
 846
 847         usb_host0_ohci: usb@ff350000 {
 848                 compatible = "generic-ohci";
 849                 reg = <0x0 0xff350000 0x0 0x10000>;
 850                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 851                 clocks = <&cru HCLK_HOST>;
 852                 clock-names = "usbhost";
 853                 phys = <&u2phy_host>;
 854                 phy-names = "usb";
 855                 power-domains = <&power PX30_PD_USB>;
 856                 status = "disabled";
 857         };
 858
 859         gmac: ethernet@ff360000 {
 860                 compatible = "rockchip,px30-gmac";
 861                 reg = <0x0 0xff360000 0x0 0x10000>;
 862                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 863                 interrupt-names = "macirq";
 864                 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
 865                          <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
 866                          <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 867                          <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
 868                 clock-names = "stmmaceth", "mac_clk_rx",
 869                               "mac_clk_tx", "clk_mac_ref",
 870                               "clk_mac_refout", "aclk_mac",
 871                               "pclk_mac", "clk_mac_speed";
 872                 rockchip,grf = <&grf>;
 873                 phy-mode = "rmii";
 874                 pinctrl-names = "default";
 875                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 876                 power-domains = <&power PX30_PD_GMAC>;
 877                 resets = <&cru SRST_GMAC_A>;
 878                 reset-names = "stmmaceth";
 879                 status = "disabled";
 880         };
 881
 882         sdmmc: dwmmc@ff370000 {
 883                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 884                 reg = <0x0 0xff370000 0x0 0x4000>;
 885                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 887                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 888                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 889                 fifo-depth = <0x100>;
 890                 max-frequency = <150000000>;
 891                 pinctrl-names = "default";
 892                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 893                 power-domains = <&power PX30_PD_SDCARD>;
 894                 status = "disabled";
 895         };
 896
 897         sdio: dwmmc@ff380000 {
 898                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 899                 reg = <0x0 0xff380000 0x0 0x4000>;
 900                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 901                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 902                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 903                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 904                 fifo-depth = <0x100>;
 905                 max-frequency = <150000000>;
 906                 pinctrl-names = "default";
 907                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 908                 power-domains = <&power PX30_PD_MMC_NAND>;
 909                 status = "disabled";
 910         };
 911
 912         emmc: dwmmc@ff390000 {
 913                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 914                 reg = <0x0 0xff390000 0x0 0x4000>;
 915                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 916                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 917                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 918                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 919                 fifo-depth = <0x100>;
 920                 max-frequency = <150000000>;
 921                 pinctrl-names = "default";
 922                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 923                 power-domains = <&power PX30_PD_MMC_NAND>;
 924                 status = "disabled";
 925         };
 926
 927         vopb: vop@ff460000 {
 928                 compatible = "rockchip,px30-vop-big";
 929                 reg = <0x0 0xff460000 0x0 0xefc>;
 930                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 931                 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
 932                          <&cru HCLK_VOPB>;
 933                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 934                 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
 935                 reset-names = "axi", "ahb", "dclk";
 936                 iommus = <&vopb_mmu>;
 937                 power-domains = <&power PX30_PD_VO>;
 938                 rockchip,grf = <&grf>;
 939                 status = "disabled";
 940
 941                 vopb_out: port {
 942                         #address-cells = <1>;
 943                         #size-cells = <0>;
 944                 };
 945         };
 946
 947         vopb_mmu: iommu@ff460f00 {
 948                 compatible = "rockchip,iommu";
 949                 reg = <0x0 0xff460f00 0x0 0x100>;
 950                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 951                 interrupt-names = "vopb_mmu";
 952                 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
 953                 clock-names = "aclk", "iface";
 954                 power-domains = <&power PX30_PD_VO>;
 955                 #iommu-cells = <0>;
 956                 status = "disabled";
 957         };
 958
 959         vopl: vop@ff470000 {
 960                 compatible = "rockchip,px30-vop-lit";
 961                 reg = <0x0 0xff470000 0x0 0xefc>;
 962                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 963                 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
 964                          <&cru HCLK_VOPL>;
 965                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 966                 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
 967                 reset-names = "axi", "ahb", "dclk";
 968                 iommus = <&vopl_mmu>;
 969                 power-domains = <&power PX30_PD_VO>;
 970                 rockchip,grf = <&grf>;
 971                 status = "disabled";
 972
 973                 vopl_out: port {
 974                         #address-cells = <1>;
 975                         #size-cells = <0>;
 976                 };
 977         };
 978
 979         vopl_mmu: iommu@ff470f00 {
 980                 compatible = "rockchip,iommu";
 981                 reg = <0x0 0xff470f00 0x0 0x100>;
 982                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 983                 interrupt-names = "vopl_mmu";
 984                 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
 985                 clock-names = "aclk", "iface";
 986                 power-domains = <&power PX30_PD_VO>;
 987                 #iommu-cells = <0>;
 988                 status = "disabled";
 989         };
 990
 991         qos_gmac: qos@ff518000 {
 992                 compatible = "syscon";
 993                 reg = <0x0 0xff518000 0x0 0x20>;
 994         };
 995
 996         qos_gpu: qos@ff520000 {
 997                 compatible = "syscon";
 998                 reg = <0x0 0xff520000 0x0 0x20>;
 999         };
1000
1001         qos_sdmmc: qos@ff52c000 {
1002                 compatible = "syscon";
1003                 reg = <0x0 0xff52c000 0x0 0x20>;
1004         };
1005
1006         qos_emmc: qos@ff538000 {
1007                 compatible = "syscon";
1008                 reg = <0x0 0xff538000 0x0 0x20>;
1009         };
1010
1011         qos_nand: qos@ff538080 {
1012                 compatible = "syscon";
1013                 reg = <0x0 0xff538080 0x0 0x20>;
1014         };
1015
1016         qos_sdio: qos@ff538100 {
1017                 compatible = "syscon";
1018                 reg = <0x0 0xff538100 0x0 0x20>;
1019         };
1020
1021         qos_sfc: qos@ff538180 {
1022                 compatible = "syscon";
1023                 reg = <0x0 0xff538180 0x0 0x20>;
1024         };
1025
1026         qos_usb_host: qos@ff540000 {
1027                 compatible = "syscon";
1028                 reg = <0x0 0xff540000 0x0 0x20>;
1029         };
1030
1031         qos_usb_otg: qos@ff540080 {
1032                 compatible = "syscon";
1033                 reg = <0x0 0xff540080 0x0 0x20>;
1034         };
1035
1036         qos_isp_128: qos@ff548000 {
1037                 compatible = "syscon";
1038                 reg = <0x0 0xff548000 0x0 0x20>;
1039         };
1040
1041         qos_isp_rd: qos@ff548080 {
1042                 compatible = "syscon";
1043                 reg = <0x0 0xff548080 0x0 0x20>;
1044         };
1045
1046         qos_isp_wr: qos@ff548100 {
1047                 compatible = "syscon";
1048                 reg = <0x0 0xff548100 0x0 0x20>;
1049         };
1050
1051         qos_isp_m1: qos@ff548180 {
1052                 compatible = "syscon";
1053                 reg = <0x0 0xff548180 0x0 0x20>;
1054         };
1055
1056         qos_vip: qos@ff548200 {
1057                 compatible = "syscon";
1058                 reg = <0x0 0xff548200 0x0 0x20>;
1059         };
1060
1061         qos_rga_rd: qos@ff550000 {
1062                 compatible = "syscon";
1063                 reg = <0x0 0xff550000 0x0 0x20>;
1064         };
1065
1066         qos_rga_wr: qos@ff550080 {
1067                 compatible = "syscon";
1068                 reg = <0x0 0xff550080 0x0 0x20>;
1069         };
1070
1071         qos_vop_m0: qos@ff550100 {
1072                 compatible = "syscon";
1073                 reg = <0x0 0xff550100 0x0 0x20>;
1074         };
1075
1076         qos_vop_m1: qos@ff550180 {
1077                 compatible = "syscon";
1078                 reg = <0x0 0xff550180 0x0 0x20>;
1079         };
1080
1081         qos_vpu: qos@ff558000 {
1082                 compatible = "syscon";
1083                 reg = <0x0 0xff558000 0x0 0x20>;
1084         };
1085
1086         qos_vpu_r128: qos@ff558080 {
1087                 compatible = "syscon";
1088                 reg = <0x0 0xff558080 0x0 0x20>;
1089         };
1090
1091         pinctrl: pinctrl {
1092                 compatible = "rockchip,px30-pinctrl";
1093                 rockchip,grf = <&grf>;
1094                 rockchip,pmu = <&pmugrf>;
1095                 #address-cells = <2>;
1096                 #size-cells = <2>;
1097                 ranges;
1098
1099                 gpio0: gpio0@ff040000 {
1100                         compatible = "rockchip,gpio-bank";
1101                         reg = <0x0 0xff040000 0x0 0x100>;
1102                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1103                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1104                         gpio-controller;
1105                         #gpio-cells = <2>;
1106
1107                         interrupt-controller;
1108                         #interrupt-cells = <2>;
1109                 };
1110
1111                 gpio1: gpio1@ff250000 {
1112                         compatible = "rockchip,gpio-bank";
1113                         reg = <0x0 0xff250000 0x0 0x100>;
1114                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1115                         clocks = <&cru PCLK_GPIO1>;
1116                         gpio-controller;
1117                         #gpio-cells = <2>;
1118
1119                         interrupt-controller;
1120                         #interrupt-cells = <2>;
1121                 };
1122
1123                 gpio2: gpio2@ff260000 {
1124                         compatible = "rockchip,gpio-bank";
1125                         reg = <0x0 0xff260000 0x0 0x100>;
1126                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1127                         clocks = <&cru PCLK_GPIO2>;
1128                         gpio-controller;
1129                         #gpio-cells = <2>;
1130
1131                         interrupt-controller;
1132                         #interrupt-cells = <2>;
1133                 };
1134
1135                 gpio3: gpio3@ff270000 {
1136                         compatible = "rockchip,gpio-bank";
1137                         reg = <0x0 0xff270000 0x0 0x100>;
1138                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1139                         clocks = <&cru PCLK_GPIO3>;
1140                         gpio-controller;
1141                         #gpio-cells = <2>;
1142
1143                         interrupt-controller;
1144                         #interrupt-cells = <2>;
1145                 };
1146
1147                 pcfg_pull_up: pcfg-pull-up {
1148                         bias-pull-up;
1149                 };
1150
1151                 pcfg_pull_down: pcfg-pull-down {
1152                         bias-pull-down;
1153                 };
1154
1155                 pcfg_pull_none: pcfg-pull-none {
1156                         bias-disable;
1157                 };
1158
1159                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1160                         bias-disable;
1161                         drive-strength = <2>;
1162                 };
1163
1164                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1165                         bias-pull-up;
1166                         drive-strength = <2>;
1167                 };
1168
1169                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1170                         bias-pull-up;
1171                         drive-strength = <4>;
1172                 };
1173
1174                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1175                         bias-disable;
1176                         drive-strength = <4>;
1177                 };
1178
1179                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1180                         bias-pull-down;
1181                         drive-strength = <4>;
1182                 };
1183
1184                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1185                         bias-disable;
1186                         drive-strength = <8>;
1187                 };
1188
1189                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1190                         bias-pull-up;
1191                         drive-strength = <8>;
1192                 };
1193
1194                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1195                         bias-disable;
1196                         drive-strength = <12>;
1197                 };
1198
1199                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1200                         bias-pull-up;
1201                         drive-strength = <12>;
1202                 };
1203
1204                 pcfg_pull_none_smt: pcfg-pull-none-smt {
1205                         bias-disable;
1206                         input-schmitt-enable;
1207                 };
1208
1209                 pcfg_output_high: pcfg-output-high {
1210                         output-high;
1211                 };
1212
1213                 pcfg_output_low: pcfg-output-low {
1214                         output-low;
1215                 };
1216
1217                 pcfg_input_high: pcfg-input-high {
1218                         bias-pull-up;
1219                         input-enable;
1220                 };
1221
1222                 pcfg_input: pcfg-input {
1223                         input-enable;
1224                 };
1225
1226                 i2c0 {
1227                         i2c0_xfer: i2c0-xfer {
1228                                 rockchip,pins =
1229                                         <0 RK_PB0 1 &pcfg_pull_none_smt>,
1230                                         <0 RK_PB1 1 &pcfg_pull_none_smt>;
1231                         };
1232                 };
1233
1234                 i2c1 {
1235                         i2c1_xfer: i2c1-xfer {
1236                                 rockchip,pins =
1237                                         <0 RK_PC2 1 &pcfg_pull_none_smt>,
1238                                         <0 RK_PC3 1 &pcfg_pull_none_smt>;
1239                         };
1240                 };
1241
1242                 i2c2 {
1243                         i2c2_xfer: i2c2-xfer {
1244                                 rockchip,pins =
1245                                         <2 RK_PB7 2 &pcfg_pull_none_smt>,
1246                                         <2 RK_PC0 2 &pcfg_pull_none_smt>;
1247                         };
1248                 };
1249
1250                 i2c3 {
1251                         i2c3_xfer: i2c3-xfer {
1252                                 rockchip,pins =
1253                                         <1 RK_PB4 4 &pcfg_pull_none_smt>,
1254                                         <1 RK_PB5 4 &pcfg_pull_none_smt>;
1255                         };
1256                 };
1257
1258                 tsadc {
1259                         tsadc_otp_gpio: tsadc-otp-gpio {
1260                                 rockchip,pins =
1261                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1262                         };
1263
1264                         tsadc_otp_out: tsadc-otp-out {
1265                                 rockchip,pins =
1266                                         <0 RK_PA6 1 &pcfg_pull_none>;
1267                         };
1268                 };
1269
1270                 uart0 {
1271                         uart0_xfer: uart0-xfer {
1272                                 rockchip,pins =
1273                                         <0 RK_PB2 1 &pcfg_pull_up>,
1274                                         <0 RK_PB3 1 &pcfg_pull_up>;
1275                         };
1276
1277                         uart0_cts: uart0-cts {
1278                                 rockchip,pins =
1279                                         <0 RK_PB4 1 &pcfg_pull_none>;
1280                         };
1281
1282                         uart0_rts: uart0-rts {
1283                                 rockchip,pins =
1284                                         <0 RK_PB5 1 &pcfg_pull_none>;
1285                         };
1286                 };
1287
1288                 uart1 {
1289                         uart1_xfer: uart1-xfer {
1290                                 rockchip,pins =
1291                                         <1 RK_PC1 1 &pcfg_pull_up>,
1292                                         <1 RK_PC0 1 &pcfg_pull_up>;
1293                         };
1294
1295                         uart1_cts: uart1-cts {
1296                                 rockchip,pins =
1297                                         <1 RK_PC2 1 &pcfg_pull_none>;
1298                         };
1299
1300                         uart1_rts: uart1-rts {
1301                                 rockchip,pins =
1302                                         <1 RK_PC3 1 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 uart2-m0 {
1307                         uart2m0_xfer: uart2m0-xfer {
1308                                 rockchip,pins =
1309                                         <1 RK_PD2 2 &pcfg_pull_up>,
1310                                         <1 RK_PD3 2 &pcfg_pull_up>;
1311                         };
1312                 };
1313
1314                 uart2-m1 {
1315                         uart2m1_xfer: uart2m1-xfer {
1316                                 rockchip,pins =
1317                                         <2 RK_PB4 2 &pcfg_pull_up>,
1318                                         <2 RK_PB6 2 &pcfg_pull_up>;
1319                         };
1320                 };
1321
1322                 uart3-m0 {
1323                         uart3m0_xfer: uart3m0-xfer {
1324                                 rockchip,pins =
1325                                         <0 RK_PC0 2 &pcfg_pull_up>,
1326                                         <0 RK_PC1 2 &pcfg_pull_up>;
1327                         };
1328
1329                         uart3m0_cts: uart3m0-cts {
1330                                 rockchip,pins =
1331                                         <0 RK_PC2 2 &pcfg_pull_none>;
1332                         };
1333
1334                         uart3m0_rts: uart3m0-rts {
1335                                 rockchip,pins =
1336                                         <0 RK_PC3 2 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 uart3-m1 {
1341                         uart3m1_xfer: uart3m1-xfer {
1342                                 rockchip,pins =
1343                                         <1 RK_PB6 2 &pcfg_pull_up>,
1344                                         <1 RK_PB7 2 &pcfg_pull_up>;
1345                         };
1346
1347                         uart3m1_cts: uart3m1-cts {
1348                                 rockchip,pins =
1349                                         <1 RK_PB4 2 &pcfg_pull_none>;
1350                         };
1351
1352                         uart3m1_rts: uart3m1-rts {
1353                                 rockchip,pins =
1354                                         <1 RK_PB5 2 &pcfg_pull_none>;
1355                         };
1356                 };
1357
1358                 uart4 {
1359                         uart4_xfer: uart4-xfer {
1360                                 rockchip,pins =
1361                                         <1 RK_PD4 2 &pcfg_pull_up>,
1362                                         <1 RK_PD5 2 &pcfg_pull_up>;
1363                         };
1364
1365                         uart4_cts: uart4-cts {
1366                                 rockchip,pins =
1367                                         <1 RK_PD6 2 &pcfg_pull_none>;
1368                         };
1369
1370                         uart4_rts: uart4-rts {
1371                                 rockchip,pins =
1372                                         <1 RK_PD7 2 &pcfg_pull_none>;
1373                         };
1374                 };
1375
1376                 uart5 {
1377                         uart5_xfer: uart5-xfer {
1378                                 rockchip,pins =
1379                                         <3 RK_PA2 4 &pcfg_pull_up>,
1380                                         <3 RK_PA1 4 &pcfg_pull_up>;
1381                         };
1382
1383                         uart5_cts: uart5-cts {
1384                                 rockchip,pins =
1385                                         <3 RK_PA3 4 &pcfg_pull_none>;
1386                         };
1387
1388                         uart5_rts: uart5-rts {
1389                                 rockchip,pins =
1390                                         <3 RK_PA5 4 &pcfg_pull_none>;
1391                         };
1392                 };
1393
1394                 spi0 {
1395                         spi0_clk: spi0-clk {
1396                                 rockchip,pins =
1397                                         <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1398                         };
1399
1400                         spi0_csn: spi0-csn {
1401                                 rockchip,pins =
1402                                         <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1403                         };
1404
1405                         spi0_miso: spi0-miso {
1406                                 rockchip,pins =
1407                                         <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1408                         };
1409
1410                         spi0_mosi: spi0-mosi {
1411                                 rockchip,pins =
1412                                         <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1413                         };
1414
1415                         spi0_clk_hs: spi0-clk-hs {
1416                                 rockchip,pins =
1417                                         <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1418                         };
1419
1420                         spi0_miso_hs: spi0-miso-hs {
1421                                 rockchip,pins =
1422                                         <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1423                         };
1424
1425                         spi0_mosi_hs: spi0-mosi-hs {
1426                                 rockchip,pins =
1427                                         <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1428                         };
1429                 };
1430
1431                 spi1 {
1432                         spi1_clk: spi1-clk {
1433                                 rockchip,pins =
1434                                         <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1435                         };
1436
1437                         spi1_csn0: spi1-csn0 {
1438                                 rockchip,pins =
1439                                         <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1440                         };
1441
1442                         spi1_csn1: spi1-csn1 {
1443                                 rockchip,pins =
1444                                         <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1445                         };
1446
1447                         spi1_miso: spi1-miso {
1448                                 rockchip,pins =
1449                                         <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1450                         };
1451
1452                         spi1_mosi: spi1-mosi {
1453                                 rockchip,pins =
1454                                         <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1455                         };
1456
1457                         spi1_clk_hs: spi1-clk-hs {
1458                                 rockchip,pins =
1459                                         <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1460                         };
1461
1462                         spi1_miso_hs: spi1-miso-hs {
1463                                 rockchip,pins =
1464                                         <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1465                         };
1466
1467                         spi1_mosi_hs: spi1-mosi-hs {
1468                                 rockchip,pins =
1469                                         <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1470                         };
1471                 };
1472
1473                 pdm {
1474                         pdm_clk0m0: pdm-clk0m0 {
1475                                 rockchip,pins =
1476                                         <3 RK_PC6 2 &pcfg_pull_none>;
1477                         };
1478
1479                         pdm_clk0m1: pdm-clk0m1 {
1480                                 rockchip,pins =
1481                                         <2 RK_PC6 1 &pcfg_pull_none>;
1482                         };
1483
1484                         pdm_clk1: pdm-clk1 {
1485                                 rockchip,pins =
1486                                         <3 RK_PC7 2 &pcfg_pull_none>;
1487                         };
1488
1489                         pdm_sdi0m0: pdm-sdi0m0 {
1490                                 rockchip,pins =
1491                                         <3 RK_PD3 2 &pcfg_pull_none>;
1492                         };
1493
1494                         pdm_sdi0m1: pdm-sdi0m1 {
1495                                 rockchip,pins =
1496                                         <2 RK_PC5 2 &pcfg_pull_none>;
1497                         };
1498
1499                         pdm_sdi1: pdm-sdi1 {
1500                                 rockchip,pins =
1501                                         <3 RK_PD0 2 &pcfg_pull_none>;
1502                         };
1503
1504                         pdm_sdi2: pdm-sdi2 {
1505                                 rockchip,pins =
1506                                         <3 RK_PD1 2 &pcfg_pull_none>;
1507                         };
1508
1509                         pdm_sdi3: pdm-sdi3 {
1510                                 rockchip,pins =
1511                                         <3 RK_PD2 2 &pcfg_pull_none>;
1512                         };
1513
1514                         pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1515                                 rockchip,pins =
1516                                         <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1517                         };
1518
1519                         pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1520                                 rockchip,pins =
1521                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1522                         };
1523
1524                         pdm_clk1_sleep: pdm-clk1-sleep {
1525                                 rockchip,pins =
1526                                         <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1527                         };
1528
1529                         pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1530                                 rockchip,pins =
1531                                         <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1532                         };
1533
1534                         pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1535                                 rockchip,pins =
1536                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1537                         };
1538
1539                         pdm_sdi1_sleep: pdm-sdi1-sleep {
1540                                 rockchip,pins =
1541                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1542                         };
1543
1544                         pdm_sdi2_sleep: pdm-sdi2-sleep {
1545                                 rockchip,pins =
1546                                         <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1547                         };
1548
1549                         pdm_sdi3_sleep: pdm-sdi3-sleep {
1550                                 rockchip,pins =
1551                                         <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1552                         };
1553                 };
1554
1555                 i2s0 {
1556                         i2s0_8ch_mclk: i2s0-8ch-mclk {
1557                                 rockchip,pins =
1558                                         <3 RK_PC1 2 &pcfg_pull_none>;
1559                         };
1560
1561                         i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1562                                 rockchip,pins =
1563                                         <3 RK_PC3 2 &pcfg_pull_none>;
1564                         };
1565
1566                         i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1567                                 rockchip,pins =
1568                                         <3 RK_PB4 2 &pcfg_pull_none>;
1569                         };
1570
1571                         i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1572                                 rockchip,pins =
1573                                         <3 RK_PC2 2 &pcfg_pull_none>;
1574                         };
1575
1576                         i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1577                                 rockchip,pins =
1578                                         <3 RK_PB5 2 &pcfg_pull_none>;
1579                         };
1580
1581                         i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1582                                 rockchip,pins =
1583                                         <3 RK_PC4 2 &pcfg_pull_none>;
1584                         };
1585
1586                         i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1587                                 rockchip,pins =
1588                                         <3 RK_PC0 2 &pcfg_pull_none>;
1589                         };
1590
1591                         i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1592                                 rockchip,pins =
1593                                         <3 RK_PB7 2 &pcfg_pull_none>;
1594                         };
1595
1596                         i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1597                                 rockchip,pins =
1598                                         <3 RK_PB6 2 &pcfg_pull_none>;
1599                         };
1600
1601                         i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1602                                 rockchip,pins =
1603                                         <3 RK_PC5 2 &pcfg_pull_none>;
1604                         };
1605
1606                         i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1607                                 rockchip,pins =
1608                                         <3 RK_PB3 2 &pcfg_pull_none>;
1609                         };
1610
1611                         i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1612                                 rockchip,pins =
1613                                         <3 RK_PB1 2 &pcfg_pull_none>;
1614                         };
1615
1616                         i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1617                                 rockchip,pins =
1618                                         <3 RK_PB0 2 &pcfg_pull_none>;
1619                         };
1620                 };
1621
1622                 i2s1 {
1623                         i2s1_2ch_mclk: i2s1-2ch-mclk {
1624                                 rockchip,pins =
1625                                         <2 RK_PC3 1 &pcfg_pull_none>;
1626                         };
1627
1628                         i2s1_2ch_sclk: i2s1-2ch-sclk {
1629                                 rockchip,pins =
1630                                         <2 RK_PC2 1 &pcfg_pull_none>;
1631                         };
1632
1633                         i2s1_2ch_lrck: i2s1-2ch-lrck {
1634                                 rockchip,pins =
1635                                         <2 RK_PC1 1 &pcfg_pull_none>;
1636                         };
1637
1638                         i2s1_2ch_sdi: i2s1-2ch-sdi {
1639                                 rockchip,pins =
1640                                         <2 RK_PC5 1 &pcfg_pull_none>;
1641                         };
1642
1643                         i2s1_2ch_sdo: i2s1-2ch-sdo {
1644                                 rockchip,pins =
1645                                         <2 RK_PC4 1 &pcfg_pull_none>;
1646                         };
1647                 };
1648
1649                 i2s2 {
1650                         i2s2_2ch_mclk: i2s2-2ch-mclk {
1651                                 rockchip,pins =
1652                                         <3 RK_PA1 2 &pcfg_pull_none>;
1653                         };
1654
1655                         i2s2_2ch_sclk: i2s2-2ch-sclk {
1656                                 rockchip,pins =
1657                                         <3 RK_PA2 2 &pcfg_pull_none>;
1658                         };
1659
1660                         i2s2_2ch_lrck: i2s2-2ch-lrck {
1661                                 rockchip,pins =
1662                                         <3 RK_PA3 2 &pcfg_pull_none>;
1663                         };
1664
1665                         i2s2_2ch_sdi: i2s2-2ch-sdi {
1666                                 rockchip,pins =
1667                                         <3 RK_PA5 2 &pcfg_pull_none>;
1668                         };
1669
1670                         i2s2_2ch_sdo: i2s2-2ch-sdo {
1671                                 rockchip,pins =
1672                                         <3 RK_PA7 2 &pcfg_pull_none>;
1673                         };
1674                 };
1675
1676                 sdmmc {
1677                         sdmmc_clk: sdmmc-clk {
1678                                 rockchip,pins =
1679                                         <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1680                         };
1681
1682                         sdmmc_cmd: sdmmc-cmd {
1683                                 rockchip,pins =
1684                                         <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1685                         };
1686
1687                         sdmmc_det: sdmmc-det {
1688                                 rockchip,pins =
1689                                         <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1690                         };
1691
1692                         sdmmc_bus1: sdmmc-bus1 {
1693                                 rockchip,pins =
1694                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1695                         };
1696
1697                         sdmmc_bus4: sdmmc-bus4 {
1698                                 rockchip,pins =
1699                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1700                                         <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1701                                         <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1702                                         <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1703                         };
1704                 };
1705
1706                 sdio {
1707                         sdio_clk: sdio-clk {
1708                                 rockchip,pins =
1709                                         <1 RK_PC5 1 &pcfg_pull_none>;
1710                         };
1711
1712                         sdio_cmd: sdio-cmd {
1713                                 rockchip,pins =
1714                                         <1 RK_PC4 1 &pcfg_pull_up>;
1715                         };
1716
1717                         sdio_bus4: sdio-bus4 {
1718                                 rockchip,pins =
1719                                         <1 RK_PC6 1 &pcfg_pull_up>,
1720                                         <1 RK_PC7 1 &pcfg_pull_up>,
1721                                         <1 RK_PD0 1 &pcfg_pull_up>,
1722                                         <1 RK_PD1 1 &pcfg_pull_up>;
1723                         };
1724                 };
1725
1726                 emmc {
1727                         emmc_clk: emmc-clk {
1728                                 rockchip,pins =
1729                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1730                         };
1731
1732                         emmc_cmd: emmc-cmd {
1733                                 rockchip,pins =
1734                                         <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1735                         };
1736
1737                         emmc_rstnout: emmc-rstnout {
1738                                 rockchip,pins =
1739                                         <1 RK_PB3 2 &pcfg_pull_none>;
1740                         };
1741
1742                         emmc_bus1: emmc-bus1 {
1743                                 rockchip,pins =
1744                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1745                         };
1746
1747                         emmc_bus4: emmc-bus4 {
1748                                 rockchip,pins =
1749                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1750                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1751                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1752                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1753                         };
1754
1755                         emmc_bus8: emmc-bus8 {
1756                                 rockchip,pins =
1757                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1758                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1759                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1760                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1761                                         <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1762                                         <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1763                                         <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1764                                         <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1765                         };
1766                 };
1767
1768                 flash {
1769                         flash_cs0: flash-cs0 {
1770                                 rockchip,pins =
1771                                         <1 RK_PB0 1 &pcfg_pull_none>;
1772                         };
1773
1774                         flash_rdy: flash-rdy {
1775                                 rockchip,pins =
1776                                         <1 RK_PB1 1 &pcfg_pull_none>;
1777                         };
1778
1779                         flash_dqs: flash-dqs {
1780                                 rockchip,pins =
1781                                         <1 RK_PB2 1 &pcfg_pull_none>;
1782                         };
1783
1784                         flash_ale: flash-ale {
1785                                 rockchip,pins =
1786                                         <1 RK_PB3 1 &pcfg_pull_none>;
1787                         };
1788
1789                         flash_cle: flash-cle {
1790                                 rockchip,pins =
1791                                         <1 RK_PB4 1 &pcfg_pull_none>;
1792                         };
1793
1794                         flash_wrn: flash-wrn {
1795                                 rockchip,pins =
1796                                         <1 RK_PB5 1 &pcfg_pull_none>;
1797                         };
1798
1799                         flash_csl: flash-csl {
1800                                 rockchip,pins =
1801                                         <1 RK_PB6 1 &pcfg_pull_none>;
1802                         };
1803
1804                         flash_rdn: flash-rdn {
1805                                 rockchip,pins =
1806                                         <1 RK_PB7 1 &pcfg_pull_none>;
1807                         };
1808
1809                         flash_bus8: flash-bus8 {
1810                                 rockchip,pins =
1811                                         <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1812                                         <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1813                                         <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1814                                         <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1815                                         <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1816                                         <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1817                                         <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1818                                         <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1819                         };
1820                 };
1821
1822                 lcdc {
1823                         lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1824                                 rockchip,pins =
1825                                         <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1826                         };
1827
1828                         lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1829                                 rockchip,pins =
1830                                         <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1831                         };
1832
1833                         lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1834                                 rockchip,pins =
1835                                         <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1836                         };
1837
1838                         lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1839                                 rockchip,pins =
1840                                         <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1841                         };
1842
1843                         lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1844                                 rockchip,pins =
1845                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1846                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1847                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1848                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1849                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1850                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1851                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1852                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1853                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1854                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1855                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1856                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1857                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1858                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1859                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1860                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1861                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1862                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1863                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1864                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1865                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1866                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1867                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1868                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1869                         };
1870
1871                         lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1872                                 rockchip,pins =
1873                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1874                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1875                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1876                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1877                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1878                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1879                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1880                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1881                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1882                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1883                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1884                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1885                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1886                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1887                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1888                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1889                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1890                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1891                         };
1892
1893                         lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
1894                                 rockchip,pins =
1895                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1896                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1897                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1898                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1899                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1900                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1901                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1902                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1903                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1904                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1905                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1906                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1907                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1908                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1909                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1910                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1911                         };
1912
1913                         lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
1914                                 rockchip,pins =
1915                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1916                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1917                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1918                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1919                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1920                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1921                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1922                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1923                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1924                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1925                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1926                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1927                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1928                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1929                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1930                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1931                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1932                         };
1933
1934                         lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
1935                                 rockchip,pins =
1936                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1937                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1938                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1939                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1940                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1941                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1942                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1943                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1944                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1945                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1946                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1947                         };
1948
1949                         lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
1950                                 rockchip,pins =
1951                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1952                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1953                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1954                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1955                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1956                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1957                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1958                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1959                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1960                         };
1961                 };
1962
1963                 pwm0 {
1964                         pwm0_pin: pwm0-pin {
1965                                 rockchip,pins =
1966                                         <0 RK_PB7 1 &pcfg_pull_none>;
1967                         };
1968                 };
1969
1970                 pwm1 {
1971                         pwm1_pin: pwm1-pin {
1972                                 rockchip,pins =
1973                                         <0 RK_PC0 1 &pcfg_pull_none>;
1974                         };
1975                 };
1976
1977                 pwm2 {
1978                         pwm2_pin: pwm2-pin {
1979                                 rockchip,pins =
1980                                         <2 RK_PB5 1 &pcfg_pull_none>;
1981                         };
1982                 };
1983
1984                 pwm3 {
1985                         pwm3_pin: pwm3-pin {
1986                                 rockchip,pins =
1987                                         <0 RK_PC1 1 &pcfg_pull_none>;
1988                         };
1989                 };
1990
1991                 pwm4 {
1992                         pwm4_pin: pwm4-pin {
1993                                 rockchip,pins =
1994                                         <3 RK_PC2 3 &pcfg_pull_none>;
1995                         };
1996                 };
1997
1998                 pwm5 {
1999                         pwm5_pin: pwm5-pin {
2000                                 rockchip,pins =
2001                                         <3 RK_PC3 3 &pcfg_pull_none>;
2002                         };
2003                 };
2004
2005                 pwm6 {
2006                         pwm6_pin: pwm6-pin {
2007                                 rockchip,pins =
2008                                         <3 RK_PC4 3 &pcfg_pull_none>;
2009                         };
2010                 };
2011
2012                 pwm7 {
2013                         pwm7_pin: pwm7-pin {
2014                                 rockchip,pins =
2015                                         <3 RK_PC5 3 &pcfg_pull_none>;
2016                         };
2017                 };
2018
2019                 gmac {
2020                         rmii_pins: rmii-pins {
2021                                 rockchip,pins =
2022                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2023                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2024                                         <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2025                                         <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2026                                         <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2027                                         <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2028                                         <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2029                                         <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2030                                         <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2031                         };
2032
2033                         mac_refclk_12ma: mac-refclk-12ma {
2034                                 rockchip,pins =
2035                                         <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2036                         };
2037
2038                         mac_refclk: mac-refclk {
2039                                 rockchip,pins =
2040                                         <2 RK_PB2 2 &pcfg_pull_none>;
2041                         };
2042                 };
2043
2044                 cif-m0 {
2045                         cif_clkout_m0: cif-clkout-m0 {
2046                                 rockchip,pins =
2047                                         <2 RK_PB3 1 &pcfg_pull_none>;
2048                         };
2049
2050                         dvp_d2d9_m0: dvp-d2d9-m0 {
2051                                 rockchip,pins =
2052                                         <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2053                                         <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2054                                         <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2055                                         <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2056                                         <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2057                                         <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2058                                         <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2059                                         <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2060                                         <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2061                                         <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2062                                         <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2063                                         <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2064                         };
2065
2066                         dvp_d0d1_m0: dvp-d0d1-m0 {
2067                                 rockchip,pins =
2068                                         <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2069                                         <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2070                         };
2071
2072                         dvp_d10d11_m0:d10-d11-m0 {
2073                                 rockchip,pins =
2074                                         <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2075                                         <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2076                         };
2077                 };
2078
2079                 cif-m1 {
2080                         cif_clkout_m1: cif-clkout-m1 {
2081                                 rockchip,pins =
2082                                         <3 RK_PD0 3 &pcfg_pull_none>;
2083                         };
2084
2085                         dvp_d2d9_m1: dvp-d2d9-m1 {
2086                                 rockchip,pins =
2087                                         <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2088                                         <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2089                                         <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2090                                         <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2091                                         <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2092                                         <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2093                                         <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2094                                         <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2095                                         <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2096                                         <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2097                                         <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2098                                         <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2099                         };
2100
2101                         dvp_d0d1_m1: dvp-d0d1-m1 {
2102                                 rockchip,pins =
2103                                         <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2104                                         <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2105                         };
2106
2107                         dvp_d10d11_m1:d10-d11-m1 {
2108                                 rockchip,pins =
2109                                         <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2110                                         <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2111                         };
2112                 };
2113
2114                 isp {
2115                         isp_prelight: isp-prelight {
2116                                 rockchip,pins =
2117                                         <3 RK_PD1 4 &pcfg_pull_none>;
2118                         };
2119                 };
2120         };
2121 };