arch/arm64/boot/dts/rockchip/px30.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/px30-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/px30-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13
  14 / {
  15         compatible = "rockchip,px30";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 serial4 = &uart4;
  32                 serial5 = &uart5;
  33                 spi0 = &spi0;
  34                 spi1 = &spi1;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a35";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         clocks = <&cru ARMCLK>;
  47                         #cooling-cells = <2>;
  48                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  49                         dynamic-power-coefficient = <90>;
  50                         operating-points-v2 = <&cpu0_opp_table>;
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a35";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         clocks = <&cru ARMCLK>;
  59                         #cooling-cells = <2>;
  60                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  61                         dynamic-power-coefficient = <90>;
  62                         operating-points-v2 = <&cpu0_opp_table>;
  63                 };
  64
  65                 cpu2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a35";
  68                         reg = <0x0 0x2>;
  69                         enable-method = "psci";
  70                         clocks = <&cru ARMCLK>;
  71                         #cooling-cells = <2>;
  72                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  73                         dynamic-power-coefficient = <90>;
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a35";
  80                         reg = <0x0 0x3>;
  81                         enable-method = "psci";
  82                         clocks = <&cru ARMCLK>;
  83                         #cooling-cells = <2>;
  84                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  85                         dynamic-power-coefficient = <90>;
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                 };
  88
  89                 idle-states {
  90                         entry-method = "psci";
  91
  92                         CPU_SLEEP: cpu-sleep {
  93                                 compatible = "arm,idle-state";
  94                                 local-timer-stop;
  95                                 arm,psci-suspend-param = <0x0010000>;
  96                                 entry-latency-us = <120>;
  97                                 exit-latency-us = <250>;
  98                                 min-residency-us = <900>;
  99                         };
 100
 101                         CLUSTER_SLEEP: cluster-sleep {
 102                                 compatible = "arm,idle-state";
 103                                 local-timer-stop;
 104                                 arm,psci-suspend-param = <0x1010000>;
 105                                 entry-latency-us = <400>;
 106                                 exit-latency-us = <500>;
 107                                 min-residency-us = <2000>;
 108                         };
 109                 };
 110         };
 111
 112         cpu0_opp_table: cpu0-opp-table {
 113                 compatible = "operating-points-v2";
 114                 opp-shared;
 115
 116                 opp-408000000 {
 117                         opp-hz = /bits/ 64 <408000000>;
 118                         opp-microvolt = <950000 950000 1350000>;
 119                         clock-latency-ns = <40000>;
 120                         opp-suspend;
 121                 };
 122                 opp-600000000 {
 123                         opp-hz = /bits/ 64 <600000000>;
 124                         opp-microvolt = <950000 950000 1350000>;
 125                         clock-latency-ns = <40000>;
 126                 };
 127                 opp-816000000 {
 128                         opp-hz = /bits/ 64 <816000000>;
 129                         opp-microvolt = <1050000 1050000 1350000>;
 130                         clock-latency-ns = <40000>;
 131                 };
 132                 opp-1008000000 {
 133                         opp-hz = /bits/ 64 <1008000000>;
 134                         opp-microvolt = <1175000 1175000 1350000>;
 135                         clock-latency-ns = <40000>;
 136                 };
 137                 opp-1200000000 {
 138                         opp-hz = /bits/ 64 <1200000000>;
 139                         opp-microvolt = <1300000 1300000 1350000>;
 140                         clock-latency-ns = <40000>;
 141                 };
 142                 opp-1296000000 {
 143                         opp-hz = /bits/ 64 <1296000000>;
 144                         opp-microvolt = <1350000 1350000 1350000>;
 145                         clock-latency-ns = <40000>;
 146                 };
 147         };
 148
 149         arm-pmu {
 150                 compatible = "arm,cortex-a53-pmu";
 151                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 155                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 156         };
 157
 158         display_subsystem: display-subsystem {
 159                 compatible = "rockchip,display-subsystem";
 160                 ports = <&vopb_out>, <&vopl_out>;
 161                 status = "disabled";
 162         };
 163
 164         firmware {
 165                 optee {
 166                         compatible = "linaro,optee-tz";
 167                         method = "smc";
 168                 };
 169         };
 170
 171         gmac_clkin: external-gmac-clock {
 172                 compatible = "fixed-clock";
 173                 clock-frequency = <50000000>;
 174                 clock-output-names = "gmac_clkin";
 175                 #clock-cells = <0>;
 176         };
 177
 178         psci {
 179                 compatible = "arm,psci-1.0";
 180                 method = "smc";
 181         };
 182
 183         timer {
 184                 compatible = "arm,armv8-timer";
 185                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 186                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 187                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 188                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 189         };
 190
 191         xin24m: xin24m {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <24000000>;
 195                 clock-output-names = "xin24m";
 196         };
 197
 198         pmu: power-management@ff000000 {
 199                 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
 200                 reg = <0x0 0xff000000 0x0 0x1000>;
 201
 202                 power: power-controller {
 203                         compatible = "rockchip,px30-power-controller";
 204                         #power-domain-cells = <1>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207
 208                         /* These power domains are grouped by VD_LOGIC */
 209                         pd_usb@PX30_PD_USB {
 210                                 reg = <PX30_PD_USB>;
 211                                 clocks = <&cru HCLK_HOST>,
 212                                          <&cru HCLK_OTG>,
 213                                          <&cru SCLK_OTG_ADP>;
 214                                 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
 215                         };
 216                         pd_sdcard@PX30_PD_SDCARD {
 217                                 reg = <PX30_PD_SDCARD>;
 218                                 clocks = <&cru HCLK_SDMMC>,
 219                                          <&cru SCLK_SDMMC>;
 220                                 pm_qos = <&qos_sdmmc>;
 221                         };
 222                         pd_gmac@PX30_PD_GMAC {
 223                                 reg = <PX30_PD_GMAC>;
 224                                 clocks = <&cru ACLK_GMAC>,
 225                                          <&cru PCLK_GMAC>,
 226                                          <&cru SCLK_MAC_REF>,
 227                                          <&cru SCLK_GMAC_RX_TX>;
 228                                 pm_qos = <&qos_gmac>;
 229                         };
 230                         pd_mmc_nand@PX30_PD_MMC_NAND {
 231                                 reg = <PX30_PD_MMC_NAND>;
 232                                 clocks =  <&cru HCLK_NANDC>,
 233                                           <&cru HCLK_EMMC>,
 234                                           <&cru HCLK_SDIO>,
 235                                           <&cru HCLK_SFC>,
 236                                           <&cru SCLK_EMMC>,
 237                                           <&cru SCLK_NANDC>,
 238                                           <&cru SCLK_SDIO>,
 239                                           <&cru SCLK_SFC>;
 240                                 pm_qos = <&qos_emmc>, <&qos_nand>,
 241                                          <&qos_sdio>, <&qos_sfc>;
 242                         };
 243                         pd_vpu@PX30_PD_VPU {
 244                                 reg = <PX30_PD_VPU>;
 245                                 clocks = <&cru ACLK_VPU>,
 246                                          <&cru HCLK_VPU>,
 247                                          <&cru SCLK_CORE_VPU>;
 248                                 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
 249                         };
 250                         pd_vo@PX30_PD_VO {
 251                                 reg = <PX30_PD_VO>;
 252                                 clocks = <&cru ACLK_RGA>,
 253                                          <&cru ACLK_VOPB>,
 254                                          <&cru ACLK_VOPL>,
 255                                          <&cru DCLK_VOPB>,
 256                                          <&cru DCLK_VOPL>,
 257                                          <&cru HCLK_RGA>,
 258                                          <&cru HCLK_VOPB>,
 259                                          <&cru HCLK_VOPL>,
 260                                          <&cru PCLK_MIPI_DSI>,
 261                                          <&cru SCLK_RGA_CORE>,
 262                                          <&cru SCLK_VOPB_PWM>;
 263                                 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 264                                          <&qos_vop_m0>, <&qos_vop_m1>;
 265                         };
 266                         pd_vi@PX30_PD_VI {
 267                                 reg = <PX30_PD_VI>;
 268                                 clocks = <&cru ACLK_CIF>,
 269                                          <&cru ACLK_ISP>,
 270                                          <&cru HCLK_CIF>,
 271                                          <&cru HCLK_ISP>,
 272                                          <&cru SCLK_ISP>;
 273                                 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 274                                          <&qos_isp_wr>, <&qos_isp_m1>,
 275                                          <&qos_vip>;
 276                         };
 277                         pd_gpu@PX30_PD_GPU {
 278                                 reg = <PX30_PD_GPU>;
 279                                 clocks = <&cru SCLK_GPU>;
 280                                 pm_qos = <&qos_gpu>;
 281                         };
 282                 };
 283         };
 284
 285         pmugrf: syscon@ff010000 {
 286                 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
 287                 reg = <0x0 0xff010000 0x0 0x1000>;
 288                 #address-cells = <1>;
 289                 #size-cells = <1>;
 290
 291                 pmu_io_domains: io-domains {
 292                         compatible = "rockchip,px30-pmu-io-voltage-domain";
 293                         status = "disabled";
 294                 };
 295
 296                 reboot-mode {
 297                         compatible = "syscon-reboot-mode";
 298                         offset = <0x200>;
 299                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 300                         mode-fastboot = <BOOT_FASTBOOT>;
 301                         mode-loader = <BOOT_BL_DOWNLOAD>;
 302                         mode-normal = <BOOT_NORMAL>;
 303                         mode-recovery = <BOOT_RECOVERY>;
 304                 };
 305         };
 306
 307         uart0: serial@ff030000 {
 308                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 309                 reg = <0x0 0xff030000 0x0 0x100>;
 310                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 311                 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 312                 clock-names = "baudclk", "apb_pclk";
 313                 dmas = <&dmac 0>, <&dmac 1>;
 314                 dma-names = "tx", "rx";
 315                 reg-shift = <2>;
 316                 reg-io-width = <4>;
 317                 pinctrl-names = "default";
 318                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 319                 status = "disabled";
 320         };
 321
 322         i2s1_2ch: i2s@ff070000 {
 323                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 324                 reg = <0x0 0xff070000 0x0 0x1000>;
 325                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 327                 clock-names = "i2s_clk", "i2s_hclk";
 328                 dmas = <&dmac 18>, <&dmac 19>;
 329                 dma-names = "tx", "rx";
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
 332                              &i2s1_2ch_sdi &i2s1_2ch_sdo>;
 333                 #sound-dai-cells = <0>;
 334                 status = "disabled";
 335         };
 336
 337         i2s2_2ch: i2s@ff080000 {
 338                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 339                 reg = <0x0 0xff080000 0x0 0x1000>;
 340                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 341                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 342                 clock-names = "i2s_clk", "i2s_hclk";
 343                 dmas = <&dmac 20>, <&dmac 21>;
 344                 dma-names = "tx", "rx";
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
 347                              &i2s2_2ch_sdi &i2s2_2ch_sdo>;
 348                 #sound-dai-cells = <0>;
 349                 status = "disabled";
 350         };
 351
 352         gic: interrupt-controller@ff131000 {
 353                 compatible = "arm,gic-400";
 354                 #interrupt-cells = <3>;
 355                 #address-cells = <0>;
 356                 interrupt-controller;
 357                 reg = <0x0 0xff131000 0 0x1000>,
 358                       <0x0 0xff132000 0 0x2000>,
 359                       <0x0 0xff134000 0 0x2000>,
 360                       <0x0 0xff136000 0 0x2000>;
 361                 interrupts = <GIC_PPI 9
 362                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 363         };
 364
 365         grf: syscon@ff140000 {
 366                 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
 367                 reg = <0x0 0xff140000 0x0 0x1000>;
 368                 #address-cells = <1>;
 369                 #size-cells = <1>;
 370
 371                 io_domains: io-domains {
 372                         compatible = "rockchip,px30-io-voltage-domain";
 373                         status = "disabled";
 374                 };
 375         };
 376
 377         uart1: serial@ff158000 {
 378                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 379                 reg = <0x0 0xff158000 0x0 0x100>;
 380                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 382                 clock-names = "baudclk", "apb_pclk";
 383                 dmas = <&dmac 2>, <&dmac 3>;
 384                 dma-names = "tx", "rx";
 385                 reg-shift = <2>;
 386                 reg-io-width = <4>;
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 389                 status = "disabled";
 390         };
 391
 392         uart2: serial@ff160000 {
 393                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 394                 reg = <0x0 0xff160000 0x0 0x100>;
 395                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 397                 clock-names = "baudclk", "apb_pclk";
 398                 dmas = <&dmac 4>, <&dmac 5>;
 399                 dma-names = "tx", "rx";
 400                 reg-shift = <2>;
 401                 reg-io-width = <4>;
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&uart2m0_xfer>;
 404                 status = "disabled";
 405         };
 406
 407         uart3: serial@ff168000 {
 408                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 409                 reg = <0x0 0xff168000 0x0 0x100>;
 410                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 411                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 412                 clock-names = "baudclk", "apb_pclk";
 413                 dmas = <&dmac 6>, <&dmac 7>;
 414                 dma-names = "tx", "rx";
 415                 reg-shift = <2>;
 416                 reg-io-width = <4>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
 419                 status = "disabled";
 420         };
 421
 422         uart4: serial@ff170000 {
 423                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 424                 reg = <0x0 0xff170000 0x0 0x100>;
 425                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 427                 clock-names = "baudclk", "apb_pclk";
 428                 dmas = <&dmac 8>, <&dmac 9>;
 429                 dma-names = "tx", "rx";
 430                 reg-shift = <2>;
 431                 reg-io-width = <4>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 434                 status = "disabled";
 435         };
 436
 437         uart5: serial@ff178000 {
 438                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 439                 reg = <0x0 0xff178000 0x0 0x100>;
 440                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 442                 clock-names = "baudclk", "apb_pclk";
 443                 dmas = <&dmac 10>, <&dmac 11>;
 444                 dma-names = "tx", "rx";
 445                 reg-shift = <2>;
 446                 reg-io-width = <4>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
 449                 status = "disabled";
 450         };
 451
 452         i2c0: i2c@ff180000 {
 453                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 454                 reg = <0x0 0xff180000 0x0 0x1000>;
 455                 clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 456                 clock-names = "i2c", "pclk";
 457                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&i2c0_xfer>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 status = "disabled";
 463         };
 464
 465         i2c1: i2c@ff190000 {
 466                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 467                 reg = <0x0 0xff190000 0x0 0x1000>;
 468                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 469                 clock-names = "i2c", "pclk";
 470                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&i2c1_xfer>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 status = "disabled";
 476         };
 477
 478         i2c2: i2c@ff1a0000 {
 479                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 480                 reg = <0x0 0xff1a0000 0x0 0x1000>;
 481                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 482                 clock-names = "i2c", "pclk";
 483                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&i2c2_xfer>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 status = "disabled";
 489         };
 490
 491         i2c3: i2c@ff1b0000 {
 492                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 493                 reg = <0x0 0xff1b0000 0x0 0x1000>;
 494                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 495                 clock-names = "i2c", "pclk";
 496                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&i2c3_xfer>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 status = "disabled";
 502         };
 503
 504         spi0: spi@ff1d0000 {
 505                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 506                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 507                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 509                 clock-names = "spiclk", "apb_pclk";
 510                 dmas = <&dmac 12>, <&dmac 13>;
 511                 dma-names = "tx", "rx";
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         spi1: spi@ff1d8000 {
 520                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 521                 reg = <0x0 0xff1d8000 0x0 0x1000>;
 522                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 523                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 524                 clock-names = "spiclk", "apb_pclk";
 525                 dmas = <&dmac 14>, <&dmac 15>;
 526                 dma-names = "tx", "rx";
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 status = "disabled";
 532         };
 533
 534         wdt: watchdog@ff1e0000 {
 535                 compatible = "snps,dw-wdt";
 536                 reg = <0x0 0xff1e0000 0x0 0x100>;
 537                 clocks = <&cru PCLK_WDT_NS>;
 538                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 539                 status = "disabled";
 540         };
 541
 542         pwm0: pwm@ff200000 {
 543                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 544                 reg = <0x0 0xff200000 0x0 0x10>;
 545                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 546                 clock-names = "pwm", "pclk";
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&pwm0_pin>;
 549                 #pwm-cells = <3>;
 550                 status = "disabled";
 551         };
 552
 553         pwm1: pwm@ff200010 {
 554                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 555                 reg = <0x0 0xff200010 0x0 0x10>;
 556                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 557                 clock-names = "pwm", "pclk";
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&pwm1_pin>;
 560                 #pwm-cells = <3>;
 561                 status = "disabled";
 562         };
 563
 564         pwm2: pwm@ff200020 {
 565                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 566                 reg = <0x0 0xff200020 0x0 0x10>;
 567                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 568                 clock-names = "pwm", "pclk";
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&pwm2_pin>;
 571                 #pwm-cells = <3>;
 572                 status = "disabled";
 573         };
 574
 575         pwm3: pwm@ff200030 {
 576                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 577                 reg = <0x0 0xff200030 0x0 0x10>;
 578                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 579                 clock-names = "pwm", "pclk";
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pwm3_pin>;
 582                 #pwm-cells = <3>;
 583                 status = "disabled";
 584         };
 585
 586         pwm4: pwm@ff208000 {
 587                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 588                 reg = <0x0 0xff208000 0x0 0x10>;
 589                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 590                 clock-names = "pwm", "pclk";
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&pwm4_pin>;
 593                 #pwm-cells = <3>;
 594                 status = "disabled";
 595         };
 596
 597         pwm5: pwm@ff208010 {
 598                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 599                 reg = <0x0 0xff208010 0x0 0x10>;
 600                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 601                 clock-names = "pwm", "pclk";
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&pwm5_pin>;
 604                 #pwm-cells = <3>;
 605                 status = "disabled";
 606         };
 607
 608         pwm6: pwm@ff208020 {
 609                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 610                 reg = <0x0 0xff208020 0x0 0x10>;
 611                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 612                 clock-names = "pwm", "pclk";
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&pwm6_pin>;
 615                 #pwm-cells = <3>;
 616                 status = "disabled";
 617         };
 618
 619         pwm7: pwm@ff208030 {
 620                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 621                 reg = <0x0 0xff208030 0x0 0x10>;
 622                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 623                 clock-names = "pwm", "pclk";
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&pwm7_pin>;
 626                 #pwm-cells = <3>;
 627                 status = "disabled";
 628         };
 629
 630         rktimer: timer@ff210000 {
 631                 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
 632                 reg = <0x0 0xff210000 0x0 0x1000>;
 633                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 635                 clock-names = "pclk", "timer";
 636         };
 637
 638         amba {
 639                 compatible = "simple-bus";
 640                 #address-cells = <2>;
 641                 #size-cells = <2>;
 642                 ranges;
 643
 644                 dmac: dmac@ff240000 {
 645                         compatible = "arm,pl330", "arm,primecell";
 646                         reg = <0x0 0xff240000 0x0 0x4000>;
 647                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 648                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 649                         clocks = <&cru ACLK_DMAC>;
 650                         clock-names = "apb_pclk";
 651                         #dma-cells = <1>;
 652                 };
 653         };
 654
 655         saradc: saradc@ff288000 {
 656                 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
 657                 reg = <0x0 0xff288000 0x0 0x100>;
 658                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 659                 #io-channel-cells = <1>;
 660                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 661                 clock-names = "saradc", "apb_pclk";
 662                 resets = <&cru SRST_SARADC_P>;
 663                 reset-names = "saradc-apb";
 664                 status = "disabled";
 665         };
 666
 667         cru: clock-controller@ff2b0000 {
 668                 compatible = "rockchip,px30-cru";
 669                 reg = <0x0 0xff2b0000 0x0 0x1000>;
 670                 rockchip,grf = <&grf>;
 671                 #clock-cells = <1>;
 672                 #reset-cells = <1>;
 673
 674                 assigned-clocks = <&cru PLL_NPLL>;
 675                 assigned-clock-rates = <1188000000>;
 676         };
 677
 678         pmucru: clock-controller@ff2bc000 {
 679                 compatible = "rockchip,px30-pmucru";
 680                 reg = <0x0 0xff2bc000 0x0 0x1000>;
 681                 rockchip,grf = <&grf>;
 682                 #clock-cells = <1>;
 683                 #reset-cells = <1>;
 684
 685                 assigned-clocks =
 686                         <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
 687                         <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
 688                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 689                         <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
 690                         <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
 691                 assigned-clock-rates =
 692                         <1200000000>, <100000000>,
 693                         <26000000>, <600000000>,
 694                         <200000000>, <200000000>,
 695                         <150000000>, <150000000>,
 696                         <100000000>, <200000000>;
 697         };
 698
 699         usb20_otg: usb@ff300000 {
 700                 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 701                              "snps,dwc2";
 702                 reg = <0x0 0xff300000 0x0 0x40000>;
 703                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 704                 clocks = <&cru HCLK_OTG>;
 705                 clock-names = "otg";
 706                 dr_mode = "otg";
 707                 g-np-tx-fifo-size = <16>;
 708                 g-rx-fifo-size = <280>;
 709                 g-tx-fifo-size = <256 128 128 64 32 16>;
 710                 g-use-dma;
 711                 power-domains = <&power PX30_PD_USB>;
 712                 status = "disabled";
 713         };
 714
 715         usb_host0_ehci: usb@ff340000 {
 716                 compatible = "generic-ehci";
 717                 reg = <0x0 0xff340000 0x0 0x10000>;
 718                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 719                 clocks = <&cru HCLK_HOST>;
 720                 clock-names = "usbhost";
 721                 power-domains = <&power PX30_PD_USB>;
 722                 status = "disabled";
 723         };
 724
 725         usb_host0_ohci: usb@ff350000 {
 726                 compatible = "generic-ohci";
 727                 reg = <0x0 0xff350000 0x0 0x10000>;
 728                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&cru HCLK_HOST>;
 730                 clock-names = "usbhost";
 731                 power-domains = <&power PX30_PD_USB>;
 732                 status = "disabled";
 733         };
 734
 735         gmac: ethernet@ff360000 {
 736                 compatible = "rockchip,px30-gmac";
 737                 reg = <0x0 0xff360000 0x0 0x10000>;
 738                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 739                 interrupt-names = "macirq";
 740                 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
 741                          <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
 742                          <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 743                          <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
 744                 clock-names = "stmmaceth", "mac_clk_rx",
 745                               "mac_clk_tx", "clk_mac_ref",
 746                               "clk_mac_refout", "aclk_mac",
 747                               "pclk_mac", "clk_mac_speed";
 748                 rockchip,grf = <&grf>;
 749                 phy-mode = "rmii";
 750                 pinctrl-names = "default";
 751                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 752                 power-domains = <&power PX30_PD_GMAC>;
 753                 resets = <&cru SRST_GMAC_A>;
 754                 reset-names = "stmmaceth";
 755                 status = "disabled";
 756         };
 757
 758         sdmmc: dwmmc@ff370000 {
 759                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 760                 reg = <0x0 0xff370000 0x0 0x4000>;
 761                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 763                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 764                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 765                 fifo-depth = <0x100>;
 766                 max-frequency = <150000000>;
 767                 pinctrl-names = "default";
 768                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 769                 power-domains = <&power PX30_PD_SDCARD>;
 770                 status = "disabled";
 771         };
 772
 773         sdio: dwmmc@ff380000 {
 774                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 775                 reg = <0x0 0xff380000 0x0 0x4000>;
 776                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 777                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 778                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 779                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 780                 fifo-depth = <0x100>;
 781                 max-frequency = <150000000>;
 782                 pinctrl-names = "default";
 783                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 784                 power-domains = <&power PX30_PD_MMC_NAND>;
 785                 status = "disabled";
 786         };
 787
 788         emmc: dwmmc@ff390000 {
 789                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 790                 reg = <0x0 0xff390000 0x0 0x4000>;
 791                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 792                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 793                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 794                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 795                 fifo-depth = <0x100>;
 796                 max-frequency = <150000000>;
 797                 pinctrl-names = "default";
 798                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 799                 power-domains = <&power PX30_PD_MMC_NAND>;
 800                 status = "disabled";
 801         };
 802
 803         vopb: vop@ff460000 {
 804                 compatible = "rockchip,px30-vop-big";
 805                 reg = <0x0 0xff460000 0x0 0xefc>;
 806                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
 808                          <&cru HCLK_VOPB>;
 809                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 810                 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
 811                 reset-names = "axi", "ahb", "dclk";
 812                 iommus = <&vopb_mmu>;
 813                 power-domains = <&power PX30_PD_VO>;
 814                 rockchip,grf = <&grf>;
 815                 status = "disabled";
 816
 817                 vopb_out: port {
 818                         #address-cells = <1>;
 819                         #size-cells = <0>;
 820                 };
 821         };
 822
 823         vopb_mmu: iommu@ff460f00 {
 824                 compatible = "rockchip,iommu";
 825                 reg = <0x0 0xff460f00 0x0 0x100>;
 826                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 827                 interrupt-names = "vopb_mmu";
 828                 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
 829                 clock-names = "aclk", "iface";
 830                 power-domains = <&power PX30_PD_VO>;
 831                 #iommu-cells = <0>;
 832                 status = "disabled";
 833         };
 834
 835         vopl: vop@ff470000 {
 836                 compatible = "rockchip,px30-vop-lit";
 837                 reg = <0x0 0xff470000 0x0 0xefc>;
 838                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
 840                          <&cru HCLK_VOPL>;
 841                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 842                 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
 843                 reset-names = "axi", "ahb", "dclk";
 844                 iommus = <&vopl_mmu>;
 845                 power-domains = <&power PX30_PD_VO>;
 846                 rockchip,grf = <&grf>;
 847                 status = "disabled";
 848
 849                 vopl_out: port {
 850                         #address-cells = <1>;
 851                         #size-cells = <0>;
 852                 };
 853         };
 854
 855         vopl_mmu: iommu@ff470f00 {
 856                 compatible = "rockchip,iommu";
 857                 reg = <0x0 0xff470f00 0x0 0x100>;
 858                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 859                 interrupt-names = "vopl_mmu";
 860                 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
 861                 clock-names = "aclk", "iface";
 862                 power-domains = <&power PX30_PD_VO>;
 863                 #iommu-cells = <0>;
 864                 status = "disabled";
 865         };
 866
 867         qos_gmac: qos@ff518000 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xff518000 0x0 0x20>;
 870         };
 871
 872         qos_gpu: qos@ff520000 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xff520000 0x0 0x20>;
 875         };
 876
 877         qos_sdmmc: qos@ff52c000 {
 878                 compatible = "syscon";
 879                 reg = <0x0 0xff52c000 0x0 0x20>;
 880         };
 881
 882         qos_emmc: qos@ff538000 {
 883                 compatible = "syscon";
 884                 reg = <0x0 0xff538000 0x0 0x20>;
 885         };
 886
 887         qos_nand: qos@ff538080 {
 888                 compatible = "syscon";
 889                 reg = <0x0 0xff538080 0x0 0x20>;
 890         };
 891
 892         qos_sdio: qos@ff538100 {
 893                 compatible = "syscon";
 894                 reg = <0x0 0xff538100 0x0 0x20>;
 895         };
 896
 897         qos_sfc: qos@ff538180 {
 898                 compatible = "syscon";
 899                 reg = <0x0 0xff538180 0x0 0x20>;
 900         };
 901
 902         qos_usb_host: qos@ff540000 {
 903                 compatible = "syscon";
 904                 reg = <0x0 0xff540000 0x0 0x20>;
 905         };
 906
 907         qos_usb_otg: qos@ff540080 {
 908                 compatible = "syscon";
 909                 reg = <0x0 0xff540080 0x0 0x20>;
 910         };
 911
 912         qos_isp_128: qos@ff548000 {
 913                 compatible = "syscon";
 914                 reg = <0x0 0xff548000 0x0 0x20>;
 915         };
 916
 917         qos_isp_rd: qos@ff548080 {
 918                 compatible = "syscon";
 919                 reg = <0x0 0xff548080 0x0 0x20>;
 920         };
 921
 922         qos_isp_wr: qos@ff548100 {
 923                 compatible = "syscon";
 924                 reg = <0x0 0xff548100 0x0 0x20>;
 925         };
 926
 927         qos_isp_m1: qos@ff548180 {
 928                 compatible = "syscon";
 929                 reg = <0x0 0xff548180 0x0 0x20>;
 930         };
 931
 932         qos_vip: qos@ff548200 {
 933                 compatible = "syscon";
 934                 reg = <0x0 0xff548200 0x0 0x20>;
 935         };
 936
 937         qos_rga_rd: qos@ff550000 {
 938                 compatible = "syscon";
 939                 reg = <0x0 0xff550000 0x0 0x20>;
 940         };
 941
 942         qos_rga_wr: qos@ff550080 {
 943                 compatible = "syscon";
 944                 reg = <0x0 0xff550080 0x0 0x20>;
 945         };
 946
 947         qos_vop_m0: qos@ff550100 {
 948                 compatible = "syscon";
 949                 reg = <0x0 0xff550100 0x0 0x20>;
 950         };
 951
 952         qos_vop_m1: qos@ff550180 {
 953                 compatible = "syscon";
 954                 reg = <0x0 0xff550180 0x0 0x20>;
 955         };
 956
 957         qos_vpu: qos@ff558000 {
 958                 compatible = "syscon";
 959                 reg = <0x0 0xff558000 0x0 0x20>;
 960         };
 961
 962         qos_vpu_r128: qos@ff558080 {
 963                 compatible = "syscon";
 964                 reg = <0x0 0xff558080 0x0 0x20>;
 965         };
 966
 967         pinctrl: pinctrl {
 968                 compatible = "rockchip,px30-pinctrl";
 969                 rockchip,grf = <&grf>;
 970                 rockchip,pmu = <&pmugrf>;
 971                 #address-cells = <2>;
 972                 #size-cells = <2>;
 973                 ranges;
 974
 975                 gpio0: gpio0@ff040000 {
 976                         compatible = "rockchip,gpio-bank";
 977                         reg = <0x0 0xff040000 0x0 0x100>;
 978                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 979                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 980                         gpio-controller;
 981                         #gpio-cells = <2>;
 982
 983                         interrupt-controller;
 984                         #interrupt-cells = <2>;
 985                 };
 986
 987                 gpio1: gpio1@ff250000 {
 988                         compatible = "rockchip,gpio-bank";
 989                         reg = <0x0 0xff250000 0x0 0x100>;
 990                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 991                         clocks = <&cru PCLK_GPIO1>;
 992                         gpio-controller;
 993                         #gpio-cells = <2>;
 994
 995                         interrupt-controller;
 996                         #interrupt-cells = <2>;
 997                 };
 998
 999                 gpio2: gpio2@ff260000 {
1000                         compatible = "rockchip,gpio-bank";
1001                         reg = <0x0 0xff260000 0x0 0x100>;
1002                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1003                         clocks = <&cru PCLK_GPIO2>;
1004                         gpio-controller;
1005                         #gpio-cells = <2>;
1006
1007                         interrupt-controller;
1008                         #interrupt-cells = <2>;
1009                 };
1010
1011                 gpio3: gpio3@ff270000 {
1012                         compatible = "rockchip,gpio-bank";
1013                         reg = <0x0 0xff270000 0x0 0x100>;
1014                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1015                         clocks = <&cru PCLK_GPIO3>;
1016                         gpio-controller;
1017                         #gpio-cells = <2>;
1018
1019                         interrupt-controller;
1020                         #interrupt-cells = <2>;
1021                 };
1022
1023                 pcfg_pull_up: pcfg-pull-up {
1024                         bias-pull-up;
1025                 };
1026
1027                 pcfg_pull_down: pcfg-pull-down {
1028                         bias-pull-down;
1029                 };
1030
1031                 pcfg_pull_none: pcfg-pull-none {
1032                         bias-disable;
1033                 };
1034
1035                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1036                         bias-disable;
1037                         drive-strength = <2>;
1038                 };
1039
1040                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1041                         bias-pull-up;
1042                         drive-strength = <2>;
1043                 };
1044
1045                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1046                         bias-pull-up;
1047                         drive-strength = <4>;
1048                 };
1049
1050                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1051                         bias-disable;
1052                         drive-strength = <4>;
1053                 };
1054
1055                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1056                         bias-pull-down;
1057                         drive-strength = <4>;
1058                 };
1059
1060                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1061                         bias-disable;
1062                         drive-strength = <8>;
1063                 };
1064
1065                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1066                         bias-pull-up;
1067                         drive-strength = <8>;
1068                 };
1069
1070                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1071                         bias-disable;
1072                         drive-strength = <12>;
1073                 };
1074
1075                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1076                         bias-pull-up;
1077                         drive-strength = <12>;
1078                 };
1079
1080                 pcfg_pull_none_smt: pcfg-pull-none-smt {
1081                         bias-disable;
1082                         input-schmitt-enable;
1083                 };
1084
1085                 pcfg_output_high: pcfg-output-high {
1086                         output-high;
1087                 };
1088
1089                 pcfg_output_low: pcfg-output-low {
1090                         output-low;
1091                 };
1092
1093                 pcfg_input_high: pcfg-input-high {
1094                         bias-pull-up;
1095                         input-enable;
1096                 };
1097
1098                 pcfg_input: pcfg-input {
1099                         input-enable;
1100                 };
1101
1102                 i2c0 {
1103                         i2c0_xfer: i2c0-xfer {
1104                                 rockchip,pins =
1105                                         <0 RK_PB0 1 &pcfg_pull_none_smt>,
1106                                         <0 RK_PB1 1 &pcfg_pull_none_smt>;
1107                         };
1108                 };
1109
1110                 i2c1 {
1111                         i2c1_xfer: i2c1-xfer {
1112                                 rockchip,pins =
1113                                         <0 RK_PC2 1 &pcfg_pull_none_smt>,
1114                                         <0 RK_PC3 1 &pcfg_pull_none_smt>;
1115                         };
1116                 };
1117
1118                 i2c2 {
1119                         i2c2_xfer: i2c2-xfer {
1120                                 rockchip,pins =
1121                                         <2 RK_PB7 2 &pcfg_pull_none_smt>,
1122                                         <2 RK_PC0 2 &pcfg_pull_none_smt>;
1123                         };
1124                 };
1125
1126                 i2c3 {
1127                         i2c3_xfer: i2c3-xfer {
1128                                 rockchip,pins =
1129                                         <1 RK_PB4 4 &pcfg_pull_none_smt>,
1130                                         <1 RK_PB5 4 &pcfg_pull_none_smt>;
1131                         };
1132                 };
1133
1134                 tsadc {
1135                         tsadc_otp_gpio: tsadc-otp-gpio {
1136                                 rockchip,pins =
1137                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1138                         };
1139
1140                         tsadc_otp_out: tsadc-otp-out {
1141                                 rockchip,pins =
1142                                         <0 RK_PA6 1 &pcfg_pull_none>;
1143                         };
1144                 };
1145
1146                 uart0 {
1147                         uart0_xfer: uart0-xfer {
1148                                 rockchip,pins =
1149                                         <0 RK_PB2 1 &pcfg_pull_up>,
1150                                         <0 RK_PB3 1 &pcfg_pull_up>;
1151                         };
1152
1153                         uart0_cts: uart0-cts {
1154                                 rockchip,pins =
1155                                         <0 RK_PB4 1 &pcfg_pull_none>;
1156                         };
1157
1158                         uart0_rts: uart0-rts {
1159                                 rockchip,pins =
1160                                         <0 RK_PB5 1 &pcfg_pull_none>;
1161                         };
1162                 };
1163
1164                 uart1 {
1165                         uart1_xfer: uart1-xfer {
1166                                 rockchip,pins =
1167                                         <1 RK_PC1 1 &pcfg_pull_up>,
1168                                         <1 RK_PC0 1 &pcfg_pull_up>;
1169                         };
1170
1171                         uart1_cts: uart1-cts {
1172                                 rockchip,pins =
1173                                         <1 RK_PC2 1 &pcfg_pull_none>;
1174                         };
1175
1176                         uart1_rts: uart1-rts {
1177                                 rockchip,pins =
1178                                         <1 RK_PC3 1 &pcfg_pull_none>;
1179                         };
1180                 };
1181
1182                 uart2-m0 {
1183                         uart2m0_xfer: uart2m0-xfer {
1184                                 rockchip,pins =
1185                                         <1 RK_PD2 2 &pcfg_pull_up>,
1186                                         <1 RK_PD3 2 &pcfg_pull_up>;
1187                         };
1188                 };
1189
1190                 uart2-m1 {
1191                         uart2m1_xfer: uart2m1-xfer {
1192                                 rockchip,pins =
1193                                         <2 RK_PB4 2 &pcfg_pull_up>,
1194                                         <2 RK_PB6 2 &pcfg_pull_up>;
1195                         };
1196                 };
1197
1198                 uart3-m0 {
1199                         uart3m0_xfer: uart3m0-xfer {
1200                                 rockchip,pins =
1201                                         <0 RK_PC0 2 &pcfg_pull_up>,
1202                                         <0 RK_PC1 2 &pcfg_pull_up>;
1203                         };
1204
1205                         uart3m0_cts: uart3m0-cts {
1206                                 rockchip,pins =
1207                                         <0 RK_PC2 2 &pcfg_pull_none>;
1208                         };
1209
1210                         uart3m0_rts: uart3m0-rts {
1211                                 rockchip,pins =
1212                                         <0 RK_PC3 2 &pcfg_pull_none>;
1213                         };
1214                 };
1215
1216                 uart3-m1 {
1217                         uart3m1_xfer: uart3m1-xfer {
1218                                 rockchip,pins =
1219                                         <1 RK_PB6 2 &pcfg_pull_up>,
1220                                         <1 RK_PB7 2 &pcfg_pull_up>;
1221                         };
1222
1223                         uart3m1_cts: uart3m1-cts {
1224                                 rockchip,pins =
1225                                         <1 RK_PB4 2 &pcfg_pull_none>;
1226                         };
1227
1228                         uart3m1_rts: uart3m1-rts {
1229                                 rockchip,pins =
1230                                         <1 RK_PB5 2 &pcfg_pull_none>;
1231                         };
1232                 };
1233
1234                 uart4 {
1235                         uart4_xfer: uart4-xfer {
1236                                 rockchip,pins =
1237                                         <1 RK_PD4 2 &pcfg_pull_up>,
1238                                         <1 RK_PD5 2 &pcfg_pull_up>;
1239                         };
1240
1241                         uart4_cts: uart4-cts {
1242                                 rockchip,pins =
1243                                         <1 RK_PD6 2 &pcfg_pull_none>;
1244                         };
1245
1246                         uart4_rts: uart4-rts {
1247                                 rockchip,pins =
1248                                         <1 RK_PD7 2 &pcfg_pull_none>;
1249                         };
1250                 };
1251
1252                 uart5 {
1253                         uart5_xfer: uart5-xfer {
1254                                 rockchip,pins =
1255                                         <3 RK_PA2 4 &pcfg_pull_up>,
1256                                         <3 RK_PA1 4 &pcfg_pull_up>;
1257                         };
1258
1259                         uart5_cts: uart5-cts {
1260                                 rockchip,pins =
1261                                         <3 RK_PA3 4 &pcfg_pull_none>;
1262                         };
1263
1264                         uart5_rts: uart5-rts {
1265                                 rockchip,pins =
1266                                         <3 RK_PA5 4 &pcfg_pull_none>;
1267                         };
1268                 };
1269
1270                 spi0 {
1271                         spi0_clk: spi0-clk {
1272                                 rockchip,pins =
1273                                         <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1274                         };
1275
1276                         spi0_csn: spi0-csn {
1277                                 rockchip,pins =
1278                                         <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1279                         };
1280
1281                         spi0_miso: spi0-miso {
1282                                 rockchip,pins =
1283                                         <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1284                         };
1285
1286                         spi0_mosi: spi0-mosi {
1287                                 rockchip,pins =
1288                                         <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1289                         };
1290
1291                         spi0_clk_hs: spi0-clk-hs {
1292                                 rockchip,pins =
1293                                         <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1294                         };
1295
1296                         spi0_miso_hs: spi0-miso-hs {
1297                                 rockchip,pins =
1298                                         <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1299                         };
1300
1301                         spi0_mosi_hs: spi0-mosi-hs {
1302                                 rockchip,pins =
1303                                         <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1304                         };
1305                 };
1306
1307                 spi1 {
1308                         spi1_clk: spi1-clk {
1309                                 rockchip,pins =
1310                                         <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1311                         };
1312
1313                         spi1_csn0: spi1-csn0 {
1314                                 rockchip,pins =
1315                                         <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1316                         };
1317
1318                         spi1_csn1: spi1-csn1 {
1319                                 rockchip,pins =
1320                                         <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1321                         };
1322
1323                         spi1_miso: spi1-miso {
1324                                 rockchip,pins =
1325                                         <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1326                         };
1327
1328                         spi1_mosi: spi1-mosi {
1329                                 rockchip,pins =
1330                                         <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1331                         };
1332
1333                         spi1_clk_hs: spi1-clk-hs {
1334                                 rockchip,pins =
1335                                         <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1336                         };
1337
1338                         spi1_miso_hs: spi1-miso-hs {
1339                                 rockchip,pins =
1340                                         <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1341                         };
1342
1343                         spi1_mosi_hs: spi1-mosi-hs {
1344                                 rockchip,pins =
1345                                         <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1346                         };
1347                 };
1348
1349                 pdm {
1350                         pdm_clk0m0: pdm-clk0m0 {
1351                                 rockchip,pins =
1352                                         <3 RK_PC6 2 &pcfg_pull_none>;
1353                         };
1354
1355                         pdm_clk0m1: pdm-clk0m1 {
1356                                 rockchip,pins =
1357                                         <2 RK_PC6 1 &pcfg_pull_none>;
1358                         };
1359
1360                         pdm_clk1: pdm-clk1 {
1361                                 rockchip,pins =
1362                                         <3 RK_PC7 2 &pcfg_pull_none>;
1363                         };
1364
1365                         pdm_sdi0m0: pdm-sdi0m0 {
1366                                 rockchip,pins =
1367                                         <3 RK_PD3 2 &pcfg_pull_none>;
1368                         };
1369
1370                         pdm_sdi0m1: pdm-sdi0m1 {
1371                                 rockchip,pins =
1372                                         <2 RK_PC5 2 &pcfg_pull_none>;
1373                         };
1374
1375                         pdm_sdi1: pdm-sdi1 {
1376                                 rockchip,pins =
1377                                         <3 RK_PD0 2 &pcfg_pull_none>;
1378                         };
1379
1380                         pdm_sdi2: pdm-sdi2 {
1381                                 rockchip,pins =
1382                                         <3 RK_PD1 2 &pcfg_pull_none>;
1383                         };
1384
1385                         pdm_sdi3: pdm-sdi3 {
1386                                 rockchip,pins =
1387                                         <3 RK_PD2 2 &pcfg_pull_none>;
1388                         };
1389
1390                         pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1391                                 rockchip,pins =
1392                                         <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1393                         };
1394
1395                         pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1396                                 rockchip,pins =
1397                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1398                         };
1399
1400                         pdm_clk1_sleep: pdm-clk1-sleep {
1401                                 rockchip,pins =
1402                                         <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1403                         };
1404
1405                         pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1406                                 rockchip,pins =
1407                                         <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1408                         };
1409
1410                         pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1411                                 rockchip,pins =
1412                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1413                         };
1414
1415                         pdm_sdi1_sleep: pdm-sdi1-sleep {
1416                                 rockchip,pins =
1417                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1418                         };
1419
1420                         pdm_sdi2_sleep: pdm-sdi2-sleep {
1421                                 rockchip,pins =
1422                                         <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1423                         };
1424
1425                         pdm_sdi3_sleep: pdm-sdi3-sleep {
1426                                 rockchip,pins =
1427                                         <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1428                         };
1429                 };
1430
1431                 i2s0 {
1432                         i2s0_8ch_mclk: i2s0-8ch-mclk {
1433                                 rockchip,pins =
1434                                         <3 RK_PC1 2 &pcfg_pull_none>;
1435                         };
1436
1437                         i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1438                                 rockchip,pins =
1439                                         <3 RK_PC3 2 &pcfg_pull_none>;
1440                         };
1441
1442                         i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1443                                 rockchip,pins =
1444                                         <3 RK_PB4 2 &pcfg_pull_none>;
1445                         };
1446
1447                         i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1448                                 rockchip,pins =
1449                                         <3 RK_PC2 2 &pcfg_pull_none>;
1450                         };
1451
1452                         i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1453                                 rockchip,pins =
1454                                         <3 RK_PB5 2 &pcfg_pull_none>;
1455                         };
1456
1457                         i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1458                                 rockchip,pins =
1459                                         <3 RK_PC4 2 &pcfg_pull_none>;
1460                         };
1461
1462                         i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1463                                 rockchip,pins =
1464                                         <3 RK_PC0 2 &pcfg_pull_none>;
1465                         };
1466
1467                         i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1468                                 rockchip,pins =
1469                                         <3 RK_PB7 2 &pcfg_pull_none>;
1470                         };
1471
1472                         i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1473                                 rockchip,pins =
1474                                         <3 RK_PB6 2 &pcfg_pull_none>;
1475                         };
1476
1477                         i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1478                                 rockchip,pins =
1479                                         <3 RK_PC5 2 &pcfg_pull_none>;
1480                         };
1481
1482                         i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1483                                 rockchip,pins =
1484                                         <3 RK_PB3 2 &pcfg_pull_none>;
1485                         };
1486
1487                         i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1488                                 rockchip,pins =
1489                                         <3 RK_PB1 2 &pcfg_pull_none>;
1490                         };
1491
1492                         i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1493                                 rockchip,pins =
1494                                         <3 RK_PB0 2 &pcfg_pull_none>;
1495                         };
1496                 };
1497
1498                 i2s1 {
1499                         i2s1_2ch_mclk: i2s1-2ch-mclk {
1500                                 rockchip,pins =
1501                                         <2 RK_PC3 1 &pcfg_pull_none>;
1502                         };
1503
1504                         i2s1_2ch_sclk: i2s1-2ch-sclk {
1505                                 rockchip,pins =
1506                                         <2 RK_PC2 1 &pcfg_pull_none>;
1507                         };
1508
1509                         i2s1_2ch_lrck: i2s1-2ch-lrck {
1510                                 rockchip,pins =
1511                                         <2 RK_PC1 1 &pcfg_pull_none>;
1512                         };
1513
1514                         i2s1_2ch_sdi: i2s1-2ch-sdi {
1515                                 rockchip,pins =
1516                                         <2 RK_PC5 1 &pcfg_pull_none>;
1517                         };
1518
1519                         i2s1_2ch_sdo: i2s1-2ch-sdo {
1520                                 rockchip,pins =
1521                                         <2 RK_PC4 1 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 i2s2 {
1526                         i2s2_2ch_mclk: i2s2-2ch-mclk {
1527                                 rockchip,pins =
1528                                         <3 RK_PA1 2 &pcfg_pull_none>;
1529                         };
1530
1531                         i2s2_2ch_sclk: i2s2-2ch-sclk {
1532                                 rockchip,pins =
1533                                         <3 RK_PA2 2 &pcfg_pull_none>;
1534                         };
1535
1536                         i2s2_2ch_lrck: i2s2-2ch-lrck {
1537                                 rockchip,pins =
1538                                         <3 RK_PA3 2 &pcfg_pull_none>;
1539                         };
1540
1541                         i2s2_2ch_sdi: i2s2-2ch-sdi {
1542                                 rockchip,pins =
1543                                         <3 RK_PA5 2 &pcfg_pull_none>;
1544                         };
1545
1546                         i2s2_2ch_sdo: i2s2-2ch-sdo {
1547                                 rockchip,pins =
1548                                         <3 RK_PA7 2 &pcfg_pull_none>;
1549                         };
1550                 };
1551
1552                 sdmmc {
1553                         sdmmc_clk: sdmmc-clk {
1554                                 rockchip,pins =
1555                                         <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1556                         };
1557
1558                         sdmmc_cmd: sdmmc-cmd {
1559                                 rockchip,pins =
1560                                         <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1561                         };
1562
1563                         sdmmc_det: sdmmc-det {
1564                                 rockchip,pins =
1565                                         <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1566                         };
1567
1568                         sdmmc_bus1: sdmmc-bus1 {
1569                                 rockchip,pins =
1570                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1571                         };
1572
1573                         sdmmc_bus4: sdmmc-bus4 {
1574                                 rockchip,pins =
1575                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1576                                         <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1577                                         <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1578                                         <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1579                         };
1580                 };
1581
1582                 sdio {
1583                         sdio_clk: sdio-clk {
1584                                 rockchip,pins =
1585                                         <1 RK_PC5 1 &pcfg_pull_none>;
1586                         };
1587
1588                         sdio_cmd: sdio-cmd {
1589                                 rockchip,pins =
1590                                         <1 RK_PC4 1 &pcfg_pull_up>;
1591                         };
1592
1593                         sdio_bus4: sdio-bus4 {
1594                                 rockchip,pins =
1595                                         <1 RK_PC6 1 &pcfg_pull_up>,
1596                                         <1 RK_PC7 1 &pcfg_pull_up>,
1597                                         <1 RK_PD0 1 &pcfg_pull_up>,
1598                                         <1 RK_PD1 1 &pcfg_pull_up>;
1599                         };
1600                 };
1601
1602                 emmc {
1603                         emmc_clk: emmc-clk {
1604                                 rockchip,pins =
1605                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1606                         };
1607
1608                         emmc_cmd: emmc-cmd {
1609                                 rockchip,pins =
1610                                         <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1611                         };
1612
1613                         emmc_rstnout: emmc-rstnout {
1614                                 rockchip,pins =
1615                                         <1 RK_PB3 2 &pcfg_pull_none>;
1616                         };
1617
1618                         emmc_bus1: emmc-bus1 {
1619                                 rockchip,pins =
1620                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1621                         };
1622
1623                         emmc_bus4: emmc-bus4 {
1624                                 rockchip,pins =
1625                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1626                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1627                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1628                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1629                         };
1630
1631                         emmc_bus8: emmc-bus8 {
1632                                 rockchip,pins =
1633                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1634                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1635                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1636                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1637                                         <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1638                                         <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1639                                         <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1640                                         <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1641                         };
1642                 };
1643
1644                 flash {
1645                         flash_cs0: flash-cs0 {
1646                                 rockchip,pins =
1647                                         <1 RK_PB0 1 &pcfg_pull_none>;
1648                         };
1649
1650                         flash_rdy: flash-rdy {
1651                                 rockchip,pins =
1652                                         <1 RK_PB1 1 &pcfg_pull_none>;
1653                         };
1654
1655                         flash_dqs: flash-dqs {
1656                                 rockchip,pins =
1657                                         <1 RK_PB2 1 &pcfg_pull_none>;
1658                         };
1659
1660                         flash_ale: flash-ale {
1661                                 rockchip,pins =
1662                                         <1 RK_PB3 1 &pcfg_pull_none>;
1663                         };
1664
1665                         flash_cle: flash-cle {
1666                                 rockchip,pins =
1667                                         <1 RK_PB4 1 &pcfg_pull_none>;
1668                         };
1669
1670                         flash_wrn: flash-wrn {
1671                                 rockchip,pins =
1672                                         <1 RK_PB5 1 &pcfg_pull_none>;
1673                         };
1674
1675                         flash_csl: flash-csl {
1676                                 rockchip,pins =
1677                                         <1 RK_PB6 1 &pcfg_pull_none>;
1678                         };
1679
1680                         flash_rdn: flash-rdn {
1681                                 rockchip,pins =
1682                                         <1 RK_PB7 1 &pcfg_pull_none>;
1683                         };
1684
1685                         flash_bus8: flash-bus8 {
1686                                 rockchip,pins =
1687                                         <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1688                                         <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1689                                         <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1690                                         <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1691                                         <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1692                                         <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1693                                         <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1694                                         <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1695                         };
1696                 };
1697
1698                 lcdc {
1699                         lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1700                                 rockchip,pins =
1701                                         <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1702                         };
1703
1704                         lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1705                                 rockchip,pins =
1706                                         <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1707                         };
1708
1709                         lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1710                                 rockchip,pins =
1711                                         <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1712                         };
1713
1714                         lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1715                                 rockchip,pins =
1716                                         <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1717                         };
1718
1719                         lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1720                                 rockchip,pins =
1721                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1722                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1723                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1724                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1725                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1726                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1727                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1728                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1729                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1730                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1731                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1732                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1733                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1734                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1735                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1736                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1737                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1738                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1739                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1740                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1741                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1742                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1743                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1744                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1745                         };
1746
1747                         lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1748                                 rockchip,pins =
1749                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1750                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1751                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1752                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1753                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1754                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1755                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1756                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1757                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1758                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1759                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1760                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1761                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1762                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1763                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1764                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1765                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1766                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1767                         };
1768
1769                         lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
1770                                 rockchip,pins =
1771                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1772                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1773                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1774                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1775                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1776                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1777                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1778                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1779                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1780                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1781                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1782                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1783                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1784                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1785                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1786                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1787                         };
1788
1789                         lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
1790                                 rockchip,pins =
1791                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1792                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1793                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1794                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1795                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1796                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1797                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1798                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1799                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1800                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1801                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1802                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1803                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1804                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1805                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1806                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1807                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1808                         };
1809
1810                         lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
1811                                 rockchip,pins =
1812                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1813                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1814                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1815                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1816                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1817                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1818                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1819                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1820                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1821                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1822                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1823                         };
1824
1825                         lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
1826                                 rockchip,pins =
1827                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1828                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1829                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1830                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1831                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1832                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1833                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1834                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1835                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1836                         };
1837                 };
1838
1839                 pwm0 {
1840                         pwm0_pin: pwm0-pin {
1841                                 rockchip,pins =
1842                                         <0 RK_PB7 1 &pcfg_pull_none>;
1843                         };
1844                 };
1845
1846                 pwm1 {
1847                         pwm1_pin: pwm1-pin {
1848                                 rockchip,pins =
1849                                         <0 RK_PC0 1 &pcfg_pull_none>;
1850                         };
1851                 };
1852
1853                 pwm2 {
1854                         pwm2_pin: pwm2-pin {
1855                                 rockchip,pins =
1856                                         <2 RK_PB5 1 &pcfg_pull_none>;
1857                         };
1858                 };
1859
1860                 pwm3 {
1861                         pwm3_pin: pwm3-pin {
1862                                 rockchip,pins =
1863                                         <0 RK_PC1 1 &pcfg_pull_none>;
1864                         };
1865                 };
1866
1867                 pwm4 {
1868                         pwm4_pin: pwm4-pin {
1869                                 rockchip,pins =
1870                                         <3 RK_PC2 3 &pcfg_pull_none>;
1871                         };
1872                 };
1873
1874                 pwm5 {
1875                         pwm5_pin: pwm5-pin {
1876                                 rockchip,pins =
1877                                         <3 RK_PC3 3 &pcfg_pull_none>;
1878                         };
1879                 };
1880
1881                 pwm6 {
1882                         pwm6_pin: pwm6-pin {
1883                                 rockchip,pins =
1884                                         <3 RK_PC4 3 &pcfg_pull_none>;
1885                         };
1886                 };
1887
1888                 pwm7 {
1889                         pwm7_pin: pwm7-pin {
1890                                 rockchip,pins =
1891                                         <3 RK_PC5 3 &pcfg_pull_none>;
1892                         };
1893                 };
1894
1895                 gmac {
1896                         rmii_pins: rmii-pins {
1897                                 rockchip,pins =
1898                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
1899                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
1900                                         <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
1901                                         <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
1902                                         <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
1903                                         <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
1904                                         <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
1905                                         <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
1906                                         <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
1907                         };
1908
1909                         mac_refclk_12ma: mac-refclk-12ma {
1910                                 rockchip,pins =
1911                                         <2 RK_PB2 2 &pcfg_pull_none_12ma>;
1912                         };
1913
1914                         mac_refclk: mac-refclk {
1915                                 rockchip,pins =
1916                                         <2 RK_PB2 2 &pcfg_pull_none>;
1917                         };
1918                 };
1919
1920                 cif-m0 {
1921                         cif_clkout_m0: cif-clkout-m0 {
1922                                 rockchip,pins =
1923                                         <2 RK_PB3 1 &pcfg_pull_none>;
1924                         };
1925
1926                         dvp_d2d9_m0: dvp-d2d9-m0 {
1927                                 rockchip,pins =
1928                                         <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
1929                                         <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
1930                                         <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
1931                                         <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
1932                                         <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
1933                                         <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
1934                                         <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
1935                                         <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
1936                                         <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
1937                                         <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
1938                                         <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
1939                                         <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
1940                         };
1941
1942                         dvp_d0d1_m0: dvp-d0d1-m0 {
1943                                 rockchip,pins =
1944                                         <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
1945                                         <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
1946                         };
1947
1948                         dvp_d10d11_m0:d10-d11-m0 {
1949                                 rockchip,pins =
1950                                         <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
1951                                         <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
1952                         };
1953                 };
1954
1955                 cif-m1 {
1956                         cif_clkout_m1: cif-clkout-m1 {
1957                                 rockchip,pins =
1958                                         <3 RK_PD0 3 &pcfg_pull_none>;
1959                         };
1960
1961                         dvp_d2d9_m1: dvp-d2d9-m1 {
1962                                 rockchip,pins =
1963                                         <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
1964                                         <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
1965                                         <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
1966                                         <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
1967                                         <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
1968                                         <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
1969                                         <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
1970                                         <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
1971                                         <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
1972                                         <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
1973                                         <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
1974                                         <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
1975                         };
1976
1977                         dvp_d0d1_m1: dvp-d0d1-m1 {
1978                                 rockchip,pins =
1979                                         <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
1980                                         <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
1981                         };
1982
1983                         dvp_d10d11_m1:d10-d11-m1 {
1984                                 rockchip,pins =
1985                                         <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
1986                                         <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
1987                         };
1988                 };
1989
1990                 isp {
1991                         isp_prelight: isp-prelight {
1992                                 rockchip,pins =
1993                                         <3 RK_PD1 4 &pcfg_pull_none>;
1994                         };
1995                 };
1996         };
1997 };