arch/arm64/boot/dts/renesas/r9a07g044.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/r9a07g044-cpg.h>
  10
  11 / {
  12         compatible = "renesas,r9a07g044";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         audio_clk1: audio_clk1 {
  17                 compatible = "fixed-clock";
  18                 #clock-cells = <0>;
  19                 /* This value must be overridden by boards that provide it */
  20                 clock-frequency = <0>;
  21         };
  22
  23         audio_clk2: audio_clk2 {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 /* This value must be overridden by boards that provide it */
  27                 clock-frequency = <0>;
  28         };
  29
  30         /* External CAN clock - to be overridden by boards that provide it */
  31         can_clk: can {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <0>;
  35         };
  36
  37         /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
  38         extal_clk: extal {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 /* This value must be overridden by the board */
  42                 clock-frequency = <0>;
  43         };
  44
  45         psci {
  46                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  47                 method = "smc";
  48         };
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu-map {
  55                         cluster0 {
  56                                 core0 {
  57                                         cpu = <&cpu0>;
  58                                 };
  59                                 core1 {
  60                                         cpu = <&cpu1>;
  61                                 };
  62                         };
  63                 };
  64
  65                 cpu0: cpu@0 {
  66                         compatible = "arm,cortex-a55";
  67                         reg = <0>;
  68                         device_type = "cpu";
  69                         next-level-cache = <&L3_CA55>;
  70                         enable-method = "psci";
  71                 };
  72
  73                 cpu1: cpu@100 {
  74                         compatible = "arm,cortex-a55";
  75                         reg = <0x100>;
  76                         device_type = "cpu";
  77                         next-level-cache = <&L3_CA55>;
  78                         enable-method = "psci";
  79                 };
  80
  81                 L3_CA55: cache-controller-0 {
  82                         compatible = "cache";
  83                         cache-unified;
  84                         cache-size = <0x40000>;
  85                 };
  86         };
  87
  88         soc: soc {
  89                 compatible = "simple-bus";
  90                 interrupt-parent = <&gic>;
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93                 ranges;
  94
  95                 ssi0: ssi@10049c00 {
  96                         compatible = "renesas,r9a07g044-ssi",
  97                                      "renesas,rz-ssi";
  98                         reg = <0 0x10049c00 0 0x400>;
  99                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 100                                      <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
 101                                      <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
 102                                      <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
 103                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 104                         clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
 105                                  <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
 106                                  <&audio_clk1>, <&audio_clk2>;
 107                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 108                         resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
 109                         dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 110                         dma-names = "tx", "rx";
 111                         power-domains = <&cpg>;
 112                         #sound-dai-cells = <0>;
 113                         status = "disabled";
 114                 };
 115
 116                 ssi1: ssi@1004a000 {
 117                         compatible = "renesas,r9a07g044-ssi",
 118                                      "renesas,rz-ssi";
 119                         reg = <0 0x1004a000 0 0x400>;
 120                         interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
 122                                      <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
 123                                      <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
 124                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 125                         clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
 126                                  <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
 127                                  <&audio_clk1>, <&audio_clk2>;
 128                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 129                         resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
 130                         dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 131                         dma-names = "tx", "rx";
 132                         power-domains = <&cpg>;
 133                         #sound-dai-cells = <0>;
 134                         status = "disabled";
 135                 };
 136
 137                 ssi2: ssi@1004a400 {
 138                         compatible = "renesas,r9a07g044-ssi",
 139                                      "renesas,rz-ssi";
 140                         reg = <0 0x1004a400 0 0x400>;
 141                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
 143                                      <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
 144                                      <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
 145                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 146                         clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
 147                                  <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
 148                                  <&audio_clk1>, <&audio_clk2>;
 149                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 150                         resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
 151                         dmas = <&dmac 0x265f>;
 152                         dma-names = "rt";
 153                         power-domains = <&cpg>;
 154                         #sound-dai-cells = <0>;
 155                         status = "disabled";
 156                 };
 157
 158                 ssi3: ssi@1004a800 {
 159                         compatible = "renesas,r9a07g044-ssi",
 160                                      "renesas,rz-ssi";
 161                         reg = <0 0x1004a800 0 0x400>;
 162                         interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 163                                      <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
 164                                      <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
 165                                      <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
 166                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 167                         clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
 168                                  <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
 169                                  <&audio_clk1>, <&audio_clk2>;
 170                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 171                         resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
 172                         dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 173                         dma-names = "tx", "rx";
 174                         power-domains = <&cpg>;
 175                         #sound-dai-cells = <0>;
 176                         status = "disabled";
 177                 };
 178
 179                 scif0: serial@1004b800 {
 180                         compatible = "renesas,scif-r9a07g044";
 181                         reg = <0 0x1004b800 0 0x400>;
 182                         interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 188                         interrupt-names = "eri", "rxi", "txi",
 189                                           "bri", "dri", "tei";
 190                         clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
 191                         clock-names = "fck";
 192                         power-domains = <&cpg>;
 193                         resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
 194                         status = "disabled";
 195                 };
 196
 197                 scif1: serial@1004bc00 {
 198                         compatible = "renesas,scif-r9a07g044";
 199                         reg = <0 0x1004bc00 0 0x400>;
 200                         interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
 206                         interrupt-names = "eri", "rxi", "txi",
 207                                           "bri", "dri", "tei";
 208                         clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
 209                         clock-names = "fck";
 210                         power-domains = <&cpg>;
 211                         resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
 212                         status = "disabled";
 213                 };
 214
 215                 scif2: serial@1004c000 {
 216                         compatible = "renesas,scif-r9a07g044";
 217                         reg = <0 0x1004c000 0 0x400>;
 218                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
 224                         interrupt-names = "eri", "rxi", "txi",
 225                                           "bri", "dri", "tei";
 226                         clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
 227                         clock-names = "fck";
 228                         power-domains = <&cpg>;
 229                         resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
 230                         status = "disabled";
 231                 };
 232
 233                 scif3: serial@1004c400 {
 234                         compatible = "renesas,scif-r9a07g044";
 235                         reg = <0 0x1004c400 0 0x400>;
 236                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 242                         interrupt-names = "eri", "rxi", "txi",
 243                                           "bri", "dri", "tei";
 244                         clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
 245                         clock-names = "fck";
 246                         power-domains = <&cpg>;
 247                         resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
 248                         status = "disabled";
 249                 };
 250
 251                 scif4: serial@1004c800 {
 252                         compatible = "renesas,scif-r9a07g044";
 253                         reg = <0 0x1004c800 0 0x400>;
 254                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 258                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 259                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 260                         interrupt-names = "eri", "rxi", "txi",
 261                                           "bri", "dri", "tei";
 262                         clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
 263                         clock-names = "fck";
 264                         power-domains = <&cpg>;
 265                         resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
 266                         status = "disabled";
 267                 };
 268
 269                 sci0: serial@1004d000 {
 270                         compatible = "renesas,r9a07g044-sci", "renesas,sci";
 271                         reg = <0 0x1004d000 0 0x400>;
 272                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 276                         interrupt-names = "eri", "rxi", "txi", "tei";
 277                         clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
 278                         clock-names = "fck";
 279                         power-domains = <&cpg>;
 280                         resets = <&cpg R9A07G044_SCI0_RST>;
 281                         status = "disabled";
 282                 };
 283
 284                 sci1: serial@1004d400 {
 285                         compatible = "renesas,r9a07g044-sci", "renesas,sci";
 286                         reg = <0 0x1004d400 0 0x400>;
 287                         interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 291                         interrupt-names = "eri", "rxi", "txi", "tei";
 292                         clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
 293                         clock-names = "fck";
 294                         power-domains = <&cpg>;
 295                         resets = <&cpg R9A07G044_SCI1_RST>;
 296                         status = "disabled";
 297                 };
 298
 299                 canfd: can@10050000 {
 300                         compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
 301                         reg = <0 0x10050000 0 0x8000>;
 302                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 310                         interrupt-names = "g_err", "g_recc",
 311                                           "ch0_err", "ch0_rec", "ch0_trx",
 312                                           "ch1_err", "ch1_rec", "ch1_trx";
 313                         clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
 314                                  <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
 315                                  <&can_clk>;
 316                         clock-names = "fck", "canfd", "can_clk";
 317                         assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
 318                         assigned-clock-rates = <50000000>;
 319                         resets = <&cpg R9A07G044_CANFD_RSTP_N>,
 320                                  <&cpg R9A07G044_CANFD_RSTC_N>;
 321                         reset-names = "rstp_n", "rstc_n";
 322                         power-domains = <&cpg>;
 323                         status = "disabled";
 324
 325                         channel0 {
 326                                 status = "disabled";
 327                         };
 328                         channel1 {
 329                                 status = "disabled";
 330                         };
 331                 };
 332
 333                 i2c0: i2c@10058000 {
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 337                         reg = <0 0x10058000 0 0x400>;
 338                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 339                                      <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
 340                                      <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
 341                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
 344                                      <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 346                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 347                                           "naki", "ali", "tmoi";
 348                         clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
 349                         clock-frequency = <100000>;
 350                         resets = <&cpg R9A07G044_I2C0_MRST>;
 351                         power-domains = <&cpg>;
 352                         status = "disabled";
 353                 };
 354
 355                 i2c1: i2c@10058400 {
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 359                         reg = <0 0x10058400 0 0x400>;
 360                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
 362                                      <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
 363                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
 367                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
 368                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 369                                           "naki", "ali", "tmoi";
 370                         clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
 371                         clock-frequency = <100000>;
 372                         resets = <&cpg R9A07G044_I2C1_MRST>;
 373                         power-domains = <&cpg>;
 374                         status = "disabled";
 375                 };
 376
 377                 i2c2: i2c@10058800 {
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 381                         reg = <0 0x10058800 0 0x400>;
 382                         interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
 383                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 384                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 385                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
 386                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
 388                                      <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 390                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 391                                           "naki", "ali", "tmoi";
 392                         clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
 393                         clock-frequency = <100000>;
 394                         resets = <&cpg R9A07G044_I2C2_MRST>;
 395                         power-domains = <&cpg>;
 396                         status = "disabled";
 397                 };
 398
 399                 i2c3: i2c@10058c00 {
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 403                         reg = <0 0x10058c00 0 0x400>;
 404                         interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
 405                                      <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
 406                                      <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 407                                      <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
 408                                      <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
 409                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
 410                                      <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
 411                                      <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
 412                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 413                                           "naki", "ali", "tmoi";
 414                         clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
 415                         clock-frequency = <100000>;
 416                         resets = <&cpg R9A07G044_I2C3_MRST>;
 417                         power-domains = <&cpg>;
 418                         status = "disabled";
 419                 };
 420
 421                 adc: adc@10059000 {
 422                         compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
 423                         reg = <0 0x10059000 0 0x400>;
 424                         interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
 425                         clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
 426                                  <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
 427                         clock-names = "adclk", "pclk";
 428                         resets = <&cpg R9A07G044_ADC_PRESETN>,
 429                                  <&cpg R9A07G044_ADC_ADRST_N>;
 430                         reset-names = "presetn", "adrst-n";
 431                         power-domains = <&cpg>;
 432                         status = "disabled";
 433
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436
 437                         channel@0 {
 438                                 reg = <0>;
 439                         };
 440                         channel@1 {
 441                                 reg = <1>;
 442                         };
 443                         channel@2 {
 444                                 reg = <2>;
 445                         };
 446                         channel@3 {
 447                                 reg = <3>;
 448                         };
 449                         channel@4 {
 450                                 reg = <4>;
 451                         };
 452                         channel@5 {
 453                                 reg = <5>;
 454                         };
 455                         channel@6 {
 456                                 reg = <6>;
 457                         };
 458                         channel@7 {
 459                                 reg = <7>;
 460                         };
 461                 };
 462
 463                 sbc: spi@10060000 {
 464                         compatible = "renesas,r9a07g044-rpc-if",
 465                                      "renesas,rzg2l-rpc-if";
 466                         reg = <0 0x10060000 0 0x10000>,
 467                               <0 0x20000000 0 0x10000000>,
 468                               <0 0x10070000 0 0x10000>;
 469                         reg-names = "regs", "dirmap", "wbuf";
 470                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
 472                                  <&cpg CPG_MOD R9A07G044_SPI_CLK>;
 473                         resets = <&cpg R9A07G044_SPI_RST>;
 474                         power-domains = <&cpg>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         status = "disabled";
 478                 };
 479
 480                 cpg: clock-controller@11010000 {
 481                         compatible = "renesas,r9a07g044-cpg";
 482                         reg = <0 0x11010000 0 0x10000>;
 483                         clocks = <&extal_clk>;
 484                         clock-names = "extal";
 485                         #clock-cells = <2>;
 486                         #reset-cells = <1>;
 487                         #power-domain-cells = <0>;
 488                 };
 489
 490                 sysc: system-controller@11020000 {
 491                         compatible = "renesas,r9a07g044-sysc";
 492                         reg = <0 0x11020000 0 0x10000>;
 493                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 494                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 497                         interrupt-names = "lpm_int", "ca55stbydone_int",
 498                                           "cm33stbyr_int", "ca55_deny";
 499                         status = "disabled";
 500                 };
 501
 502                 pinctrl: pin-controller@11030000 {
 503                         compatible = "renesas,r9a07g044-pinctrl";
 504                         reg = <0 0x11030000 0 0x10000>;
 505                         gpio-controller;
 506                         #gpio-cells = <2>;
 507                         gpio-ranges = <&pinctrl 0 0 392>;
 508                         clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
 509                         power-domains = <&cpg>;
 510                         resets = <&cpg R9A07G044_GPIO_RSTN>,
 511                                  <&cpg R9A07G044_GPIO_PORT_RESETN>,
 512                                  <&cpg R9A07G044_GPIO_SPARE_RESETN>;
 513                 };
 514
 515                 dmac: dma-controller@11820000 {
 516                         compatible = "renesas,r9a07g044-dmac",
 517                                      "renesas,rz-dmac";
 518                         reg = <0 0x11820000 0 0x10000>,
 519                               <0 0x11830000 0 0x10000>;
 520                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
 521                                      <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
 522                                      <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
 523                                      <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
 524                                      <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
 525                                      <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
 526                                      <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
 527                                      <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
 528                                      <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
 529                                      <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
 530                                      <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
 531                                      <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
 532                                      <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 533                                      <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
 534                                      <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
 535                                      <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
 536                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 537                         interrupt-names = "error",
 538                                           "ch0", "ch1", "ch2", "ch3",
 539                                           "ch4", "ch5", "ch6", "ch7",
 540                                           "ch8", "ch9", "ch10", "ch11",
 541                                           "ch12", "ch13", "ch14", "ch15";
 542                         clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
 543                                  <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
 544                         power-domains = <&cpg>;
 545                         resets = <&cpg R9A07G044_DMAC_ARESETN>,
 546                                  <&cpg R9A07G044_DMAC_RST_ASYNC>;
 547                         #dma-cells = <1>;
 548                         dma-channels = <16>;
 549                 };
 550
 551                 gic: interrupt-controller@11900000 {
 552                         compatible = "arm,gic-v3";
 553                         #interrupt-cells = <3>;
 554                         #address-cells = <0>;
 555                         interrupt-controller;
 556                         reg = <0x0 0x11900000 0 0x40000>,
 557                               <0x0 0x11940000 0 0x60000>;
 558                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 559                 };
 560
 561                 sdhi0: mmc@11c00000  {
 562                         compatible = "renesas,sdhi-r9a07g044",
 563                                      "renesas,rcar-gen3-sdhi";
 564                         reg = <0x0 0x11c00000 0 0x10000>;
 565                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
 568                                  <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
 569                                  <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
 570                                  <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
 571                         clock-names = "imclk", "imclk2", "clk_hs", "aclk";
 572                         resets = <&cpg R9A07G044_SDHI0_IXRST>;
 573                         power-domains = <&cpg>;
 574                         status = "disabled";
 575                 };
 576
 577                 sdhi1: mmc@11c10000 {
 578                         compatible = "renesas,sdhi-r9a07g044",
 579                                      "renesas,rcar-gen3-sdhi";
 580                         reg = <0x0 0x11c10000 0 0x10000>;
 581                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 583                         clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
 584                                  <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
 585                                  <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
 586                                  <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
 587                         clock-names = "imclk", "imclk2", "clk_hs", "aclk";
 588                         resets = <&cpg R9A07G044_SDHI1_IXRST>;
 589                         power-domains = <&cpg>;
 590                         status = "disabled";
 591                 };
 592
 593                 eth0: ethernet@11c20000 {
 594                         compatible = "renesas,r9a07g044-gbeth",
 595                                      "renesas,rzg2l-gbeth";
 596                         reg = <0 0x11c20000 0 0x10000>;
 597                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 600                         interrupt-names = "mux", "fil", "arp_ns";
 601                         phy-mode = "rgmii";
 602                         clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
 603                                  <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
 604                                  <&cpg CPG_CORE R9A07G044_CLK_HP>;
 605                         clock-names = "axi", "chi", "refclk";
 606                         resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
 607                         power-domains = <&cpg>;
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         status = "disabled";
 611                 };
 612
 613                 eth1: ethernet@11c30000 {
 614                         compatible = "renesas,r9a07g044-gbeth",
 615                                      "renesas,rzg2l-gbeth";
 616                         reg = <0 0x11c30000 0 0x10000>;
 617                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 618                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 619                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 620                         interrupt-names = "mux", "fil", "arp_ns";
 621                         phy-mode = "rgmii";
 622                         clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
 623                                  <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
 624                                  <&cpg CPG_CORE R9A07G044_CLK_HP>;
 625                         clock-names = "axi", "chi", "refclk";
 626                         resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
 627                         power-domains = <&cpg>;
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630                         status = "disabled";
 631                 };
 632
 633                 phyrst: usbphy-ctrl@11c40000 {
 634                         compatible = "renesas,r9a07g044-usbphy-ctrl",
 635                                      "renesas,rzg2l-usbphy-ctrl";
 636                         reg = <0 0x11c40000 0 0x10000>;
 637                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
 638                         resets = <&cpg R9A07G044_USB_PRESETN>;
 639                         power-domains = <&cpg>;
 640                         #reset-cells = <1>;
 641                         status = "disabled";
 642                 };
 643
 644                 ohci0: usb@11c50000 {
 645                         compatible = "generic-ohci";
 646                         reg = <0 0x11c50000 0 0x100>;
 647                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 648                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 649                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 650                         resets = <&phyrst 0>,
 651                                  <&cpg R9A07G044_USB_U2H0_HRESETN>;
 652                         phys = <&usb2_phy0 1>;
 653                         phy-names = "usb";
 654                         power-domains = <&cpg>;
 655                         status = "disabled";
 656                 };
 657
 658                 ohci1: usb@11c70000 {
 659                         compatible = "generic-ohci";
 660                         reg = <0 0x11c70000 0 0x100>;
 661                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 662                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 663                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 664                         resets = <&phyrst 1>,
 665                                  <&cpg R9A07G044_USB_U2H1_HRESETN>;
 666                         phys = <&usb2_phy1 1>;
 667                         phy-names = "usb";
 668                         power-domains = <&cpg>;
 669                         status = "disabled";
 670                 };
 671
 672                 ehci0: usb@11c50100 {
 673                         compatible = "generic-ehci";
 674                         reg = <0 0x11c50100 0 0x100>;
 675                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 677                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 678                         resets = <&phyrst 0>,
 679                                  <&cpg R9A07G044_USB_U2H0_HRESETN>;
 680                         phys = <&usb2_phy0 2>;
 681                         phy-names = "usb";
 682                         companion = <&ohci0>;
 683                         power-domains = <&cpg>;
 684                         status = "disabled";
 685                 };
 686
 687                 ehci1: usb@11c70100 {
 688                         compatible = "generic-ehci";
 689                         reg = <0 0x11c70100 0 0x100>;
 690                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 692                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 693                         resets = <&phyrst 1>,
 694                                  <&cpg R9A07G044_USB_U2H1_HRESETN>;
 695                         phys = <&usb2_phy1 2>;
 696                         phy-names = "usb";
 697                         companion = <&ohci1>;
 698                         power-domains = <&cpg>;
 699                         status = "disabled";
 700                 };
 701
 702                 usb2_phy0: usb-phy@11c50200 {
 703                         compatible = "renesas,usb2-phy-r9a07g044",
 704                                      "renesas,rzg2l-usb2-phy";
 705                         reg = <0 0x11c50200 0 0x700>;
 706                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 708                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 709                         resets = <&phyrst 0>;
 710                         #phy-cells = <1>;
 711                         power-domains = <&cpg>;
 712                         status = "disabled";
 713                 };
 714
 715                 usb2_phy1: usb-phy@11c70200 {
 716                         compatible = "renesas,usb2-phy-r9a07g044",
 717                                      "renesas,rzg2l-usb2-phy";
 718                         reg = <0 0x11c70200 0 0x700>;
 719                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 720                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 721                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 722                         resets = <&phyrst 1>;
 723                         #phy-cells = <1>;
 724                         power-domains = <&cpg>;
 725                         status = "disabled";
 726                 };
 727
 728                 hsusb: usb@11c60000 {
 729                         compatible = "renesas,usbhs-r9a07g044",
 730                                      "renesas,rza2-usbhs";
 731                         reg = <0 0x11c60000 0 0x10000>;
 732                         interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
 733                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 736                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 737                                  <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
 738                         resets = <&phyrst 0>,
 739                                  <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
 740                         renesas,buswait = <7>;
 741                         phys = <&usb2_phy0 3>;
 742                         phy-names = "usb";
 743                         power-domains = <&cpg>;
 744                         status = "disabled";
 745                 };
 746         };
 747
 748         timer {
 749                 compatible = "arm,armv8-timer";
 750                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 751                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 752                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 753                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 754         };
 755 };