arch/arm64/boot/dts/renesas/r8a779f0.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
   2 /*
   3  * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a779f0-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a779f0";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 a55_0: cpu@0 {
  22                         compatible = "arm,cortex-a55";
  23                         reg = <0>;
  24                         device_type = "cpu";
  25                         power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
  26                 };
  27         };
  28
  29         extal_clk: extal {
  30                 compatible = "fixed-clock";
  31                 #clock-cells = <0>;
  32                 /* This value must be overridden by the board */
  33                 clock-frequency = <0>;
  34         };
  35
  36         extalr_clk: extalr {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 /* This value must be overridden by the board */
  40                 clock-frequency = <0>;
  41         };
  42
  43         pmu_a55 {
  44                 compatible = "arm,cortex-a55-pmu";
  45                 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  46         };
  47
  48         /* External SCIF clock - to be overridden by boards that provide it */
  49         scif_clk: scif {
  50                 compatible = "fixed-clock";
  51                 #clock-cells = <0>;
  52                 clock-frequency = <0>;
  53         };
  54
  55         soc: soc {
  56                 compatible = "simple-bus";
  57                 interrupt-parent = <&gic>;
  58                 #address-cells = <2>;
  59                 #size-cells = <2>;
  60                 ranges;
  61
  62                 cpg: clock-controller@e6150000 {
  63                         compatible = "renesas,r8a779f0-cpg-mssr";
  64                         reg = <0 0xe6150000 0 0x4000>;
  65                         clocks = <&extal_clk>, <&extalr_clk>;
  66                         clock-names = "extal", "extalr";
  67                         #clock-cells = <2>;
  68                         #power-domain-cells = <0>;
  69                         #reset-cells = <1>;
  70                 };
  71
  72                 rst: reset-controller@e6160000 {
  73                         compatible = "renesas,r8a779f0-rst";
  74                         reg = <0 0xe6160000 0 0x4000>;
  75                 };
  76
  77                 sysc: system-controller@e6180000 {
  78                         compatible = "renesas,r8a779f0-sysc";
  79                         reg = <0 0xe6180000 0 0x4000>;
  80                         #power-domain-cells = <1>;
  81                 };
  82
  83                 scif3: serial@e6c50000 {
  84                         compatible = "renesas,scif-r8a779f0",
  85                                      "renesas,rcar-gen4-scif", "renesas,scif";
  86                         reg = <0 0xe6c50000 0 64>;
  87                         interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
  88                         clocks = <&cpg CPG_MOD 704>,
  89                                  <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
  90                                  <&scif_clk>;
  91                         clock-names = "fck", "brg_int", "scif_clk";
  92                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
  93                         resets = <&cpg 704>;
  94                         status = "disabled";
  95                 };
  96
  97                 gic: interrupt-controller@f1000000 {
  98                         compatible = "arm,gic-v3";
  99                         #interrupt-cells = <3>;
 100                         #address-cells = <0>;
 101                         interrupt-controller;
 102                         reg = <0x0 0xf1000000 0 0x20000>,
 103                               <0x0 0xf1060000 0 0x110000>;
 104                         interrupts = <GIC_PPI 9
 105                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 106                 };
 107
 108                 prr: chipid@fff00044 {
 109                         compatible = "renesas,prr";
 110                         reg = <0 0xfff00044 0 4>;
 111                 };
 112         };
 113
 114         timer {
 115                 compatible = "arm,armv8-timer";
 116                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 117                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 118                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 119                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 120         };
 121 };