arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Falcon CPU board
   4  *
   5  * Copyright (C) 2020 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "r8a779a0.dtsi"
  10
  11 / {
  12         model = "Renesas Falcon CPU board";
  13         compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
  14
  15         memory@48000000 {
  16                 device_type = "memory";
  17                 /* first 128MB is reserved for secure area. */
  18                 reg = <0x0 0x48000000 0x0 0x78000000>;
  19         };
  20
  21         memory@500000000 {
  22                 device_type = "memory";
  23                 reg = <0x5 0x00000000 0x0 0x80000000>;
  24         };
  25
  26         memory@600000000 {
  27                 device_type = "memory";
  28                 reg = <0x6 0x00000000 0x0 0x80000000>;
  29         };
  30
  31         memory@700000000 {
  32                 device_type = "memory";
  33                 reg = <0x7 0x00000000 0x0 0x80000000>;
  34         };
  35
  36         reg_1p8v: regulator-1p8v {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "fixed-1.8V";
  39                 regulator-min-microvolt = <1800000>;
  40                 regulator-max-microvolt = <1800000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45         reg_3p3v: regulator-3p3v {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "fixed-3.3V";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 regulator-boot-on;
  51                 regulator-always-on;
  52         };
  53 };
  54
  55 &avb0 {
  56         pinctrl-0 = <&avb0_pins>;
  57         pinctrl-names = "default";
  58         phy-handle = <&phy0>;
  59         tx-internal-delay-ps = <2000>;
  60         status = "okay";
  61
  62         phy0: ethernet-phy@0 {
  63                 rxc-skew-ps = <1500>;
  64                 reg = <0>;
  65                 interrupt-parent = <&gpio4>;
  66                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
  67                 reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
  68         };
  69 };
  70
  71 &extal_clk {
  72         clock-frequency = <16666666>;
  73 };
  74
  75 &extalr_clk {
  76         clock-frequency = <32768>;
  77 };
  78
  79 &i2c0 {
  80         pinctrl-0 = <&i2c0_pins>;
  81         pinctrl-names = "default";
  82
  83         status = "okay";
  84         clock-frequency = <400000>;
  85 };
  86
  87 &i2c1 {
  88         pinctrl-0 = <&i2c1_pins>;
  89         pinctrl-names = "default";
  90
  91         status = "okay";
  92         clock-frequency = <400000>;
  93 };
  94
  95 &i2c6 {
  96         pinctrl-0 = <&i2c6_pins>;
  97         pinctrl-names = "default";
  98
  99         status = "okay";
 100         clock-frequency = <400000>;
 101 };
 102
 103 &mmc0 {
 104         pinctrl-0 = <&mmc_pins>;
 105         pinctrl-1 = <&mmc_pins>;
 106         pinctrl-names = "default", "state_uhs";
 107
 108         vmmc-supply = <&reg_3p3v>;
 109         vqmmc-supply = <&reg_1p8v>;
 110         mmc-hs200-1_8v;
 111         mmc-hs400-1_8v;
 112         bus-width = <8>;
 113         no-sd;
 114         no-sdio;
 115         non-removable;
 116         full-pwr-cycle-in-suspend;
 117         status = "okay";
 118 };
 119
 120 &pfc {
 121         pinctrl-0 = <&scif_clk_pins>;
 122         pinctrl-names = "default";
 123
 124         avb0_pins: avb0 {
 125                 mux {
 126                         groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
 127                         function = "avb0";
 128                 };
 129
 130                 pins_mdio {
 131                         groups = "avb0_mdio";
 132                         drive-strength = <21>;
 133                 };
 134
 135                 pins_mii {
 136                         groups = "avb0_rgmii";
 137                         drive-strength = <21>;
 138                 };
 139
 140         };
 141
 142         i2c0_pins: i2c0 {
 143                 groups = "i2c0";
 144                 function = "i2c0";
 145         };
 146
 147         i2c1_pins: i2c1 {
 148                 groups = "i2c1";
 149                 function = "i2c1";
 150         };
 151
 152         i2c6_pins: i2c6 {
 153                 groups = "i2c6";
 154                 function = "i2c6";
 155         };
 156
 157         mmc_pins: mmc {
 158                 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
 159                 function = "mmc";
 160                 power-source = <1800>;
 161         };
 162
 163         scif0_pins: scif0 {
 164                 groups = "scif0_data", "scif0_ctrl";
 165                 function = "scif0";
 166         };
 167
 168         scif_clk_pins: scif_clk {
 169                 groups = "scif_clk";
 170                 function = "scif_clk";
 171         };
 172 };
 173
 174 &scif0 {
 175         pinctrl-0 = <&scif0_pins>;
 176         pinctrl-names = "default";
 177
 178         uart-has-rtscts;
 179         status = "okay";
 180 };
 181
 182 &scif_clk {
 183         clock-frequency = <24000000>;
 184 };