1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the ebisu board
5 * Copyright (C) 2018 Renesas Electronics Corp.
9 #include "r8a77990.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Renesas Ebisu board based on r8a77990";
14 compatible = "renesas,ebisu", "renesas,r8a77990";
25 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
26 stdout-path = "serial0:115200n8";
29 audio_clkout: audio-clkout {
31 * This is same as <&rcar_sound 0>
32 * but needed to avoid cs2000/rcar_sound probe dead-lock
34 compatible = "fixed-clock";
36 clock-frequency = <11289600>;
39 backlight: backlight {
40 compatible = "pwm-backlight";
41 pwms = <&pwm3 0 50000>;
43 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
44 default-brightness-level = <10>;
46 power-supply = <®_12p0v>;
50 compatible = "composite-video-connector";
55 remote-endpoint = <&adv7482_ain7>;
61 compatible = "hdmi-connector";
66 hdmi_in_con: endpoint {
67 remote-endpoint = <&adv7482_hdmi>;
73 compatible = "hdmi-connector";
77 hdmi_con_out: endpoint {
78 remote-endpoint = <&adv7511_out>;
84 compatible = "thine,thc63lvd1024";
85 vcc-supply = <®_3p3v>;
93 thc63lvd1024_in: endpoint {
94 remote-endpoint = <&lvds0_out>;
100 thc63lvd1024_out: endpoint {
101 remote-endpoint = <&adv7511_in>;
108 device_type = "memory";
109 /* first 128MB is reserved for secure area. */
110 reg = <0x0 0x48000000 0x0 0x38000000>;
113 reg_1p8v: regulator0 {
114 compatible = "regulator-fixed";
115 regulator-name = "fixed-1.8V";
116 regulator-min-microvolt = <1800000>;
117 regulator-max-microvolt = <1800000>;
122 reg_3p3v: regulator1 {
123 compatible = "regulator-fixed";
124 regulator-name = "fixed-3.3V";
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
131 reg_12p0v: regulator2 {
132 compatible = "regulator-fixed";
133 regulator-name = "D12.0V";
134 regulator-min-microvolt = <12000000>;
135 regulator-max-microvolt = <12000000>;
141 compatible = "simple-audio-card";
143 simple-audio-card,name = "rsnd-ak4613";
144 simple-audio-card,format = "left_j";
145 simple-audio-card,bitclock-master = <&sndcpu>;
146 simple-audio-card,frame-master = <&sndcpu>;
148 sndcodec: simple-audio-card,codec {
149 sound-dai = <&ak4613>;
152 sndcpu: simple-audio-card,cpu {
153 sound-dai = <&rcar_sound>;
157 vbus0_usb2: regulator-vbus0-usb2 {
158 compatible = "regulator-fixed";
160 regulator-name = "USB20_VBUS_CN";
161 regulator-min-microvolt = <5000000>;
162 regulator-max-microvolt = <5000000>;
164 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
168 vcc_sdhi0: regulator-vcc-sdhi0 {
169 compatible = "regulator-fixed";
171 regulator-name = "SDHI0 Vcc";
172 regulator-min-microvolt = <3300000>;
173 regulator-max-microvolt = <3300000>;
175 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
179 vccq_sdhi0: regulator-vccq-sdhi0 {
180 compatible = "regulator-gpio";
182 regulator-name = "SDHI0 VccQ";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <3300000>;
186 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
188 states = <3300000 1>, <1800000 0>;
191 vcc_sdhi1: regulator-vcc-sdhi1 {
192 compatible = "regulator-fixed";
194 regulator-name = "SDHI1 Vcc";
195 regulator-min-microvolt = <3300000>;
196 regulator-max-microvolt = <3300000>;
198 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
202 vccq_sdhi1: regulator-vccq-sdhi1 {
203 compatible = "regulator-gpio";
205 regulator-name = "SDHI1 VccQ";
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <3300000>;
209 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
211 states = <3300000 1>, <1800000 0>;
215 compatible = "vga-connector";
219 remote-endpoint = <&adv7123_out>;
225 compatible = "adi,adv7123";
228 #address-cells = <1>;
233 adv7123_in: endpoint {
234 remote-endpoint = <&du_out_rgb>;
239 adv7123_out: endpoint {
240 remote-endpoint = <&vga_in>;
247 compatible = "fixed-clock";
249 clock-frequency = <24576000>;
253 compatible = "fixed-clock";
255 clock-frequency = <74250000>;
260 clock-frequency = <22579200>;
264 pinctrl-0 = <&avb_pins>;
265 pinctrl-names = "default";
266 phy-handle = <&phy0>;
269 phy0: ethernet-phy@0 {
270 rxc-skew-ps = <1500>;
272 interrupt-parent = <&gpio2>;
273 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
274 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
276 * TX clock internal delay mode is required for reliable
277 * 1Gbps communication using the KSZ9031RNX phy present on
278 * the Ebisu board, however, TX clock internal delay mode
279 * isn't supported on r8a77990. Thus, limit speed to
280 * 100Mbps for reliable communication.
287 pinctrl-0 = <&canfd0_pins>;
288 pinctrl-names = "default";
304 remote-endpoint = <&adv7482_txa>;
311 pinctrl-0 = <&du_pins>;
312 pinctrl-names = "default";
315 clocks = <&cpg CPG_MOD 724>,
318 clock-names = "du.0", "du.1", "dclkin.0";
323 remote-endpoint = <&adv7123_in>;
335 clock-frequency = <48000000>;
346 io_expander: gpio@20 {
347 compatible = "onnn,pca9654";
351 interrupt-parent = <&gpio2>;
352 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
356 compatible = "adi,adv7511w";
358 interrupt-parent = <&gpio1>;
359 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
361 adi,input-depth = <8>;
362 adi,input-colorspace = "rgb";
363 adi,input-clock = "1x";
366 #address-cells = <1>;
371 adv7511_in: endpoint {
372 remote-endpoint = <&thc63lvd1024_out>;
378 adv7511_out: endpoint {
379 remote-endpoint = <&hdmi_con_out>;
386 compatible = "adi,adv7482";
389 #address-cells = <1>;
392 interrupt-parent = <&gpio0>;
393 interrupt-names = "intrq1", "intrq2";
394 interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
395 <17 IRQ_TYPE_LEVEL_LOW>;
400 adv7482_ain7: endpoint {
401 remote-endpoint = <&cvbs_con>;
408 adv7482_hdmi: endpoint {
409 remote-endpoint = <&hdmi_in_con>;
416 adv7482_txa: endpoint {
419 remote-endpoint = <&csi40_in>;
429 compatible = "asahi-kasei,ak4613";
430 #sound-dai-cells = <0>;
432 clocks = <&rcar_sound 3>;
434 asahi-kasei,in1-single-end;
435 asahi-kasei,in2-single-end;
436 asahi-kasei,out1-single-end;
437 asahi-kasei,out2-single-end;
438 asahi-kasei,out3-single-end;
439 asahi-kasei,out4-single-end;
440 asahi-kasei,out5-single-end;
441 asahi-kasei,out6-single-end;
444 cs2000: clk-multiplier@4f {
446 compatible = "cirrus,cs2000-cp";
448 clocks = <&audio_clkout>, <&x12_clk>;
449 clock-names = "clk_in", "ref_clk";
451 assigned-clocks = <&cs2000>;
452 assigned-clock-rates = <24576000>; /* 1/1 divide */
459 clock-frequency = <400000>;
462 pinctrl-0 = <&irq0_pins>;
463 pinctrl-names = "default";
465 compatible = "rohm,bd9571mwv";
467 interrupt-parent = <&intc_ex>;
468 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
473 rohm,ddr-backup-power = <0x1>;
481 clocks = <&cpg CPG_MOD 727>,
484 clock-names = "fck", "dclkin.0", "extal";
488 lvds0_out: endpoint {
489 remote-endpoint = <&thc63lvd1024_in>;
497 * Even though the LVDS1 output is not connected, the encoder must be
498 * enabled to supply a pixel clock to the DU for the DPAD output when
503 clocks = <&cpg CPG_MOD 727>,
506 clock-names = "fck", "dclkin.0", "extal";
515 clock-frequency = <100000000>;
524 groups = "avb_link", "avb_mii";
528 canfd0_pins: canfd0 {
529 groups = "canfd0_data";
534 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
539 groups = "intc_ex_irq0";
540 function = "intc_ex";
554 groups = "scif2_data_a";
559 groups = "sdhi0_data4", "sdhi0_ctrl";
561 power-source = <3300>;
564 sdhi0_pins_uhs: sd0_uhs {
565 groups = "sdhi0_data4", "sdhi0_ctrl";
567 power-source = <1800>;
571 groups = "sdhi1_data4", "sdhi1_ctrl";
573 power-source = <3300>;
576 sdhi1_pins_uhs: sd1_uhs {
577 groups = "sdhi1_data4", "sdhi1_ctrl";
579 power-source = <1800>;
583 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
585 power-source = <1800>;
588 sound_clk_pins: sound_clk {
589 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
590 "audio_clkout_a", "audio_clkout1_a";
591 function = "audio_clk";
595 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
600 groups = "usb0_b", "usb0_id";
611 pinctrl-0 = <&pwm3_pins>;
612 pinctrl-names = "default";
618 pinctrl-0 = <&pwm5_pins>;
619 pinctrl-names = "default";
625 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
626 pinctrl-names = "default";
629 #sound-dai-cells = <0>;
631 /* audio_clkout0/1/2/3 */
633 clock-frequency = <12288000 11289600>;
637 /* update <audio_clk_b> to <cs2000> */
638 clocks = <&cpg CPG_MOD 1005>,
639 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
640 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
641 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
642 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
643 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
644 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
645 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
646 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
647 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
648 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
649 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
650 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
651 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
652 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
653 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
657 playback = <&ssi0>, <&src0>, <&dvc0>;
658 capture = <&ssi1>, <&src1>, <&dvc1>;
670 pinctrl-0 = <&scif2_pins>;
671 pinctrl-names = "default";
677 pinctrl-0 = <&sdhi0_pins>;
678 pinctrl-1 = <&sdhi0_pins_uhs>;
679 pinctrl-names = "default", "state_uhs";
681 vmmc-supply = <&vcc_sdhi0>;
682 vqmmc-supply = <&vccq_sdhi0>;
683 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
684 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
692 pinctrl-0 = <&sdhi1_pins>;
693 pinctrl-1 = <&sdhi1_pins_uhs>;
694 pinctrl-names = "default", "state_uhs";
696 vmmc-supply = <&vcc_sdhi1>;
697 vqmmc-supply = <&vccq_sdhi1>;
698 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
706 /* used for on-board 8bit eMMC */
707 pinctrl-0 = <&sdhi3_pins>;
708 pinctrl-1 = <&sdhi3_pins>;
709 pinctrl-names = "default", "state_uhs";
711 vmmc-supply = <®_3p3v>;
712 vqmmc-supply = <®_1p8v>;
719 full-pwr-cycle-in-suspend;
728 pinctrl-0 = <&usb0_pins>;
729 pinctrl-names = "default";
731 vbus-supply = <&vbus0_usb2>;
736 companion = <&xhci0>;
749 pinctrl-0 = <&usb30_pins>;
750 pinctrl-names = "default";