1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the ebisu board
5 * Copyright (C) 2018 Renesas Electronics Corp.
9 #include "r8a77990.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Renesas Ebisu board based on r8a77990";
14 compatible = "renesas,ebisu", "renesas,r8a77990";
22 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
23 stdout-path = "serial0:115200n8";
26 audio_clkout: audio-clkout {
28 * This is same as <&rcar_sound 0>
29 * but needed to avoid cs2000/rcar_sound probe dead-lock
31 compatible = "fixed-clock";
33 clock-frequency = <11289600>;
36 backlight: backlight {
37 compatible = "pwm-backlight";
38 pwms = <&pwm3 0 50000>;
40 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
41 default-brightness-level = <10>;
43 power-supply = <®_12p0v>;
47 compatible = "composite-video-connector";
52 remote-endpoint = <&adv7482_ain7>;
58 compatible = "hdmi-connector";
63 hdmi_in_con: endpoint {
64 remote-endpoint = <&adv7482_hdmi>;
70 compatible = "hdmi-connector";
74 hdmi_con_out: endpoint {
75 remote-endpoint = <&adv7511_out>;
81 compatible = "thine,thc63lvd1024";
82 vcc-supply = <®_3p3v>;
90 thc63lvd1024_in: endpoint {
91 remote-endpoint = <&lvds0_out>;
97 thc63lvd1024_out: endpoint {
98 remote-endpoint = <&adv7511_in>;
105 device_type = "memory";
106 /* first 128MB is reserved for secure area. */
107 reg = <0x0 0x48000000 0x0 0x38000000>;
110 reg_1p8v: regulator0 {
111 compatible = "regulator-fixed";
112 regulator-name = "fixed-1.8V";
113 regulator-min-microvolt = <1800000>;
114 regulator-max-microvolt = <1800000>;
119 reg_3p3v: regulator1 {
120 compatible = "regulator-fixed";
121 regulator-name = "fixed-3.3V";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
128 reg_12p0v: regulator2 {
129 compatible = "regulator-fixed";
130 regulator-name = "D12.0V";
131 regulator-min-microvolt = <12000000>;
132 regulator-max-microvolt = <12000000>;
138 compatible = "simple-audio-card";
140 simple-audio-card,name = "rsnd-ak4613";
141 simple-audio-card,format = "left_j";
142 simple-audio-card,bitclock-master = <&sndcpu>;
143 simple-audio-card,frame-master = <&sndcpu>;
145 sndcodec: simple-audio-card,codec {
146 sound-dai = <&ak4613>;
149 sndcpu: simple-audio-card,cpu {
150 sound-dai = <&rcar_sound>;
154 vbus0_usb2: regulator-vbus0-usb2 {
155 compatible = "regulator-fixed";
157 regulator-name = "USB20_VBUS_CN";
158 regulator-min-microvolt = <5000000>;
159 regulator-max-microvolt = <5000000>;
161 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
165 vcc_sdhi0: regulator-vcc-sdhi0 {
166 compatible = "regulator-fixed";
168 regulator-name = "SDHI0 Vcc";
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
172 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
176 vccq_sdhi0: regulator-vccq-sdhi0 {
177 compatible = "regulator-gpio";
179 regulator-name = "SDHI0 VccQ";
180 regulator-min-microvolt = <1800000>;
181 regulator-max-microvolt = <3300000>;
183 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
185 states = <3300000 1>, <1800000 0>;
188 vcc_sdhi1: regulator-vcc-sdhi1 {
189 compatible = "regulator-fixed";
191 regulator-name = "SDHI1 Vcc";
192 regulator-min-microvolt = <3300000>;
193 regulator-max-microvolt = <3300000>;
195 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
199 vccq_sdhi1: regulator-vccq-sdhi1 {
200 compatible = "regulator-gpio";
202 regulator-name = "SDHI1 VccQ";
203 regulator-min-microvolt = <1800000>;
204 regulator-max-microvolt = <3300000>;
206 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
208 states = <3300000 1>, <1800000 0>;
212 compatible = "vga-connector";
216 remote-endpoint = <&adv7123_out>;
222 compatible = "adi,adv7123";
225 #address-cells = <1>;
230 adv7123_in: endpoint {
231 remote-endpoint = <&du_out_rgb>;
236 adv7123_out: endpoint {
237 remote-endpoint = <&vga_in>;
244 compatible = "fixed-clock";
246 clock-frequency = <24576000>;
250 compatible = "fixed-clock";
252 clock-frequency = <74250000>;
257 clock-frequency = <22579200>;
261 pinctrl-0 = <&avb_pins>;
262 pinctrl-names = "default";
263 phy-handle = <&phy0>;
266 phy0: ethernet-phy@0 {
267 rxc-skew-ps = <1500>;
269 interrupt-parent = <&gpio2>;
270 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
271 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
273 * TX clock internal delay mode is required for reliable
274 * 1Gbps communication using the KSZ9031RNX phy present on
275 * the Ebisu board, however, TX clock internal delay mode
276 * isn't supported on r8a77990. Thus, limit speed to
277 * 100Mbps for reliable communication.
284 pinctrl-0 = <&canfd0_pins>;
285 pinctrl-names = "default";
303 remote-endpoint = <&adv7482_txa>;
310 pinctrl-0 = <&du_pins>;
311 pinctrl-names = "default";
314 clocks = <&cpg CPG_MOD 724>,
317 clock-names = "du.0", "du.1", "dclkin.0";
322 remote-endpoint = <&adv7123_in>;
334 clock-frequency = <48000000>;
345 io_expander: gpio@20 {
346 compatible = "onnn,pca9654";
350 interrupt-parent = <&gpio2>;
351 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
355 compatible = "adi,adv7511w";
357 interrupt-parent = <&gpio1>;
358 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
360 adi,input-depth = <8>;
361 adi,input-colorspace = "rgb";
362 adi,input-clock = "1x";
365 #address-cells = <1>;
370 adv7511_in: endpoint {
371 remote-endpoint = <&thc63lvd1024_out>;
377 adv7511_out: endpoint {
378 remote-endpoint = <&hdmi_con_out>;
385 compatible = "adi,adv7482";
388 #address-cells = <1>;
391 interrupt-parent = <&gpio0>;
392 interrupt-names = "intrq1", "intrq2";
393 interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
394 <17 IRQ_TYPE_LEVEL_LOW>;
399 adv7482_ain7: endpoint {
400 remote-endpoint = <&cvbs_con>;
407 adv7482_hdmi: endpoint {
408 remote-endpoint = <&hdmi_in_con>;
415 adv7482_txa: endpoint {
418 remote-endpoint = <&csi40_in>;
428 compatible = "asahi-kasei,ak4613";
429 #sound-dai-cells = <0>;
431 clocks = <&rcar_sound 3>;
433 asahi-kasei,in1-single-end;
434 asahi-kasei,in2-single-end;
435 asahi-kasei,out1-single-end;
436 asahi-kasei,out2-single-end;
437 asahi-kasei,out3-single-end;
438 asahi-kasei,out4-single-end;
439 asahi-kasei,out5-single-end;
440 asahi-kasei,out6-single-end;
443 cs2000: clk-multiplier@4f {
445 compatible = "cirrus,cs2000-cp";
447 clocks = <&audio_clkout>, <&x12_clk>;
448 clock-names = "clk_in", "ref_clk";
450 assigned-clocks = <&cs2000>;
451 assigned-clock-rates = <24576000>; /* 1/1 divide */
458 clock-frequency = <400000>;
461 pinctrl-0 = <&irq0_pins>;
462 pinctrl-names = "default";
464 compatible = "rohm,bd9571mwv";
466 interrupt-parent = <&intc_ex>;
467 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 rohm,ddr-backup-power = <0x1>;
480 clocks = <&cpg CPG_MOD 727>,
483 clock-names = "fck", "dclkin.0", "extal";
487 lvds0_out: endpoint {
488 remote-endpoint = <&thc63lvd1024_in>;
496 * Even though the LVDS1 output is not connected, the encoder must be
497 * enabled to supply a pixel clock to the DU for the DPAD output when
502 clocks = <&cpg CPG_MOD 727>,
505 clock-names = "fck", "dclkin.0", "extal";
514 clock-frequency = <100000000>;
524 groups = "avb_link", "avb_mii";
529 canfd0_pins: canfd0 {
530 groups = "canfd0_data";
535 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
540 groups = "intc_ex_irq0";
541 function = "intc_ex";
555 groups = "scif2_data_a";
560 groups = "sdhi0_data4", "sdhi0_ctrl";
562 power-source = <3300>;
565 sdhi0_pins_uhs: sd0_uhs {
566 groups = "sdhi0_data4", "sdhi0_ctrl";
568 power-source = <1800>;
572 groups = "sdhi1_data4", "sdhi1_ctrl";
574 power-source = <3300>;
577 sdhi1_pins_uhs: sd1_uhs {
578 groups = "sdhi1_data4", "sdhi1_ctrl";
580 power-source = <1800>;
584 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
586 power-source = <1800>;
589 sound_clk_pins: sound_clk {
590 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
591 "audio_clkout_a", "audio_clkout1_a";
592 function = "audio_clk";
596 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
601 groups = "usb0_b", "usb0_id";
612 pinctrl-0 = <&pwm3_pins>;
613 pinctrl-names = "default";
619 pinctrl-0 = <&pwm5_pins>;
620 pinctrl-names = "default";
626 pinctrl-0 = <&sound_pins &sound_clk_pins>;
627 pinctrl-names = "default";
630 #sound-dai-cells = <0>;
632 /* audio_clkout0/1/2/3 */
634 clock-frequency = <12288000 11289600>;
638 /* update <audio_clk_b> to <cs2000> */
639 clocks = <&cpg CPG_MOD 1005>,
640 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
641 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
642 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
643 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
644 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
645 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
646 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
647 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
648 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
649 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
650 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
651 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
652 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
653 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
654 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
658 playback = <&ssi0 &src0 &dvc0>;
659 capture = <&ssi1 &src1 &dvc1>;
671 pinctrl-0 = <&scif2_pins>;
672 pinctrl-names = "default";
678 pinctrl-0 = <&sdhi0_pins>;
679 pinctrl-1 = <&sdhi0_pins_uhs>;
680 pinctrl-names = "default", "state_uhs";
682 vmmc-supply = <&vcc_sdhi0>;
683 vqmmc-supply = <&vccq_sdhi0>;
684 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
685 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
693 pinctrl-0 = <&sdhi1_pins>;
694 pinctrl-1 = <&sdhi1_pins_uhs>;
695 pinctrl-names = "default", "state_uhs";
697 vmmc-supply = <&vcc_sdhi1>;
698 vqmmc-supply = <&vccq_sdhi1>;
699 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
707 /* used for on-board 8bit eMMC */
708 pinctrl-0 = <&sdhi3_pins>;
709 pinctrl-1 = <&sdhi3_pins>;
710 pinctrl-names = "default", "state_uhs";
712 vmmc-supply = <®_3p3v>;
713 vqmmc-supply = <®_1p8v>;
726 pinctrl-0 = <&usb0_pins>;
727 pinctrl-names = "default";
729 vbus-supply = <&vbus0_usb2>;
734 companion = <&xhci0>;
747 pinctrl-0 = <&usb30_pins>;
748 pinctrl-names = "default";