2 * Device Tree Source for the r8a77970 SoC
4 * Copyright (C) 2016-2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/renesas-cpg-mssr.h>
17 compatible = "renesas,r8a77970";
22 compatible = "arm,psci-1.0", "arm,psci-0.2";
32 compatible = "arm,cortex-a53", "arm,armv8";
34 clocks = <&cpg CPG_CORE 0>;
35 power-domains = <&sysc 5>;
36 next-level-cache = <&L2_CA53>;
37 enable-method = "psci";
40 L2_CA53: cache-controller {
42 power-domains = <&sysc 21>;
49 compatible = "fixed-clock";
51 /* This value must be overridden by the board */
52 clock-frequency = <0>;
56 compatible = "fixed-clock";
58 /* This value must be overridden by the board */
59 clock-frequency = <0>;
62 /* External SCIF clock - to be overridden by boards that provide it */
64 compatible = "fixed-clock";
66 clock-frequency = <0>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
77 gic: interrupt-controller@f1010000 {
78 compatible = "arm,gic-400";
79 #interrupt-cells = <3>;
82 reg = <0 0xf1010000 0 0x1000>,
83 <0 0xf1020000 0 0x20000>,
84 <0 0xf1040000 0 0x20000>,
85 <0 0xf1060000 0 0x20000>;
86 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
87 IRQ_TYPE_LEVEL_HIGH)>;
88 clocks = <&cpg CPG_MOD 408>;
90 power-domains = <&sysc 32>;
95 compatible = "arm,armv8-timer";
96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
101 IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
103 IRQ_TYPE_LEVEL_LOW)>;
106 cpg: clock-controller@e6150000 {
107 compatible = "renesas,r8a77970-cpg-mssr";
108 reg = <0 0xe6150000 0 0x1000>;
109 clocks = <&extal_clk>, <&extalr_clk>;
110 clock-names = "extal", "extalr";
112 #power-domain-cells = <0>;
116 rst: reset-controller@e6160000 {
117 compatible = "renesas,r8a77970-rst";
118 reg = <0 0xe6160000 0 0x200>;
121 sysc: system-controller@e6180000 {
122 compatible = "renesas,r8a77970-sysc";
123 reg = <0 0xe6180000 0 0x440>;
124 #power-domain-cells = <1>;
127 intc_ex: interrupt-controller@e61c0000 {
128 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 reg = <0 0xe61c0000 0 0x200>;
132 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
134 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
135 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cpg CPG_MOD 407>;
139 power-domains = <&sysc 32>;
143 prr: chipid@fff00044 {
144 compatible = "renesas,prr";
145 reg = <0 0xfff00044 0 4>;
148 dmac1: dma-controller@e7300000 {
149 compatible = "renesas,dmac-r8a77970",
151 reg = <0 0xe7300000 0 0x10000>;
152 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
153 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
154 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
155 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
156 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
157 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
158 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
159 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
160 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-names = "error",
162 "ch0", "ch1", "ch2", "ch3",
163 "ch4", "ch5", "ch6", "ch7";
164 clocks = <&cpg CPG_MOD 218>;
166 power-domains = <&sysc 32>;
172 dmac2: dma-controller@e7310000 {
173 compatible = "renesas,dmac-r8a77970",
175 reg = <0 0xe7310000 0 0x10000>;
176 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
177 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
178 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
179 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
180 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
181 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
182 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
183 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "error",
186 "ch0", "ch1", "ch2", "ch3",
187 "ch4", "ch5", "ch6", "ch7";
188 clocks = <&cpg CPG_MOD 217>;
190 power-domains = <&sysc 32>;
196 hscif0: serial@e6540000 {
197 compatible = "renesas,hscif-r8a77970",
198 "renesas,rcar-gen3-hscif",
200 reg = <0 0xe6540000 0 96>;
201 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cpg CPG_MOD 520>,
205 clock-names = "fck", "brg_int", "scif_clk";
206 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
207 <&dmac2 0x31>, <&dmac2 0x30>;
208 dma-names = "tx", "rx", "tx", "rx";
209 power-domains = <&sysc 32>;
214 hscif1: serial@e6550000 {
215 compatible = "renesas,hscif-r8a77970",
216 "renesas,rcar-gen3-hscif",
218 reg = <0 0xe6550000 0 96>;
219 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cpg CPG_MOD 519>,
223 clock-names = "fck", "brg_int", "scif_clk";
224 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
225 <&dmac2 0x33>, <&dmac2 0x32>;
226 dma-names = "tx", "rx", "tx", "rx";
227 power-domains = <&sysc 32>;
232 hscif2: serial@e6560000 {
233 compatible = "renesas,hscif-r8a77970",
234 "renesas,rcar-gen3-hscif",
236 reg = <0 0xe6560000 0 96>;
237 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cpg CPG_MOD 518>,
241 clock-names = "fck", "brg_int", "scif_clk";
242 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
243 <&dmac2 0x35>, <&dmac2 0x34>;
244 dma-names = "tx", "rx", "tx", "rx";
245 power-domains = <&sysc 32>;
250 hscif3: serial@e66a0000 {
251 compatible = "renesas,hscif-r8a77970",
252 "renesas,rcar-gen3-hscif", "renesas,hscif";
253 reg = <0 0xe66a0000 0 96>;
254 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cpg CPG_MOD 517>,
258 clock-names = "fck", "brg_int", "scif_clk";
259 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
260 <&dmac2 0x37>, <&dmac2 0x36>;
261 dma-names = "tx", "rx", "tx", "rx";
262 power-domains = <&sysc 32>;
267 scif0: serial@e6e60000 {
268 compatible = "renesas,scif-r8a77970",
269 "renesas,rcar-gen3-scif",
271 reg = <0 0xe6e60000 0 64>;
272 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cpg CPG_MOD 207>,
276 clock-names = "fck", "brg_int", "scif_clk";
277 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
278 <&dmac2 0x51>, <&dmac2 0x50>;
279 dma-names = "tx", "rx", "tx", "rx";
280 power-domains = <&sysc 32>;
285 scif1: serial@e6e68000 {
286 compatible = "renesas,scif-r8a77970",
287 "renesas,rcar-gen3-scif",
289 reg = <0 0xe6e68000 0 64>;
290 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cpg CPG_MOD 206>,
294 clock-names = "fck", "brg_int", "scif_clk";
295 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
296 <&dmac2 0x53>, <&dmac2 0x52>;
297 dma-names = "tx", "rx", "tx", "rx";
298 power-domains = <&sysc 32>;
303 scif3: serial@e6c50000 {
304 compatible = "renesas,scif-r8a77970",
305 "renesas,rcar-gen3-scif",
307 reg = <0 0xe6c50000 0 64>;
308 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cpg CPG_MOD 204>,
312 clock-names = "fck", "brg_int", "scif_clk";
313 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
314 <&dmac2 0x57>, <&dmac2 0x56>;
315 dma-names = "tx", "rx", "tx", "rx";
316 power-domains = <&sysc 32>;
321 scif4: serial@e6c40000 {
322 compatible = "renesas,scif-r8a77970",
323 "renesas,rcar-gen3-scif", "renesas,scif";
324 reg = <0 0xe6c40000 0 64>;
325 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&cpg CPG_MOD 203>,
329 clock-names = "fck", "brg_int", "scif_clk";
330 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
331 <&dmac2 0x59>, <&dmac2 0x58>;
332 dma-names = "tx", "rx", "tx", "rx";
333 power-domains = <&sysc 32>;
338 avb: ethernet@e6800000 {
339 compatible = "renesas,etheravb-r8a77970",
340 "renesas,etheravb-rcar-gen3";
341 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
342 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-names = "ch0", "ch1", "ch2", "ch3",
368 "ch4", "ch5", "ch6", "ch7",
369 "ch8", "ch9", "ch10", "ch11",
370 "ch12", "ch13", "ch14", "ch15",
371 "ch16", "ch17", "ch18", "ch19",
372 "ch20", "ch21", "ch22", "ch23",
374 clocks = <&cpg CPG_MOD 812>;
375 power-domains = <&sysc 32>;
377 phy-mode = "rgmii-id";
378 #address-cells = <1>;