1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
12 #define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4
15 compatible = "renesas,r8a77961";
20 * The external audio clocks are configured as 0 Hz fixed frequency
22 * Boards that provide audio clocks should override them.
24 audio_clk_a: audio_clk_a {
25 compatible = "fixed-clock";
27 clock-frequency = <0>;
30 audio_clk_b: audio_clk_b {
31 compatible = "fixed-clock";
33 clock-frequency = <0>;
36 audio_clk_c: audio_clk_c {
37 compatible = "fixed-clock";
39 clock-frequency = <0>;
42 /* External CAN clock - to be overridden by boards that provide it */
44 compatible = "fixed-clock";
46 clock-frequency = <0>;
49 cluster0_opp: opp_table0 {
50 compatible = "operating-points-v2";
54 opp-hz = /bits/ 64 <500000000>;
55 opp-microvolt = <820000>;
56 clock-latency-ns = <300000>;
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <820000>;
61 clock-latency-ns = <300000>;
64 opp-hz = /bits/ 64 <1500000000>;
65 opp-microvolt = <820000>;
66 clock-latency-ns = <300000>;
69 opp-hz = /bits/ 64 <1600000000>;
70 opp-microvolt = <900000>;
71 clock-latency-ns = <300000>;
75 opp-hz = /bits/ 64 <1700000000>;
76 opp-microvolt = <900000>;
77 clock-latency-ns = <300000>;
81 opp-hz = /bits/ 64 <1800000000>;
82 opp-microvolt = <960000>;
83 clock-latency-ns = <300000>;
88 cluster1_opp: opp_table1 {
89 compatible = "operating-points-v2";
93 opp-hz = /bits/ 64 <800000000>;
94 opp-microvolt = <820000>;
95 clock-latency-ns = <300000>;
98 opp-hz = /bits/ 64 <1000000000>;
99 opp-microvolt = <820000>;
100 clock-latency-ns = <300000>;
103 opp-hz = /bits/ 64 <1200000000>;
104 opp-microvolt = <820000>;
105 clock-latency-ns = <300000>;
108 opp-hz = /bits/ 64 <1300000000>;
109 opp-microvolt = <820000>;
110 clock-latency-ns = <300000>;
116 #address-cells = <1>;
146 compatible = "arm,cortex-a57";
149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>;
150 next-level-cache = <&L2_CA57>;
151 enable-method = "psci";
152 cpu-idle-states = <&CPU_SLEEP_0>;
153 dynamic-power-coefficient = <854>;
154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
155 operating-points-v2 = <&cluster0_opp>;
156 capacity-dmips-mhz = <1024>;
157 #cooling-cells = <2>;
161 compatible = "arm,cortex-a57";
164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>;
165 next-level-cache = <&L2_CA57>;
166 enable-method = "psci";
167 cpu-idle-states = <&CPU_SLEEP_0>;
168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
169 operating-points-v2 = <&cluster0_opp>;
170 capacity-dmips-mhz = <1024>;
171 #cooling-cells = <2>;
175 compatible = "arm,cortex-a53";
178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>;
179 next-level-cache = <&L2_CA53>;
180 enable-method = "psci";
181 cpu-idle-states = <&CPU_SLEEP_1>;
182 #cooling-cells = <2>;
183 dynamic-power-coefficient = <277>;
184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
185 operating-points-v2 = <&cluster1_opp>;
186 capacity-dmips-mhz = <535>;
190 compatible = "arm,cortex-a53";
193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>;
194 next-level-cache = <&L2_CA53>;
195 enable-method = "psci";
196 cpu-idle-states = <&CPU_SLEEP_1>;
197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
198 operating-points-v2 = <&cluster1_opp>;
199 capacity-dmips-mhz = <535>;
203 compatible = "arm,cortex-a53";
206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>;
207 next-level-cache = <&L2_CA53>;
208 enable-method = "psci";
209 cpu-idle-states = <&CPU_SLEEP_1>;
210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
211 operating-points-v2 = <&cluster1_opp>;
212 capacity-dmips-mhz = <535>;
216 compatible = "arm,cortex-a53";
219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>;
220 next-level-cache = <&L2_CA53>;
221 enable-method = "psci";
222 cpu-idle-states = <&CPU_SLEEP_1>;
223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
224 operating-points-v2 = <&cluster1_opp>;
225 capacity-dmips-mhz = <535>;
228 L2_CA57: cache-controller-0 {
229 compatible = "cache";
230 power-domains = <&sysc R8A77961_PD_CA57_SCU>;
235 L2_CA53: cache-controller-1 {
236 compatible = "cache";
237 power-domains = <&sysc R8A77961_PD_CA53_SCU>;
243 entry-method = "psci";
245 CPU_SLEEP_0: cpu-sleep-0 {
246 compatible = "arm,idle-state";
247 arm,psci-suspend-param = <0x0010000>;
249 entry-latency-us = <400>;
250 exit-latency-us = <500>;
251 min-residency-us = <4000>;
254 CPU_SLEEP_1: cpu-sleep-1 {
255 compatible = "arm,idle-state";
256 arm,psci-suspend-param = <0x0010000>;
258 entry-latency-us = <700>;
259 exit-latency-us = <700>;
260 min-residency-us = <5000>;
266 compatible = "fixed-clock";
268 /* This value must be overridden by the board */
269 clock-frequency = <0>;
273 compatible = "fixed-clock";
275 /* This value must be overridden by the board */
276 clock-frequency = <0>;
279 /* External PCIe clock - can be overridden by the board */
280 pcie_bus_clk: pcie_bus {
281 compatible = "fixed-clock";
283 clock-frequency = <0>;
287 compatible = "arm,cortex-a53-pmu";
288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
296 compatible = "arm,cortex-a57-pmu";
297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-affinity = <&a57_0>, <&a57_1>;
303 compatible = "arm,psci-1.0", "arm,psci-0.2";
307 /* External SCIF clock - to be overridden by boards that provide it */
309 compatible = "fixed-clock";
311 clock-frequency = <0>;
315 compatible = "simple-bus";
316 interrupt-parent = <&gic>;
317 #address-cells = <2>;
321 rwdt: watchdog@e6020000 {
322 reg = <0 0xe6020000 0 0x0c>;
326 gpio2: gpio@e6052000 {
327 reg = <0 0xe6052000 0 0x50>;
330 #interrupt-cells = <2>;
331 interrupt-controller;
335 gpio3: gpio@e6053000 {
336 reg = <0 0xe6053000 0 0x50>;
339 #interrupt-cells = <2>;
340 interrupt-controller;
344 gpio4: gpio@e6054000 {
345 reg = <0 0xe6054000 0 0x50>;
348 #interrupt-cells = <2>;
349 interrupt-controller;
353 gpio5: gpio@e6055000 {
354 reg = <0 0xe6055000 0 0x50>;
357 #interrupt-cells = <2>;
358 interrupt-controller;
362 gpio6: gpio@e6055400 {
363 reg = <0 0xe6055400 0 0x50>;
366 #interrupt-cells = <2>;
367 interrupt-controller;
371 pfc: pin-controller@e6060000 {
372 compatible = "renesas,pfc-r8a77961";
373 reg = <0 0xe6060000 0 0x50c>;
376 cpg: clock-controller@e6150000 {
377 compatible = "renesas,r8a77961-cpg-mssr";
378 reg = <0 0xe6150000 0 0x1000>;
379 clocks = <&extal_clk>, <&extalr_clk>;
380 clock-names = "extal", "extalr";
382 #power-domain-cells = <0>;
386 rst: reset-controller@e6160000 {
387 compatible = "renesas,r8a77961-rst";
388 reg = <0 0xe6160000 0 0x0200>;
391 sysc: system-controller@e6180000 {
392 compatible = "renesas,r8a77961-sysc";
393 reg = <0 0xe6180000 0 0x0400>;
394 #power-domain-cells = <1>;
397 intc_ex: interrupt-controller@e61c0000 {
398 #interrupt-cells = <2>;
399 interrupt-controller;
400 reg = <0 0xe61c0000 0 0x200>;
405 #address-cells = <1>;
407 reg = <0 0xe6510000 0 0x40>;
412 #address-cells = <1>;
414 reg = <0 0xe66d8000 0 0x40>;
418 i2c_dvfs: i2c@e60b0000 {
419 #address-cells = <1>;
421 reg = <0 0xe60b0000 0 0x425>;
425 hscif1: serial@e6550000 {
426 reg = <0 0xe6550000 0 0x60>;
430 hsusb: usb@e6590000 {
431 reg = <0 0xe6590000 0 0x200>;
435 usb3_phy0: usb-phy@e65ee000 {
436 reg = <0 0xe65ee000 0 0x90>;
441 avb: ethernet@e6800000 {
442 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
443 #address-cells = <1>;
449 reg = <0 0xe6e31000 0 8>;
454 scif1: serial@e6e68000 {
455 reg = <0 0xe6e68000 0 64>;
459 scif2: serial@e6e88000 {
460 compatible = "renesas,scif-r8a77961",
461 "renesas,rcar-gen3-scif", "renesas,scif";
462 reg = <0 0xe6e88000 0 64>;
463 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cpg CPG_MOD 310>,
465 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
467 clock-names = "fck", "brg_int", "scif_clk";
468 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
473 vin0: video@e6ef0000 {
474 reg = <0 0xe6ef0000 0 0x1000>;
478 vin1: video@e6ef1000 {
479 reg = <0 0xe6ef1000 0 0x1000>;
483 vin2: video@e6ef2000 {
484 reg = <0 0xe6ef2000 0 0x1000>;
488 vin3: video@e6ef3000 {
489 reg = <0 0xe6ef3000 0 0x1000>;
493 vin4: video@e6ef4000 {
494 reg = <0 0xe6ef4000 0 0x1000>;
498 vin5: video@e6ef5000 {
499 reg = <0 0xe6ef5000 0 0x1000>;
503 vin6: video@e6ef6000 {
504 reg = <0 0xe6ef6000 0 0x1000>;
508 vin7: video@e6ef7000 {
509 reg = <0 0xe6ef7000 0 0x1000>;
513 rcar_sound: sound@ec500000 {
514 reg = <0 0xec500000 0 0x1000>, /* SCU */
515 <0 0xec5a0000 0 0x100>, /* ADG */
516 <0 0xec540000 0 0x1000>, /* SSIU */
517 <0 0xec541000 0 0x280>, /* SSI */
518 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
536 xhci0: usb@ee000000 {
537 reg = <0 0xee000000 0 0xc00>;
541 usb3_peri0: usb@ee020000 {
542 reg = <0 0xee020000 0 0x400>;
546 ohci0: usb@ee080000 {
547 reg = <0 0xee080000 0 0x100>;
551 ohci1: usb@ee0a0000 {
552 reg = <0 0xee0a0000 0 0x100>;
556 ehci0: usb@ee080100 {
557 reg = <0 0xee080100 0 0x100>;
561 ehci1: usb@ee0a0100 {
562 reg = <0 0xee0a0100 0 0x100>;
566 usb2_phy0: usb-phy@ee080200 {
567 reg = <0 0xee080200 0 0x700>;
571 usb2_phy1: usb-phy@ee0a0200 {
572 reg = <0 0xee0a0200 0 0x700>;
577 reg = <0 0xee100000 0 0x2000>;
582 reg = <0 0xee140000 0 0x2000>;
587 reg = <0 0xee160000 0 0x2000>;
591 gic: interrupt-controller@f1010000 {
592 compatible = "arm,gic-400";
593 #interrupt-cells = <3>;
594 #address-cells = <0>;
595 interrupt-controller;
596 reg = <0x0 0xf1010000 0 0x1000>,
597 <0x0 0xf1020000 0 0x20000>,
598 <0x0 0xf1040000 0 0x20000>,
599 <0x0 0xf1060000 0 0x20000>;
600 interrupts = <GIC_PPI 9
601 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
602 clocks = <&cpg CPG_MOD 408>;
604 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
608 pciec0: pcie@fe000000 {
609 reg = <0 0xfe000000 0 0x80000>;
613 pciec1: pcie@ee800000 {
614 reg = <0 0xee800000 0 0x80000>;
618 csi20: csi2@fea80000 {
619 reg = <0 0xfea80000 0 0x10000>;
623 #address-cells = <1>;
627 #address-cells = <1>;
634 csi40: csi2@feaa0000 {
635 reg = <0 0xfeaa0000 0 0x10000>;
639 #address-cells = <1>;
643 #address-cells = <1>;
651 hdmi0: hdmi@fead0000 {
652 reg = <0 0xfead0000 0 0x10000>;
656 #address-cells = <1>;
671 du: display@feb00000 {
672 reg = <0 0xfeb00000 0 0x70000>;
676 #address-cells = <1>;
681 du_out_rgb: endpoint {
686 du_out_hdmi0: endpoint {
691 du_out_lvds0: endpoint {
697 prr: chipid@fff00044 {
698 compatible = "renesas,prr";
699 reg = <0 0xfff00044 0 4>;
704 compatible = "arm,armv8-timer";
705 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
706 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
707 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
708 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
711 /* External USB clocks - can be overridden by the board */
713 compatible = "fixed-clock";
715 clock-frequency = <0>;
718 usb_extal_clk: usb_extal {
719 compatible = "fixed-clock";
721 clock-frequency = <0>;