1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Draak board
5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
13 model = "Renesas Draak board";
14 compatible = "renesas,draak";
21 audio_clkout: audio-clkout {
23 * This is same as <&rcar_sound 0>
24 * but needed to avoid cs2000/rcar_sound probe dead-lock
26 compatible = "fixed-clock";
28 clock-frequency = <12288000>;
31 backlight: backlight {
32 compatible = "pwm-backlight";
33 pwms = <&pwm1 0 50000>;
35 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
36 default-brightness-level = <10>;
38 power-supply = <®_12p0v>;
39 enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
43 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
44 stdout-path = "serial0:115200n8";
48 compatible = "composite-video-connector";
51 composite_con_in: endpoint {
52 remote-endpoint = <&adv7180_in>;
58 compatible = "hdmi-connector";
62 hdmi_con_in: endpoint {
63 remote-endpoint = <&adv7612_in>;
69 compatible = "hdmi-connector";
73 hdmi_con_out: endpoint {
74 remote-endpoint = <&adv7511_out>;
80 compatible = "gpio-keys";
82 pinctrl-0 = <&keys_pins>;
83 pinctrl-names = "default";
86 gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
90 debounce-interval = <20>;
93 gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
97 debounce-interval = <20>;
100 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
101 linux,code = <KEY_3>;
104 debounce-interval = <20>;
107 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
108 linux,code = <KEY_4>;
111 debounce-interval = <20>;
116 compatible = "thine,thc63lvd1024";
117 vcc-supply = <®_3p3v>;
120 #address-cells = <1>;
125 thc63lvd1024_in: endpoint {
126 remote-endpoint = <&lvds0_out>;
132 thc63lvd1024_out: endpoint {
133 remote-endpoint = <&adv7511_in>;
140 device_type = "memory";
141 /* first 128MB is reserved for secure area. */
142 reg = <0x0 0x48000000 0x0 0x18000000>;
145 reg_1p8v: regulator-1p8v {
146 compatible = "regulator-fixed";
147 regulator-name = "fixed-1.8V";
148 regulator-min-microvolt = <1800000>;
149 regulator-max-microvolt = <1800000>;
154 reg_3p3v: regulator-3p3v {
155 compatible = "regulator-fixed";
156 regulator-name = "fixed-3.3V";
157 regulator-min-microvolt = <3300000>;
158 regulator-max-microvolt = <3300000>;
163 reg_12p0v: regulator-12p0v {
164 compatible = "regulator-fixed";
165 regulator-name = "D12.0V";
166 regulator-min-microvolt = <12000000>;
167 regulator-max-microvolt = <12000000>;
173 compatible = "audio-graph-card";
175 dais = <&rsnd_port0 /* ak4613 */
176 /* HDMI is not yet supported */
181 compatible = "vga-connector";
185 remote-endpoint = <&adv7123_out>;
191 compatible = "adi,adv7123";
194 #address-cells = <1>;
199 adv7123_in: endpoint {
200 remote-endpoint = <&du_out_rgb>;
205 adv7123_out: endpoint {
206 remote-endpoint = <&vga_in>;
213 compatible = "fixed-clock";
215 clock-frequency = <74250000>;
219 compatible = "fixed-clock";
221 clock-frequency = <24576000>;
227 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
228 * and R-Car Sound uses AUDIO_CLKB.
229 * Note is that schematic indicates VI4_FIELD conection only
230 * not AUDIO_CLKB at SoC page.
231 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
232 * SW60 should be 1-2.
235 clock-frequency = <22579200>;
239 pinctrl-0 = <&avb0_pins>;
240 pinctrl-names = "default";
241 renesas,no-ether-link;
242 phy-handle = <&phy0>;
245 phy0: ethernet-phy@0 {
246 compatible = "ethernet-phy-id0022.1622",
247 "ethernet-phy-ieee802.3-c22";
248 rxc-skew-ps = <1500>;
250 interrupt-parent = <&gpio5>;
251 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
252 reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
254 * TX clock internal delay mode is required for reliable
255 * 1Gbps communication using the KSZ9031RNX phy present on
256 * the Draak board, however, TX clock internal delay mode
257 * isn't supported on R-Car D3(e). Thus, limit speed to
258 * 100Mbps for reliable communication.
265 pinctrl-0 = <&can0_pins>;
266 pinctrl-names = "default";
271 pinctrl-0 = <&can1_pins>;
272 pinctrl-names = "default";
277 pinctrl-0 = <&du_pins>;
278 pinctrl-names = "default";
281 clocks = <&cpg CPG_MOD 724>,
284 clock-names = "du.0", "du.1", "dclkin.0";
288 du_out_rgb: endpoint {
289 remote-endpoint = <&adv7123_in>;
301 clock-frequency = <48000000>;
310 pinctrl-0 = <&i2c0_pins>;
311 pinctrl-names = "default";
315 compatible = "asahi-kasei,ak4613";
316 #sound-dai-cells = <0>;
318 clocks = <&rcar_sound 0>; /* audio_clkout */
320 asahi-kasei,in1-single-end;
321 asahi-kasei,in2-single-end;
322 asahi-kasei,out1-single-end;
323 asahi-kasei,out2-single-end;
324 asahi-kasei,out3-single-end;
325 asahi-kasei,out4-single-end;
326 asahi-kasei,out5-single-end;
327 asahi-kasei,out6-single-end;
330 ak4613_endpoint: endpoint {
331 remote-endpoint = <&rsnd_for_ak4613>;
337 compatible = "adi,adv7180cp";
341 #address-cells = <1>;
346 adv7180_in: endpoint {
347 remote-endpoint = <&composite_con_in>;
355 * The VIN4 video input path is shared between
356 * CVBS and HDMI inputs through SW[49-53]
359 * HDMI is the default selection, leave CVBS
360 * not connected here.
368 compatible = "adi,adv7511w";
369 reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
370 reg-names = "main", "edid", "cec", "packet";
371 interrupt-parent = <&gpio1>;
372 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
374 avdd-supply = <®_1p8v>;
375 dvdd-supply = <®_1p8v>;
376 pvdd-supply = <®_1p8v>;
377 dvdd-3v-supply = <®_3p3v>;
378 bgvdd-supply = <®_1p8v>;
380 adi,input-depth = <8>;
381 adi,input-colorspace = "rgb";
382 adi,input-clock = "1x";
385 #address-cells = <1>;
390 adv7511_in: endpoint {
391 remote-endpoint = <&thc63lvd1024_out>;
397 adv7511_out: endpoint {
398 remote-endpoint = <&hdmi_con_out>;
405 compatible = "adi,adv7612";
410 #address-cells = <1>;
416 adv7612_in: endpoint {
417 remote-endpoint = <&hdmi_con_in>;
425 * The VIN4 video input path is shared between
426 * CVBS and HDMI inputs through SW[49-53]
429 * HDMI is the default selection, link it to
432 adv7612_out: endpoint {
433 remote-endpoint = <&vin4_in>;
439 cs2000: clk-multiplier@4f {
441 compatible = "cirrus,cs2000-cp";
443 clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
444 clock-names = "clk_in", "ref_clk";
446 assigned-clocks = <&cs2000>;
447 assigned-clock-rates = <24576000>; /* 1/1 divide */
451 compatible = "rohm,br24t01", "atmel,24c01";
458 pinctrl-0 = <&i2c1_pins>;
459 pinctrl-names = "default";
466 clocks = <&cpg CPG_MOD 727>,
469 clock-names = "fck", "dclkin.0", "extal";
473 lvds0_out: endpoint {
474 remote-endpoint = <&thc63lvd1024_in>;
482 * Even though the LVDS1 output is not connected, the encoder must be
483 * enabled to supply a pixel clock to the DU for the DPAD output when
488 clocks = <&cpg CPG_MOD 727>,
491 clock-names = "fck", "dclkin.0", "extal";
501 groups = "avb0_link", "avb0_mdio", "avb0_mii";
506 groups = "can0_data_a";
511 groups = "can1_data_a";
516 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
531 pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
546 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
552 groups = "scif2_data";
557 groups = "mmc_data8", "mmc_ctrl";
559 power-source = <1800>;
562 sdhi2_pins_uhs: sd2_uhs {
563 groups = "mmc_data8", "mmc_ctrl";
565 power-source = <1800>;
569 groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
573 sound_clk_pins: sound-clk {
574 groups = "audio_clk_a", "audio_clk_b",
575 "audio_clkout", "audio_clkout1";
576 function = "audio_clk";
585 groups = "vin4_data24", "vin4_sync", "vin4_clk";
591 pinctrl-0 = <&pwm0_pins>;
592 pinctrl-names = "default";
598 pinctrl-0 = <&pwm1_pins>;
599 pinctrl-names = "default";
605 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
606 pinctrl-names = "default";
609 #sound-dai-cells = <0>;
611 /* audio_clkout0/1 */
613 clock-frequency = <12288000 11289600>;
617 clocks = <&cpg CPG_MOD 1005>,
618 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
619 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
620 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
621 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
622 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
623 <&cs2000>, <&audio_clk_b>,
624 <&cpg CPG_CORE R8A77995_CLK_ZA2>;
628 rsnd_for_ak4613: endpoint {
629 remote-endpoint = <&ak4613_endpoint>;
630 dai-format = "left_j";
631 bitclock-master = <&rsnd_for_ak4613>;
632 frame-master = <&rsnd_for_ak4613>;
633 playback = <&ssi3>, <&src5>, <&dvc0>;
634 capture = <&ssi4>, <&src6>, <&dvc1>;
641 pinctrl-0 = <&rpc_pins>;
642 pinctrl-names = "default";
644 /* Left disabled. To be enabled by firmware when unlocked. */
647 compatible = "cypress,hyperflash", "cfi-flash";
651 compatible = "fixed-partitions";
652 #address-cells = <1>;
656 reg = <0x00000000 0x040000>;
660 reg = <0x00040000 0x140000>;
663 cert_header_sa6@180000 {
664 reg = <0x00180000 0x040000>;
668 reg = <0x001c0000 0x040000>;
672 reg = <0x00200000 0x440000>;
676 reg = <0x00640000 0x100000>;
680 reg = <0x00740000 0x080000>;
683 reg = <0x007c0000 0x1400000>;
686 reg = <0x01bc0000 0x2440000>;
698 pinctrl-0 = <&scif2_pins>;
699 pinctrl-names = "default";
705 /* used for on-board eMMC */
706 pinctrl-0 = <&sdhi2_pins>;
707 pinctrl-1 = <&sdhi2_pins_uhs>;
708 pinctrl-names = "default", "state_uhs";
710 vmmc-supply = <®_3p3v>;
711 vqmmc-supply = <®_1p8v>;
725 pinctrl-0 = <&usb0_pins>;
726 pinctrl-names = "default";
733 pinctrl-0 = <&vin4_pins>;
734 pinctrl-names = "default";
744 remote-endpoint = <&adv7612_out>;