arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2020, Compass Electronics Group, LLC
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         memory@48000000 {
  10                 device_type = "memory";
  11                 /* first 128MB is reserved for secure area. */
  12                 reg = <0x0 0x48000000 0x0 0x78000000>;
  13         };
  14
  15         memory@600000000 {
  16                 device_type = "memory";
  17                 reg = <0x6 0x00000000 0x0 0x80000000>;
  18         };
  19
  20         osc_32k: osc_32k {
  21                 compatible = "fixed-clock";
  22                 #clock-cells = <0>;
  23                 clock-frequency = <32768>;
  24                 clock-output-names = "osc_32k";
  25         };
  26
  27         reg_1p8v: regulator0 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "fixed-1.8V";
  30                 regulator-min-microvolt = <1800000>;
  31                 regulator-max-microvolt = <1800000>;
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35
  36         reg_3p3v: regulator1 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "fixed-3.3V";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45         wlan_pwrseq: wlan_pwrseq {
  46                 compatible = "mmc-pwrseq-simple";
  47                 reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
  48                 clocks = <&osc_32k>;
  49                 clock-names = "ext_clock";
  50                 post-power-on-delay-ms = <80>;
  51         };
  52 };
  53
  54 &avb {
  55         pinctrl-0 = <&avb_pins>;
  56         pinctrl-names = "default";
  57         phy-handle = <&phy0>;
  58         rx-internal-delay-ps = <1800>;
  59         tx-internal-delay-ps = <2000>;
  60         status = "okay";
  61
  62         phy0: ethernet-phy@0 {
  63                 reg = <0>;
  64                 interrupt-parent = <&gpio2>;
  65                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  66                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  67         };
  68 };
  69
  70 &extal_clk {
  71         clock-frequency = <16666666>;
  72 };
  73
  74 &extalr_clk {
  75         clock-frequency = <32768>;
  76 };
  77
  78 &gpio6 {
  79         usb_hub_reset {
  80                 gpio-hog;
  81                 gpios = <10 GPIO_ACTIVE_HIGH>;
  82                 output-high;
  83                 line-name = "usb-hub-reset";
  84         };
  85 };
  86
  87 &hscif0 {
  88         pinctrl-0 = <&hscif0_pins>;
  89         pinctrl-names = "default";
  90         uart-has-rtscts;
  91         status = "okay";
  92         max-speed = <4000000>;
  93
  94         bluetooth {
  95                 compatible = "brcm,bcm43438-bt";
  96                 shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
  97                 host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  98                 device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
  99                 clocks = <&osc_32k>;
 100                 clock-names = "extclk";
 101         };
 102 };
 103
 104 &hscif2 {
 105         status = "okay";
 106         pinctrl-0 = <&hscif2_pins>;
 107         pinctrl-names = "default";
 108 };
 109
 110 &i2c4 {
 111         status = "okay";
 112         clock-frequency = <400000>;
 113
 114         pca9654: gpio@20 {
 115                 compatible = "onnn,pca9654";
 116                 reg = <0x20>;
 117                 gpio-controller;
 118                 #gpio-cells = <2>;
 119                 gpio-line-names =
 120                         "i2c4_20_0",
 121                         "wl_reg_on",
 122                         "bt_reg_on",
 123                         "i2c4_20_3",
 124                         "i2c4_20_4",
 125                         "bt_dev_wake",
 126                         "i2c4_20_6",
 127                         "i2c4_20_7";
 128         };
 129
 130         pca9654_lte: gpio@21 {
 131                 compatible = "onnn,pca9654";
 132                 reg = <0x21>;
 133                 interrupt-parent = <&gpio5>;
 134                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 135                 interrupt-controller;
 136                 #interrupt-cells = <2>;
 137                 gpio-controller;
 138                 #gpio-cells = <2>;
 139                 gpio-line-names =
 140                         "i2c4_21_0",
 141                         "zoe_pwr_on",
 142                         "zoe_extint",
 143                         "zoe_reset_n",
 144                         "sara_reset",
 145                         "i2c4_21_5",
 146                         "sara_pwr_off",
 147                         "sara_networking_status";
 148         };
 149
 150         eeprom@50 {
 151                 compatible = "microchip,at24c64", "atmel,24c64";
 152                 pagesize = <32>;
 153                 read-only;      /* Manufacturing EEPROM programmed at factory */
 154                 reg = <0x50>;
 155         };
 156
 157         rtc@51 {
 158                 compatible = "nxp,pcf85263";
 159                 reg = <0x51>;
 160         };
 161
 162         versaclock5: versaclock_som@6a {
 163                 compatible = "idt,5p49v6965";
 164                 reg = <0x6a>;
 165                 #clock-cells = <1>;
 166                 clocks = <&x304_clk>;
 167                 clock-names = "xin";
 168                 /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
 169                 assigned-clocks = <&versaclock5 1>,
 170                                    <&versaclock5 2>,
 171                                    <&versaclock5 3>,
 172                                    <&versaclock5 4>;
 173                 assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
 174         };
 175 };
 176
 177 &pfc {
 178         pinctrl-0 = <&scif_clk_pins>;
 179         pinctrl-names = "default";
 180
 181         avb_pins: avb {
 182                 mux {
 183                         groups = "avb_link", "avb_mdio", "avb_mii";
 184                         function = "avb";
 185                 };
 186
 187                 pins_mdio {
 188                         groups = "avb_mdio";
 189                         drive-strength = <24>;
 190                 };
 191
 192                 pins_mii_tx {
 193                         pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 194                                "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 195                         drive-strength = <12>;
 196                 };
 197         };
 198
 199         scif2_pins: scif2 {
 200                 groups = "scif2_data_a";
 201                 function = "scif2";
 202         };
 203
 204         hscif0_pins: hscif0 {
 205                 groups = "hscif0_data", "hscif0_ctrl";
 206                 function = "hscif0";
 207         };
 208
 209         hscif1_pins: hscif1 {
 210                 groups = "hscif1_data_a", "hscif1_ctrl_a";
 211                 function = "hscif1";
 212         };
 213
 214         hscif2_pins: hscif2 {
 215                 groups = "hscif2_data_a";
 216                 function = "hscif2";
 217         };
 218
 219         scif0_pins: scif0 {
 220                 groups = "scif0_data";
 221                 function = "scif0";
 222         };
 223
 224         scif5_pins: scif5 {
 225                 groups = "scif5_data_a";
 226                 function = "scif5";
 227         };
 228
 229         scif_clk_pins: scif_clk {
 230                 groups = "scif_clk_a";
 231                 function = "scif_clk";
 232         };
 233
 234         i2c0_pins: i2c0 {
 235                 groups = "i2c0";
 236                 function = "i2c0";
 237         };
 238
 239         sdhi2_pins: sd2 {
 240                 groups = "sdhi2_data4", "sdhi2_ctrl";
 241                 function = "sdhi2";
 242                 power-source = <1800>;
 243         };
 244
 245         sdhi3_pins: sd3 {
 246                 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
 247                 function = "sdhi3";
 248                 power-source = <1800>;
 249         };
 250 };
 251
 252 &scif_clk {
 253         clock-frequency = <14745600>;
 254 };
 255
 256 &scif2 {
 257         pinctrl-0 = <&scif2_pins>;
 258         pinctrl-names = "default";
 259         status = "okay";
 260 };
 261
 262 &sdhi2 {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&sdhi2_pins>;
 265         bus-width = <4>;
 266         vmmc-supply = <&reg_3p3v>;
 267         vqmmc-supply = <&reg_1p8v>;
 268         non-removable;
 269         cap-power-off-card;
 270         pm-ignore-notify;
 271         keep-power-in-suspend;
 272         mmc-pwrseq = <&wlan_pwrseq>;
 273         status = "okay";
 274         #address-cells = <1>;
 275         #size-cells = <0>;
 276
 277         brcmf: bcrmf@1 {
 278                 reg = <1>;
 279                 compatible = "brcm,bcm4329-fmac";
 280                 interrupt-parent = <&gpio1>;
 281                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 282                 interrupt-names = "host-wake";
 283         };
 284 };
 285
 286 &sdhi3 {
 287         pinctrl-0 = <&sdhi3_pins>;
 288         pinctrl-1 = <&sdhi3_pins>;
 289         pinctrl-names = "default", "state_uhs";
 290         vmmc-supply = <&reg_3p3v>;
 291         vqmmc-supply = <&reg_1p8v>;
 292         bus-width = <8>;
 293         mmc-hs200-1_8v;
 294         non-removable;
 295         fixed-emmc-driver-type = <1>;
 296         status = "okay";
 297 };
 298
 299 &usb_extal_clk {
 300         clock-frequency = <50000000>;
 301 };
 302
 303 &usb3s0_clk {
 304         clock-frequency = <100000000>;
 305 };
 306
 307 &vspb {
 308         status = "okay";
 309 };
 310
 311 &vspi0 {
 312         status = "okay";
 313 };