arch/arm64/boot/dts/qcom/sm8450.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
  10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
  11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
  12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/firmware/qcom,scm.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/mailbox/qcom-ipcc.h>
  17 #include <dt-bindings/phy/phy-qcom-qmp.h>
  18 #include <dt-bindings/power/qcom,rpmhpd.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/interconnect/qcom,icc.h>
  21 #include <dt-bindings/interconnect/qcom,sm8450.h>
  22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
  23 #include <dt-bindings/soc/qcom,gpr.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  26 #include <dt-bindings/thermal/thermal.h>
  27
  28 / {
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         chosen { };
  35
  36         clocks {
  37                 xo_board: xo-board {
  38                         compatible = "fixed-clock";
  39                         #clock-cells = <0>;
  40                         clock-frequency = <76800000>;
  41                 };
  42
  43                 sleep_clk: sleep-clk {
  44                         compatible = "fixed-clock";
  45                         #clock-cells = <0>;
  46                         clock-frequency = <32000>;
  47                 };
  48         };
  49
  50         cpus {
  51                 #address-cells = <2>;
  52                 #size-cells = <0>;
  53
  54                 CPU0: cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "qcom,kryo780";
  57                         reg = <0x0 0x0>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&L2_0>;
  60                         power-domains = <&CPU_PD0>;
  61                         power-domain-names = "psci";
  62                         qcom,freq-domain = <&cpufreq_hw 0>;
  63                         #cooling-cells = <2>;
  64                         clocks = <&cpufreq_hw 0>;
  65                         L2_0: l2-cache {
  66                                 compatible = "cache";
  67                                 cache-level = <2>;
  68                                 cache-unified;
  69                                 next-level-cache = <&L3_0>;
  70                                 L3_0: l3-cache {
  71                                         compatible = "cache";
  72                                         cache-level = <3>;
  73                                         cache-unified;
  74                                 };
  75                         };
  76                 };
  77
  78                 CPU1: cpu@100 {
  79                         device_type = "cpu";
  80                         compatible = "qcom,kryo780";
  81                         reg = <0x0 0x100>;
  82                         enable-method = "psci";
  83                         next-level-cache = <&L2_100>;
  84                         power-domains = <&CPU_PD1>;
  85                         power-domain-names = "psci";
  86                         qcom,freq-domain = <&cpufreq_hw 0>;
  87                         #cooling-cells = <2>;
  88                         clocks = <&cpufreq_hw 0>;
  89                         L2_100: l2-cache {
  90                                 compatible = "cache";
  91                                 cache-level = <2>;
  92                                 cache-unified;
  93                                 next-level-cache = <&L3_0>;
  94                         };
  95                 };
  96
  97                 CPU2: cpu@200 {
  98                         device_type = "cpu";
  99                         compatible = "qcom,kryo780";
 100                         reg = <0x0 0x200>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&L2_200>;
 103                         power-domains = <&CPU_PD2>;
 104                         power-domain-names = "psci";
 105                         qcom,freq-domain = <&cpufreq_hw 0>;
 106                         #cooling-cells = <2>;
 107                         clocks = <&cpufreq_hw 0>;
 108                         L2_200: l2-cache {
 109                                 compatible = "cache";
 110                                 cache-level = <2>;
 111                                 cache-unified;
 112                                 next-level-cache = <&L3_0>;
 113                         };
 114                 };
 115
 116                 CPU3: cpu@300 {
 117                         device_type = "cpu";
 118                         compatible = "qcom,kryo780";
 119                         reg = <0x0 0x300>;
 120                         enable-method = "psci";
 121                         next-level-cache = <&L2_300>;
 122                         power-domains = <&CPU_PD3>;
 123                         power-domain-names = "psci";
 124                         qcom,freq-domain = <&cpufreq_hw 0>;
 125                         #cooling-cells = <2>;
 126                         clocks = <&cpufreq_hw 0>;
 127                         L2_300: l2-cache {
 128                                 compatible = "cache";
 129                                 cache-level = <2>;
 130                                 cache-unified;
 131                                 next-level-cache = <&L3_0>;
 132                         };
 133                 };
 134
 135                 CPU4: cpu@400 {
 136                         device_type = "cpu";
 137                         compatible = "qcom,kryo780";
 138                         reg = <0x0 0x400>;
 139                         enable-method = "psci";
 140                         next-level-cache = <&L2_400>;
 141                         power-domains = <&CPU_PD4>;
 142                         power-domain-names = "psci";
 143                         qcom,freq-domain = <&cpufreq_hw 1>;
 144                         #cooling-cells = <2>;
 145                         clocks = <&cpufreq_hw 1>;
 146                         L2_400: l2-cache {
 147                                 compatible = "cache";
 148                                 cache-level = <2>;
 149                                 cache-unified;
 150                                 next-level-cache = <&L3_0>;
 151                         };
 152                 };
 153
 154                 CPU5: cpu@500 {
 155                         device_type = "cpu";
 156                         compatible = "qcom,kryo780";
 157                         reg = <0x0 0x500>;
 158                         enable-method = "psci";
 159                         next-level-cache = <&L2_500>;
 160                         power-domains = <&CPU_PD5>;
 161                         power-domain-names = "psci";
 162                         qcom,freq-domain = <&cpufreq_hw 1>;
 163                         #cooling-cells = <2>;
 164                         clocks = <&cpufreq_hw 1>;
 165                         L2_500: l2-cache {
 166                                 compatible = "cache";
 167                                 cache-level = <2>;
 168                                 cache-unified;
 169                                 next-level-cache = <&L3_0>;
 170                         };
 171                 };
 172
 173                 CPU6: cpu@600 {
 174                         device_type = "cpu";
 175                         compatible = "qcom,kryo780";
 176                         reg = <0x0 0x600>;
 177                         enable-method = "psci";
 178                         next-level-cache = <&L2_600>;
 179                         power-domains = <&CPU_PD6>;
 180                         power-domain-names = "psci";
 181                         qcom,freq-domain = <&cpufreq_hw 1>;
 182                         #cooling-cells = <2>;
 183                         clocks = <&cpufreq_hw 1>;
 184                         L2_600: l2-cache {
 185                                 compatible = "cache";
 186                                 cache-level = <2>;
 187                                 cache-unified;
 188                                 next-level-cache = <&L3_0>;
 189                         };
 190                 };
 191
 192                 CPU7: cpu@700 {
 193                         device_type = "cpu";
 194                         compatible = "qcom,kryo780";
 195                         reg = <0x0 0x700>;
 196                         enable-method = "psci";
 197                         next-level-cache = <&L2_700>;
 198                         power-domains = <&CPU_PD7>;
 199                         power-domain-names = "psci";
 200                         qcom,freq-domain = <&cpufreq_hw 2>;
 201                         #cooling-cells = <2>;
 202                         clocks = <&cpufreq_hw 2>;
 203                         L2_700: l2-cache {
 204                                 compatible = "cache";
 205                                 cache-level = <2>;
 206                                 cache-unified;
 207                                 next-level-cache = <&L3_0>;
 208                         };
 209                 };
 210
 211                 cpu-map {
 212                         cluster0 {
 213                                 core0 {
 214                                         cpu = <&CPU0>;
 215                                 };
 216
 217                                 core1 {
 218                                         cpu = <&CPU1>;
 219                                 };
 220
 221                                 core2 {
 222                                         cpu = <&CPU2>;
 223                                 };
 224
 225                                 core3 {
 226                                         cpu = <&CPU3>;
 227                                 };
 228
 229                                 core4 {
 230                                         cpu = <&CPU4>;
 231                                 };
 232
 233                                 core5 {
 234                                         cpu = <&CPU5>;
 235                                 };
 236
 237                                 core6 {
 238                                         cpu = <&CPU6>;
 239                                 };
 240
 241                                 core7 {
 242                                         cpu = <&CPU7>;
 243                                 };
 244                         };
 245                 };
 246
 247                 idle-states {
 248                         entry-method = "psci";
 249
 250                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 251                                 compatible = "arm,idle-state";
 252                                 idle-state-name = "silver-rail-power-collapse";
 253                                 arm,psci-suspend-param = <0x40000004>;
 254                                 entry-latency-us = <800>;
 255                                 exit-latency-us = <750>;
 256                                 min-residency-us = <4090>;
 257                                 local-timer-stop;
 258                         };
 259
 260                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 261                                 compatible = "arm,idle-state";
 262                                 idle-state-name = "gold-rail-power-collapse";
 263                                 arm,psci-suspend-param = <0x40000004>;
 264                                 entry-latency-us = <600>;
 265                                 exit-latency-us = <1550>;
 266                                 min-residency-us = <4791>;
 267                                 local-timer-stop;
 268                         };
 269                 };
 270
 271                 domain-idle-states {
 272                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 273                                 compatible = "domain-idle-state";
 274                                 arm,psci-suspend-param = <0x41000044>;
 275                                 entry-latency-us = <1050>;
 276                                 exit-latency-us = <2500>;
 277                                 min-residency-us = <5309>;
 278                         };
 279
 280                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 281                                 compatible = "domain-idle-state";
 282                                 arm,psci-suspend-param = <0x4100c344>;
 283                                 entry-latency-us = <2700>;
 284                                 exit-latency-us = <3500>;
 285                                 min-residency-us = <13959>;
 286                         };
 287                 };
 288         };
 289
 290         firmware {
 291                 scm: scm {
 292                         compatible = "qcom,scm-sm8450", "qcom,scm";
 293                         qcom,dload-mode = <&tcsr 0x13000>;
 294                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 295                         #reset-cells = <1>;
 296                 };
 297         };
 298
 299         clk_virt: interconnect-0 {
 300                 compatible = "qcom,sm8450-clk-virt";
 301                 #interconnect-cells = <2>;
 302                 qcom,bcm-voters = <&apps_bcm_voter>;
 303         };
 304
 305         mc_virt: interconnect-1 {
 306                 compatible = "qcom,sm8450-mc-virt";
 307                 #interconnect-cells = <2>;
 308                 qcom,bcm-voters = <&apps_bcm_voter>;
 309         };
 310
 311         memory@a0000000 {
 312                 device_type = "memory";
 313                 /* We expect the bootloader to fill in the size */
 314                 reg = <0x0 0xa0000000 0x0 0x0>;
 315         };
 316
 317         pmu {
 318                 compatible = "arm,armv8-pmuv3";
 319                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 320         };
 321
 322         psci {
 323                 compatible = "arm,psci-1.0";
 324                 method = "smc";
 325
 326                 CPU_PD0: power-domain-cpu0 {
 327                         #power-domain-cells = <0>;
 328                         power-domains = <&CLUSTER_PD>;
 329                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 330                 };
 331
 332                 CPU_PD1: power-domain-cpu1 {
 333                         #power-domain-cells = <0>;
 334                         power-domains = <&CLUSTER_PD>;
 335                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 336                 };
 337
 338                 CPU_PD2: power-domain-cpu2 {
 339                         #power-domain-cells = <0>;
 340                         power-domains = <&CLUSTER_PD>;
 341                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 342                 };
 343
 344                 CPU_PD3: power-domain-cpu3 {
 345                         #power-domain-cells = <0>;
 346                         power-domains = <&CLUSTER_PD>;
 347                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 348                 };
 349
 350                 CPU_PD4: power-domain-cpu4 {
 351                         #power-domain-cells = <0>;
 352                         power-domains = <&CLUSTER_PD>;
 353                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 354                 };
 355
 356                 CPU_PD5: power-domain-cpu5 {
 357                         #power-domain-cells = <0>;
 358                         power-domains = <&CLUSTER_PD>;
 359                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 360                 };
 361
 362                 CPU_PD6: power-domain-cpu6 {
 363                         #power-domain-cells = <0>;
 364                         power-domains = <&CLUSTER_PD>;
 365                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 366                 };
 367
 368                 CPU_PD7: power-domain-cpu7 {
 369                         #power-domain-cells = <0>;
 370                         power-domains = <&CLUSTER_PD>;
 371                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 372                 };
 373
 374                 CLUSTER_PD: power-domain-cpu-cluster0 {
 375                         #power-domain-cells = <0>;
 376                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 377                 };
 378         };
 379
 380         qup_opp_table_100mhz: opp-table-qup {
 381                 compatible = "operating-points-v2";
 382
 383                 opp-50000000 {
 384                         opp-hz = /bits/ 64 <50000000>;
 385                         required-opps = <&rpmhpd_opp_min_svs>;
 386                 };
 387
 388                 opp-75000000 {
 389                         opp-hz = /bits/ 64 <75000000>;
 390                         required-opps = <&rpmhpd_opp_low_svs>;
 391                 };
 392
 393                 opp-100000000 {
 394                         opp-hz = /bits/ 64 <100000000>;
 395                         required-opps = <&rpmhpd_opp_svs>;
 396                 };
 397         };
 398
 399         reserved_memory: reserved-memory {
 400                 #address-cells = <2>;
 401                 #size-cells = <2>;
 402                 ranges;
 403
 404                 hyp_mem: memory@80000000 {
 405                         reg = <0x0 0x80000000 0x0 0x600000>;
 406                         no-map;
 407                 };
 408
 409                 xbl_dt_log_mem: memory@80600000 {
 410                         reg = <0x0 0x80600000 0x0 0x40000>;
 411                         no-map;
 412                 };
 413
 414                 xbl_ramdump_mem: memory@80640000 {
 415                         reg = <0x0 0x80640000 0x0 0x180000>;
 416                         no-map;
 417                 };
 418
 419                 xbl_sc_mem: memory@807c0000 {
 420                         reg = <0x0 0x807c0000 0x0 0x40000>;
 421                         no-map;
 422                 };
 423
 424                 aop_image_mem: memory@80800000 {
 425                         reg = <0x0 0x80800000 0x0 0x60000>;
 426                         no-map;
 427                 };
 428
 429                 aop_cmd_db_mem: memory@80860000 {
 430                         compatible = "qcom,cmd-db";
 431                         reg = <0x0 0x80860000 0x0 0x20000>;
 432                         no-map;
 433                 };
 434
 435                 aop_config_mem: memory@80880000 {
 436                         reg = <0x0 0x80880000 0x0 0x20000>;
 437                         no-map;
 438                 };
 439
 440                 tme_crash_dump_mem: memory@808a0000 {
 441                         reg = <0x0 0x808a0000 0x0 0x40000>;
 442                         no-map;
 443                 };
 444
 445                 tme_log_mem: memory@808e0000 {
 446                         reg = <0x0 0x808e0000 0x0 0x4000>;
 447                         no-map;
 448                 };
 449
 450                 uefi_log_mem: memory@808e4000 {
 451                         reg = <0x0 0x808e4000 0x0 0x10000>;
 452                         no-map;
 453                 };
 454
 455                 /* secdata region can be reused by apps */
 456                 smem: memory@80900000 {
 457                         compatible = "qcom,smem";
 458                         reg = <0x0 0x80900000 0x0 0x200000>;
 459                         hwlocks = <&tcsr_mutex 3>;
 460                         no-map;
 461                 };
 462
 463                 cpucp_fw_mem: memory@80b00000 {
 464                         reg = <0x0 0x80b00000 0x0 0x100000>;
 465                         no-map;
 466                 };
 467
 468                 cdsp_secure_heap: memory@80c00000 {
 469                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 470                         no-map;
 471                 };
 472
 473                 video_mem: memory@85700000 {
 474                         reg = <0x0 0x85700000 0x0 0x700000>;
 475                         no-map;
 476                 };
 477
 478                 adsp_mem: memory@85e00000 {
 479                         reg = <0x0 0x85e00000 0x0 0x2100000>;
 480                         no-map;
 481                 };
 482
 483                 slpi_mem: memory@88000000 {
 484                         reg = <0x0 0x88000000 0x0 0x1900000>;
 485                         no-map;
 486                 };
 487
 488                 cdsp_mem: memory@89900000 {
 489                         reg = <0x0 0x89900000 0x0 0x2000000>;
 490                         no-map;
 491                 };
 492
 493                 ipa_fw_mem: memory@8b900000 {
 494                         reg = <0x0 0x8b900000 0x0 0x10000>;
 495                         no-map;
 496                 };
 497
 498                 ipa_gsi_mem: memory@8b910000 {
 499                         reg = <0x0 0x8b910000 0x0 0xa000>;
 500                         no-map;
 501                 };
 502
 503                 gpu_micro_code_mem: memory@8b91a000 {
 504                         reg = <0x0 0x8b91a000 0x0 0x2000>;
 505                         no-map;
 506                 };
 507
 508                 spss_region_mem: memory@8ba00000 {
 509                         reg = <0x0 0x8ba00000 0x0 0x180000>;
 510                         no-map;
 511                 };
 512
 513                 /* First part of the "SPU secure shared memory" region */
 514                 spu_tz_shared_mem: memory@8bb80000 {
 515                         reg = <0x0 0x8bb80000 0x0 0x60000>;
 516                         no-map;
 517                 };
 518
 519                 /* Second part of the "SPU secure shared memory" region */
 520                 spu_modem_shared_mem: memory@8bbe0000 {
 521                         reg = <0x0 0x8bbe0000 0x0 0x20000>;
 522                         no-map;
 523                 };
 524
 525                 mpss_mem: memory@8bc00000 {
 526                         reg = <0x0 0x8bc00000 0x0 0x13200000>;
 527                         no-map;
 528                 };
 529
 530                 cvp_mem: memory@9ee00000 {
 531                         reg = <0x0 0x9ee00000 0x0 0x700000>;
 532                         no-map;
 533                 };
 534
 535                 camera_mem: memory@9f500000 {
 536                         reg = <0x0 0x9f500000 0x0 0x800000>;
 537                         no-map;
 538                 };
 539
 540                 rmtfs_mem: memory@9fd00000 {
 541                         compatible = "qcom,rmtfs-mem";
 542                         reg = <0x0 0x9fd00000 0x0 0x280000>;
 543                         no-map;
 544
 545                         qcom,client-id = <1>;
 546                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 547                 };
 548
 549                 xbl_sc_mem2: memory@a6e00000 {
 550                         reg = <0x0 0xa6e00000 0x0 0x40000>;
 551                         no-map;
 552                 };
 553
 554                 global_sync_mem: memory@a6f00000 {
 555                         reg = <0x0 0xa6f00000 0x0 0x100000>;
 556                         no-map;
 557                 };
 558
 559                 /* uefi region can be reused by APPS */
 560
 561                 /* Linux kernel image is loaded at 0xa0000000 */
 562
 563                 oem_vm_mem: memory@bb000000 {
 564                         reg = <0x0 0xbb000000 0x0 0x5000000>;
 565                         no-map;
 566                 };
 567
 568                 mte_mem: memory@c0000000 {
 569                         reg = <0x0 0xc0000000 0x0 0x20000000>;
 570                         no-map;
 571                 };
 572
 573                 qheebsp_reserved_mem: memory@e0000000 {
 574                         reg = <0x0 0xe0000000 0x0 0x600000>;
 575                         no-map;
 576                 };
 577
 578                 cpusys_vm_mem: memory@e0600000 {
 579                         reg = <0x0 0xe0600000 0x0 0x400000>;
 580                         no-map;
 581                 };
 582
 583                 hyp_reserved_mem: memory@e0a00000 {
 584                         reg = <0x0 0xe0a00000 0x0 0x100000>;
 585                         no-map;
 586                 };
 587
 588                 trust_ui_vm_mem: memory@e0b00000 {
 589                         reg = <0x0 0xe0b00000 0x0 0x4af3000>;
 590                         no-map;
 591                 };
 592
 593                 trust_ui_vm_qrtr: memory@e55f3000 {
 594                         reg = <0x0 0xe55f3000 0x0 0x9000>;
 595                         no-map;
 596                 };
 597
 598                 trust_ui_vm_vblk0_ring: memory@e55fc000 {
 599                         reg = <0x0 0xe55fc000 0x0 0x4000>;
 600                         no-map;
 601                 };
 602
 603                 trust_ui_vm_swiotlb: memory@e5600000 {
 604                         reg = <0x0 0xe5600000 0x0 0x100000>;
 605                         no-map;
 606                 };
 607
 608                 tz_stat_mem: memory@e8800000 {
 609                         reg = <0x0 0xe8800000 0x0 0x100000>;
 610                         no-map;
 611                 };
 612
 613                 tags_mem: memory@e8900000 {
 614                         reg = <0x0 0xe8900000 0x0 0x1200000>;
 615                         no-map;
 616                 };
 617
 618                 qtee_mem: memory@e9b00000 {
 619                         reg = <0x0 0xe9b00000 0x0 0x500000>;
 620                         no-map;
 621                 };
 622
 623                 trusted_apps_mem: memory@ea000000 {
 624                         reg = <0x0 0xea000000 0x0 0x3900000>;
 625                         no-map;
 626                 };
 627
 628                 trusted_apps_ext_mem: memory@ed900000 {
 629                         reg = <0x0 0xed900000 0x0 0x3b00000>;
 630                         no-map;
 631                 };
 632         };
 633
 634         smp2p-adsp {
 635                 compatible = "qcom,smp2p";
 636                 qcom,smem = <443>, <429>;
 637                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 638                                              IPCC_MPROC_SIGNAL_SMP2P
 639                                              IRQ_TYPE_EDGE_RISING>;
 640                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 641                                 IPCC_MPROC_SIGNAL_SMP2P>;
 642
 643                 qcom,local-pid = <0>;
 644                 qcom,remote-pid = <2>;
 645
 646                 smp2p_adsp_out: master-kernel {
 647                         qcom,entry-name = "master-kernel";
 648                         #qcom,smem-state-cells = <1>;
 649                 };
 650
 651                 smp2p_adsp_in: slave-kernel {
 652                         qcom,entry-name = "slave-kernel";
 653                         interrupt-controller;
 654                         #interrupt-cells = <2>;
 655                 };
 656         };
 657
 658         smp2p-cdsp {
 659                 compatible = "qcom,smp2p";
 660                 qcom,smem = <94>, <432>;
 661                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 662                                              IPCC_MPROC_SIGNAL_SMP2P
 663                                              IRQ_TYPE_EDGE_RISING>;
 664                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 665                                 IPCC_MPROC_SIGNAL_SMP2P>;
 666
 667                 qcom,local-pid = <0>;
 668                 qcom,remote-pid = <5>;
 669
 670                 smp2p_cdsp_out: master-kernel {
 671                         qcom,entry-name = "master-kernel";
 672                         #qcom,smem-state-cells = <1>;
 673                 };
 674
 675                 smp2p_cdsp_in: slave-kernel {
 676                         qcom,entry-name = "slave-kernel";
 677                         interrupt-controller;
 678                         #interrupt-cells = <2>;
 679                 };
 680         };
 681
 682         smp2p-modem {
 683                 compatible = "qcom,smp2p";
 684                 qcom,smem = <435>, <428>;
 685                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 686                                              IPCC_MPROC_SIGNAL_SMP2P
 687                                              IRQ_TYPE_EDGE_RISING>;
 688                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 689                                 IPCC_MPROC_SIGNAL_SMP2P>;
 690
 691                 qcom,local-pid = <0>;
 692                 qcom,remote-pid = <1>;
 693
 694                 smp2p_modem_out: master-kernel {
 695                         qcom,entry-name = "master-kernel";
 696                         #qcom,smem-state-cells = <1>;
 697                 };
 698
 699                 smp2p_modem_in: slave-kernel {
 700                         qcom,entry-name = "slave-kernel";
 701                         interrupt-controller;
 702                         #interrupt-cells = <2>;
 703                 };
 704
 705                 ipa_smp2p_out: ipa-ap-to-modem {
 706                         qcom,entry-name = "ipa";
 707                         #qcom,smem-state-cells = <1>;
 708                 };
 709
 710                 ipa_smp2p_in: ipa-modem-to-ap {
 711                         qcom,entry-name = "ipa";
 712                         interrupt-controller;
 713                         #interrupt-cells = <2>;
 714                 };
 715         };
 716
 717         smp2p-slpi {
 718                 compatible = "qcom,smp2p";
 719                 qcom,smem = <481>, <430>;
 720                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 721                                              IPCC_MPROC_SIGNAL_SMP2P
 722                                              IRQ_TYPE_EDGE_RISING>;
 723                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 724                                 IPCC_MPROC_SIGNAL_SMP2P>;
 725
 726                 qcom,local-pid = <0>;
 727                 qcom,remote-pid = <3>;
 728
 729                 smp2p_slpi_out: master-kernel {
 730                         qcom,entry-name = "master-kernel";
 731                         #qcom,smem-state-cells = <1>;
 732                 };
 733
 734                 smp2p_slpi_in: slave-kernel {
 735                         qcom,entry-name = "slave-kernel";
 736                         interrupt-controller;
 737                         #interrupt-cells = <2>;
 738                 };
 739         };
 740
 741         soc: soc@0 {
 742                 #address-cells = <2>;
 743                 #size-cells = <2>;
 744                 ranges = <0 0 0 0 0x10 0>;
 745                 dma-ranges = <0 0 0 0 0x10 0>;
 746                 compatible = "simple-bus";
 747
 748                 gcc: clock-controller@100000 {
 749                         compatible = "qcom,gcc-sm8450";
 750                         reg = <0x0 0x00100000 0x0 0x1f4200>;
 751                         #clock-cells = <1>;
 752                         #reset-cells = <1>;
 753                         #power-domain-cells = <1>;
 754                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 755                                  <&sleep_clk>,
 756                                  <&pcie0_phy>,
 757                                  <&pcie1_phy>,
 758                                  <0>,
 759                                  <&ufs_mem_phy 0>,
 760                                  <&ufs_mem_phy 1>,
 761                                  <&ufs_mem_phy 2>,
 762                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 763                         clock-names = "bi_tcxo",
 764                                       "sleep_clk",
 765                                       "pcie_0_pipe_clk",
 766                                       "pcie_1_pipe_clk",
 767                                       "pcie_1_phy_aux_clk",
 768                                       "ufs_phy_rx_symbol_0_clk",
 769                                       "ufs_phy_rx_symbol_1_clk",
 770                                       "ufs_phy_tx_symbol_0_clk",
 771                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 772                 };
 773
 774                 gpi_dma2: dma-controller@800000 {
 775                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
 776                         #dma-cells = <3>;
 777                         reg = <0 0x00800000 0 0x60000>;
 778                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 779                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 780                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 781                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 782                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 783                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 784                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 787                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 788                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 790                         dma-channels = <12>;
 791                         dma-channel-mask = <0x7e>;
 792                         iommus = <&apps_smmu 0x496 0x0>;
 793                         status = "disabled";
 794                 };
 795
 796                 qupv3_id_2: geniqup@8c0000 {
 797                         compatible = "qcom,geni-se-qup";
 798                         reg = <0x0 0x008c0000 0x0 0x2000>;
 799                         clock-names = "m-ahb", "s-ahb";
 800                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 801                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 802                         iommus = <&apps_smmu 0x483 0x0>;
 803                         #address-cells = <2>;
 804                         #size-cells = <2>;
 805                         ranges;
 806                         status = "disabled";
 807
 808                         i2c15: i2c@880000 {
 809                                 compatible = "qcom,geni-i2c";
 810                                 reg = <0x0 0x00880000 0x0 0x4000>;
 811                                 clock-names = "se";
 812                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 813                                 pinctrl-names = "default";
 814                                 pinctrl-0 = <&qup_i2c15_data_clk>;
 815                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 816                                 #address-cells = <1>;
 817                                 #size-cells = <0>;
 818                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 819                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 820                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 821                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 822                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 823                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 824                                 dma-names = "tx", "rx";
 825                                 status = "disabled";
 826                         };
 827
 828                         spi15: spi@880000 {
 829                                 compatible = "qcom,geni-spi";
 830                                 reg = <0x0 0x00880000 0x0 0x4000>;
 831                                 clock-names = "se";
 832                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 833                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 834                                 pinctrl-names = "default";
 835                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
 836                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 837                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 838                                 interconnect-names = "qup-core", "qup-config";
 839                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 840                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 841                                 dma-names = "tx", "rx";
 842                                 #address-cells = <1>;
 843                                 #size-cells = <0>;
 844                                 status = "disabled";
 845                         };
 846
 847                         i2c16: i2c@884000 {
 848                                 compatible = "qcom,geni-i2c";
 849                                 reg = <0x0 0x00884000 0x0 0x4000>;
 850                                 clock-names = "se";
 851                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 852                                 pinctrl-names = "default";
 853                                 pinctrl-0 = <&qup_i2c16_data_clk>;
 854                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 855                                 #address-cells = <1>;
 856                                 #size-cells = <0>;
 857                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 858                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 859                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 860                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 861                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 862                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 863                                 dma-names = "tx", "rx";
 864                                 status = "disabled";
 865                         };
 866
 867                         spi16: spi@884000 {
 868                                 compatible = "qcom,geni-spi";
 869                                 reg = <0x0 0x00884000 0x0 0x4000>;
 870                                 clock-names = "se";
 871                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 872                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 873                                 pinctrl-names = "default";
 874                                 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
 875                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 876                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 877                                 interconnect-names = "qup-core", "qup-config";
 878                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 879                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 880                                 dma-names = "tx", "rx";
 881                                 #address-cells = <1>;
 882                                 #size-cells = <0>;
 883                                 status = "disabled";
 884                         };
 885
 886                         i2c17: i2c@888000 {
 887                                 compatible = "qcom,geni-i2c";
 888                                 reg = <0x0 0x00888000 0x0 0x4000>;
 889                                 clock-names = "se";
 890                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 891                                 pinctrl-names = "default";
 892                                 pinctrl-0 = <&qup_i2c17_data_clk>;
 893                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 894                                 #address-cells = <1>;
 895                                 #size-cells = <0>;
 896                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 897                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 898                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 899                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 900                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 901                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 902                                 dma-names = "tx", "rx";
 903                                 status = "disabled";
 904                         };
 905
 906                         spi17: spi@888000 {
 907                                 compatible = "qcom,geni-spi";
 908                                 reg = <0x0 0x00888000 0x0 0x4000>;
 909                                 clock-names = "se";
 910                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 911                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
 914                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 915                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 916                                 interconnect-names = "qup-core", "qup-config";
 917                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 918                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 919                                 dma-names = "tx", "rx";
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 status = "disabled";
 923                         };
 924
 925                         i2c18: i2c@88c000 {
 926                                 compatible = "qcom,geni-i2c";
 927                                 reg = <0x0 0x0088c000 0x0 0x4000>;
 928                                 clock-names = "se";
 929                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 930                                 pinctrl-names = "default";
 931                                 pinctrl-0 = <&qup_i2c18_data_clk>;
 932                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 933                                 #address-cells = <1>;
 934                                 #size-cells = <0>;
 935                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 936                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 937                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 938                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 939                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 940                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 941                                 dma-names = "tx", "rx";
 942                                 status = "disabled";
 943                         };
 944
 945                         spi18: spi@88c000 {
 946                                 compatible = "qcom,geni-spi";
 947                                 reg = <0 0x0088c000 0 0x4000>;
 948                                 clock-names = "se";
 949                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 950                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 951                                 pinctrl-names = "default";
 952                                 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
 953                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 954                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 955                                 interconnect-names = "qup-core", "qup-config";
 956                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 957                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 958                                 dma-names = "tx", "rx";
 959                                 #address-cells = <1>;
 960                                 #size-cells = <0>;
 961                                 status = "disabled";
 962                         };
 963
 964                         i2c19: i2c@890000 {
 965                                 compatible = "qcom,geni-i2c";
 966                                 reg = <0x0 0x00890000 0x0 0x4000>;
 967                                 clock-names = "se";
 968                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 969                                 pinctrl-names = "default";
 970                                 pinctrl-0 = <&qup_i2c19_data_clk>;
 971                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 975                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 976                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 977                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 978                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 979                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 980                                 dma-names = "tx", "rx";
 981                                 status = "disabled";
 982                         };
 983
 984                         spi19: spi@890000 {
 985                                 compatible = "qcom,geni-spi";
 986                                 reg = <0 0x00890000 0 0x4000>;
 987                                 clock-names = "se";
 988                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 989                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 990                                 pinctrl-names = "default";
 991                                 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
 992                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 993                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 994                                 interconnect-names = "qup-core", "qup-config";
 995                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 996                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 997                                 dma-names = "tx", "rx";
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c20: i2c@894000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0x0 0x00894000 0x0 0x4000>;
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&qup_i2c20_data_clk>;
1010                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019                                 dma-names = "tx", "rx";
1020                                 status = "disabled";
1021                         };
1022
1023                         uart20: serial@894000 {
1024                                 compatible = "qcom,geni-uart";
1025                                 reg = <0 0x00894000 0 0x4000>;
1026                                 clock-names = "se";
1027                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028                                 pinctrl-names = "default";
1029                                 pinctrl-0 = <&qup_uart20_default>;
1030                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035                                 interconnect-names = "qup-core",
1036                                                      "qup-config";
1037                                 status = "disabled";
1038                         };
1039
1040                         spi20: spi@894000 {
1041                                 compatible = "qcom,geni-spi";
1042                                 reg = <0 0x00894000 0 0x4000>;
1043                                 clock-names = "se";
1044                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046                                 pinctrl-names = "default";
1047                                 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050                                 interconnect-names = "qup-core", "qup-config";
1051                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053                                 dma-names = "tx", "rx";
1054                                 #address-cells = <1>;
1055                                 #size-cells = <0>;
1056                                 status = "disabled";
1057                         };
1058
1059                         i2c21: i2c@898000 {
1060                                 compatible = "qcom,geni-i2c";
1061                                 reg = <0x0 0x00898000 0x0 0x4000>;
1062                                 clock-names = "se";
1063                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064                                 pinctrl-names = "default";
1065                                 pinctrl-0 = <&qup_i2c21_data_clk>;
1066                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067                                 #address-cells = <1>;
1068                                 #size-cells = <0>;
1069                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074                                        <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075                                 dma-names = "tx", "rx";
1076                                 status = "disabled";
1077                         };
1078
1079                         spi21: spi@898000 {
1080                                 compatible = "qcom,geni-spi";
1081                                 reg = <0 0x00898000 0 0x4000>;
1082                                 clock-names = "se";
1083                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085                                 pinctrl-names = "default";
1086                                 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089                                 interconnect-names = "qup-core", "qup-config";
1090                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091                                        <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092                                 dma-names = "tx", "rx";
1093                                 #address-cells = <1>;
1094                                 #size-cells = <0>;
1095                                 status = "disabled";
1096                         };
1097                 };
1098
1099                 gpi_dma0: dma-controller@900000 {
1100                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101                         #dma-cells = <3>;
1102                         reg = <0 0x00900000 0 0x60000>;
1103                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115                         dma-channels = <12>;
1116                         dma-channel-mask = <0x7e>;
1117                         iommus = <&apps_smmu 0x5b6 0x0>;
1118                         status = "disabled";
1119                 };
1120
1121                 qupv3_id_0: geniqup@9c0000 {
1122                         compatible = "qcom,geni-se-qup";
1123                         reg = <0x0 0x009c0000 0x0 0x2000>;
1124                         clock-names = "m-ahb", "s-ahb";
1125                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127                         iommus = <&apps_smmu 0x5a3 0x0>;
1128                         interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129                         interconnect-names = "qup-core";
1130                         #address-cells = <2>;
1131                         #size-cells = <2>;
1132                         ranges;
1133                         status = "disabled";
1134
1135                         i2c0: i2c@980000 {
1136                                 compatible = "qcom,geni-i2c";
1137                                 reg = <0x0 0x00980000 0x0 0x4000>;
1138                                 clock-names = "se";
1139                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140                                 pinctrl-names = "default";
1141                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1142                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143                                 #address-cells = <1>;
1144                                 #size-cells = <0>;
1145                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151                                 dma-names = "tx", "rx";
1152                                 status = "disabled";
1153                         };
1154
1155                         spi0: spi@980000 {
1156                                 compatible = "qcom,geni-spi";
1157                                 reg = <0x0 0x00980000 0x0 0x4000>;
1158                                 clock-names = "se";
1159                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161                                 pinctrl-names = "default";
1162                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163                                 power-domains = <&rpmhpd RPMHPD_CX>;
1164                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1165                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171                                 dma-names = "tx", "rx";
1172                                 #address-cells = <1>;
1173                                 #size-cells = <0>;
1174                                 status = "disabled";
1175                         };
1176
1177                         i2c1: i2c@984000 {
1178                                 compatible = "qcom,geni-i2c";
1179                                 reg = <0x0 0x00984000 0x0 0x4000>;
1180                                 clock-names = "se";
1181                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182                                 pinctrl-names = "default";
1183                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1184                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185                                 #address-cells = <1>;
1186                                 #size-cells = <0>;
1187                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193                                 dma-names = "tx", "rx";
1194                                 status = "disabled";
1195                         };
1196
1197                         spi1: spi@984000 {
1198                                 compatible = "qcom,geni-spi";
1199                                 reg = <0x0 0x00984000 0x0 0x4000>;
1200                                 clock-names = "se";
1201                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203                                 pinctrl-names = "default";
1204                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211                                 dma-names = "tx", "rx";
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 status = "disabled";
1215                         };
1216
1217                         i2c2: i2c@988000 {
1218                                 compatible = "qcom,geni-i2c";
1219                                 reg = <0x0 0x00988000 0x0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222                                 pinctrl-names = "default";
1223                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1224                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225                                 #address-cells = <1>;
1226                                 #size-cells = <0>;
1227                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233                                 dma-names = "tx", "rx";
1234                                 status = "disabled";
1235                         };
1236
1237                         spi2: spi@988000 {
1238                                 compatible = "qcom,geni-spi";
1239                                 reg = <0x0 0x00988000 0x0 0x4000>;
1240                                 clock-names = "se";
1241                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251                                 dma-names = "tx", "rx";
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 status = "disabled";
1255                         };
1256
1257
1258                         i2c3: i2c@98c000 {
1259                                 compatible = "qcom,geni-i2c";
1260                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1261                                 clock-names = "se";
1262                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263                                 pinctrl-names = "default";
1264                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1265                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266                                 #address-cells = <1>;
1267                                 #size-cells = <0>;
1268                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274                                 dma-names = "tx", "rx";
1275                                 status = "disabled";
1276                         };
1277
1278                         spi3: spi@98c000 {
1279                                 compatible = "qcom,geni-spi";
1280                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1281                                 clock-names = "se";
1282                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284                                 pinctrl-names = "default";
1285                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292                                 dma-names = "tx", "rx";
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                                 status = "disabled";
1296                         };
1297
1298                         i2c4: i2c@990000 {
1299                                 compatible = "qcom,geni-i2c";
1300                                 reg = <0x0 0x00990000 0x0 0x4000>;
1301                                 clock-names = "se";
1302                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303                                 pinctrl-names = "default";
1304                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1305                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306                                 #address-cells = <1>;
1307                                 #size-cells = <0>;
1308                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314                                 dma-names = "tx", "rx";
1315                                 status = "disabled";
1316                         };
1317
1318                         spi4: spi@990000 {
1319                                 compatible = "qcom,geni-spi";
1320                                 reg = <0x0 0x00990000 0x0 0x4000>;
1321                                 clock-names = "se";
1322                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324                                 pinctrl-names = "default";
1325                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326                                 power-domains = <&rpmhpd RPMHPD_CX>;
1327                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1328                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334                                 dma-names = "tx", "rx";
1335                                 #address-cells = <1>;
1336                                 #size-cells = <0>;
1337                                 status = "disabled";
1338                         };
1339
1340                         i2c5: i2c@994000 {
1341                                 compatible = "qcom,geni-i2c";
1342                                 reg = <0x0 0x00994000 0x0 0x4000>;
1343                                 clock-names = "se";
1344                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345                                 pinctrl-names = "default";
1346                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1347                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348                                 #address-cells = <1>;
1349                                 #size-cells = <0>;
1350                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356                                 dma-names = "tx", "rx";
1357                                 status = "disabled";
1358                         };
1359
1360                         spi5: spi@994000 {
1361                                 compatible = "qcom,geni-spi";
1362                                 reg = <0x0 0x00994000 0x0 0x4000>;
1363                                 clock-names = "se";
1364                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366                                 pinctrl-names = "default";
1367                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374                                 dma-names = "tx", "rx";
1375                                 #address-cells = <1>;
1376                                 #size-cells = <0>;
1377                                 status = "disabled";
1378                         };
1379
1380
1381                         i2c6: i2c@998000 {
1382                                 compatible = "qcom,geni-i2c";
1383                                 reg = <0x0 0x00998000 0x0 0x4000>;
1384                                 clock-names = "se";
1385                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386                                 pinctrl-names = "default";
1387                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1388                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389                                 #address-cells = <1>;
1390                                 #size-cells = <0>;
1391                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397                                 dma-names = "tx", "rx";
1398                                 status = "disabled";
1399                         };
1400
1401                         spi6: spi@998000 {
1402                                 compatible = "qcom,geni-spi";
1403                                 reg = <0x0 0x00998000 0x0 0x4000>;
1404                                 clock-names = "se";
1405                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407                                 pinctrl-names = "default";
1408                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415                                 dma-names = "tx", "rx";
1416                                 #address-cells = <1>;
1417                                 #size-cells = <0>;
1418                                 status = "disabled";
1419                         };
1420
1421                         uart7: serial@99c000 {
1422                                 compatible = "qcom,geni-debug-uart";
1423                                 reg = <0 0x0099c000 0 0x4000>;
1424                                 clock-names = "se";
1425                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426                                 pinctrl-names = "default";
1427                                 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433                                 interconnect-names = "qup-core",
1434                                                      "qup-config";
1435                                 status = "disabled";
1436                         };
1437                 };
1438
1439                 gpi_dma1: dma-controller@a00000 {
1440                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441                         #dma-cells = <3>;
1442                         reg = <0 0x00a00000 0 0x60000>;
1443                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455                         dma-channels = <12>;
1456                         dma-channel-mask = <0x7e>;
1457                         iommus = <&apps_smmu 0x56 0x0>;
1458                         status = "disabled";
1459                 };
1460
1461                 qupv3_id_1: geniqup@ac0000 {
1462                         compatible = "qcom,geni-se-qup";
1463                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1464                         clock-names = "m-ahb", "s-ahb";
1465                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467                         iommus = <&apps_smmu 0x43 0x0>;
1468                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469                         interconnect-names = "qup-core";
1470                         #address-cells = <2>;
1471                         #size-cells = <2>;
1472                         ranges;
1473                         status = "disabled";
1474
1475                         i2c8: i2c@a80000 {
1476                                 compatible = "qcom,geni-i2c";
1477                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1478                                 clock-names = "se";
1479                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480                                 pinctrl-names = "default";
1481                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1482                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483                                 #address-cells = <1>;
1484                                 #size-cells = <0>;
1485                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491                                 dma-names = "tx", "rx";
1492                                 status = "disabled";
1493                         };
1494
1495                         spi8: spi@a80000 {
1496                                 compatible = "qcom,geni-spi";
1497                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1498                                 clock-names = "se";
1499                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501                                 pinctrl-names = "default";
1502                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509                                 dma-names = "tx", "rx";
1510                                 #address-cells = <1>;
1511                                 #size-cells = <0>;
1512                                 status = "disabled";
1513                         };
1514
1515                         i2c9: i2c@a84000 {
1516                                 compatible = "qcom,geni-i2c";
1517                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1518                                 clock-names = "se";
1519                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520                                 pinctrl-names = "default";
1521                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1522                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523                                 #address-cells = <1>;
1524                                 #size-cells = <0>;
1525                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531                                 dma-names = "tx", "rx";
1532                                 status = "disabled";
1533                         };
1534
1535                         spi9: spi@a84000 {
1536                                 compatible = "qcom,geni-spi";
1537                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1538                                 clock-names = "se";
1539                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541                                 pinctrl-names = "default";
1542                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549                                 dma-names = "tx", "rx";
1550                                 #address-cells = <1>;
1551                                 #size-cells = <0>;
1552                                 status = "disabled";
1553                         };
1554
1555                         i2c10: i2c@a88000 {
1556                                 compatible = "qcom,geni-i2c";
1557                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1558                                 clock-names = "se";
1559                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560                                 pinctrl-names = "default";
1561                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1562                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563                                 #address-cells = <1>;
1564                                 #size-cells = <0>;
1565                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571                                 dma-names = "tx", "rx";
1572                                 status = "disabled";
1573                         };
1574
1575                         spi10: spi@a88000 {
1576                                 compatible = "qcom,geni-spi";
1577                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1578                                 clock-names = "se";
1579                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581                                 pinctrl-names = "default";
1582                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589                                 dma-names = "tx", "rx";
1590                                 #address-cells = <1>;
1591                                 #size-cells = <0>;
1592                                 status = "disabled";
1593                         };
1594
1595                         i2c11: i2c@a8c000 {
1596                                 compatible = "qcom,geni-i2c";
1597                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598                                 clock-names = "se";
1599                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600                                 pinctrl-names = "default";
1601                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1602                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603                                 #address-cells = <1>;
1604                                 #size-cells = <0>;
1605                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611                                 dma-names = "tx", "rx";
1612                                 status = "disabled";
1613                         };
1614
1615                         spi11: spi@a8c000 {
1616                                 compatible = "qcom,geni-spi";
1617                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618                                 clock-names = "se";
1619                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621                                 pinctrl-names = "default";
1622                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629                                 dma-names = "tx", "rx";
1630                                 #address-cells = <1>;
1631                                 #size-cells = <0>;
1632                                 status = "disabled";
1633                         };
1634
1635                         i2c12: i2c@a90000 {
1636                                 compatible = "qcom,geni-i2c";
1637                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1638                                 clock-names = "se";
1639                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640                                 pinctrl-names = "default";
1641                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1642                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643                                 #address-cells = <1>;
1644                                 #size-cells = <0>;
1645                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651                                 dma-names = "tx", "rx";
1652                                 status = "disabled";
1653                         };
1654
1655                         spi12: spi@a90000 {
1656                                 compatible = "qcom,geni-spi";
1657                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1658                                 clock-names = "se";
1659                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661                                 pinctrl-names = "default";
1662                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669                                 dma-names = "tx", "rx";
1670                                 #address-cells = <1>;
1671                                 #size-cells = <0>;
1672                                 status = "disabled";
1673                         };
1674
1675                         i2c13: i2c@a94000 {
1676                                 compatible = "qcom,geni-i2c";
1677                                 reg = <0 0x00a94000 0 0x4000>;
1678                                 clock-names = "se";
1679                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680                                 pinctrl-names = "default";
1681                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1682                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689                                 dma-names = "tx", "rx";
1690                                 #address-cells = <1>;
1691                                 #size-cells = <0>;
1692                                 status = "disabled";
1693                         };
1694
1695                         spi13: spi@a94000 {
1696                                 compatible = "qcom,geni-spi";
1697                                 reg = <0x0 0x00a94000 0x0 0x4000>;
1698                                 clock-names = "se";
1699                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701                                 pinctrl-names = "default";
1702                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709                                 dma-names = "tx", "rx";
1710                                 #address-cells = <1>;
1711                                 #size-cells = <0>;
1712                                 status = "disabled";
1713                         };
1714
1715                         i2c14: i2c@a98000 {
1716                                 compatible = "qcom,geni-i2c";
1717                                 reg = <0 0x00a98000 0 0x4000>;
1718                                 clock-names = "se";
1719                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720                                 pinctrl-names = "default";
1721                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1722                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729                                 dma-names = "tx", "rx";
1730                                 #address-cells = <1>;
1731                                 #size-cells = <0>;
1732                                 status = "disabled";
1733                         };
1734
1735                         spi14: spi@a98000 {
1736                                 compatible = "qcom,geni-spi";
1737                                 reg = <0x0 0x00a98000 0x0 0x4000>;
1738                                 clock-names = "se";
1739                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741                                 pinctrl-names = "default";
1742                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749                                 dma-names = "tx", "rx";
1750                                 #address-cells = <1>;
1751                                 #size-cells = <0>;
1752                                 status = "disabled";
1753                         };
1754                 };
1755
1756                 rng: rng@10c3000 {
1757                         compatible = "qcom,sm8450-trng", "qcom,trng";
1758                         reg = <0 0x010c3000 0 0x1000>;
1759                 };
1760
1761                 pcie0: pcie@1c00000 {
1762                         compatible = "qcom,pcie-sm8450-pcie0";
1763                         reg = <0 0x01c00000 0 0x3000>,
1764                               <0 0x60000000 0 0xf1d>,
1765                               <0 0x60000f20 0 0xa8>,
1766                               <0 0x60001000 0 0x1000>,
1767                               <0 0x60100000 0 0x100000>;
1768                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1769                         device_type = "pci";
1770                         linux,pci-domain = <0>;
1771                         bus-range = <0x00 0xff>;
1772                         num-lanes = <1>;
1773
1774                         #address-cells = <3>;
1775                         #size-cells = <2>;
1776
1777                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779
1780                         /*
1781                          * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1782                          * Hence, the IDs are swapped.
1783                          */
1784                         msi-map = <0x0 &gic_its 0x5981 0x1>,
1785                                   <0x100 &gic_its 0x5980 0x1>;
1786                         msi-map-mask = <0xff00>;
1787                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1788                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1789                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1790                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1791                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1792                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1793                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1794                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1795                         interrupt-names = "msi0",
1796                                           "msi1",
1797                                           "msi2",
1798                                           "msi3",
1799                                           "msi4",
1800                                           "msi5",
1801                                           "msi6",
1802                                           "msi7";
1803                         #interrupt-cells = <1>;
1804                         interrupt-map-mask = <0 0 0 0x7>;
1805                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1806                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1807                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1808                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1809
1810                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1811                                  <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1812                                  <&pcie0_phy>,
1813                                  <&rpmhcc RPMH_CXO_CLK>,
1814                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1815                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1816                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1817                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1818                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1819                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1820                                  <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1821                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1822                         clock-names = "pipe",
1823                                       "pipe_mux",
1824                                       "phy_pipe",
1825                                       "ref",
1826                                       "aux",
1827                                       "cfg",
1828                                       "bus_master",
1829                                       "bus_slave",
1830                                       "slave_q2a",
1831                                       "ddrss_sf_tbu",
1832                                       "aggre0",
1833                                       "aggre1";
1834
1835                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1836                                     <0x100 &apps_smmu 0x1c01 0x1>;
1837
1838                         resets = <&gcc GCC_PCIE_0_BCR>;
1839                         reset-names = "pci";
1840
1841                         power-domains = <&gcc PCIE_0_GDSC>;
1842
1843                         phys = <&pcie0_phy>;
1844                         phy-names = "pciephy";
1845
1846                         perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1847                         wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1848
1849                         pinctrl-names = "default";
1850                         pinctrl-0 = <&pcie0_default_state>;
1851
1852                         status = "disabled";
1853                 };
1854
1855                 pcie0_phy: phy@1c06000 {
1856                         compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1857                         reg = <0 0x01c06000 0 0x2000>;
1858
1859                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1860                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1861                                  <&gcc GCC_PCIE_0_CLKREF_EN>,
1862                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1863                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1864                         clock-names = "aux",
1865                                       "cfg_ahb",
1866                                       "ref",
1867                                       "rchng",
1868                                       "pipe";
1869
1870                         clock-output-names = "pcie_0_pipe_clk";
1871                         #clock-cells = <0>;
1872
1873                         #phy-cells = <0>;
1874
1875                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1876                         reset-names = "phy";
1877
1878                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1879                         assigned-clock-rates = <100000000>;
1880
1881                         status = "disabled";
1882                 };
1883
1884                 pcie1: pcie@1c08000 {
1885                         compatible = "qcom,pcie-sm8450-pcie1";
1886                         reg = <0 0x01c08000 0 0x3000>,
1887                               <0 0x40000000 0 0xf1d>,
1888                               <0 0x40000f20 0 0xa8>,
1889                               <0 0x40001000 0 0x1000>,
1890                               <0 0x40100000 0 0x100000>;
1891                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1892                         device_type = "pci";
1893                         linux,pci-domain = <1>;
1894                         bus-range = <0x00 0xff>;
1895                         num-lanes = <2>;
1896
1897                         #address-cells = <3>;
1898                         #size-cells = <2>;
1899
1900                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1901                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1902
1903                         /*
1904                          * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1905                          * Hence, the IDs are swapped.
1906                          */
1907                         msi-map = <0x0 &gic_its 0x5a01 0x1>,
1908                                   <0x100 &gic_its 0x5a00 0x1>;
1909                         msi-map-mask = <0xff00>;
1910                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1911                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1912                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1913                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1914                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1915                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1916                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1917                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1918                         interrupt-names = "msi0",
1919                                           "msi1",
1920                                           "msi2",
1921                                           "msi3",
1922                                           "msi4",
1923                                           "msi5",
1924                                           "msi6",
1925                                           "msi7";
1926                         #interrupt-cells = <1>;
1927                         interrupt-map-mask = <0 0 0 0x7>;
1928                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1929                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1930                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1931                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1932
1933                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1934                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1935                                  <&pcie1_phy>,
1936                                  <&rpmhcc RPMH_CXO_CLK>,
1937                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1938                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1939                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1940                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1941                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1942                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1943                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1944                         clock-names = "pipe",
1945                                       "pipe_mux",
1946                                       "phy_pipe",
1947                                       "ref",
1948                                       "aux",
1949                                       "cfg",
1950                                       "bus_master",
1951                                       "bus_slave",
1952                                       "slave_q2a",
1953                                       "ddrss_sf_tbu",
1954                                       "aggre1";
1955
1956                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1957                                     <0x100 &apps_smmu 0x1c81 0x1>;
1958
1959                         resets = <&gcc GCC_PCIE_1_BCR>;
1960                         reset-names = "pci";
1961
1962                         power-domains = <&gcc PCIE_1_GDSC>;
1963
1964                         phys = <&pcie1_phy>;
1965                         phy-names = "pciephy";
1966
1967                         perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1968                         wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1969
1970                         pinctrl-names = "default";
1971                         pinctrl-0 = <&pcie1_default_state>;
1972
1973                         status = "disabled";
1974                 };
1975
1976                 pcie1_phy: phy@1c0e000 {
1977                         compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1978                         reg = <0 0x01c0e000 0 0x2000>;
1979
1980                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1981                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1982                                  <&gcc GCC_PCIE_1_CLKREF_EN>,
1983                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1984                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1985                         clock-names = "aux",
1986                                       "cfg_ahb",
1987                                       "ref",
1988                                       "rchng",
1989                                       "pipe";
1990
1991                         clock-output-names = "pcie_1_pipe_clk";
1992                         #clock-cells = <0>;
1993
1994                         #phy-cells = <0>;
1995
1996                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1997                         reset-names = "phy";
1998
1999                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2000                         assigned-clock-rates = <100000000>;
2001
2002                         status = "disabled";
2003                 };
2004
2005                 config_noc: interconnect@1500000 {
2006                         compatible = "qcom,sm8450-config-noc";
2007                         reg = <0 0x01500000 0 0x1c000>;
2008                         #interconnect-cells = <2>;
2009                         qcom,bcm-voters = <&apps_bcm_voter>;
2010                 };
2011
2012                 system_noc: interconnect@1680000 {
2013                         compatible = "qcom,sm8450-system-noc";
2014                         reg = <0 0x01680000 0 0x1e200>;
2015                         #interconnect-cells = <2>;
2016                         qcom,bcm-voters = <&apps_bcm_voter>;
2017                 };
2018
2019                 pcie_noc: interconnect@16c0000 {
2020                         compatible = "qcom,sm8450-pcie-anoc";
2021                         reg = <0 0x016c0000 0 0xe280>;
2022                         #interconnect-cells = <2>;
2023                         qcom,bcm-voters = <&apps_bcm_voter>;
2024                 };
2025
2026                 aggre1_noc: interconnect@16e0000 {
2027                         compatible = "qcom,sm8450-aggre1-noc";
2028                         reg = <0 0x016e0000 0 0x1c080>;
2029                         #interconnect-cells = <2>;
2030                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2031                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2032                         qcom,bcm-voters = <&apps_bcm_voter>;
2033                 };
2034
2035                 aggre2_noc: interconnect@1700000 {
2036                         compatible = "qcom,sm8450-aggre2-noc";
2037                         reg = <0 0x01700000 0 0x31080>;
2038                         #interconnect-cells = <2>;
2039                         qcom,bcm-voters = <&apps_bcm_voter>;
2040                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2041                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2042                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2043                                  <&rpmhcc RPMH_IPA_CLK>;
2044                 };
2045
2046                 mmss_noc: interconnect@1740000 {
2047                         compatible = "qcom,sm8450-mmss-noc";
2048                         reg = <0 0x01740000 0 0x1f080>;
2049                         #interconnect-cells = <2>;
2050                         qcom,bcm-voters = <&apps_bcm_voter>;
2051                 };
2052
2053                 tcsr_mutex: hwlock@1f40000 {
2054                         compatible = "qcom,tcsr-mutex";
2055                         reg = <0x0 0x01f40000 0x0 0x40000>;
2056                         #hwlock-cells = <1>;
2057                 };
2058
2059                 tcsr: syscon@1fc0000 {
2060                         compatible = "qcom,sm8450-tcsr", "syscon";
2061                         reg = <0x0 0x1fc0000 0x0 0x30000>;
2062                 };
2063
2064                 gpu: gpu@3d00000 {
2065                         compatible = "qcom,adreno-730.1", "qcom,adreno";
2066                         reg = <0x0 0x03d00000 0x0 0x40000>,
2067                               <0x0 0x03d9e000 0x0 0x1000>,
2068                               <0x0 0x03d61000 0x0 0x800>;
2069                         reg-names = "kgsl_3d0_reg_memory",
2070                                     "cx_mem",
2071                                     "cx_dbgc";
2072
2073                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2074
2075                         iommus = <&adreno_smmu 0 0x400>,
2076                                  <&adreno_smmu 1 0x400>;
2077
2078                         operating-points-v2 = <&gpu_opp_table>;
2079
2080                         qcom,gmu = <&gmu>;
2081                         #cooling-cells = <2>;
2082
2083                         status = "disabled";
2084
2085                         zap-shader {
2086                                 memory-region = <&gpu_micro_code_mem>;
2087                         };
2088
2089                         gpu_opp_table: opp-table {
2090                                 compatible = "operating-points-v2";
2091
2092                                 opp-818000000 {
2093                                         opp-hz = /bits/ 64 <818000000>;
2094                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2095                                 };
2096
2097                                 opp-791000000 {
2098                                         opp-hz = /bits/ 64 <791000000>;
2099                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2100                                 };
2101
2102                                 opp-734000000 {
2103                                         opp-hz = /bits/ 64 <734000000>;
2104                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2105                                 };
2106
2107                                 opp-640000000 {
2108                                         opp-hz = /bits/ 64 <640000000>;
2109                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2110                                 };
2111
2112                                 opp-599000000 {
2113                                         opp-hz = /bits/ 64 <599000000>;
2114                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2115                                 };
2116
2117                                 opp-545000000 {
2118                                         opp-hz = /bits/ 64 <545000000>;
2119                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2120                                 };
2121
2122                                 opp-492000000 {
2123                                         opp-hz = /bits/ 64 <492000000>;
2124                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2125                                 };
2126
2127                                 opp-421000000 {
2128                                         opp-hz = /bits/ 64 <421000000>;
2129                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2130                                 };
2131
2132                                 opp-350000000 {
2133                                         opp-hz = /bits/ 64 <350000000>;
2134                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2135                                 };
2136
2137                                 opp-317000000 {
2138                                         opp-hz = /bits/ 64 <317000000>;
2139                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2140                                 };
2141
2142                                 opp-285000000 {
2143                                         opp-hz = /bits/ 64 <285000000>;
2144                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2145                                 };
2146
2147                                 opp-220000000 {
2148                                         opp-hz = /bits/ 64 <220000000>;
2149                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2150                                 };
2151                         };
2152                 };
2153
2154                 gmu: gmu@3d6a000 {
2155                         compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2156                         reg = <0x0 0x03d6a000 0x0 0x35000>,
2157                               <0x0 0x03d50000 0x0 0x10000>,
2158                               <0x0 0x0b290000 0x0 0x10000>;
2159                         reg-names = "gmu", "rscc", "gmu_pdc";
2160
2161                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2162                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2163                         interrupt-names = "hfi", "gmu";
2164
2165                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2166                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2167                                  <&gpucc GPU_CC_CXO_CLK>,
2168                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2169                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2170                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2171                                  <&gpucc GPU_CC_DEMET_CLK>;
2172                         clock-names = "ahb",
2173                                       "gmu",
2174                                       "cxo",
2175                                       "axi",
2176                                       "memnoc",
2177                                       "hub",
2178                                       "demet";
2179
2180                         power-domains = <&gpucc GPU_CX_GDSC>,
2181                                         <&gpucc GPU_GX_GDSC>;
2182                         power-domain-names = "cx",
2183                                              "gx";
2184
2185                         iommus = <&adreno_smmu 5 0x400>;
2186
2187                         qcom,qmp = <&aoss_qmp>;
2188
2189                         operating-points-v2 = <&gmu_opp_table>;
2190
2191                         gmu_opp_table: opp-table {
2192                                 compatible = "operating-points-v2";
2193
2194                                 opp-500000000 {
2195                                         opp-hz = /bits/ 64 <500000000>;
2196                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2197                                 };
2198
2199                                 opp-200000000 {
2200                                         opp-hz = /bits/ 64 <200000000>;
2201                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2202                                 };
2203                         };
2204                 };
2205
2206                 gpucc: clock-controller@3d90000 {
2207                         compatible = "qcom,sm8450-gpucc";
2208                         reg = <0x0 0x03d90000 0x0 0xa000>;
2209                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2210                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2211                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2212                         #clock-cells = <1>;
2213                         #reset-cells = <1>;
2214                         #power-domain-cells = <1>;
2215                 };
2216
2217                 adreno_smmu: iommu@3da0000 {
2218                         compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2219                                      "qcom,smmu-500", "arm,mmu-500";
2220                         reg = <0x0 0x03da0000 0x0 0x40000>;
2221                         #iommu-cells = <2>;
2222                         #global-interrupts = <1>;
2223                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2224                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2225                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2226                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2227                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2228                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2229                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2230                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2231                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2232                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2233                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2234                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2235                                      <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2236                                      <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2237                                      <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2238                                      <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2239                                      <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2240                                      <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2241                                      <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2242                                      <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2243                                      <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2244                                      <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2245                                      <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2246                                      <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2247                                      <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
2248                                      <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
2249                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2250                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2251                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2252                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2253                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2254                                  <&gpucc GPU_CC_AHB_CLK>;
2255                         clock-names = "gmu",
2256                                       "hub",
2257                                       "hlos",
2258                                       "bus",
2259                                       "iface",
2260                                       "ahb";
2261                         power-domains = <&gpucc GPU_CX_GDSC>;
2262                         dma-coherent;
2263                 };
2264
2265                 usb_1_hsphy: phy@88e3000 {
2266                         compatible = "qcom,sm8450-usb-hs-phy",
2267                                      "qcom,usb-snps-hs-7nm-phy";
2268                         reg = <0 0x088e3000 0 0x400>;
2269                         status = "disabled";
2270                         #phy-cells = <0>;
2271
2272                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2273                         clock-names = "ref";
2274
2275                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2276                 };
2277
2278                 usb_1_qmpphy: phy@88e8000 {
2279                         compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2280                         reg = <0 0x088e8000 0 0x3000>;
2281
2282                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2283                                  <&rpmhcc RPMH_CXO_CLK>,
2284                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2285                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2286                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2287
2288                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2289                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2290                         reset-names = "phy", "common";
2291
2292                         #clock-cells = <1>;
2293                         #phy-cells = <1>;
2294
2295                         status = "disabled";
2296
2297                         ports {
2298                                 #address-cells = <1>;
2299                                 #size-cells = <0>;
2300
2301                                 port@0 {
2302                                         reg = <0>;
2303
2304                                         usb_1_qmpphy_out: endpoint {
2305                                         };
2306                                 };
2307
2308                                 port@1 {
2309                                         reg = <1>;
2310
2311                                         usb_1_qmpphy_usb_ss_in: endpoint {
2312                                         };
2313                                 };
2314
2315                                 port@2 {
2316                                         reg = <2>;
2317
2318                                         usb_1_qmpphy_dp_in: endpoint {
2319                                         };
2320                                 };
2321                         };
2322                 };
2323
2324                 remoteproc_slpi: remoteproc@2400000 {
2325                         compatible = "qcom,sm8450-slpi-pas";
2326                         reg = <0 0x02400000 0 0x4000>;
2327
2328                         interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2329                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2330                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2331                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2332                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2333                         interrupt-names = "wdog", "fatal", "ready",
2334                                           "handover", "stop-ack";
2335
2336                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2337                         clock-names = "xo";
2338
2339                         power-domains = <&rpmhpd RPMHPD_LCX>,
2340                                         <&rpmhpd RPMHPD_LMX>;
2341                         power-domain-names = "lcx", "lmx";
2342
2343                         memory-region = <&slpi_mem>;
2344
2345                         qcom,qmp = <&aoss_qmp>;
2346
2347                         qcom,smem-states = <&smp2p_slpi_out 0>;
2348                         qcom,smem-state-names = "stop";
2349
2350                         status = "disabled";
2351
2352                         glink-edge {
2353                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2354                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2355                                                              IRQ_TYPE_EDGE_RISING>;
2356                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2357                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2358
2359                                 label = "slpi";
2360                                 qcom,remote-pid = <3>;
2361
2362                                 fastrpc {
2363                                         compatible = "qcom,fastrpc";
2364                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2365                                         label = "sdsp";
2366                                         #address-cells = <1>;
2367                                         #size-cells = <0>;
2368
2369                                         compute-cb@1 {
2370                                                 compatible = "qcom,fastrpc-compute-cb";
2371                                                 reg = <1>;
2372                                                 iommus = <&apps_smmu 0x0541 0x0>;
2373                                         };
2374
2375                                         compute-cb@2 {
2376                                                 compatible = "qcom,fastrpc-compute-cb";
2377                                                 reg = <2>;
2378                                                 iommus = <&apps_smmu 0x0542 0x0>;
2379                                         };
2380
2381                                         compute-cb@3 {
2382                                                 compatible = "qcom,fastrpc-compute-cb";
2383                                                 reg = <3>;
2384                                                 iommus = <&apps_smmu 0x0543 0x0>;
2385                                                 /* note: shared-cb = <4> in downstream */
2386                                         };
2387                                 };
2388                         };
2389                 };
2390
2391                 wsa2macro: codec@31e0000 {
2392                         compatible = "qcom,sm8450-lpass-wsa-macro";
2393                         reg = <0 0x031e0000 0 0x1000>;
2394                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2395                                  <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2396                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2397                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2398                                  <&vamacro>;
2399                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2400
2401                         #clock-cells = <0>;
2402                         clock-output-names = "wsa2-mclk";
2403                         #sound-dai-cells = <1>;
2404                 };
2405
2406                 swr4: soundwire@31f0000 {
2407                         compatible = "qcom,soundwire-v1.7.0";
2408                         reg = <0 0x031f0000 0 0x2000>;
2409                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2410                         clocks = <&wsa2macro>;
2411                         clock-names = "iface";
2412                         label = "WSA2";
2413
2414                         pinctrl-0 = <&wsa2_swr_active>;
2415                         pinctrl-names = "default";
2416
2417                         qcom,din-ports = <2>;
2418                         qcom,dout-ports = <6>;
2419
2420                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2421                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2422                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2423                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2424                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2425                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2426                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2427                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2428                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2429
2430                         #address-cells = <2>;
2431                         #size-cells = <0>;
2432                         #sound-dai-cells = <1>;
2433                         status = "disabled";
2434                 };
2435
2436                 rxmacro: codec@3200000 {
2437                         compatible = "qcom,sm8450-lpass-rx-macro";
2438                         reg = <0 0x03200000 0 0x1000>;
2439                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2440                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2441                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2442                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2443                                  <&vamacro>;
2444                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2445
2446                         #clock-cells = <0>;
2447                         clock-output-names = "mclk";
2448                         #sound-dai-cells = <1>;
2449                 };
2450
2451                 swr1: soundwire@3210000 {
2452                         compatible = "qcom,soundwire-v1.7.0";
2453                         reg = <0 0x03210000 0 0x2000>;
2454                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2455                         clocks = <&rxmacro>;
2456                         clock-names = "iface";
2457                         label = "RX";
2458                         qcom,din-ports = <0>;
2459                         qcom,dout-ports = <5>;
2460
2461                         pinctrl-0 = <&rx_swr_active>;
2462                         pinctrl-names = "default";
2463
2464                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2465                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2466                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2467                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2468                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2469                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2470                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2471                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2472                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2473
2474                         #address-cells = <2>;
2475                         #size-cells = <0>;
2476                         #sound-dai-cells = <1>;
2477                         status = "disabled";
2478                 };
2479
2480                 txmacro: codec@3220000 {
2481                         compatible = "qcom,sm8450-lpass-tx-macro";
2482                         reg = <0 0x03220000 0 0x1000>;
2483                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2484                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2485                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2486                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2487                                  <&vamacro>;
2488                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2489
2490                         #clock-cells = <0>;
2491                         clock-output-names = "mclk";
2492                         #sound-dai-cells = <1>;
2493                 };
2494
2495                 wsamacro: codec@3240000 {
2496                         compatible = "qcom,sm8450-lpass-wsa-macro";
2497                         reg = <0 0x03240000 0 0x1000>;
2498                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502                                  <&vamacro>;
2503                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2504
2505                         #clock-cells = <0>;
2506                         clock-output-names = "mclk";
2507                         #sound-dai-cells = <1>;
2508                 };
2509
2510                 swr0: soundwire@3250000 {
2511                         compatible = "qcom,soundwire-v1.7.0";
2512                         reg = <0 0x03250000 0 0x2000>;
2513                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2514                         clocks = <&wsamacro>;
2515                         clock-names = "iface";
2516                         label = "WSA";
2517
2518                         pinctrl-0 = <&wsa_swr_active>;
2519                         pinctrl-names = "default";
2520
2521                         qcom,din-ports = <2>;
2522                         qcom,dout-ports = <6>;
2523
2524                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533
2534                         #address-cells = <2>;
2535                         #size-cells = <0>;
2536                         #sound-dai-cells = <1>;
2537                         status = "disabled";
2538                 };
2539
2540                 swr2: soundwire@33b0000 {
2541                         compatible = "qcom,soundwire-v1.7.0";
2542                         reg = <0 0x033b0000 0 0x2000>;
2543                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2544                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2545                         interrupt-names = "core", "wakeup";
2546
2547                         clocks = <&txmacro>;
2548                         clock-names = "iface";
2549                         label = "TX";
2550
2551                         pinctrl-0 = <&tx_swr_active>;
2552                         pinctrl-names = "default";
2553
2554                         qcom,din-ports = <4>;
2555                         qcom,dout-ports = <0>;
2556                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2557                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2558                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2559                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2560                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2561                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2562                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2563                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2564                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2565
2566                         #address-cells = <2>;
2567                         #size-cells = <0>;
2568                         #sound-dai-cells = <1>;
2569                         status = "disabled";
2570                 };
2571
2572                 vamacro: codec@33f0000 {
2573                         compatible = "qcom,sm8450-lpass-va-macro";
2574                         reg = <0 0x033f0000 0 0x1000>;
2575                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2576                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2577                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2578                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2579                         clock-names = "mclk", "macro", "dcodec", "npl";
2580
2581                         #clock-cells = <0>;
2582                         clock-output-names = "fsgen";
2583                         #sound-dai-cells = <1>;
2584                         status = "disabled";
2585                 };
2586
2587                 remoteproc_adsp: remoteproc@30000000 {
2588                         compatible = "qcom,sm8450-adsp-pas";
2589                         reg = <0 0x30000000 0 0x100>;
2590
2591                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2592                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2593                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2594                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2595                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2596                         interrupt-names = "wdog", "fatal", "ready",
2597                                           "handover", "stop-ack";
2598
2599                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2600                         clock-names = "xo";
2601
2602                         power-domains = <&rpmhpd RPMHPD_LCX>,
2603                                         <&rpmhpd RPMHPD_LMX>;
2604                         power-domain-names = "lcx", "lmx";
2605
2606                         memory-region = <&adsp_mem>;
2607
2608                         qcom,qmp = <&aoss_qmp>;
2609
2610                         qcom,smem-states = <&smp2p_adsp_out 0>;
2611                         qcom,smem-state-names = "stop";
2612
2613                         status = "disabled";
2614
2615                         remoteproc_adsp_glink: glink-edge {
2616                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2617                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2618                                                              IRQ_TYPE_EDGE_RISING>;
2619                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2620                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2621
2622                                 label = "lpass";
2623                                 qcom,remote-pid = <2>;
2624
2625                                 gpr {
2626                                         compatible = "qcom,gpr";
2627                                         qcom,glink-channels = "adsp_apps";
2628                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2629                                         qcom,intents = <512 20>;
2630                                         #address-cells = <1>;
2631                                         #size-cells = <0>;
2632
2633                                         q6apm: service@1 {
2634                                                 compatible = "qcom,q6apm";
2635                                                 reg = <GPR_APM_MODULE_IID>;
2636                                                 #sound-dai-cells = <0>;
2637                                                 qcom,protection-domain = "avs/audio",
2638                                                                          "msm/adsp/audio_pd";
2639
2640                                                 q6apmdai: dais {
2641                                                         compatible = "qcom,q6apm-dais";
2642                                                         iommus = <&apps_smmu 0x1801 0x0>;
2643                                                 };
2644
2645                                                 q6apmbedai: bedais {
2646                                                         compatible = "qcom,q6apm-lpass-dais";
2647                                                         #sound-dai-cells = <1>;
2648                                                 };
2649                                         };
2650
2651                                         q6prm: service@2 {
2652                                                 compatible = "qcom,q6prm";
2653                                                 reg = <GPR_PRM_MODULE_IID>;
2654                                                 qcom,protection-domain = "avs/audio",
2655                                                                          "msm/adsp/audio_pd";
2656
2657                                                 q6prmcc: clock-controller {
2658                                                         compatible = "qcom,q6prm-lpass-clocks";
2659                                                         #clock-cells = <2>;
2660                                                 };
2661                                         };
2662                                 };
2663
2664                                 fastrpc {
2665                                         compatible = "qcom,fastrpc";
2666                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2667                                         label = "adsp";
2668                                         #address-cells = <1>;
2669                                         #size-cells = <0>;
2670
2671                                         compute-cb@3 {
2672                                                 compatible = "qcom,fastrpc-compute-cb";
2673                                                 reg = <3>;
2674                                                 iommus = <&apps_smmu 0x1803 0x0>;
2675                                         };
2676
2677                                         compute-cb@4 {
2678                                                 compatible = "qcom,fastrpc-compute-cb";
2679                                                 reg = <4>;
2680                                                 iommus = <&apps_smmu 0x1804 0x0>;
2681                                         };
2682
2683                                         compute-cb@5 {
2684                                                 compatible = "qcom,fastrpc-compute-cb";
2685                                                 reg = <5>;
2686                                                 iommus = <&apps_smmu 0x1805 0x0>;
2687                                         };
2688                                 };
2689                         };
2690                 };
2691
2692                 remoteproc_cdsp: remoteproc@32300000 {
2693                         compatible = "qcom,sm8450-cdsp-pas";
2694                         reg = <0 0x32300000 0 0x1400000>;
2695
2696                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2697                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2698                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2699                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2700                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2701                         interrupt-names = "wdog", "fatal", "ready",
2702                                           "handover", "stop-ack";
2703
2704                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2705                         clock-names = "xo";
2706
2707                         power-domains = <&rpmhpd RPMHPD_CX>,
2708                                         <&rpmhpd RPMHPD_MXC>;
2709                         power-domain-names = "cx", "mxc";
2710
2711                         memory-region = <&cdsp_mem>;
2712
2713                         qcom,qmp = <&aoss_qmp>;
2714
2715                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2716                         qcom,smem-state-names = "stop";
2717
2718                         status = "disabled";
2719
2720                         glink-edge {
2721                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2722                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2723                                                              IRQ_TYPE_EDGE_RISING>;
2724                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2725                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2726
2727                                 label = "cdsp";
2728                                 qcom,remote-pid = <5>;
2729
2730                                 fastrpc {
2731                                         compatible = "qcom,fastrpc";
2732                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2733                                         label = "cdsp";
2734                                         #address-cells = <1>;
2735                                         #size-cells = <0>;
2736
2737                                         compute-cb@1 {
2738                                                 compatible = "qcom,fastrpc-compute-cb";
2739                                                 reg = <1>;
2740                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2741                                                          <&apps_smmu 0x1021 0x1420>;
2742                                         };
2743
2744                                         compute-cb@2 {
2745                                                 compatible = "qcom,fastrpc-compute-cb";
2746                                                 reg = <2>;
2747                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2748                                                          <&apps_smmu 0x1022 0x1420>;
2749                                         };
2750
2751                                         compute-cb@3 {
2752                                                 compatible = "qcom,fastrpc-compute-cb";
2753                                                 reg = <3>;
2754                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2755                                                          <&apps_smmu 0x1023 0x1420>;
2756                                         };
2757
2758                                         compute-cb@4 {
2759                                                 compatible = "qcom,fastrpc-compute-cb";
2760                                                 reg = <4>;
2761                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2762                                                          <&apps_smmu 0x1024 0x1420>;
2763                                         };
2764
2765                                         compute-cb@5 {
2766                                                 compatible = "qcom,fastrpc-compute-cb";
2767                                                 reg = <5>;
2768                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2769                                                          <&apps_smmu 0x1025 0x1420>;
2770                                         };
2771
2772                                         compute-cb@6 {
2773                                                 compatible = "qcom,fastrpc-compute-cb";
2774                                                 reg = <6>;
2775                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2776                                                          <&apps_smmu 0x1026 0x1420>;
2777                                         };
2778
2779                                         compute-cb@7 {
2780                                                 compatible = "qcom,fastrpc-compute-cb";
2781                                                 reg = <7>;
2782                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2783                                                          <&apps_smmu 0x1027 0x1420>;
2784                                         };
2785
2786                                         compute-cb@8 {
2787                                                 compatible = "qcom,fastrpc-compute-cb";
2788                                                 reg = <8>;
2789                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2790                                                          <&apps_smmu 0x1028 0x1420>;
2791                                         };
2792
2793                                         /* note: secure cb9 in downstream */
2794                                 };
2795                         };
2796                 };
2797
2798                 remoteproc_mpss: remoteproc@4080000 {
2799                         compatible = "qcom,sm8450-mpss-pas";
2800                         reg = <0x0 0x04080000 0x0 0x4040>;
2801
2802                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2803                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2804                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2805                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2806                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2807                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2808                         interrupt-names = "wdog", "fatal", "ready", "handover",
2809                                           "stop-ack", "shutdown-ack";
2810
2811                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2812                         clock-names = "xo";
2813
2814                         power-domains = <&rpmhpd RPMHPD_CX>,
2815                                         <&rpmhpd RPMHPD_MSS>;
2816                         power-domain-names = "cx", "mss";
2817
2818                         memory-region = <&mpss_mem>;
2819
2820                         qcom,qmp = <&aoss_qmp>;
2821
2822                         qcom,smem-states = <&smp2p_modem_out 0>;
2823                         qcom,smem-state-names = "stop";
2824
2825                         status = "disabled";
2826
2827                         glink-edge {
2828                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2829                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2830                                                              IRQ_TYPE_EDGE_RISING>;
2831                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2832                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2833                                 label = "modem";
2834                                 qcom,remote-pid = <1>;
2835                         };
2836                 };
2837
2838                 videocc: clock-controller@aaf0000 {
2839                         compatible = "qcom,sm8450-videocc";
2840                         reg = <0 0x0aaf0000 0 0x10000>;
2841                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2842                                  <&gcc GCC_VIDEO_AHB_CLK>;
2843                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2844                         required-opps = <&rpmhpd_opp_low_svs>;
2845                         #clock-cells = <1>;
2846                         #reset-cells = <1>;
2847                         #power-domain-cells = <1>;
2848                 };
2849
2850                 cci0: cci@ac15000 {
2851                         compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2852                         reg = <0 0x0ac15000 0 0x1000>;
2853                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2854                         power-domains = <&camcc TITAN_TOP_GDSC>;
2855
2856                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2857                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2858                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
2859                                  <&camcc CAM_CC_CCI_0_CLK>,
2860                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
2861                         clock-names = "camnoc_axi",
2862                                       "slow_ahb_src",
2863                                       "cpas_ahb",
2864                                       "cci",
2865                                       "cci_src";
2866                         pinctrl-0 = <&cci0_default &cci1_default>;
2867                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2868                         pinctrl-names = "default", "sleep";
2869
2870                         status = "disabled";
2871                         #address-cells = <1>;
2872                         #size-cells = <0>;
2873
2874                         cci0_i2c0: i2c-bus@0 {
2875                                 reg = <0>;
2876                                 clock-frequency = <1000000>;
2877                                 #address-cells = <1>;
2878                                 #size-cells = <0>;
2879                         };
2880
2881                         cci0_i2c1: i2c-bus@1 {
2882                                 reg = <1>;
2883                                 clock-frequency = <1000000>;
2884                                 #address-cells = <1>;
2885                                 #size-cells = <0>;
2886                         };
2887                 };
2888
2889                 cci1: cci@ac16000 {
2890                         compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2891                         reg = <0 0x0ac16000 0 0x1000>;
2892                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2893                         power-domains = <&camcc TITAN_TOP_GDSC>;
2894
2895                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2896                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2897                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
2898                                  <&camcc CAM_CC_CCI_1_CLK>,
2899                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
2900                         clock-names = "camnoc_axi",
2901                                       "slow_ahb_src",
2902                                       "cpas_ahb",
2903                                       "cci",
2904                                       "cci_src";
2905                         pinctrl-0 = <&cci2_default &cci3_default>;
2906                         pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2907                         pinctrl-names = "default", "sleep";
2908
2909                         status = "disabled";
2910                         #address-cells = <1>;
2911                         #size-cells = <0>;
2912
2913                         cci1_i2c0: i2c-bus@0 {
2914                                 reg = <0>;
2915                                 clock-frequency = <1000000>;
2916                                 #address-cells = <1>;
2917                                 #size-cells = <0>;
2918                         };
2919
2920                         cci1_i2c1: i2c-bus@1 {
2921                                 reg = <1>;
2922                                 clock-frequency = <1000000>;
2923                                 #address-cells = <1>;
2924                                 #size-cells = <0>;
2925                         };
2926                 };
2927
2928                 camcc: clock-controller@ade0000 {
2929                         compatible = "qcom,sm8450-camcc";
2930                         reg = <0 0x0ade0000 0 0x20000>;
2931                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2932                                  <&rpmhcc RPMH_CXO_CLK>,
2933                                  <&rpmhcc RPMH_CXO_CLK_A>,
2934                                  <&sleep_clk>;
2935                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2936                         required-opps = <&rpmhpd_opp_low_svs>;
2937                         #clock-cells = <1>;
2938                         #reset-cells = <1>;
2939                         #power-domain-cells = <1>;
2940                         status = "disabled";
2941                 };
2942
2943                 mdss: display-subsystem@ae00000 {
2944                         compatible = "qcom,sm8450-mdss";
2945                         reg = <0 0x0ae00000 0 0x1000>;
2946                         reg-names = "mdss";
2947
2948                         /* same path used twice */
2949                         interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2950                                         <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2951                                         <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2952                                          &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2953                         interconnect-names = "mdp0-mem",
2954                                              "mdp1-mem",
2955                                              "cpu-cfg";
2956
2957                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2958
2959                         power-domains = <&dispcc MDSS_GDSC>;
2960
2961                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2962                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2963                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2964                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2965
2966                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2967                         interrupt-controller;
2968                         #interrupt-cells = <1>;
2969
2970                         iommus = <&apps_smmu 0x2800 0x402>;
2971
2972                         #address-cells = <2>;
2973                         #size-cells = <2>;
2974                         ranges;
2975
2976                         status = "disabled";
2977
2978                         mdss_mdp: display-controller@ae01000 {
2979                                 compatible = "qcom,sm8450-dpu";
2980                                 reg = <0 0x0ae01000 0 0x8f000>,
2981                                       <0 0x0aeb0000 0 0x2008>;
2982                                 reg-names = "mdp", "vbif";
2983
2984                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2985                                         <&gcc GCC_DISP_SF_AXI_CLK>,
2986                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
2987                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2988                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
2989                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2990                                 clock-names = "bus",
2991                                               "nrt_bus",
2992                                               "iface",
2993                                               "lut",
2994                                               "core",
2995                                               "vsync";
2996
2997                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2998                                 assigned-clock-rates = <19200000>;
2999
3000                                 operating-points-v2 = <&mdp_opp_table>;
3001                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3002
3003                                 interrupt-parent = <&mdss>;
3004                                 interrupts = <0>;
3005
3006                                 ports {
3007                                         #address-cells = <1>;
3008                                         #size-cells = <0>;
3009
3010                                         port@0 {
3011                                                 reg = <0>;
3012                                                 dpu_intf1_out: endpoint {
3013                                                         remote-endpoint = <&mdss_dsi0_in>;
3014                                                 };
3015                                         };
3016
3017                                         port@1 {
3018                                                 reg = <1>;
3019                                                 dpu_intf2_out: endpoint {
3020                                                         remote-endpoint = <&mdss_dsi1_in>;
3021                                                 };
3022                                         };
3023
3024                                         port@2 {
3025                                                 reg = <2>;
3026                                                 dpu_intf0_out: endpoint {
3027                                                         remote-endpoint = <&mdss_dp0_in>;
3028                                                 };
3029                                         };
3030                                 };
3031
3032                                 mdp_opp_table: opp-table {
3033                                         compatible = "operating-points-v2";
3034
3035                                         opp-172000000 {
3036                                                 opp-hz = /bits/ 64 <172000000>;
3037                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
3038                                         };
3039
3040                                         opp-200000000 {
3041                                                 opp-hz = /bits/ 64 <200000000>;
3042                                                 required-opps = <&rpmhpd_opp_low_svs>;
3043                                         };
3044
3045                                         opp-325000000 {
3046                                                 opp-hz = /bits/ 64 <325000000>;
3047                                                 required-opps = <&rpmhpd_opp_svs>;
3048                                         };
3049
3050                                         opp-375000000 {
3051                                                 opp-hz = /bits/ 64 <375000000>;
3052                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3053                                         };
3054
3055                                         opp-500000000 {
3056                                                 opp-hz = /bits/ 64 <500000000>;
3057                                                 required-opps = <&rpmhpd_opp_nom>;
3058                                         };
3059                                 };
3060                         };
3061
3062                         mdss_dp0: displayport-controller@ae90000 {
3063                                 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3064                                 reg = <0 0xae90000 0 0x200>,
3065                                       <0 0xae90200 0 0x200>,
3066                                       <0 0xae90400 0 0xc00>,
3067                                       <0 0xae91000 0 0x400>,
3068                                       <0 0xae91400 0 0x400>;
3069                                 interrupt-parent = <&mdss>;
3070                                 interrupts = <12>;
3071                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3072                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3073                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3074                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3075                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3076                                 clock-names = "core_iface",
3077                                               "core_aux",
3078                                               "ctrl_link",
3079                                               "ctrl_link_iface",
3080                                               "stream_pixel";
3081
3082                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3083                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3084                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3085                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3086
3087                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3088                                 phy-names = "dp";
3089
3090                                 #sound-dai-cells = <0>;
3091
3092                                 operating-points-v2 = <&dp_opp_table>;
3093                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3094
3095                                 status = "disabled";
3096
3097                                 ports {
3098                                         #address-cells = <1>;
3099                                         #size-cells = <0>;
3100
3101                                         port@0 {
3102                                                 reg = <0>;
3103                                                 mdss_dp0_in: endpoint {
3104                                                         remote-endpoint = <&dpu_intf0_out>;
3105                                                 };
3106                                         };
3107                                 };
3108
3109                                 dp_opp_table: opp-table {
3110                                         compatible = "operating-points-v2";
3111
3112                                         opp-160000000 {
3113                                                 opp-hz = /bits/ 64 <160000000>;
3114                                                 required-opps = <&rpmhpd_opp_low_svs>;
3115                                         };
3116
3117                                         opp-270000000 {
3118                                                 opp-hz = /bits/ 64 <270000000>;
3119                                                 required-opps = <&rpmhpd_opp_svs>;
3120                                         };
3121
3122                                         opp-540000000 {
3123                                                 opp-hz = /bits/ 64 <540000000>;
3124                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3125                                         };
3126
3127                                         opp-810000000 {
3128                                                 opp-hz = /bits/ 64 <810000000>;
3129                                                 required-opps = <&rpmhpd_opp_nom>;
3130                                         };
3131                                 };
3132                         };
3133
3134                         mdss_dsi0: dsi@ae94000 {
3135                                 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3136                                 reg = <0 0x0ae94000 0 0x400>;
3137                                 reg-names = "dsi_ctrl";
3138
3139                                 interrupt-parent = <&mdss>;
3140                                 interrupts = <4>;
3141
3142                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3143                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3144                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3145                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3146                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3147                                         <&gcc GCC_DISP_HF_AXI_CLK>;
3148                                 clock-names = "byte",
3149                                               "byte_intf",
3150                                               "pixel",
3151                                               "core",
3152                                               "iface",
3153                                               "bus";
3154
3155                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3156                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3157
3158                                 operating-points-v2 = <&mdss_dsi_opp_table>;
3159                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3160
3161                                 phys = <&mdss_dsi0_phy>;
3162                                 phy-names = "dsi";
3163
3164                                 #address-cells = <1>;
3165                                 #size-cells = <0>;
3166
3167                                 status = "disabled";
3168
3169                                 ports {
3170                                         #address-cells = <1>;
3171                                         #size-cells = <0>;
3172
3173                                         port@0 {
3174                                                 reg = <0>;
3175                                                 mdss_dsi0_in: endpoint {
3176                                                         remote-endpoint = <&dpu_intf1_out>;
3177                                                 };
3178                                         };
3179
3180                                         port@1 {
3181                                                 reg = <1>;
3182                                                 mdss_dsi0_out: endpoint {
3183                                                 };
3184                                         };
3185                                 };
3186
3187                                 mdss_dsi_opp_table: opp-table {
3188                                         compatible = "operating-points-v2";
3189
3190                                         opp-187500000 {
3191                                                 opp-hz = /bits/ 64 <187500000>;
3192                                                 required-opps = <&rpmhpd_opp_low_svs>;
3193                                         };
3194
3195                                         opp-300000000 {
3196                                                 opp-hz = /bits/ 64 <300000000>;
3197                                                 required-opps = <&rpmhpd_opp_svs>;
3198                                         };
3199
3200                                         opp-358000000 {
3201                                                 opp-hz = /bits/ 64 <358000000>;
3202                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3203                                         };
3204                                 };
3205                         };
3206
3207                         mdss_dsi0_phy: phy@ae94400 {
3208                                 compatible = "qcom,sm8450-dsi-phy-5nm";
3209                                 reg = <0 0x0ae94400 0 0x200>,
3210                                       <0 0x0ae94600 0 0x280>,
3211                                       <0 0x0ae94900 0 0x260>;
3212                                 reg-names = "dsi_phy",
3213                                             "dsi_phy_lane",
3214                                             "dsi_pll";
3215
3216                                 #clock-cells = <1>;
3217                                 #phy-cells = <0>;
3218
3219                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3220                                          <&rpmhcc RPMH_CXO_CLK>;
3221                                 clock-names = "iface", "ref";
3222
3223                                 status = "disabled";
3224                         };
3225
3226                         mdss_dsi1: dsi@ae96000 {
3227                                 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3228                                 reg = <0 0x0ae96000 0 0x400>;
3229                                 reg-names = "dsi_ctrl";
3230
3231                                 interrupt-parent = <&mdss>;
3232                                 interrupts = <5>;
3233
3234                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3235                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3236                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3237                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3238                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3239                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3240                                 clock-names = "byte",
3241                                               "byte_intf",
3242                                               "pixel",
3243                                               "core",
3244                                               "iface",
3245                                               "bus";
3246
3247                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3248                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3249
3250                                 operating-points-v2 = <&mdss_dsi_opp_table>;
3251                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3252
3253                                 phys = <&mdss_dsi1_phy>;
3254                                 phy-names = "dsi";
3255
3256                                 #address-cells = <1>;
3257                                 #size-cells = <0>;
3258
3259                                 status = "disabled";
3260
3261                                 ports {
3262                                         #address-cells = <1>;
3263                                         #size-cells = <0>;
3264
3265                                         port@0 {
3266                                                 reg = <0>;
3267                                                 mdss_dsi1_in: endpoint {
3268                                                         remote-endpoint = <&dpu_intf2_out>;
3269                                                 };
3270                                         };
3271
3272                                         port@1 {
3273                                                 reg = <1>;
3274                                                 mdss_dsi1_out: endpoint {
3275                                                 };
3276                                         };
3277                                 };
3278                         };
3279
3280                         mdss_dsi1_phy: phy@ae96400 {
3281                                 compatible = "qcom,sm8450-dsi-phy-5nm";
3282                                 reg = <0 0x0ae96400 0 0x200>,
3283                                       <0 0x0ae96600 0 0x280>,
3284                                       <0 0x0ae96900 0 0x260>;
3285                                 reg-names = "dsi_phy",
3286                                             "dsi_phy_lane",
3287                                             "dsi_pll";
3288
3289                                 #clock-cells = <1>;
3290                                 #phy-cells = <0>;
3291
3292                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3293                                          <&rpmhcc RPMH_CXO_CLK>;
3294                                 clock-names = "iface", "ref";
3295
3296                                 status = "disabled";
3297                         };
3298                 };
3299
3300                 dispcc: clock-controller@af00000 {
3301                         compatible = "qcom,sm8450-dispcc";
3302                         reg = <0 0x0af00000 0 0x20000>;
3303                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3304                                  <&rpmhcc RPMH_CXO_CLK_A>,
3305                                  <&gcc GCC_DISP_AHB_CLK>,
3306                                  <&sleep_clk>,
3307                                  <&mdss_dsi0_phy 0>,
3308                                  <&mdss_dsi0_phy 1>,
3309                                  <&mdss_dsi1_phy 0>,
3310                                  <&mdss_dsi1_phy 1>,
3311                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3312                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3313                                  <0>, /* dp1 */
3314                                  <0>,
3315                                  <0>, /* dp2 */
3316                                  <0>,
3317                                  <0>, /* dp3 */
3318                                  <0>;
3319                         power-domains = <&rpmhpd RPMHPD_MMCX>;
3320                         required-opps = <&rpmhpd_opp_low_svs>;
3321                         #clock-cells = <1>;
3322                         #reset-cells = <1>;
3323                         #power-domain-cells = <1>;
3324                         status = "disabled";
3325                 };
3326
3327                 pdc: interrupt-controller@b220000 {
3328                         compatible = "qcom,sm8450-pdc", "qcom,pdc";
3329                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3330                         qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3331                                           <94 609 31>, <125 63 1>, <126 716 12>;
3332                         #interrupt-cells = <2>;
3333                         interrupt-parent = <&intc>;
3334                         interrupt-controller;
3335                 };
3336
3337                 tsens0: thermal-sensor@c263000 {
3338                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3339                         reg = <0 0x0c263000 0 0x1000>, /* TM */
3340                               <0 0x0c222000 0 0x1000>; /* SROT */
3341                         #qcom,sensors = <16>;
3342                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3343                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3344                         interrupt-names = "uplow", "critical";
3345                         #thermal-sensor-cells = <1>;
3346                 };
3347
3348                 tsens1: thermal-sensor@c265000 {
3349                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3350                         reg = <0 0x0c265000 0 0x1000>, /* TM */
3351                               <0 0x0c223000 0 0x1000>; /* SROT */
3352                         #qcom,sensors = <16>;
3353                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3354                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3355                         interrupt-names = "uplow", "critical";
3356                         #thermal-sensor-cells = <1>;
3357                 };
3358
3359                 aoss_qmp: power-management@c300000 {
3360                         compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3361                         reg = <0 0x0c300000 0 0x400>;
3362                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3363                                                      IRQ_TYPE_EDGE_RISING>;
3364                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3365
3366                         #clock-cells = <0>;
3367                 };
3368
3369                 sram@c3f0000 {
3370                         compatible = "qcom,rpmh-stats";
3371                         reg = <0 0x0c3f0000 0 0x400>;
3372                 };
3373
3374                 spmi_bus: spmi@c400000 {
3375                         compatible = "qcom,spmi-pmic-arb";
3376                         reg = <0 0x0c400000 0 0x00003000>,
3377                               <0 0x0c500000 0 0x00400000>,
3378                               <0 0x0c440000 0 0x00080000>,
3379                               <0 0x0c4c0000 0 0x00010000>,
3380                               <0 0x0c42d000 0 0x00010000>;
3381                         reg-names = "core",
3382                                     "chnls",
3383                                     "obsrvr",
3384                                     "intr",
3385                                     "cnfg";
3386                         interrupt-names = "periph_irq";
3387                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3388                         qcom,ee = <0>;
3389                         qcom,channel = <0>;
3390                         interrupt-controller;
3391                         #interrupt-cells = <4>;
3392                         #address-cells = <2>;
3393                         #size-cells = <0>;
3394                 };
3395
3396                 ipcc: mailbox@ed18000 {
3397                         compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3398                         reg = <0 0x0ed18000 0 0x1000>;
3399                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3400                         interrupt-controller;
3401                         #interrupt-cells = <3>;
3402                         #mbox-cells = <2>;
3403                 };
3404
3405                 tlmm: pinctrl@f100000 {
3406                         compatible = "qcom,sm8450-tlmm";
3407                         reg = <0 0x0f100000 0 0x300000>;
3408                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3409                         gpio-controller;
3410                         #gpio-cells = <2>;
3411                         interrupt-controller;
3412                         #interrupt-cells = <2>;
3413                         gpio-ranges = <&tlmm 0 0 211>;
3414                         wakeup-parent = <&pdc>;
3415
3416                         sdc2_default_state: sdc2-default-state {
3417                                 clk-pins {
3418                                         pins = "sdc2_clk";
3419                                         drive-strength = <16>;
3420                                         bias-disable;
3421                                 };
3422
3423                                 cmd-pins {
3424                                         pins = "sdc2_cmd";
3425                                         drive-strength = <16>;
3426                                         bias-pull-up;
3427                                 };
3428
3429                                 data-pins {
3430                                         pins = "sdc2_data";
3431                                         drive-strength = <16>;
3432                                         bias-pull-up;
3433                                 };
3434                         };
3435
3436                         sdc2_sleep_state: sdc2-sleep-state {
3437                                 clk-pins {
3438                                         pins = "sdc2_clk";
3439                                         drive-strength = <2>;
3440                                         bias-disable;
3441                                 };
3442
3443                                 cmd-pins {
3444                                         pins = "sdc2_cmd";
3445                                         drive-strength = <2>;
3446                                         bias-pull-up;
3447                                 };
3448
3449                                 data-pins {
3450                                         pins = "sdc2_data";
3451                                         drive-strength = <2>;
3452                                         bias-pull-up;
3453                                 };
3454                         };
3455
3456                         cci0_default: cci0-default-state {
3457                                 /* SDA, SCL */
3458                                 pins = "gpio110", "gpio111";
3459                                 function = "cci_i2c";
3460                                 drive-strength = <2>;
3461                                 bias-pull-up;
3462                         };
3463
3464                         cci0_sleep: cci0-sleep-state {
3465                                 /* SDA, SCL */
3466                                 pins = "gpio110", "gpio111";
3467                                 function = "cci_i2c";
3468                                 drive-strength = <2>;
3469                                 bias-pull-down;
3470                         };
3471
3472                         cci1_default: cci1-default-state {
3473                                 /* SDA, SCL */
3474                                 pins = "gpio112", "gpio113";
3475                                 function = "cci_i2c";
3476                                 drive-strength = <2>;
3477                                 bias-pull-up;
3478                         };
3479
3480                         cci1_sleep: cci1-sleep-state {
3481                                 /* SDA, SCL */
3482                                 pins = "gpio112", "gpio113";
3483                                 function = "cci_i2c";
3484                                 drive-strength = <2>;
3485                                 bias-pull-down;
3486                         };
3487
3488                         cci2_default: cci2-default-state {
3489                                 /* SDA, SCL */
3490                                 pins = "gpio114", "gpio115";
3491                                 function = "cci_i2c";
3492                                 drive-strength = <2>;
3493                                 bias-pull-up;
3494                         };
3495
3496                         cci2_sleep: cci2-sleep-state {
3497                                 /* SDA, SCL */
3498                                 pins = "gpio114", "gpio115";
3499                                 function = "cci_i2c";
3500                                 drive-strength = <2>;
3501                                 bias-pull-down;
3502                         };
3503
3504                         cci3_default: cci3-default-state {
3505                                 /* SDA, SCL */
3506                                 pins = "gpio208", "gpio209";
3507                                 function = "cci_i2c";
3508                                 drive-strength = <2>;
3509                                 bias-pull-up;
3510                         };
3511
3512                         cci3_sleep: cci3-sleep-state {
3513                                 /* SDA, SCL */
3514                                 pins = "gpio208", "gpio209";
3515                                 function = "cci_i2c";
3516                                 drive-strength = <2>;
3517                                 bias-pull-down;
3518                         };
3519
3520                         pcie0_default_state: pcie0-default-state {
3521                                 perst-pins {
3522                                         pins = "gpio94";
3523                                         function = "gpio";
3524                                         drive-strength = <2>;
3525                                         bias-pull-down;
3526                                 };
3527
3528                                 clkreq-pins {
3529                                         pins = "gpio95";
3530                                         function = "pcie0_clkreqn";
3531                                         drive-strength = <2>;
3532                                         bias-pull-up;
3533                                 };
3534
3535                                 wake-pins {
3536                                         pins = "gpio96";
3537                                         function = "gpio";
3538                                         drive-strength = <2>;
3539                                         bias-pull-up;
3540                                 };
3541                         };
3542
3543                         pcie1_default_state: pcie1-default-state {
3544                                 perst-pins {
3545                                         pins = "gpio97";
3546                                         function = "gpio";
3547                                         drive-strength = <2>;
3548                                         bias-pull-down;
3549                                 };
3550
3551                                 clkreq-pins {
3552                                         pins = "gpio98";
3553                                         function = "pcie1_clkreqn";
3554                                         drive-strength = <2>;
3555                                         bias-pull-up;
3556                                 };
3557
3558                                 wake-pins {
3559                                         pins = "gpio99";
3560                                         function = "gpio";
3561                                         drive-strength = <2>;
3562                                         bias-pull-up;
3563                                 };
3564                         };
3565
3566                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3567                                 pins = "gpio0", "gpio1";
3568                                 function = "qup0";
3569                         };
3570
3571                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3572                                 pins = "gpio4", "gpio5";
3573                                 function = "qup1";
3574                         };
3575
3576                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3577                                 pins = "gpio8", "gpio9";
3578                                 function = "qup2";
3579                         };
3580
3581                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3582                                 pins = "gpio12", "gpio13";
3583                                 function = "qup3";
3584                         };
3585
3586                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3587                                 pins = "gpio16", "gpio17";
3588                                 function = "qup4";
3589                         };
3590
3591                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3592                                 pins = "gpio206", "gpio207";
3593                                 function = "qup5";
3594                         };
3595
3596                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3597                                 pins = "gpio20", "gpio21";
3598                                 function = "qup6";
3599                         };
3600
3601                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3602                                 pins = "gpio28", "gpio29";
3603                                 function = "qup8";
3604                         };
3605
3606                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3607                                 pins = "gpio32", "gpio33";
3608                                 function = "qup9";
3609                         };
3610
3611                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3612                                 pins = "gpio36", "gpio37";
3613                                 function = "qup10";
3614                         };
3615
3616                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3617                                 pins = "gpio40", "gpio41";
3618                                 function = "qup11";
3619                         };
3620
3621                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3622                                 pins = "gpio44", "gpio45";
3623                                 function = "qup12";
3624                         };
3625
3626                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3627                                 pins = "gpio48", "gpio49";
3628                                 function = "qup13";
3629                                 drive-strength = <2>;
3630                                 bias-pull-up;
3631                         };
3632
3633                         qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3634                                 pins = "gpio52", "gpio53";
3635                                 function = "qup14";
3636                                 drive-strength = <2>;
3637                                 bias-pull-up;
3638                         };
3639
3640                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3641                                 pins = "gpio56", "gpio57";
3642                                 function = "qup15";
3643                         };
3644
3645                         qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3646                                 pins = "gpio60", "gpio61";
3647                                 function = "qup16";
3648                         };
3649
3650                         qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3651                                 pins = "gpio64", "gpio65";
3652                                 function = "qup17";
3653                         };
3654
3655                         qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3656                                 pins = "gpio68", "gpio69";
3657                                 function = "qup18";
3658                         };
3659
3660                         qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3661                                 pins = "gpio72", "gpio73";
3662                                 function = "qup19";
3663                         };
3664
3665                         qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3666                                 pins = "gpio76", "gpio77";
3667                                 function = "qup20";
3668                         };
3669
3670                         qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3671                                 pins = "gpio80", "gpio81";
3672                                 function = "qup21";
3673                         };
3674
3675                         qup_spi0_cs: qup-spi0-cs-state {
3676                                 pins = "gpio3";
3677                                 function = "qup0";
3678                         };
3679
3680                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3681                                 pins = "gpio0", "gpio1", "gpio2";
3682                                 function = "qup0";
3683                         };
3684
3685                         qup_spi1_cs: qup-spi1-cs-state {
3686                                 pins = "gpio7";
3687                                 function = "qup1";
3688                         };
3689
3690                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3691                                 pins = "gpio4", "gpio5", "gpio6";
3692                                 function = "qup1";
3693                         };
3694
3695                         qup_spi2_cs: qup-spi2-cs-state {
3696                                 pins = "gpio11";
3697                                 function = "qup2";
3698                         };
3699
3700                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3701                                 pins = "gpio8", "gpio9", "gpio10";
3702                                 function = "qup2";
3703                         };
3704
3705                         qup_spi3_cs: qup-spi3-cs-state {
3706                                 pins = "gpio15";
3707                                 function = "qup3";
3708                         };
3709
3710                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3711                                 pins = "gpio12", "gpio13", "gpio14";
3712                                 function = "qup3";
3713                         };
3714
3715                         qup_spi4_cs: qup-spi4-cs-state {
3716                                 pins = "gpio19";
3717                                 function = "qup4";
3718                                 drive-strength = <6>;
3719                                 bias-disable;
3720                         };
3721
3722                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3723                                 pins = "gpio16", "gpio17", "gpio18";
3724                                 function = "qup4";
3725                         };
3726
3727                         qup_spi5_cs: qup-spi5-cs-state {
3728                                 pins = "gpio85";
3729                                 function = "qup5";
3730                         };
3731
3732                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3733                                 pins = "gpio206", "gpio207", "gpio84";
3734                                 function = "qup5";
3735                         };
3736
3737                         qup_spi6_cs: qup-spi6-cs-state {
3738                                 pins = "gpio23";
3739                                 function = "qup6";
3740                         };
3741
3742                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3743                                 pins = "gpio20", "gpio21", "gpio22";
3744                                 function = "qup6";
3745                         };
3746
3747                         qup_spi8_cs: qup-spi8-cs-state {
3748                                 pins = "gpio31";
3749                                 function = "qup8";
3750                         };
3751
3752                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3753                                 pins = "gpio28", "gpio29", "gpio30";
3754                                 function = "qup8";
3755                         };
3756
3757                         qup_spi9_cs: qup-spi9-cs-state {
3758                                 pins = "gpio35";
3759                                 function = "qup9";
3760                         };
3761
3762                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3763                                 pins = "gpio32", "gpio33", "gpio34";
3764                                 function = "qup9";
3765                         };
3766
3767                         qup_spi10_cs: qup-spi10-cs-state {
3768                                 pins = "gpio39";
3769                                 function = "qup10";
3770                         };
3771
3772                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3773                                 pins = "gpio36", "gpio37", "gpio38";
3774                                 function = "qup10";
3775                         };
3776
3777                         qup_spi11_cs: qup-spi11-cs-state {
3778                                 pins = "gpio43";
3779                                 function = "qup11";
3780                         };
3781
3782                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3783                                 pins = "gpio40", "gpio41", "gpio42";
3784                                 function = "qup11";
3785                         };
3786
3787                         qup_spi12_cs: qup-spi12-cs-state {
3788                                 pins = "gpio47";
3789                                 function = "qup12";
3790                         };
3791
3792                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3793                                 pins = "gpio44", "gpio45", "gpio46";
3794                                 function = "qup12";
3795                         };
3796
3797                         qup_spi13_cs: qup-spi13-cs-state {
3798                                 pins = "gpio51";
3799                                 function = "qup13";
3800                         };
3801
3802                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3803                                 pins = "gpio48", "gpio49", "gpio50";
3804                                 function = "qup13";
3805                         };
3806
3807                         qup_spi14_cs: qup-spi14-cs-state {
3808                                 pins = "gpio55";
3809                                 function = "qup14";
3810                         };
3811
3812                         qup_spi14_data_clk: qup-spi14-data-clk-state {
3813                                 pins = "gpio52", "gpio53", "gpio54";
3814                                 function = "qup14";
3815                         };
3816
3817                         qup_spi15_cs: qup-spi15-cs-state {
3818                                 pins = "gpio59";
3819                                 function = "qup15";
3820                         };
3821
3822                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3823                                 pins = "gpio56", "gpio57", "gpio58";
3824                                 function = "qup15";
3825                         };
3826
3827                         qup_spi16_cs: qup-spi16-cs-state {
3828                                 pins = "gpio63";
3829                                 function = "qup16";
3830                         };
3831
3832                         qup_spi16_data_clk: qup-spi16-data-clk-state {
3833                                 pins = "gpio60", "gpio61", "gpio62";
3834                                 function = "qup16";
3835                         };
3836
3837                         qup_spi17_cs: qup-spi17-cs-state {
3838                                 pins = "gpio67";
3839                                 function = "qup17";
3840                         };
3841
3842                         qup_spi17_data_clk: qup-spi17-data-clk-state {
3843                                 pins = "gpio64", "gpio65", "gpio66";
3844                                 function = "qup17";
3845                         };
3846
3847                         qup_spi18_cs: qup-spi18-cs-state {
3848                                 pins = "gpio71";
3849                                 function = "qup18";
3850                                 drive-strength = <6>;
3851                                 bias-disable;
3852                         };
3853
3854                         qup_spi18_data_clk: qup-spi18-data-clk-state {
3855                                 pins = "gpio68", "gpio69", "gpio70";
3856                                 function = "qup18";
3857                                 drive-strength = <6>;
3858                                 bias-disable;
3859                         };
3860
3861                         qup_spi19_cs: qup-spi19-cs-state {
3862                                 pins = "gpio75";
3863                                 function = "qup19";
3864                                 drive-strength = <6>;
3865                                 bias-disable;
3866                         };
3867
3868                         qup_spi19_data_clk: qup-spi19-data-clk-state {
3869                                 pins = "gpio72", "gpio73", "gpio74";
3870                                 function = "qup19";
3871                                 drive-strength = <6>;
3872                                 bias-disable;
3873                         };
3874
3875                         qup_spi20_cs: qup-spi20-cs-state {
3876                                 pins = "gpio79";
3877                                 function = "qup20";
3878                         };
3879
3880                         qup_spi20_data_clk: qup-spi20-data-clk-state {
3881                                 pins = "gpio76", "gpio77", "gpio78";
3882                                 function = "qup20";
3883                         };
3884
3885                         qup_spi21_cs: qup-spi21-cs-state {
3886                                 pins = "gpio83";
3887                                 function = "qup21";
3888                         };
3889
3890                         qup_spi21_data_clk: qup-spi21-data-clk-state {
3891                                 pins = "gpio80", "gpio81", "gpio82";
3892                                 function = "qup21";
3893                         };
3894
3895                         qup_uart7_rx: qup-uart7-rx-state {
3896                                 pins = "gpio26";
3897                                 function = "qup7";
3898                                 drive-strength = <2>;
3899                                 bias-disable;
3900                         };
3901
3902                         qup_uart7_tx: qup-uart7-tx-state {
3903                                 pins = "gpio27";
3904                                 function = "qup7";
3905                                 drive-strength = <2>;
3906                                 bias-disable;
3907                         };
3908
3909                         qup_uart20_default: qup-uart20-default-state {
3910                                 pins = "gpio76", "gpio77", "gpio78", "gpio79";
3911                                 function = "qup20";
3912                         };
3913                 };
3914
3915                 lpass_tlmm: pinctrl@3440000 {
3916                         compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3917                         reg = <0 0x03440000 0x0 0x20000>,
3918                               <0 0x034d0000 0x0 0x10000>;
3919                         gpio-controller;
3920                         #gpio-cells = <2>;
3921                         gpio-ranges = <&lpass_tlmm 0 0 23>;
3922
3923                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3924                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3925                         clock-names = "core", "audio";
3926
3927                         tx_swr_active: tx-swr-active-state {
3928                                 clk-pins {
3929                                         pins = "gpio0";
3930                                         function = "swr_tx_clk";
3931                                         drive-strength = <2>;
3932                                         slew-rate = <1>;
3933                                         bias-disable;
3934                                 };
3935
3936                                 data-pins {
3937                                         pins = "gpio1", "gpio2", "gpio14";
3938                                         function = "swr_tx_data";
3939                                         drive-strength = <2>;
3940                                         slew-rate = <1>;
3941                                         bias-bus-hold;
3942                                 };
3943                         };
3944
3945                         rx_swr_active: rx-swr-active-state {
3946                                 clk-pins {
3947                                         pins = "gpio3";
3948                                         function = "swr_rx_clk";
3949                                         drive-strength = <2>;
3950                                         slew-rate = <1>;
3951                                         bias-disable;
3952                                 };
3953
3954                                 data-pins {
3955                                         pins = "gpio4", "gpio5";
3956                                         function = "swr_rx_data";
3957                                         drive-strength = <2>;
3958                                         slew-rate = <1>;
3959                                         bias-bus-hold;
3960                                 };
3961                         };
3962
3963                         dmic01_default: dmic01-default-state {
3964                                 clk-pins {
3965                                         pins = "gpio6";
3966                                         function = "dmic1_clk";
3967                                         drive-strength = <8>;
3968                                         output-high;
3969                                 };
3970
3971                                 data-pins {
3972                                         pins = "gpio7";
3973                                         function = "dmic1_data";
3974                                         drive-strength = <8>;
3975                                 };
3976                         };
3977
3978                         dmic23_default: dmic23-default-state {
3979                                 clk-pins {
3980                                         pins = "gpio8";
3981                                         function = "dmic2_clk";
3982                                         drive-strength = <8>;
3983                                         output-high;
3984                                 };
3985
3986                                 data-pins {
3987                                         pins = "gpio9";
3988                                         function = "dmic2_data";
3989                                         drive-strength = <8>;
3990                                 };
3991                         };
3992
3993                         wsa_swr_active: wsa-swr-active-state {
3994                                 clk-pins {
3995                                         pins = "gpio10";
3996                                         function = "wsa_swr_clk";
3997                                         drive-strength = <2>;
3998                                         slew-rate = <1>;
3999                                         bias-disable;
4000                                 };
4001
4002                                 data-pins {
4003                                         pins = "gpio11";
4004                                         function = "wsa_swr_data";
4005                                         drive-strength = <2>;
4006                                         slew-rate = <1>;
4007                                         bias-bus-hold;
4008                                 };
4009                         };
4010
4011                         wsa2_swr_active: wsa2-swr-active-state {
4012                                 clk-pins {
4013                                         pins = "gpio15";
4014                                         function = "wsa2_swr_clk";
4015                                         drive-strength = <2>;
4016                                         slew-rate = <1>;
4017                                         bias-disable;
4018                                 };
4019
4020                                 data-pins {
4021                                         pins = "gpio16";
4022                                         function = "wsa2_swr_data";
4023                                         drive-strength = <2>;
4024                                         slew-rate = <1>;
4025                                         bias-bus-hold;
4026                                 };
4027                         };
4028                 };
4029
4030                 sram@146aa000 {
4031                         compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4032                         reg = <0 0x146aa000 0 0x1000>;
4033                         ranges = <0 0 0x146aa000 0x1000>;
4034
4035                         #address-cells = <1>;
4036                         #size-cells = <1>;
4037
4038                         pil-reloc@94c {
4039                                 compatible = "qcom,pil-reloc-info";
4040                                 reg = <0x94c 0xc8>;
4041                         };
4042                 };
4043
4044                 apps_smmu: iommu@15000000 {
4045                         compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4046                         reg = <0 0x15000000 0 0x100000>;
4047                         #iommu-cells = <2>;
4048                         #global-interrupts = <1>;
4049                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4050                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4051                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4052                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4053                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4054                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4055                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4056                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4057                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4058                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4059                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4060                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4061                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4062                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4063                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4064                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4065                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4066                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4067                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4068                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4069                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4070                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4071                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4072                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4073                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4074                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4075                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4076                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4077                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4078                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4079                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4080                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4081                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4082                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4083                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4084                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4085                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4086                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4087                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4088                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4089                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4090                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4091                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4092                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4093                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4094                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4095                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4096                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4097                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4098                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4099                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4100                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4101                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4102                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4103                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4104                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4105                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4106                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4107                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4108                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4109                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4110                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4111                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4112                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4113                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4114                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4115                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4116                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4117                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4118                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4119                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4120                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4121                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4122                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4123                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4124                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4125                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4126                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4127                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4128                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4129                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4130                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4131                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4132                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4133                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4134                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4135                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4136                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4137                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4138                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4139                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4140                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4141                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4142                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4143                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4144                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4145                                      <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4146                 };
4147
4148                 intc: interrupt-controller@17100000 {
4149                         compatible = "arm,gic-v3";
4150                         #interrupt-cells = <3>;
4151                         interrupt-controller;
4152                         #redistributor-regions = <1>;
4153                         redistributor-stride = <0x0 0x40000>;
4154                         reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
4155                               <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
4156                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4157                         #address-cells = <2>;
4158                         #size-cells = <2>;
4159                         ranges;
4160
4161                         gic_its: msi-controller@17140000 {
4162                                 compatible = "arm,gic-v3-its";
4163                                 reg = <0x0 0x17140000 0x0 0x20000>;
4164                                 msi-controller;
4165                                 #msi-cells = <1>;
4166                         };
4167                 };
4168
4169                 timer@17420000 {
4170                         compatible = "arm,armv7-timer-mem";
4171                         #address-cells = <1>;
4172                         #size-cells = <1>;
4173                         ranges = <0 0 0 0x20000000>;
4174                         reg = <0x0 0x17420000 0x0 0x1000>;
4175                         clock-frequency = <19200000>;
4176
4177                         frame@17421000 {
4178                                 frame-number = <0>;
4179                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4180                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4181                                 reg = <0x17421000 0x1000>,
4182                                       <0x17422000 0x1000>;
4183                         };
4184
4185                         frame@17423000 {
4186                                 frame-number = <1>;
4187                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4188                                 reg = <0x17423000 0x1000>;
4189                                 status = "disabled";
4190                         };
4191
4192                         frame@17425000 {
4193                                 frame-number = <2>;
4194                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4195                                 reg = <0x17425000 0x1000>;
4196                                 status = "disabled";
4197                         };
4198
4199                         frame@17427000 {
4200                                 frame-number = <3>;
4201                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4202                                 reg = <0x17427000 0x1000>;
4203                                 status = "disabled";
4204                         };
4205
4206                         frame@17429000 {
4207                                 frame-number = <4>;
4208                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4209                                 reg = <0x17429000 0x1000>;
4210                                 status = "disabled";
4211                         };
4212
4213                         frame@1742b000 {
4214                                 frame-number = <5>;
4215                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4216                                 reg = <0x1742b000 0x1000>;
4217                                 status = "disabled";
4218                         };
4219
4220                         frame@1742d000 {
4221                                 frame-number = <6>;
4222                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4223                                 reg = <0x1742d000 0x1000>;
4224                                 status = "disabled";
4225                         };
4226                 };
4227
4228                 apps_rsc: rsc@17a00000 {
4229                         label = "apps_rsc";
4230                         compatible = "qcom,rpmh-rsc";
4231                         reg = <0x0 0x17a00000 0x0 0x10000>,
4232                               <0x0 0x17a10000 0x0 0x10000>,
4233                               <0x0 0x17a20000 0x0 0x10000>,
4234                               <0x0 0x17a30000 0x0 0x10000>;
4235                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4236                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4237                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4238                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4239                         qcom,tcs-offset = <0xd00>;
4240                         qcom,drv-id = <2>;
4241                         qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
4242                                           <WAKE_TCS    2>, <CONTROL_TCS 0>;
4243                         power-domains = <&CLUSTER_PD>;
4244
4245                         apps_bcm_voter: bcm-voter {
4246                                 compatible = "qcom,bcm-voter";
4247                         };
4248
4249                         rpmhcc: clock-controller {
4250                                 compatible = "qcom,sm8450-rpmh-clk";
4251                                 #clock-cells = <1>;
4252                                 clock-names = "xo";
4253                                 clocks = <&xo_board>;
4254                         };
4255
4256                         rpmhpd: power-controller {
4257                                 compatible = "qcom,sm8450-rpmhpd";
4258                                 #power-domain-cells = <1>;
4259                                 operating-points-v2 = <&rpmhpd_opp_table>;
4260
4261                                 rpmhpd_opp_table: opp-table {
4262                                         compatible = "operating-points-v2";
4263
4264                                         rpmhpd_opp_ret: opp1 {
4265                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4266                                         };
4267
4268                                         rpmhpd_opp_min_svs: opp2 {
4269                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4270                                         };
4271
4272                                         rpmhpd_opp_low_svs_d1: opp3 {
4273                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4274                                         };
4275
4276                                         rpmhpd_opp_low_svs: opp4 {
4277                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4278                                         };
4279
4280                                         rpmhpd_opp_low_svs_l1: opp5 {
4281                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4282                                         };
4283
4284                                         rpmhpd_opp_svs: opp6 {
4285                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4286                                         };
4287
4288                                         rpmhpd_opp_svs_l0: opp7 {
4289                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4290                                         };
4291
4292                                         rpmhpd_opp_svs_l1: opp8 {
4293                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4294                                         };
4295
4296                                         rpmhpd_opp_svs_l2: opp9 {
4297                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4298                                         };
4299
4300                                         rpmhpd_opp_nom: opp10 {
4301                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4302                                         };
4303
4304                                         rpmhpd_opp_nom_l1: opp11 {
4305                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4306                                         };
4307
4308                                         rpmhpd_opp_nom_l2: opp12 {
4309                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4310                                         };
4311
4312                                         rpmhpd_opp_turbo: opp13 {
4313                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4314                                         };
4315
4316                                         rpmhpd_opp_turbo_l1: opp14 {
4317                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4318                                         };
4319                                 };
4320                         };
4321                 };
4322
4323                 cpufreq_hw: cpufreq@17d91000 {
4324                         compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4325                         reg = <0 0x17d91000 0 0x1000>,
4326                               <0 0x17d92000 0 0x1000>,
4327                               <0 0x17d93000 0 0x1000>;
4328                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4329                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4330                         clock-names = "xo", "alternate";
4331                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4332                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4333                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4334                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4335                         #freq-domain-cells = <1>;
4336                         #clock-cells = <1>;
4337                 };
4338
4339                 gem_noc: interconnect@19100000 {
4340                         compatible = "qcom,sm8450-gem-noc";
4341                         reg = <0 0x19100000 0 0xbb800>;
4342                         #interconnect-cells = <2>;
4343                         qcom,bcm-voters = <&apps_bcm_voter>;
4344                 };
4345
4346                 system-cache-controller@19200000 {
4347                         compatible = "qcom,sm8450-llcc";
4348                         reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4349                               <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4350                               <0 0x19a00000 0 0x80000>;
4351                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4352                                     "llcc3_base", "llcc_broadcast_base";
4353                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4354                 };
4355
4356                 ufs_mem_hc: ufshc@1d84000 {
4357                         compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4358                                      "jedec,ufs-2.0";
4359                         reg = <0 0x01d84000 0 0x3000>;
4360                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4361                         phys = <&ufs_mem_phy>;
4362                         phy-names = "ufsphy";
4363                         lanes-per-direction = <2>;
4364                         #reset-cells = <1>;
4365                         resets = <&gcc GCC_UFS_PHY_BCR>;
4366                         reset-names = "rst";
4367
4368                         power-domains = <&gcc UFS_PHY_GDSC>;
4369
4370                         iommus = <&apps_smmu 0xe0 0x0>;
4371                         dma-coherent;
4372
4373                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4374                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4375                         interconnect-names = "ufs-ddr", "cpu-ufs";
4376                         clock-names =
4377                                 "core_clk",
4378                                 "bus_aggr_clk",
4379                                 "iface_clk",
4380                                 "core_clk_unipro",
4381                                 "ref_clk",
4382                                 "tx_lane0_sync_clk",
4383                                 "rx_lane0_sync_clk",
4384                                 "rx_lane1_sync_clk";
4385                         clocks =
4386                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
4387                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4388                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
4389                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4390                                 <&rpmhcc RPMH_CXO_CLK>,
4391                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4392                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4393                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4394                         freq-table-hz =
4395                                 <75000000 300000000>,
4396                                 <0 0>,
4397                                 <0 0>,
4398                                 <75000000 300000000>,
4399                                 <75000000 300000000>,
4400                                 <0 0>,
4401                                 <0 0>,
4402                                 <0 0>;
4403                         qcom,ice = <&ice>;
4404
4405                         status = "disabled";
4406                 };
4407
4408                 ufs_mem_phy: phy@1d87000 {
4409                         compatible = "qcom,sm8450-qmp-ufs-phy";
4410                         reg = <0 0x01d87000 0 0x1000>;
4411
4412                         clock-names = "ref", "ref_aux", "qref";
4413                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4414                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4415                                  <&gcc GCC_UFS_0_CLKREF_EN>;
4416
4417                         resets = <&ufs_mem_hc 0>;
4418                         reset-names = "ufsphy";
4419
4420                         #clock-cells = <1>;
4421                         #phy-cells = <0>;
4422
4423                         status = "disabled";
4424                 };
4425
4426                 ice: crypto@1d88000 {
4427                         compatible = "qcom,sm8450-inline-crypto-engine",
4428                                      "qcom,inline-crypto-engine";
4429                         reg = <0 0x01d88000 0 0x8000>;
4430                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4431                 };
4432
4433                 cryptobam: dma-controller@1dc4000 {
4434                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4435                         reg = <0 0x01dc4000 0 0x28000>;
4436                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4437                         #dma-cells = <1>;
4438                         qcom,ee = <0>;
4439                         qcom,controlled-remotely;
4440                         iommus = <&apps_smmu 0x584 0x11>,
4441                                  <&apps_smmu 0x588 0x0>,
4442                                  <&apps_smmu 0x598 0x5>,
4443                                  <&apps_smmu 0x59a 0x0>,
4444                                  <&apps_smmu 0x59f 0x0>;
4445                 };
4446
4447                 crypto: crypto@1dfa000 {
4448                         compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4449                         reg = <0 0x01dfa000 0 0x6000>;
4450                         dmas = <&cryptobam 4>, <&cryptobam 5>;
4451                         dma-names = "rx", "tx";
4452                         iommus = <&apps_smmu 0x584 0x11>,
4453                                  <&apps_smmu 0x588 0x0>,
4454                                  <&apps_smmu 0x598 0x5>,
4455                                  <&apps_smmu 0x59a 0x0>,
4456                                  <&apps_smmu 0x59f 0x0>;
4457                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4458                         interconnect-names = "memory";
4459                 };
4460
4461                 sdhc_2: mmc@8804000 {
4462                         compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4463                         reg = <0 0x08804000 0 0x1000>;
4464
4465                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4466                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4467                         interrupt-names = "hc_irq", "pwr_irq";
4468
4469                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4470                                  <&gcc GCC_SDCC2_APPS_CLK>,
4471                                  <&rpmhcc RPMH_CXO_CLK>;
4472                         clock-names = "iface", "core", "xo";
4473                         resets = <&gcc GCC_SDCC2_BCR>;
4474                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4475                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4476                         interconnect-names = "sdhc-ddr","cpu-sdhc";
4477                         iommus = <&apps_smmu 0x4a0 0x0>;
4478                         power-domains = <&rpmhpd RPMHPD_CX>;
4479                         operating-points-v2 = <&sdhc2_opp_table>;
4480                         bus-width = <4>;
4481                         dma-coherent;
4482
4483                         /* Forbid SDR104/SDR50 - broken hw! */
4484                         sdhci-caps-mask = <0x3 0x0>;
4485
4486                         status = "disabled";
4487
4488                         sdhc2_opp_table: opp-table {
4489                                 compatible = "operating-points-v2";
4490
4491                                 opp-100000000 {
4492                                         opp-hz = /bits/ 64 <100000000>;
4493                                         required-opps = <&rpmhpd_opp_low_svs>;
4494                                 };
4495
4496                                 opp-202000000 {
4497                                         opp-hz = /bits/ 64 <202000000>;
4498                                         required-opps = <&rpmhpd_opp_svs_l1>;
4499                                 };
4500                         };
4501                 };
4502
4503                 usb_1: usb@a6f8800 {
4504                         compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4505                         reg = <0 0x0a6f8800 0 0x400>;
4506                         status = "disabled";
4507                         #address-cells = <2>;
4508                         #size-cells = <2>;
4509                         ranges;
4510
4511                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4512                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4513                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4514                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4515                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4516                                  <&gcc GCC_USB3_0_CLKREF_EN>;
4517                         clock-names = "cfg_noc",
4518                                       "core",
4519                                       "iface",
4520                                       "sleep",
4521                                       "mock_utmi",
4522                                       "xo";
4523
4524                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4525                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4526                         assigned-clock-rates = <19200000>, <200000000>;
4527
4528                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4529                                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4530                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4531                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4532                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4533                         interrupt-names = "pwr_event",
4534                                           "hs_phy_irq",
4535                                           "dp_hs_phy_irq",
4536                                           "dm_hs_phy_irq",
4537                                           "ss_phy_irq";
4538
4539                         power-domains = <&gcc USB30_PRIM_GDSC>;
4540
4541                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4542
4543                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4544                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4545                         interconnect-names = "usb-ddr", "apps-usb";
4546
4547                         usb_1_dwc3: usb@a600000 {
4548                                 compatible = "snps,dwc3";
4549                                 reg = <0 0x0a600000 0 0xcd00>;
4550                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4551                                 iommus = <&apps_smmu 0x0 0x0>;
4552                                 snps,dis_u2_susphy_quirk;
4553                                 snps,dis_enblslpm_quirk;
4554                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4555                                 phy-names = "usb2-phy", "usb3-phy";
4556
4557                                 ports {
4558                                         #address-cells = <1>;
4559                                         #size-cells = <0>;
4560
4561                                         port@0 {
4562                                                 reg = <0>;
4563
4564                                                 usb_1_dwc3_hs: endpoint {
4565                                                 };
4566                                         };
4567
4568                                         port@1 {
4569                                                 reg = <1>;
4570
4571                                                 usb_1_dwc3_ss: endpoint {
4572                                                 };
4573                                         };
4574                                 };
4575                         };
4576                 };
4577
4578                 nsp_noc: interconnect@320c0000 {
4579                         compatible = "qcom,sm8450-nsp-noc";
4580                         reg = <0 0x320c0000 0 0x10000>;
4581                         #interconnect-cells = <2>;
4582                         qcom,bcm-voters = <&apps_bcm_voter>;
4583                 };
4584
4585                 lpass_ag_noc: interconnect@3c40000 {
4586                         compatible = "qcom,sm8450-lpass-ag-noc";
4587                         reg = <0 0x03c40000 0 0x17200>;
4588                         #interconnect-cells = <2>;
4589                         qcom,bcm-voters = <&apps_bcm_voter>;
4590                 };
4591         };
4592
4593         sound: sound {
4594         };
4595
4596         thermal-zones {
4597                 aoss0-thermal {
4598                         polling-delay-passive = <0>;
4599                         polling-delay = <0>;
4600                         thermal-sensors = <&tsens0 0>;
4601
4602                         trips {
4603                                 thermal-engine-config {
4604                                         temperature = <125000>;
4605                                         hysteresis = <1000>;
4606                                         type = "passive";
4607                                 };
4608
4609                                 reset-mon-cfg {
4610                                         temperature = <115000>;
4611                                         hysteresis = <5000>;
4612                                         type = "passive";
4613                                 };
4614                         };
4615                 };
4616
4617                 cpuss0-thermal {
4618                         polling-delay-passive = <0>;
4619                         polling-delay = <0>;
4620                         thermal-sensors = <&tsens0 1>;
4621
4622                         trips {
4623                                 thermal-engine-config {
4624                                         temperature = <125000>;
4625                                         hysteresis = <1000>;
4626                                         type = "passive";
4627                                 };
4628
4629                                 reset-mon-cfg {
4630                                         temperature = <115000>;
4631                                         hysteresis = <5000>;
4632                                         type = "passive";
4633                                 };
4634                         };
4635                 };
4636
4637                 cpuss1-thermal {
4638                         polling-delay-passive = <0>;
4639                         polling-delay = <0>;
4640                         thermal-sensors = <&tsens0 2>;
4641
4642                         trips {
4643                                 thermal-engine-config {
4644                                         temperature = <125000>;
4645                                         hysteresis = <1000>;
4646                                         type = "passive";
4647                                 };
4648
4649                                 reset-mon-cfg {
4650                                         temperature = <115000>;
4651                                         hysteresis = <5000>;
4652                                         type = "passive";
4653                                 };
4654                         };
4655                 };
4656
4657                 cpuss3-thermal {
4658                         polling-delay-passive = <0>;
4659                         polling-delay = <0>;
4660                         thermal-sensors = <&tsens0 3>;
4661
4662                         trips {
4663                                 thermal-engine-config {
4664                                         temperature = <125000>;
4665                                         hysteresis = <1000>;
4666                                         type = "passive";
4667                                 };
4668
4669                                 reset-mon-cfg {
4670                                         temperature = <115000>;
4671                                         hysteresis = <5000>;
4672                                         type = "passive";
4673                                 };
4674                         };
4675                 };
4676
4677                 cpuss4-thermal {
4678                         polling-delay-passive = <0>;
4679                         polling-delay = <0>;
4680                         thermal-sensors = <&tsens0 4>;
4681
4682                         trips {
4683                                 thermal-engine-config {
4684                                         temperature = <125000>;
4685                                         hysteresis = <1000>;
4686                                         type = "passive";
4687                                 };
4688
4689                                 reset-mon-cfg {
4690                                         temperature = <115000>;
4691                                         hysteresis = <5000>;
4692                                         type = "passive";
4693                                 };
4694                         };
4695                 };
4696
4697                 cpu4-top-thermal {
4698                         polling-delay-passive = <0>;
4699                         polling-delay = <0>;
4700                         thermal-sensors = <&tsens0 5>;
4701
4702                         trips {
4703                                 cpu4_top_alert0: trip-point0 {
4704                                         temperature = <90000>;
4705                                         hysteresis = <2000>;
4706                                         type = "passive";
4707                                 };
4708
4709                                 cpu4_top_alert1: trip-point1 {
4710                                         temperature = <95000>;
4711                                         hysteresis = <2000>;
4712                                         type = "passive";
4713                                 };
4714
4715                                 cpu4_top_crit: cpu-crit {
4716                                         temperature = <110000>;
4717                                         hysteresis = <1000>;
4718                                         type = "critical";
4719                                 };
4720                         };
4721                 };
4722
4723                 cpu4-bottom-thermal {
4724                         polling-delay-passive = <0>;
4725                         polling-delay = <0>;
4726                         thermal-sensors = <&tsens0 6>;
4727
4728                         trips {
4729                                 cpu4_bottom_alert0: trip-point0 {
4730                                         temperature = <90000>;
4731                                         hysteresis = <2000>;
4732                                         type = "passive";
4733                                 };
4734
4735                                 cpu4_bottom_alert1: trip-point1 {
4736                                         temperature = <95000>;
4737                                         hysteresis = <2000>;
4738                                         type = "passive";
4739                                 };
4740
4741                                 cpu4_bottom_crit: cpu-crit {
4742                                         temperature = <110000>;
4743                                         hysteresis = <1000>;
4744                                         type = "critical";
4745                                 };
4746                         };
4747                 };
4748
4749                 cpu5-top-thermal {
4750                         polling-delay-passive = <0>;
4751                         polling-delay = <0>;
4752                         thermal-sensors = <&tsens0 7>;
4753
4754                         trips {
4755                                 cpu5_top_alert0: trip-point0 {
4756                                         temperature = <90000>;
4757                                         hysteresis = <2000>;
4758                                         type = "passive";
4759                                 };
4760
4761                                 cpu5_top_alert1: trip-point1 {
4762                                         temperature = <95000>;
4763                                         hysteresis = <2000>;
4764                                         type = "passive";
4765                                 };
4766
4767                                 cpu5_top_crit: cpu-crit {
4768                                         temperature = <110000>;
4769                                         hysteresis = <1000>;
4770                                         type = "critical";
4771                                 };
4772                         };
4773                 };
4774
4775                 cpu5-bottom-thermal {
4776                         polling-delay-passive = <0>;
4777                         polling-delay = <0>;
4778                         thermal-sensors = <&tsens0 8>;
4779
4780                         trips {
4781                                 cpu5_bottom_alert0: trip-point0 {
4782                                         temperature = <90000>;
4783                                         hysteresis = <2000>;
4784                                         type = "passive";
4785                                 };
4786
4787                                 cpu5_bottom_alert1: trip-point1 {
4788                                         temperature = <95000>;
4789                                         hysteresis = <2000>;
4790                                         type = "passive";
4791                                 };
4792
4793                                 cpu5_bottom_crit: cpu-crit {
4794                                         temperature = <110000>;
4795                                         hysteresis = <1000>;
4796                                         type = "critical";
4797                                 };
4798                         };
4799                 };
4800
4801                 cpu6-top-thermal {
4802                         polling-delay-passive = <0>;
4803                         polling-delay = <0>;
4804                         thermal-sensors = <&tsens0 9>;
4805
4806                         trips {
4807                                 cpu6_top_alert0: trip-point0 {
4808                                         temperature = <90000>;
4809                                         hysteresis = <2000>;
4810                                         type = "passive";
4811                                 };
4812
4813                                 cpu6_top_alert1: trip-point1 {
4814                                         temperature = <95000>;
4815                                         hysteresis = <2000>;
4816                                         type = "passive";
4817                                 };
4818
4819                                 cpu6_top_crit: cpu-crit {
4820                                         temperature = <110000>;
4821                                         hysteresis = <1000>;
4822                                         type = "critical";
4823                                 };
4824                         };
4825                 };
4826
4827                 cpu6-bottom-thermal {
4828                         polling-delay-passive = <0>;
4829                         polling-delay = <0>;
4830                         thermal-sensors = <&tsens0 10>;
4831
4832                         trips {
4833                                 cpu6_bottom_alert0: trip-point0 {
4834                                         temperature = <90000>;
4835                                         hysteresis = <2000>;
4836                                         type = "passive";
4837                                 };
4838
4839                                 cpu6_bottom_alert1: trip-point1 {
4840                                         temperature = <95000>;
4841                                         hysteresis = <2000>;
4842                                         type = "passive";
4843                                 };
4844
4845                                 cpu6_bottom_crit: cpu-crit {
4846                                         temperature = <110000>;
4847                                         hysteresis = <1000>;
4848                                         type = "critical";
4849                                 };
4850                         };
4851                 };
4852
4853                 cpu7-top-thermal {
4854                         polling-delay-passive = <0>;
4855                         polling-delay = <0>;
4856                         thermal-sensors = <&tsens0 11>;
4857
4858                         trips {
4859                                 cpu7_top_alert0: trip-point0 {
4860                                         temperature = <90000>;
4861                                         hysteresis = <2000>;
4862                                         type = "passive";
4863                                 };
4864
4865                                 cpu7_top_alert1: trip-point1 {
4866                                         temperature = <95000>;
4867                                         hysteresis = <2000>;
4868                                         type = "passive";
4869                                 };
4870
4871                                 cpu7_top_crit: cpu-crit {
4872                                         temperature = <110000>;
4873                                         hysteresis = <1000>;
4874                                         type = "critical";
4875                                 };
4876                         };
4877                 };
4878
4879                 cpu7-middle-thermal {
4880                         polling-delay-passive = <0>;
4881                         polling-delay = <0>;
4882                         thermal-sensors = <&tsens0 12>;
4883
4884                         trips {
4885                                 cpu7_middle_alert0: trip-point0 {
4886                                         temperature = <90000>;
4887                                         hysteresis = <2000>;
4888                                         type = "passive";
4889                                 };
4890
4891                                 cpu7_middle_alert1: trip-point1 {
4892                                         temperature = <95000>;
4893                                         hysteresis = <2000>;
4894                                         type = "passive";
4895                                 };
4896
4897                                 cpu7_middle_crit: cpu-crit {
4898                                         temperature = <110000>;
4899                                         hysteresis = <1000>;
4900                                         type = "critical";
4901                                 };
4902                         };
4903                 };
4904
4905                 cpu7-bottom-thermal {
4906                         polling-delay-passive = <0>;
4907                         polling-delay = <0>;
4908                         thermal-sensors = <&tsens0 13>;
4909
4910                         trips {
4911                                 cpu7_bottom_alert0: trip-point0 {
4912                                         temperature = <90000>;
4913                                         hysteresis = <2000>;
4914                                         type = "passive";
4915                                 };
4916
4917                                 cpu7_bottom_alert1: trip-point1 {
4918                                         temperature = <95000>;
4919                                         hysteresis = <2000>;
4920                                         type = "passive";
4921                                 };
4922
4923                                 cpu7_bottom_crit: cpu-crit {
4924                                         temperature = <110000>;
4925                                         hysteresis = <1000>;
4926                                         type = "critical";
4927                                 };
4928                         };
4929                 };
4930
4931                 gpu-top-thermal {
4932                         polling-delay-passive = <10>;
4933                         polling-delay = <0>;
4934                         thermal-sensors = <&tsens0 14>;
4935
4936                         cooling-maps {
4937                                 map0 {
4938                                         trip = <&gpu_top_alert0>;
4939                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4940                                 };
4941                         };
4942
4943                         trips {
4944                                 thermal-engine-config {
4945                                         temperature = <125000>;
4946                                         hysteresis = <1000>;
4947                                         type = "passive";
4948                                 };
4949
4950                                 thermal-hal-config {
4951                                         temperature = <125000>;
4952                                         hysteresis = <1000>;
4953                                         type = "passive";
4954                                 };
4955
4956                                 reset-mon-cfg {
4957                                         temperature = <115000>;
4958                                         hysteresis = <5000>;
4959                                         type = "passive";
4960                                 };
4961
4962                                 gpu_top_alert0: trip-point0 {
4963                                         temperature = <95000>;
4964                                         hysteresis = <5000>;
4965                                         type = "passive";
4966                                 };
4967                         };
4968                 };
4969
4970                 gpu-bottom-thermal {
4971                         polling-delay-passive = <10>;
4972                         polling-delay = <0>;
4973                         thermal-sensors = <&tsens0 15>;
4974
4975                         cooling-maps {
4976                                 map0 {
4977                                         trip = <&gpu_bottom_alert0>;
4978                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4979                                 };
4980                         };
4981
4982                         trips {
4983                                 thermal-engine-config {
4984                                         temperature = <125000>;
4985                                         hysteresis = <1000>;
4986                                         type = "passive";
4987                                 };
4988
4989                                 thermal-hal-config {
4990                                         temperature = <125000>;
4991                                         hysteresis = <1000>;
4992                                         type = "passive";
4993                                 };
4994
4995                                 reset-mon-cfg {
4996                                         temperature = <115000>;
4997                                         hysteresis = <5000>;
4998                                         type = "passive";
4999                                 };
5000
5001                                 gpu_bottom_alert0: trip-point0 {
5002                                         temperature = <95000>;
5003                                         hysteresis = <5000>;
5004                                         type = "passive";
5005                                 };
5006                         };
5007                 };
5008
5009                 aoss1-thermal {
5010                         polling-delay-passive = <0>;
5011                         polling-delay = <0>;
5012                         thermal-sensors = <&tsens1 0>;
5013
5014                         trips {
5015                                 thermal-engine-config {
5016                                         temperature = <125000>;
5017                                         hysteresis = <1000>;
5018                                         type = "passive";
5019                                 };
5020
5021                                 reset-mon-cfg {
5022                                         temperature = <115000>;
5023                                         hysteresis = <5000>;
5024                                         type = "passive";
5025                                 };
5026                         };
5027                 };
5028
5029                 cpu0-thermal {
5030                         polling-delay-passive = <0>;
5031                         polling-delay = <0>;
5032                         thermal-sensors = <&tsens1 1>;
5033
5034                         trips {
5035                                 cpu0_alert0: trip-point0 {
5036                                         temperature = <90000>;
5037                                         hysteresis = <2000>;
5038                                         type = "passive";
5039                                 };
5040
5041                                 cpu0_alert1: trip-point1 {
5042                                         temperature = <95000>;
5043                                         hysteresis = <2000>;
5044                                         type = "passive";
5045                                 };
5046
5047                                 cpu0_crit: cpu-crit {
5048                                         temperature = <110000>;
5049                                         hysteresis = <1000>;
5050                                         type = "critical";
5051                                 };
5052                         };
5053                 };
5054
5055                 cpu1-thermal {
5056                         polling-delay-passive = <0>;
5057                         polling-delay = <0>;
5058                         thermal-sensors = <&tsens1 2>;
5059
5060                         trips {
5061                                 cpu1_alert0: trip-point0 {
5062                                         temperature = <90000>;
5063                                         hysteresis = <2000>;
5064                                         type = "passive";
5065                                 };
5066
5067                                 cpu1_alert1: trip-point1 {
5068                                         temperature = <95000>;
5069                                         hysteresis = <2000>;
5070                                         type = "passive";
5071                                 };
5072
5073                                 cpu1_crit: cpu-crit {
5074                                         temperature = <110000>;
5075                                         hysteresis = <1000>;
5076                                         type = "critical";
5077                                 };
5078                         };
5079                 };
5080
5081                 cpu2-thermal {
5082                         polling-delay-passive = <0>;
5083                         polling-delay = <0>;
5084                         thermal-sensors = <&tsens1 3>;
5085
5086                         trips {
5087                                 cpu2_alert0: trip-point0 {
5088                                         temperature = <90000>;
5089                                         hysteresis = <2000>;
5090                                         type = "passive";
5091                                 };
5092
5093                                 cpu2_alert1: trip-point1 {
5094                                         temperature = <95000>;
5095                                         hysteresis = <2000>;
5096                                         type = "passive";
5097                                 };
5098
5099                                 cpu2_crit: cpu-crit {
5100                                         temperature = <110000>;
5101                                         hysteresis = <1000>;
5102                                         type = "critical";
5103                                 };
5104                         };
5105                 };
5106
5107                 cpu3-thermal {
5108                         polling-delay-passive = <0>;
5109                         polling-delay = <0>;
5110                         thermal-sensors = <&tsens1 4>;
5111
5112                         trips {
5113                                 cpu3_alert0: trip-point0 {
5114                                         temperature = <90000>;
5115                                         hysteresis = <2000>;
5116                                         type = "passive";
5117                                 };
5118
5119                                 cpu3_alert1: trip-point1 {
5120                                         temperature = <95000>;
5121                                         hysteresis = <2000>;
5122                                         type = "passive";
5123                                 };
5124
5125                                 cpu3_crit: cpu-crit {
5126                                         temperature = <110000>;
5127                                         hysteresis = <1000>;
5128                                         type = "critical";
5129                                 };
5130                         };
5131                 };
5132
5133                 cdsp0-thermal {
5134                         polling-delay-passive = <10>;
5135                         polling-delay = <0>;
5136                         thermal-sensors = <&tsens1 5>;
5137
5138                         trips {
5139                                 thermal-engine-config {
5140                                         temperature = <125000>;
5141                                         hysteresis = <1000>;
5142                                         type = "passive";
5143                                 };
5144
5145                                 thermal-hal-config {
5146                                         temperature = <125000>;
5147                                         hysteresis = <1000>;
5148                                         type = "passive";
5149                                 };
5150
5151                                 reset-mon-cfg {
5152                                         temperature = <115000>;
5153                                         hysteresis = <5000>;
5154                                         type = "passive";
5155                                 };
5156
5157                                 cdsp_0_config: junction-config {
5158                                         temperature = <95000>;
5159                                         hysteresis = <5000>;
5160                                         type = "passive";
5161                                 };
5162                         };
5163                 };
5164
5165                 cdsp1-thermal {
5166                         polling-delay-passive = <10>;
5167                         polling-delay = <0>;
5168                         thermal-sensors = <&tsens1 6>;
5169
5170                         trips {
5171                                 thermal-engine-config {
5172                                         temperature = <125000>;
5173                                         hysteresis = <1000>;
5174                                         type = "passive";
5175                                 };
5176
5177                                 thermal-hal-config {
5178                                         temperature = <125000>;
5179                                         hysteresis = <1000>;
5180                                         type = "passive";
5181                                 };
5182
5183                                 reset-mon-cfg {
5184                                         temperature = <115000>;
5185                                         hysteresis = <5000>;
5186                                         type = "passive";
5187                                 };
5188
5189                                 cdsp_1_config: junction-config {
5190                                         temperature = <95000>;
5191                                         hysteresis = <5000>;
5192                                         type = "passive";
5193                                 };
5194                         };
5195                 };
5196
5197                 cdsp2-thermal {
5198                         polling-delay-passive = <10>;
5199                         polling-delay = <0>;
5200                         thermal-sensors = <&tsens1 7>;
5201
5202                         trips {
5203                                 thermal-engine-config {
5204                                         temperature = <125000>;
5205                                         hysteresis = <1000>;
5206                                         type = "passive";
5207                                 };
5208
5209                                 thermal-hal-config {
5210                                         temperature = <125000>;
5211                                         hysteresis = <1000>;
5212                                         type = "passive";
5213                                 };
5214
5215                                 reset-mon-cfg {
5216                                         temperature = <115000>;
5217                                         hysteresis = <5000>;
5218                                         type = "passive";
5219                                 };
5220
5221                                 cdsp_2_config: junction-config {
5222                                         temperature = <95000>;
5223                                         hysteresis = <5000>;
5224                                         type = "passive";
5225                                 };
5226                         };
5227                 };
5228
5229                 video-thermal {
5230                         polling-delay-passive = <0>;
5231                         polling-delay = <0>;
5232                         thermal-sensors = <&tsens1 8>;
5233
5234                         trips {
5235                                 thermal-engine-config {
5236                                         temperature = <125000>;
5237                                         hysteresis = <1000>;
5238                                         type = "passive";
5239                                 };
5240
5241                                 reset-mon-cfg {
5242                                         temperature = <115000>;
5243                                         hysteresis = <5000>;
5244                                         type = "passive";
5245                                 };
5246                         };
5247                 };
5248
5249                 mem-thermal {
5250                         polling-delay-passive = <10>;
5251                         polling-delay = <0>;
5252                         thermal-sensors = <&tsens1 9>;
5253
5254                         trips {
5255                                 thermal-engine-config {
5256                                         temperature = <125000>;
5257                                         hysteresis = <1000>;
5258                                         type = "passive";
5259                                 };
5260
5261                                 ddr_config0: ddr0-config {
5262                                         temperature = <90000>;
5263                                         hysteresis = <5000>;
5264                                         type = "passive";
5265                                 };
5266
5267                                 reset-mon-cfg {
5268                                         temperature = <115000>;
5269                                         hysteresis = <5000>;
5270                                         type = "passive";
5271                                 };
5272                         };
5273                 };
5274
5275                 modem0-thermal {
5276                         polling-delay-passive = <0>;
5277                         polling-delay = <0>;
5278                         thermal-sensors = <&tsens1 10>;
5279
5280                         trips {
5281                                 thermal-engine-config {
5282                                         temperature = <125000>;
5283                                         hysteresis = <1000>;
5284                                         type = "passive";
5285                                 };
5286
5287                                 mdmss0_config0: mdmss0-config0 {
5288                                         temperature = <102000>;
5289                                         hysteresis = <3000>;
5290                                         type = "passive";
5291                                 };
5292
5293                                 mdmss0_config1: mdmss0-config1 {
5294                                         temperature = <105000>;
5295                                         hysteresis = <3000>;
5296                                         type = "passive";
5297                                 };
5298
5299                                 reset-mon-cfg {
5300                                         temperature = <115000>;
5301                                         hysteresis = <5000>;
5302                                         type = "passive";
5303                                 };
5304                         };
5305                 };
5306
5307                 modem1-thermal {
5308                         polling-delay-passive = <0>;
5309                         polling-delay = <0>;
5310                         thermal-sensors = <&tsens1 11>;
5311
5312                         trips {
5313                                 thermal-engine-config {
5314                                         temperature = <125000>;
5315                                         hysteresis = <1000>;
5316                                         type = "passive";
5317                                 };
5318
5319                                 mdmss1_config0: mdmss1-config0 {
5320                                         temperature = <102000>;
5321                                         hysteresis = <3000>;
5322                                         type = "passive";
5323                                 };
5324
5325                                 mdmss1_config1: mdmss1-config1 {
5326                                         temperature = <105000>;
5327                                         hysteresis = <3000>;
5328                                         type = "passive";
5329                                 };
5330
5331                                 reset-mon-cfg {
5332                                         temperature = <115000>;
5333                                         hysteresis = <5000>;
5334                                         type = "passive";
5335                                 };
5336                         };
5337                 };
5338
5339                 modem2-thermal {
5340                         polling-delay-passive = <0>;
5341                         polling-delay = <0>;
5342                         thermal-sensors = <&tsens1 12>;
5343
5344                         trips {
5345                                 thermal-engine-config {
5346                                         temperature = <125000>;
5347                                         hysteresis = <1000>;
5348                                         type = "passive";
5349                                 };
5350
5351                                 mdmss2_config0: mdmss2-config0 {
5352                                         temperature = <102000>;
5353                                         hysteresis = <3000>;
5354                                         type = "passive";
5355                                 };
5356
5357                                 mdmss2_config1: mdmss2-config1 {
5358                                         temperature = <105000>;
5359                                         hysteresis = <3000>;
5360                                         type = "passive";
5361                                 };
5362
5363                                 reset-mon-cfg {
5364                                         temperature = <115000>;
5365                                         hysteresis = <5000>;
5366                                         type = "passive";
5367                                 };
5368                         };
5369                 };
5370
5371                 modem3-thermal {
5372                         polling-delay-passive = <0>;
5373                         polling-delay = <0>;
5374                         thermal-sensors = <&tsens1 13>;
5375
5376                         trips {
5377                                 thermal-engine-config {
5378                                         temperature = <125000>;
5379                                         hysteresis = <1000>;
5380                                         type = "passive";
5381                                 };
5382
5383                                 mdmss3_config0: mdmss3-config0 {
5384                                         temperature = <102000>;
5385                                         hysteresis = <3000>;
5386                                         type = "passive";
5387                                 };
5388
5389                                 mdmss3_config1: mdmss3-config1 {
5390                                         temperature = <105000>;
5391                                         hysteresis = <3000>;
5392                                         type = "passive";
5393                                 };
5394
5395                                 reset-mon-cfg {
5396                                         temperature = <115000>;
5397                                         hysteresis = <5000>;
5398                                         type = "passive";
5399                                 };
5400                         };
5401                 };
5402
5403                 camera0-thermal {
5404                         polling-delay-passive = <0>;
5405                         polling-delay = <0>;
5406                         thermal-sensors = <&tsens1 14>;
5407
5408                         trips {
5409                                 thermal-engine-config {
5410                                         temperature = <125000>;
5411                                         hysteresis = <1000>;
5412                                         type = "passive";
5413                                 };
5414
5415                                 reset-mon-cfg {
5416                                         temperature = <115000>;
5417                                         hysteresis = <5000>;
5418                                         type = "passive";
5419                                 };
5420                         };
5421                 };
5422
5423                 camera1-thermal {
5424                         polling-delay-passive = <0>;
5425                         polling-delay = <0>;
5426                         thermal-sensors = <&tsens1 15>;
5427
5428                         trips {
5429                                 thermal-engine-config {
5430                                         temperature = <125000>;
5431                                         hysteresis = <1000>;
5432                                         type = "passive";
5433                                 };
5434
5435                                 reset-mon-cfg {
5436                                         temperature = <115000>;
5437                                         hysteresis = <5000>;
5438                                         type = "passive";
5439                                 };
5440                         };
5441                 };
5442         };
5443
5444         timer {
5445                 compatible = "arm,armv8-timer";
5446                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5447                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5448                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5449                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5450                 clock-frequency = <19200000>;
5451         };
5452 };