arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/interconnect/qcom,sm8350.h>
  10 #include <dt-bindings/mailbox/qcom-ipcc.h>
  11 #include <dt-bindings/power/qcom-aoss-qmp.h>
  12 #include <dt-bindings/power/qcom-rpmpd.h>
  13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15 #include <dt-bindings/interconnect/qcom,sm8350.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         clocks {
  26                 xo_board: xo-board {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <38400000>;
  30                         clock-output-names = "xo_board";
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         clock-frequency = <32000>;
  36                         #clock-cells = <0>;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <2>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "qcom,kryo685";
  47                         reg = <0x0 0x0>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&L2_0>;
  50                         qcom,freq-domain = <&cpufreq_hw 0>;
  51                         #cooling-cells = <2>;
  52                         L2_0: l2-cache {
  53                               compatible = "cache";
  54                               next-level-cache = <&L3_0>;
  55                                 L3_0: l3-cache {
  56                                       compatible = "cache";
  57                                 };
  58                         };
  59                 };
  60
  61                 CPU1: cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "qcom,kryo685";
  64                         reg = <0x0 0x100>;
  65                         enable-method = "psci";
  66                         next-level-cache = <&L2_100>;
  67                         qcom,freq-domain = <&cpufreq_hw 0>;
  68                         #cooling-cells = <2>;
  69                         L2_100: l2-cache {
  70                               compatible = "cache";
  71                               next-level-cache = <&L3_0>;
  72                         };
  73                 };
  74
  75                 CPU2: cpu@200 {
  76                         device_type = "cpu";
  77                         compatible = "qcom,kryo685";
  78                         reg = <0x0 0x200>;
  79                         enable-method = "psci";
  80                         next-level-cache = <&L2_200>;
  81                         qcom,freq-domain = <&cpufreq_hw 0>;
  82                         #cooling-cells = <2>;
  83                         L2_200: l2-cache {
  84                               compatible = "cache";
  85                               next-level-cache = <&L3_0>;
  86                         };
  87                 };
  88
  89                 CPU3: cpu@300 {
  90                         device_type = "cpu";
  91                         compatible = "qcom,kryo685";
  92                         reg = <0x0 0x300>;
  93                         enable-method = "psci";
  94                         next-level-cache = <&L2_300>;
  95                         qcom,freq-domain = <&cpufreq_hw 0>;
  96                         #cooling-cells = <2>;
  97                         L2_300: l2-cache {
  98                               compatible = "cache";
  99                               next-level-cache = <&L3_0>;
 100                         };
 101                 };
 102
 103                 CPU4: cpu@400 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo685";
 106                         reg = <0x0 0x400>;
 107                         enable-method = "psci";
 108                         next-level-cache = <&L2_400>;
 109                         qcom,freq-domain = <&cpufreq_hw 1>;
 110                         #cooling-cells = <2>;
 111                         L2_400: l2-cache {
 112                               compatible = "cache";
 113                               next-level-cache = <&L3_0>;
 114                         };
 115                 };
 116
 117                 CPU5: cpu@500 {
 118                         device_type = "cpu";
 119                         compatible = "qcom,kryo685";
 120                         reg = <0x0 0x500>;
 121                         enable-method = "psci";
 122                         next-level-cache = <&L2_500>;
 123                         qcom,freq-domain = <&cpufreq_hw 1>;
 124                         #cooling-cells = <2>;
 125                         L2_500: l2-cache {
 126                               compatible = "cache";
 127                               next-level-cache = <&L3_0>;
 128                         };
 129
 130                 };
 131
 132                 CPU6: cpu@600 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo685";
 135                         reg = <0x0 0x600>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&L2_600>;
 138                         qcom,freq-domain = <&cpufreq_hw 1>;
 139                         #cooling-cells = <2>;
 140                         L2_600: l2-cache {
 141                               compatible = "cache";
 142                               next-level-cache = <&L3_0>;
 143                         };
 144                 };
 145
 146                 CPU7: cpu@700 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo685";
 149                         reg = <0x0 0x700>;
 150                         enable-method = "psci";
 151                         next-level-cache = <&L2_700>;
 152                         qcom,freq-domain = <&cpufreq_hw 2>;
 153                         #cooling-cells = <2>;
 154                         L2_700: l2-cache {
 155                               compatible = "cache";
 156                               next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159         };
 160
 161         firmware {
 162                 scm: scm {
 163                         compatible = "qcom,scm-sm8350", "qcom,scm";
 164                         #reset-cells = <1>;
 165                 };
 166         };
 167
 168         memory@80000000 {
 169                 device_type = "memory";
 170                 /* We expect the bootloader to fill in the size */
 171                 reg = <0x0 0x80000000 0x0 0x0>;
 172         };
 173
 174         pmu {
 175                 compatible = "arm,armv8-pmuv3";
 176                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 177         };
 178
 179         psci {
 180                 compatible = "arm,psci-1.0";
 181                 method = "smc";
 182         };
 183
 184         reserved_memory: reserved-memory {
 185                 #address-cells = <2>;
 186                 #size-cells = <2>;
 187                 ranges;
 188
 189                 hyp_mem: memory@80000000 {
 190                         reg = <0x0 0x80000000 0x0 0x600000>;
 191                         no-map;
 192                 };
 193
 194                 xbl_aop_mem: memory@80700000 {
 195                         no-map;
 196                         reg = <0x0 0x80700000 0x0 0x160000>;
 197                 };
 198
 199                 cmd_db: memory@80860000 {
 200                         compatible = "qcom,cmd-db";
 201                         reg = <0x0 0x80860000 0x0 0x20000>;
 202                         no-map;
 203                 };
 204
 205                 reserved_xbl_uefi_log: memory@80880000 {
 206                         reg = <0x0 0x80880000 0x0 0x14000>;
 207                         no-map;
 208                 };
 209
 210                 smem_mem: memory@80900000 {
 211                         reg = <0x0 0x80900000 0x0 0x200000>;
 212                         no-map;
 213                 };
 214
 215                 cpucp_fw_mem: memory@80b00000 {
 216                         reg = <0x0 0x80b00000 0x0 0x100000>;
 217                         no-map;
 218                 };
 219
 220                 cdsp_secure_heap: memory@80c00000 {
 221                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 222                         no-map;
 223                 };
 224
 225                 pil_camera_mem: mmeory@85200000 {
 226                         reg = <0x0 0x85200000 0x0 0x500000>;
 227                         no-map;
 228                 };
 229
 230                 pil_video_mem: memory@85700000 {
 231                         reg = <0x0 0x85700000 0x0 0x500000>;
 232                         no-map;
 233                 };
 234
 235                 pil_cvp_mem: memory@85c00000 {
 236                         reg = <0x0 0x85c00000 0x0 0x500000>;
 237                         no-map;
 238                 };
 239
 240                 pil_adsp_mem: memory@86100000 {
 241                         reg = <0x0 0x86100000 0x0 0x2100000>;
 242                         no-map;
 243                 };
 244
 245                 pil_slpi_mem: memory@88200000 {
 246                         reg = <0x0 0x88200000 0x0 0x1500000>;
 247                         no-map;
 248                 };
 249
 250                 pil_cdsp_mem: memory@89700000 {
 251                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 252                         no-map;
 253                 };
 254
 255                 pil_ipa_fw_mem: memory@8b500000 {
 256                         reg = <0x0 0x8b500000 0x0 0x10000>;
 257                         no-map;
 258                 };
 259
 260                 pil_ipa_gsi_mem: memory@8b510000 {
 261                         reg = <0x0 0x8b510000 0x0 0xa000>;
 262                         no-map;
 263                 };
 264
 265                 pil_gpu_mem: memory@8b51a000 {
 266                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 267                         no-map;
 268                 };
 269
 270                 pil_spss_mem: memory@8b600000 {
 271                         reg = <0x0 0x8b600000 0x0 0x100000>;
 272                         no-map;
 273                 };
 274
 275                 pil_modem_mem: memory@8b800000 {
 276                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 277                         no-map;
 278                 };
 279
 280                 rmtfs_mem: memory@9b800000 {
 281                         compatible = "qcom,rmtfs-mem";
 282                         reg = <0x0 0x9b800000 0x0 0x280000>;
 283                         no-map;
 284
 285                         qcom,client-id = <1>;
 286                         qcom,vmid = <15>;
 287                 };
 288
 289                 hyp_reserved_mem: memory@d0000000 {
 290                         reg = <0x0 0xd0000000 0x0 0x800000>;
 291                         no-map;
 292                 };
 293
 294                 pil_trustedvm_mem: memory@d0800000 {
 295                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 296                         no-map;
 297                 };
 298
 299                 qrtr_shbuf: memory@d7ef7000 {
 300                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 301                         no-map;
 302                 };
 303
 304                 chan0_shbuf: memory@d7f00000 {
 305                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 306                         no-map;
 307                 };
 308
 309                 chan1_shbuf: memory@d7f80000 {
 310                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 311                         no-map;
 312                 };
 313
 314                 removed_mem: memory@d8800000 {
 315                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 316                         no-map;
 317                 };
 318         };
 319
 320         smem: qcom,smem {
 321                 compatible = "qcom,smem";
 322                 memory-region = <&smem_mem>;
 323                 hwlocks = <&tcsr_mutex 3>;
 324         };
 325
 326         smp2p-adsp {
 327                 compatible = "qcom,smp2p";
 328                 qcom,smem = <443>, <429>;
 329                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 330                                              IPCC_MPROC_SIGNAL_SMP2P
 331                                              IRQ_TYPE_EDGE_RISING>;
 332                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 333                                 IPCC_MPROC_SIGNAL_SMP2P>;
 334
 335                 qcom,local-pid = <0>;
 336                 qcom,remote-pid = <2>;
 337
 338                 smp2p_adsp_out: master-kernel {
 339                         qcom,entry-name = "master-kernel";
 340                         #qcom,smem-state-cells = <1>;
 341                 };
 342
 343                 smp2p_adsp_in: slave-kernel {
 344                         qcom,entry-name = "slave-kernel";
 345                         interrupt-controller;
 346                         #interrupt-cells = <2>;
 347                 };
 348         };
 349
 350         smp2p-cdsp {
 351                 compatible = "qcom,smp2p";
 352                 qcom,smem = <94>, <432>;
 353                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 354                                              IPCC_MPROC_SIGNAL_SMP2P
 355                                              IRQ_TYPE_EDGE_RISING>;
 356                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 357                                 IPCC_MPROC_SIGNAL_SMP2P>;
 358
 359                 qcom,local-pid = <0>;
 360                 qcom,remote-pid = <5>;
 361
 362                 smp2p_cdsp_out: master-kernel {
 363                         qcom,entry-name = "master-kernel";
 364                         #qcom,smem-state-cells = <1>;
 365                 };
 366
 367                 smp2p_cdsp_in: slave-kernel {
 368                         qcom,entry-name = "slave-kernel";
 369                         interrupt-controller;
 370                         #interrupt-cells = <2>;
 371                 };
 372         };
 373
 374         smp2p-modem {
 375                 compatible = "qcom,smp2p";
 376                 qcom,smem = <435>, <428>;
 377                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 378                                              IPCC_MPROC_SIGNAL_SMP2P
 379                                              IRQ_TYPE_EDGE_RISING>;
 380                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 381                                 IPCC_MPROC_SIGNAL_SMP2P>;
 382
 383                 qcom,local-pid = <0>;
 384                 qcom,remote-pid = <1>;
 385
 386                 smp2p_modem_out: master-kernel {
 387                         qcom,entry-name = "master-kernel";
 388                         #qcom,smem-state-cells = <1>;
 389                 };
 390
 391                 smp2p_modem_in: slave-kernel {
 392                         qcom,entry-name = "slave-kernel";
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 ipa_smp2p_out: ipa-ap-to-modem {
 398                         qcom,entry-name = "ipa";
 399                         #qcom,smem-state-cells = <1>;
 400                 };
 401
 402                 ipa_smp2p_in: ipa-modem-to-ap {
 403                         qcom,entry-name = "ipa";
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                 };
 407         };
 408
 409         smp2p-slpi {
 410                 compatible = "qcom,smp2p";
 411                 qcom,smem = <481>, <430>;
 412                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 413                                              IPCC_MPROC_SIGNAL_SMP2P
 414                                              IRQ_TYPE_EDGE_RISING>;
 415                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 416                                 IPCC_MPROC_SIGNAL_SMP2P>;
 417
 418                 qcom,local-pid = <0>;
 419                 qcom,remote-pid = <3>;
 420
 421                 smp2p_slpi_out: master-kernel {
 422                         qcom,entry-name = "master-kernel";
 423                         #qcom,smem-state-cells = <1>;
 424                 };
 425
 426                 smp2p_slpi_in: slave-kernel {
 427                         qcom,entry-name = "slave-kernel";
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                 };
 431         };
 432
 433         soc: soc@0 {
 434                 #address-cells = <2>;
 435                 #size-cells = <2>;
 436                 ranges = <0 0 0 0 0x10 0>;
 437                 dma-ranges = <0 0 0 0 0x10 0>;
 438                 compatible = "simple-bus";
 439
 440                 gcc: clock-controller@100000 {
 441                         compatible = "qcom,gcc-sm8350";
 442                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 443                         #clock-cells = <1>;
 444                         #reset-cells = <1>;
 445                         #power-domain-cells = <1>;
 446                         clock-names = "bi_tcxo", "sleep_clk";
 447                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
 448                 };
 449
 450                 ipcc: mailbox@408000 {
 451                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 452                         reg = <0 0x00408000 0 0x1000>;
 453                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 454                         interrupt-controller;
 455                         #interrupt-cells = <3>;
 456                         #mbox-cells = <2>;
 457                 };
 458
 459                 qupv3_id_1: geniqup@9c0000 {
 460                         compatible = "qcom,geni-se-qup";
 461                         reg = <0x0 0x009c0000 0x0 0x6000>;
 462                         clock-names = "m-ahb", "s-ahb";
 463                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 464                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 465                         #address-cells = <2>;
 466                         #size-cells = <2>;
 467                         ranges;
 468                         status = "disabled";
 469
 470                         uart2: serial@98c000 {
 471                                 compatible = "qcom,geni-debug-uart";
 472                                 reg = <0 0x0098c000 0 0x4000>;
 473                                 clock-names = "se";
 474                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 475                                 pinctrl-names = "default";
 476                                 pinctrl-0 = <&qup_uart3_default_state>;
 477                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480                                 status = "disabled";
 481                         };
 482                 };
 483
 484                 apps_smmu: iommu@15000000 {
 485                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
 486                         reg = <0 0x15000000 0 0x100000>;
 487                         #iommu-cells = <2>;
 488                         #global-interrupts = <2>;
 489                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 490                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 491                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 492                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 493                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 494                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 495                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 496                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 497                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 498                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 499                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 500                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 501                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 502                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 503                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 504                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 505                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 506                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 507                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 508                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 509                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 510                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 511                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 512                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 513                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 514                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 515                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 516                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 517                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 518                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 519                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 520                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 521                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 522                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 523                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 524                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 525                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 526                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 527                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 528                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 529                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 530                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 531                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 532                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 533                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 534                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 535                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
 536                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 537                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 538                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 539                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 540                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 541                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 542                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 543                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 544                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 545                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 546                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 547                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 548                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 549                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 550                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 551                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 552                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 553                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 554                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 555                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 556                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 557                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 558                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 559                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 560                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 561                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 562                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 563                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 564                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 565                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 566                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 567                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 568                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 569                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
 570                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
 571                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
 572                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 573                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 574                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 575                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 576                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 577                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 578                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
 579                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
 580                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
 581                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
 582                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
 583                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
 584                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
 585                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
 586                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
 587                 };
 588
 589                 config_noc: interconnect@1500000 {
 590                         compatible = "qcom,sm8350-config-noc";
 591                         reg = <0 0x01500000 0 0xa580>;
 592                         #interconnect-cells = <1>;
 593                         qcom,bcm-voters = <&apps_bcm_voter>;
 594                 };
 595
 596                 mc_virt: interconnect@1580000 {
 597                         compatible = "qcom,sm8350-mc-virt";
 598                         reg = <0 0x01580000 0 0x1000>;
 599                         #interconnect-cells = <1>;
 600                         qcom,bcm-voters = <&apps_bcm_voter>;
 601                 };
 602
 603                 system_noc: interconnect@1680000 {
 604                         compatible = "qcom,sm8350-system-noc";
 605                         reg = <0 0x01680000 0 0x1c200>;
 606                         #interconnect-cells = <1>;
 607                         qcom,bcm-voters = <&apps_bcm_voter>;
 608                 };
 609
 610                 aggre1_noc: interconnect@16e0000 {
 611                         compatible = "qcom,sm8350-aggre1-noc";
 612                         reg = <0 0x016e0000 0 0x1f180>;
 613                         #interconnect-cells = <1>;
 614                         qcom,bcm-voters = <&apps_bcm_voter>;
 615                 };
 616
 617                 aggre2_noc: interconnect@1700000 {
 618                         compatible = "qcom,sm8350-aggre2-noc";
 619                         reg = <0 0x01700000 0 0x33000>;
 620                         #interconnect-cells = <1>;
 621                         qcom,bcm-voters = <&apps_bcm_voter>;
 622                 };
 623
 624                 mmss_noc: interconnect@1740000 {
 625                         compatible = "qcom,sm8350-mmss-noc";
 626                         reg = <0 0x01740000 0 0x1f080>;
 627                         #interconnect-cells = <1>;
 628                         qcom,bcm-voters = <&apps_bcm_voter>;
 629                 };
 630
 631                 lpass_ag_noc: interconnect@3c40000 {
 632                         compatible = "qcom,sm8350-lpass-ag-noc";
 633                         reg = <0 0x03c40000 0 0xf080>;
 634                         #interconnect-cells = <1>;
 635                         qcom,bcm-voters = <&apps_bcm_voter>;
 636                 };
 637
 638                 compute_noc: interconnect@a0c0000{
 639                         compatible = "qcom,sm8350-compute-noc";
 640                         reg = <0 0x0a0c0000 0 0xa180>;
 641                         #interconnect-cells = <1>;
 642                         qcom,bcm-voters = <&apps_bcm_voter>;
 643                 };
 644
 645                 ipa: ipa@1e40000 {
 646                         compatible = "qcom,sm8350-ipa";
 647
 648                         iommus = <&apps_smmu 0x5c0 0x0>,
 649                                  <&apps_smmu 0x5c2 0x0>;
 650                         reg = <0 0x1e40000 0 0x8000>,
 651                               <0 0x1e50000 0 0x4b20>,
 652                               <0 0x1e04000 0 0x23000>;
 653                         reg-names = "ipa-reg",
 654                                     "ipa-shared",
 655                                     "gsi";
 656
 657                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
 658                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
 659                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 660                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
 661                         interrupt-names = "ipa",
 662                                           "gsi",
 663                                           "ipa-clock-query",
 664                                           "ipa-setup-ready";
 665
 666                         clocks = <&rpmhcc RPMH_IPA_CLK>;
 667                         clock-names = "core";
 668
 669                         interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
 670                                         <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
 671                                         <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
 672                         interconnect-names = "ipa_to_llcc",
 673                                              "llcc_to_ebi1",
 674                                              "appss_to_ipa";
 675
 676                         qcom,smem-states = <&ipa_smp2p_out 0>,
 677                                            <&ipa_smp2p_out 1>;
 678                         qcom,smem-state-names = "ipa-clock-enabled-valid",
 679                                                 "ipa-clock-enabled";
 680
 681                         status = "disabled";
 682                 };
 683
 684                 tcsr_mutex: hwlock@1f40000 {
 685                         compatible = "qcom,tcsr-mutex";
 686                         reg = <0x0 0x01f40000 0x0 0x40000>;
 687                         #hwlock-cells = <1>;
 688                 };
 689
 690                 mpss: remoteproc@4080000 {
 691                         compatible = "qcom,sm8350-mpss-pas";
 692                         reg = <0x0 0x04080000 0x0 0x4040>;
 693
 694                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
 695                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
 696                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
 697                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
 698                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
 699                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
 700                         interrupt-names = "wdog", "fatal", "ready", "handover",
 701                                           "stop-ack", "shutdown-ack";
 702
 703                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 704                         clock-names = "xo";
 705
 706                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
 707                                         <&rpmhpd 0>,
 708                                         <&rpmhpd 12>;
 709                         power-domain-names = "load_state", "cx", "mss";
 710
 711                         interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
 712
 713                         memory-region = <&pil_modem_mem>;
 714
 715                         qcom,smem-states = <&smp2p_modem_out 0>;
 716                         qcom,smem-state-names = "stop";
 717
 718                         status = "disabled";
 719
 720                         glink-edge {
 721                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 722                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
 723                                                              IRQ_TYPE_EDGE_RISING>;
 724                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 725                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
 726                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
 727                                 label = "modem";
 728                                 qcom,remote-pid = <1>;
 729                         };
 730                 };
 731
 732                 pdc: interrupt-controller@b220000 {
 733                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
 734                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
 735                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
 736                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
 737                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
 738                                           <156 716 12>;
 739                         #interrupt-cells = <2>;
 740                         interrupt-parent = <&intc>;
 741                         interrupt-controller;
 742                 };
 743
 744                 tsens0: thermal-sensor@c263000 {
 745                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
 746                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
 747                               <0 0x0c222000 0 0x8>; /* SROT */
 748                         #qcom,sensors = <15>;
 749                         interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
 751                         interrupt-names = "uplow", "critical";
 752                         #thermal-sensor-cells = <1>;
 753                 };
 754
 755                 tsens1: thermal-sensor@c265000 {
 756                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
 757                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
 758                               <0 0x0c223000 0 0x8>; /* SROT */
 759                         #qcom,sensors = <14>;
 760                         interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
 762                         interrupt-names = "uplow", "critical";
 763                         #thermal-sensor-cells = <1>;
 764                 };
 765
 766                 aoss_qmp: power-controller@c300000 {
 767                         compatible = "qcom,sm8350-aoss-qmp";
 768                         reg = <0 0x0c300000 0 0x100000>;
 769                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
 770                                                      IRQ_TYPE_EDGE_RISING>;
 771                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
 772
 773                         #clock-cells = <0>;
 774                         #power-domain-cells = <1>;
 775                 };
 776
 777                 spmi_bus: spmi@c440000 {
 778                         compatible = "qcom,spmi-pmic-arb";
 779                         reg = <0x0 0xc440000 0x0 0x1100>,
 780                               <0x0 0xc600000 0x0 0x2000000>,
 781                               <0x0 0xe600000 0x0 0x100000>,
 782                               <0x0 0xe700000 0x0 0xa0000>,
 783                               <0x0 0xc40a000 0x0 0x26000>;
 784                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 785                         interrupt-names = "periph_irq";
 786                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
 787                         qcom,ee = <0>;
 788                         qcom,channel = <0>;
 789                         #address-cells = <2>;
 790                         #size-cells = <0>;
 791                         interrupt-controller;
 792                         #interrupt-cells = <4>;
 793                 };
 794
 795                 tlmm: pinctrl@f100000 {
 796                         compatible = "qcom,sm8350-tlmm";
 797                         reg = <0 0x0f100000 0 0x300000>;
 798                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 799                         gpio-controller;
 800                         #gpio-cells = <2>;
 801                         interrupt-controller;
 802                         #interrupt-cells = <2>;
 803                         gpio-ranges = <&tlmm 0 0 204>;
 804                         wakeup-parent = <&pdc>;
 805
 806                         qup_uart3_default_state: qup-uart3-default-state {
 807                                 rx {
 808                                         pins = "gpio18";
 809                                         function = "qup3";
 810                                 };
 811                                 tx {
 812                                         pins = "gpio19";
 813                                         function = "qup3";
 814                                 };
 815                         };
 816                 };
 817
 818                 rng: rng@10d3000 {
 819                         compatible = "qcom,prng-ee";
 820                         reg = <0 0x010d3000 0 0x1000>;
 821                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
 822                         clock-names = "core";
 823                 };
 824
 825                 intc: interrupt-controller@17a00000 {
 826                         compatible = "arm,gic-v3";
 827                         #interrupt-cells = <3>;
 828                         interrupt-controller;
 829                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
 830                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
 831                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 832                 };
 833
 834                 timer@17c20000 {
 835                         compatible = "arm,armv7-timer-mem";
 836                         #address-cells = <2>;
 837                         #size-cells = <2>;
 838                         ranges;
 839                         reg = <0x0 0x17c20000 0x0 0x1000>;
 840                         clock-frequency = <19200000>;
 841
 842                         frame@17c21000 {
 843                                 frame-number = <0>;
 844                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 845                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 846                                 reg = <0x0 0x17c21000 0x0 0x1000>,
 847                                       <0x0 0x17c22000 0x0 0x1000>;
 848                         };
 849
 850                         frame@17c23000 {
 851                                 frame-number = <1>;
 852                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 853                                 reg = <0x0 0x17c23000 0x0 0x1000>;
 854                                 status = "disabled";
 855                         };
 856
 857                         frame@17c25000 {
 858                                 frame-number = <2>;
 859                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 860                                 reg = <0x0 0x17c25000 0x0 0x1000>;
 861                                 status = "disabled";
 862                         };
 863
 864                         frame@17c27000 {
 865                                 frame-number = <3>;
 866                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 867                                 reg = <0x0 0x17c27000 0x0 0x1000>;
 868                                 status = "disabled";
 869                         };
 870
 871                         frame@17c29000 {
 872                                 frame-number = <4>;
 873                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 874                                 reg = <0x0 0x17c29000 0x0 0x1000>;
 875                                 status = "disabled";
 876                         };
 877
 878                         frame@17c2b000 {
 879                                 frame-number = <5>;
 880                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 881                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
 882                                 status = "disabled";
 883                         };
 884
 885                         frame@17c2d000 {
 886                                 frame-number = <6>;
 887                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 888                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
 889                                 status = "disabled";
 890                         };
 891                 };
 892
 893                 apps_rsc: rsc@18200000 {
 894                         label = "apps_rsc";
 895                         compatible = "qcom,rpmh-rsc";
 896                         reg = <0x0 0x18200000 0x0 0x10000>,
 897                                 <0x0 0x18210000 0x0 0x10000>,
 898                                 <0x0 0x18220000 0x0 0x10000>;
 899                         reg-names = "drv-0", "drv-1", "drv-2";
 900                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 902                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 903                         qcom,tcs-offset = <0xd00>;
 904                         qcom,drv-id = <2>;
 905                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
 906                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
 907
 908                         rpmhcc: clock-controller {
 909                                 compatible = "qcom,sm8350-rpmh-clk";
 910                                 #clock-cells = <1>;
 911                                 clock-names = "xo";
 912                                 clocks = <&xo_board>;
 913                         };
 914
 915                         rpmhpd: power-controller {
 916                                 compatible = "qcom,sm8350-rpmhpd";
 917                                 #power-domain-cells = <1>;
 918                                 operating-points-v2 = <&rpmhpd_opp_table>;
 919
 920                                 rpmhpd_opp_table: opp-table {
 921                                         compatible = "operating-points-v2";
 922
 923                                         rpmhpd_opp_ret: opp1 {
 924                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 925                                         };
 926
 927                                         rpmhpd_opp_min_svs: opp2 {
 928                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 929                                         };
 930
 931                                         rpmhpd_opp_low_svs: opp3 {
 932                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 933                                         };
 934
 935                                         rpmhpd_opp_svs: opp4 {
 936                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 937                                         };
 938
 939                                         rpmhpd_opp_svs_l1: opp5 {
 940                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 941                                         };
 942
 943                                         rpmhpd_opp_nom: opp6 {
 944                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 945                                         };
 946
 947                                         rpmhpd_opp_nom_l1: opp7 {
 948                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 949                                         };
 950
 951                                         rpmhpd_opp_nom_l2: opp8 {
 952                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
 953                                         };
 954
 955                                         rpmhpd_opp_turbo: opp9 {
 956                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 957                                         };
 958
 959                                         rpmhpd_opp_turbo_l1: opp10 {
 960                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 961                                         };
 962                                 };
 963                         };
 964
 965                         apps_bcm_voter: bcm_voter {
 966                                 compatible = "qcom,bcm-voter";
 967                         };
 968                 };
 969
 970                 cpufreq_hw: cpufreq@18591000 {
 971                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
 972                         reg = <0 0x18591000 0 0x1000>,
 973                               <0 0x18592000 0 0x1000>,
 974                               <0 0x18593000 0 0x1000>;
 975                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
 976
 977                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
 978                         clock-names = "xo", "alternate";
 979
 980                         #freq-domain-cells = <1>;
 981                 };
 982
 983                 ufs_mem_hc: ufshc@1d84000 {
 984                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
 985                                      "jedec,ufs-2.0";
 986                         reg = <0 0x01d84000 0 0x3000>;
 987                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 988                         phys = <&ufs_mem_phy_lanes>;
 989                         phy-names = "ufsphy";
 990                         lanes-per-direction = <2>;
 991                         #reset-cells = <1>;
 992                         resets = <&gcc GCC_UFS_PHY_BCR>;
 993                         reset-names = "rst";
 994
 995                         power-domains = <&gcc UFS_PHY_GDSC>;
 996
 997                         iommus = <&apps_smmu 0xe0 0x0>;
 998
 999                         clock-names =
1000                                 "ref_clk",
1001                                 "core_clk",
1002                                 "bus_aggr_clk",
1003                                 "iface_clk",
1004                                 "core_clk_unipro",
1005                                 "ref_clk",
1006                                 "tx_lane0_sync_clk",
1007                                 "rx_lane0_sync_clk",
1008                                 "rx_lane1_sync_clk";
1009                         clocks =
1010                                 <&rpmhcc RPMH_CXO_CLK>,
1011                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1012                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1013                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1014                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1015                                 <&rpmhcc RPMH_CXO_CLK>,
1016                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1017                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1018                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1019                         freq-table-hz =
1020                                 <75000000 300000000>,
1021                                 <75000000 300000000>,
1022                                 <0 0>,
1023                                 <0 0>,
1024                                 <75000000 300000000>,
1025                                 <0 0>,
1026                                 <0 0>,
1027                                 <75000000 300000000>,
1028                                 <75000000 300000000>;
1029                         status = "disabled";
1030                 };
1031
1032                 ufs_mem_phy: phy@1d87000 {
1033                         compatible = "qcom,sm8350-qmp-ufs-phy";
1034                         reg = <0 0x01d87000 0 0xe10>;
1035                         #address-cells = <2>;
1036                         #size-cells = <2>;
1037                         #clock-cells = <1>;
1038                         ranges;
1039                         clock-names = "ref",
1040                                       "ref_aux";
1041                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1042                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1043
1044                         resets = <&ufs_mem_hc 0>;
1045                         reset-names = "ufsphy";
1046                         status = "disabled";
1047
1048                         ufs_mem_phy_lanes: lanes@1d87400 {
1049                                 reg = <0 0x01d87400 0 0x108>,
1050                                       <0 0x01d87600 0 0x1e0>,
1051                                       <0 0x01d87c00 0 0x1dc>,
1052                                       <0 0x01d87800 0 0x108>,
1053                                       <0 0x01d87a00 0 0x1e0>;
1054                                 #phy-cells = <0>;
1055                                 #clock-cells = <0>;
1056                         };
1057                 };
1058
1059                 slpi: remoteproc@5c00000 {
1060                         compatible = "qcom,sm8350-slpi-pas";
1061                         reg = <0 0x05c00000 0 0x4000>;
1062
1063                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1064                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1065                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1066                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1067                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1068                         interrupt-names = "wdog", "fatal", "ready",
1069                                           "handover", "stop-ack";
1070
1071                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1072                         clock-names = "xo";
1073
1074                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1075                                         <&rpmhpd 4>,
1076                                         <&rpmhpd 5>;
1077                         power-domain-names = "load_state", "lcx", "lmx";
1078
1079                         memory-region = <&pil_slpi_mem>;
1080
1081                         qcom,smem-states = <&smp2p_slpi_out 0>;
1082                         qcom,smem-state-names = "stop";
1083
1084                         status = "disabled";
1085
1086                         glink-edge {
1087                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1088                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1089                                                              IRQ_TYPE_EDGE_RISING>;
1090                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1091                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1092
1093                                 label = "slpi";
1094                                 qcom,remote-pid = <3>;
1095
1096                         };
1097                 };
1098
1099                 cdsp: remoteproc@98900000 {
1100                         compatible = "qcom,sm8350-cdsp-pas";
1101                         reg = <0 0x098900000 0 0x1400000>;
1102
1103                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1104                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1105                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1106                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1107                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1108                         interrupt-names = "wdog", "fatal", "ready",
1109                                           "handover", "stop-ack";
1110
1111                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1112                         clock-names = "xo";
1113
1114                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1115                                         <&rpmhpd 0>,
1116                                         <&rpmhpd 10>;
1117                         power-domain-names = "load_state", "cx", "mxc";
1118
1119                         interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
1120
1121                         memory-region = <&pil_cdsp_mem>;
1122
1123                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1124                         qcom,smem-state-names = "stop";
1125
1126                         status = "disabled";
1127
1128                         glink-edge {
1129                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1130                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1131                                                              IRQ_TYPE_EDGE_RISING>;
1132                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1133                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1134
1135                                 label = "cdsp";
1136                                 qcom,remote-pid = <5>;
1137                         };
1138                 };
1139
1140                 usb_1_hsphy: phy@88e3000 {
1141                         compatible = "qcom,sm8350-usb-hs-phy",
1142                                      "qcom,usb-snps-hs-7nm-phy";
1143                         reg = <0 0x088e3000 0 0x400>;
1144                         status = "disabled";
1145                         #phy-cells = <0>;
1146
1147                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1148                         clock-names = "ref";
1149
1150                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1151                 };
1152
1153                 usb_2_hsphy: phy@88e4000 {
1154                         compatible = "qcom,sm8250-usb-hs-phy",
1155                                      "qcom,usb-snps-hs-7nm-phy";
1156                         reg = <0 0x088e4000 0 0x400>;
1157                         status = "disabled";
1158                         #phy-cells = <0>;
1159
1160                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1161                         clock-names = "ref";
1162
1163                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1164                 };
1165
1166                 usb_1_qmpphy: phy-wrapper@88e9000 {
1167                         compatible = "qcom,sm8350-qmp-usb3-phy";
1168                         reg = <0 0x088e9000 0 0x200>,
1169                               <0 0x088e8000 0 0x20>;
1170                         reg-names = "reg-base", "dp_com";
1171                         status = "disabled";
1172                         #clock-cells = <1>;
1173                         #address-cells = <2>;
1174                         #size-cells = <2>;
1175                         ranges;
1176
1177                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1178                                  <&rpmhcc RPMH_CXO_CLK>,
1179                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1180                         clock-names = "aux", "ref_clk_src", "com_aux";
1181
1182                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1183                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1184                         reset-names = "phy", "common";
1185
1186                         usb_1_ssphy: phy@88e9200 {
1187                                 reg = <0 0x088e9200 0 0x200>,
1188                                       <0 0x088e9400 0 0x200>,
1189                                       <0 0x088e9c00 0 0x400>,
1190                                       <0 0x088e9600 0 0x200>,
1191                                       <0 0x088e9800 0 0x200>,
1192                                       <0 0x088e9a00 0 0x100>;
1193                                 #phy-cells = <0>;
1194                                 #clock-cells = <1>;
1195                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1196                                 clock-names = "pipe0";
1197                                 clock-output-names = "usb3_phy_pipe_clk_src";
1198                         };
1199                 };
1200
1201                 usb_2_qmpphy: phy-wrapper@88eb000 {
1202                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
1203                         reg = <0 0x088eb000 0 0x200>;
1204                         status = "disabled";
1205                         #clock-cells = <1>;
1206                         #address-cells = <2>;
1207                         #size-cells = <2>;
1208                         ranges;
1209
1210                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1211                                  <&rpmhcc RPMH_CXO_CLK>,
1212                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
1213                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1214                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1215
1216                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1217                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
1218                         reset-names = "phy", "common";
1219
1220                         usb_2_ssphy: phy@88ebe00 {
1221                                 reg = <0 0x088ebe00 0 0x200>,
1222                                       <0 0x088ec000 0 0x200>,
1223                                       <0 0x088eb200 0 0x1100>;
1224                                 #phy-cells = <0>;
1225                                 #clock-cells = <1>;
1226                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1227                                 clock-names = "pipe0";
1228                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1229                         };
1230                 };
1231
1232                 dc_noc: interconnect@90c0000 {
1233                         compatible = "qcom,sm8350-dc-noc";
1234                         reg = <0 0x090c0000 0 0x4200>;
1235                         #interconnect-cells = <1>;
1236                         qcom,bcm-voters = <&apps_bcm_voter>;
1237                 };
1238
1239                 gem_noc: interconnect@9100000 {
1240                         compatible = "qcom,sm8350-gem-noc";
1241                         reg = <0 0x09100000 0 0xb4000>;
1242                         #interconnect-cells = <1>;
1243                         qcom,bcm-voters = <&apps_bcm_voter>;
1244                 };
1245
1246                 usb_1: usb@a6f8800 {
1247                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1248                         reg = <0 0x0a6f8800 0 0x400>;
1249                         status = "disabled";
1250                         #address-cells = <2>;
1251                         #size-cells = <2>;
1252                         ranges;
1253
1254                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1255                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1256                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1257                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1258                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1259                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1260                                       "sleep";
1261
1262                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1263                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1264                         assigned-clock-rates = <19200000>, <200000000>;
1265
1266                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1267                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1268                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1269                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1270                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1271                                           "dm_hs_phy_irq", "ss_phy_irq";
1272
1273                         power-domains = <&gcc USB30_PRIM_GDSC>;
1274
1275                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1276
1277                         usb_1_dwc3: usb@a600000 {
1278                                 compatible = "snps,dwc3";
1279                                 reg = <0 0x0a600000 0 0xcd00>;
1280                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1281                                 iommus = <&apps_smmu 0x0 0x0>;
1282                                 snps,dis_u2_susphy_quirk;
1283                                 snps,dis_enblslpm_quirk;
1284                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1285                                 phy-names = "usb2-phy", "usb3-phy";
1286                         };
1287                 };
1288
1289                 usb_2: usb@a8f8800 {
1290                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
1291                         reg = <0 0x0a8f8800 0 0x400>;
1292                         status = "disabled";
1293                         #address-cells = <2>;
1294                         #size-cells = <2>;
1295                         ranges;
1296
1297                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1298                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1299                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1300                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1301                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1302                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1303                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1304                                       "sleep", "xo";
1305
1306                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1307                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1308                         assigned-clock-rates = <19200000>, <200000000>;
1309
1310                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1311                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1312                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1313                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1314                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1315                                           "dm_hs_phy_irq", "ss_phy_irq";
1316
1317                         power-domains = <&gcc USB30_SEC_GDSC>;
1318
1319                         resets = <&gcc GCC_USB30_SEC_BCR>;
1320
1321                         usb_2_dwc3: usb@a800000 {
1322                                 compatible = "snps,dwc3";
1323                                 reg = <0 0x0a800000 0 0xcd00>;
1324                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1325                                 iommus = <&apps_smmu 0x20 0x0>;
1326                                 snps,dis_u2_susphy_quirk;
1327                                 snps,dis_enblslpm_quirk;
1328                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1329                                 phy-names = "usb2-phy", "usb3-phy";
1330                         };
1331                 };
1332
1333                 adsp: remoteproc@17300000 {
1334                         compatible = "qcom,sm8350-adsp-pas";
1335                         reg = <0 0x17300000 0 0x100>;
1336
1337                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1338                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1339                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1340                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1341                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1342                         interrupt-names = "wdog", "fatal", "ready",
1343                                           "handover", "stop-ack";
1344
1345                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1346                         clock-names = "xo";
1347
1348                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1349                                         <&rpmhpd 4>,
1350                                         <&rpmhpd 5>;
1351                         power-domain-names = "load_state", "lcx", "lmx";
1352
1353                         memory-region = <&pil_adsp_mem>;
1354
1355                         qcom,smem-states = <&smp2p_adsp_out 0>;
1356                         qcom,smem-state-names = "stop";
1357
1358                         status = "disabled";
1359
1360                         glink-edge {
1361                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1362                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1363                                                              IRQ_TYPE_EDGE_RISING>;
1364                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
1365                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1366
1367                                 label = "lpass";
1368                                 qcom,remote-pid = <2>;
1369                         };
1370                 };
1371         };
1372
1373         thermal_zones: thermal-zones {
1374                 cpu0-thermal {
1375                         polling-delay-passive = <250>;
1376                         polling-delay = <1000>;
1377
1378                         thermal-sensors = <&tsens0 1>;
1379
1380                         trips {
1381                                 cpu0_alert0: trip-point0 {
1382                                         temperature = <90000>;
1383                                         hysteresis = <2000>;
1384                                         type = "passive";
1385                                 };
1386
1387                                 cpu0_alert1: trip-point1 {
1388                                         temperature = <95000>;
1389                                         hysteresis = <2000>;
1390                                         type = "passive";
1391                                 };
1392
1393                                 cpu0_crit: cpu_crit {
1394                                         temperature = <110000>;
1395                                         hysteresis = <1000>;
1396                                         type = "critical";
1397                                 };
1398                         };
1399
1400                         cooling-maps {
1401                                 map0 {
1402                                         trip = <&cpu0_alert0>;
1403                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1404                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1405                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1406                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1407                                 };
1408                                 map1 {
1409                                         trip = <&cpu0_alert1>;
1410                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1411                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1412                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1413                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1414                                 };
1415                         };
1416                 };
1417
1418                 cpu1-thermal {
1419                         polling-delay-passive = <250>;
1420                         polling-delay = <1000>;
1421
1422                         thermal-sensors = <&tsens0 2>;
1423
1424                         trips {
1425                                 cpu1_alert0: trip-point0 {
1426                                         temperature = <90000>;
1427                                         hysteresis = <2000>;
1428                                         type = "passive";
1429                                 };
1430
1431                                 cpu1_alert1: trip-point1 {
1432                                         temperature = <95000>;
1433                                         hysteresis = <2000>;
1434                                         type = "passive";
1435                                 };
1436
1437                                 cpu1_crit: cpu_crit {
1438                                         temperature = <110000>;
1439                                         hysteresis = <1000>;
1440                                         type = "critical";
1441                                 };
1442                         };
1443
1444                         cooling-maps {
1445                                 map0 {
1446                                         trip = <&cpu1_alert0>;
1447                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1448                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1449                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1450                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1451                                 };
1452                                 map1 {
1453                                         trip = <&cpu1_alert1>;
1454                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1455                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1456                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1457                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1458                                 };
1459                         };
1460                 };
1461
1462                 cpu2-thermal {
1463                         polling-delay-passive = <250>;
1464                         polling-delay = <1000>;
1465
1466                         thermal-sensors = <&tsens0 3>;
1467
1468                         trips {
1469                                 cpu2_alert0: trip-point0 {
1470                                         temperature = <90000>;
1471                                         hysteresis = <2000>;
1472                                         type = "passive";
1473                                 };
1474
1475                                 cpu2_alert1: trip-point1 {
1476                                         temperature = <95000>;
1477                                         hysteresis = <2000>;
1478                                         type = "passive";
1479                                 };
1480
1481                                 cpu2_crit: cpu_crit {
1482                                         temperature = <110000>;
1483                                         hysteresis = <1000>;
1484                                         type = "critical";
1485                                 };
1486                         };
1487
1488                         cooling-maps {
1489                                 map0 {
1490                                         trip = <&cpu2_alert0>;
1491                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1492                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1493                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1494                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1495                                 };
1496                                 map1 {
1497                                         trip = <&cpu2_alert1>;
1498                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1499                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1500                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1501                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1502                                 };
1503                         };
1504                 };
1505
1506                 cpu3-thermal {
1507                         polling-delay-passive = <250>;
1508                         polling-delay = <1000>;
1509
1510                         thermal-sensors = <&tsens0 4>;
1511
1512                         trips {
1513                                 cpu3_alert0: trip-point0 {
1514                                         temperature = <90000>;
1515                                         hysteresis = <2000>;
1516                                         type = "passive";
1517                                 };
1518
1519                                 cpu3_alert1: trip-point1 {
1520                                         temperature = <95000>;
1521                                         hysteresis = <2000>;
1522                                         type = "passive";
1523                                 };
1524
1525                                 cpu3_crit: cpu_crit {
1526                                         temperature = <110000>;
1527                                         hysteresis = <1000>;
1528                                         type = "critical";
1529                                 };
1530                         };
1531
1532                         cooling-maps {
1533                                 map0 {
1534                                         trip = <&cpu3_alert0>;
1535                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1536                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1537                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1538                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1539                                 };
1540                                 map1 {
1541                                         trip = <&cpu3_alert1>;
1542                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1543                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1544                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1545                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1546                                 };
1547                         };
1548                 };
1549
1550                 cpu4-top-thermal {
1551                         polling-delay-passive = <250>;
1552                         polling-delay = <1000>;
1553
1554                         thermal-sensors = <&tsens0 7>;
1555
1556                         trips {
1557                                 cpu4_top_alert0: trip-point0 {
1558                                         temperature = <90000>;
1559                                         hysteresis = <2000>;
1560                                         type = "passive";
1561                                 };
1562
1563                                 cpu4_top_alert1: trip-point1 {
1564                                         temperature = <95000>;
1565                                         hysteresis = <2000>;
1566                                         type = "passive";
1567                                 };
1568
1569                                 cpu4_top_crit: cpu_crit {
1570                                         temperature = <110000>;
1571                                         hysteresis = <1000>;
1572                                         type = "critical";
1573                                 };
1574                         };
1575
1576                         cooling-maps {
1577                                 map0 {
1578                                         trip = <&cpu4_top_alert0>;
1579                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1580                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1581                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1582                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1583                                 };
1584                                 map1 {
1585                                         trip = <&cpu4_top_alert1>;
1586                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1587                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1588                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1589                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1590                                 };
1591                         };
1592                 };
1593
1594                 cpu5-top-thermal {
1595                         polling-delay-passive = <250>;
1596                         polling-delay = <1000>;
1597
1598                         thermal-sensors = <&tsens0 8>;
1599
1600                         trips {
1601                                 cpu5_top_alert0: trip-point0 {
1602                                         temperature = <90000>;
1603                                         hysteresis = <2000>;
1604                                         type = "passive";
1605                                 };
1606
1607                                 cpu5_top_alert1: trip-point1 {
1608                                         temperature = <95000>;
1609                                         hysteresis = <2000>;
1610                                         type = "passive";
1611                                 };
1612
1613                                 cpu5_top_crit: cpu_crit {
1614                                         temperature = <110000>;
1615                                         hysteresis = <1000>;
1616                                         type = "critical";
1617                                 };
1618                         };
1619
1620                         cooling-maps {
1621                                 map0 {
1622                                         trip = <&cpu5_top_alert0>;
1623                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1624                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1625                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1626                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1627                                 };
1628                                 map1 {
1629                                         trip = <&cpu5_top_alert1>;
1630                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1631                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1632                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1633                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1634                                 };
1635                         };
1636                 };
1637
1638                 cpu6-top-thermal {
1639                         polling-delay-passive = <250>;
1640                         polling-delay = <1000>;
1641
1642                         thermal-sensors = <&tsens0 9>;
1643
1644                         trips {
1645                                 cpu6_top_alert0: trip-point0 {
1646                                         temperature = <90000>;
1647                                         hysteresis = <2000>;
1648                                         type = "passive";
1649                                 };
1650
1651                                 cpu6_top_alert1: trip-point1 {
1652                                         temperature = <95000>;
1653                                         hysteresis = <2000>;
1654                                         type = "passive";
1655                                 };
1656
1657                                 cpu6_top_crit: cpu_crit {
1658                                         temperature = <110000>;
1659                                         hysteresis = <1000>;
1660                                         type = "critical";
1661                                 };
1662                         };
1663
1664                         cooling-maps {
1665                                 map0 {
1666                                         trip = <&cpu6_top_alert0>;
1667                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1668                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1669                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1670                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1671                                 };
1672                                 map1 {
1673                                         trip = <&cpu6_top_alert1>;
1674                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1675                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1676                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1677                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1678                                 };
1679                         };
1680                 };
1681
1682                 cpu7-top-thermal {
1683                         polling-delay-passive = <250>;
1684                         polling-delay = <1000>;
1685
1686                         thermal-sensors = <&tsens0 10>;
1687
1688                         trips {
1689                                 cpu7_top_alert0: trip-point0 {
1690                                         temperature = <90000>;
1691                                         hysteresis = <2000>;
1692                                         type = "passive";
1693                                 };
1694
1695                                 cpu7_top_alert1: trip-point1 {
1696                                         temperature = <95000>;
1697                                         hysteresis = <2000>;
1698                                         type = "passive";
1699                                 };
1700
1701                                 cpu7_top_crit: cpu_crit {
1702                                         temperature = <110000>;
1703                                         hysteresis = <1000>;
1704                                         type = "critical";
1705                                 };
1706                         };
1707
1708                         cooling-maps {
1709                                 map0 {
1710                                         trip = <&cpu7_top_alert0>;
1711                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1712                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1713                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1714                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1715                                 };
1716                                 map1 {
1717                                         trip = <&cpu7_top_alert1>;
1718                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1719                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1720                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1721                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1722                                 };
1723                         };
1724                 };
1725
1726                 cpu4-bottom-thermal {
1727                         polling-delay-passive = <250>;
1728                         polling-delay = <1000>;
1729
1730                         thermal-sensors = <&tsens0 11>;
1731
1732                         trips {
1733                                 cpu4_bottom_alert0: trip-point0 {
1734                                         temperature = <90000>;
1735                                         hysteresis = <2000>;
1736                                         type = "passive";
1737                                 };
1738
1739                                 cpu4_bottom_alert1: trip-point1 {
1740                                         temperature = <95000>;
1741                                         hysteresis = <2000>;
1742                                         type = "passive";
1743                                 };
1744
1745                                 cpu4_bottom_crit: cpu_crit {
1746                                         temperature = <110000>;
1747                                         hysteresis = <1000>;
1748                                         type = "critical";
1749                                 };
1750                         };
1751
1752                         cooling-maps {
1753                                 map0 {
1754                                         trip = <&cpu4_bottom_alert0>;
1755                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1756                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1757                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1758                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1759                                 };
1760                                 map1 {
1761                                         trip = <&cpu4_bottom_alert1>;
1762                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1763                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1764                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1765                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1766                                 };
1767                         };
1768                 };
1769
1770                 cpu5-bottom-thermal {
1771                         polling-delay-passive = <250>;
1772                         polling-delay = <1000>;
1773
1774                         thermal-sensors = <&tsens0 12>;
1775
1776                         trips {
1777                                 cpu5_bottom_alert0: trip-point0 {
1778                                         temperature = <90000>;
1779                                         hysteresis = <2000>;
1780                                         type = "passive";
1781                                 };
1782
1783                                 cpu5_bottom_alert1: trip-point1 {
1784                                         temperature = <95000>;
1785                                         hysteresis = <2000>;
1786                                         type = "passive";
1787                                 };
1788
1789                                 cpu5_bottom_crit: cpu_crit {
1790                                         temperature = <110000>;
1791                                         hysteresis = <1000>;
1792                                         type = "critical";
1793                                 };
1794                         };
1795
1796                         cooling-maps {
1797                                 map0 {
1798                                         trip = <&cpu5_bottom_alert0>;
1799                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1800                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1801                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1802                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1803                                 };
1804                                 map1 {
1805                                         trip = <&cpu5_bottom_alert1>;
1806                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1807                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1808                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1809                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1810                                 };
1811                         };
1812                 };
1813
1814                 cpu6-bottom-thermal {
1815                         polling-delay-passive = <250>;
1816                         polling-delay = <1000>;
1817
1818                         thermal-sensors = <&tsens0 13>;
1819
1820                         trips {
1821                                 cpu6_bottom_alert0: trip-point0 {
1822                                         temperature = <90000>;
1823                                         hysteresis = <2000>;
1824                                         type = "passive";
1825                                 };
1826
1827                                 cpu6_bottom_alert1: trip-point1 {
1828                                         temperature = <95000>;
1829                                         hysteresis = <2000>;
1830                                         type = "passive";
1831                                 };
1832
1833                                 cpu6_bottom_crit: cpu_crit {
1834                                         temperature = <110000>;
1835                                         hysteresis = <1000>;
1836                                         type = "critical";
1837                                 };
1838                         };
1839
1840                         cooling-maps {
1841                                 map0 {
1842                                         trip = <&cpu6_bottom_alert0>;
1843                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1844                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1845                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1846                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1847                                 };
1848                                 map1 {
1849                                         trip = <&cpu6_bottom_alert1>;
1850                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1851                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1852                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1853                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1854                                 };
1855                         };
1856                 };
1857
1858                 cpu7-bottom-thermal {
1859                         polling-delay-passive = <250>;
1860                         polling-delay = <1000>;
1861
1862                         thermal-sensors = <&tsens0 14>;
1863
1864                         trips {
1865                                 cpu7_bottom_alert0: trip-point0 {
1866                                         temperature = <90000>;
1867                                         hysteresis = <2000>;
1868                                         type = "passive";
1869                                 };
1870
1871                                 cpu7_bottom_alert1: trip-point1 {
1872                                         temperature = <95000>;
1873                                         hysteresis = <2000>;
1874                                         type = "passive";
1875                                 };
1876
1877                                 cpu7_bottom_crit: cpu_crit {
1878                                         temperature = <110000>;
1879                                         hysteresis = <1000>;
1880                                         type = "critical";
1881                                 };
1882                         };
1883
1884                         cooling-maps {
1885                                 map0 {
1886                                         trip = <&cpu7_bottom_alert0>;
1887                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1888                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1889                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1890                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1891                                 };
1892                                 map1 {
1893                                         trip = <&cpu7_bottom_alert1>;
1894                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1895                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1896                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1897                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1898                                 };
1899                         };
1900                 };
1901
1902                 aoss0-thermal {
1903                         polling-delay-passive = <250>;
1904                         polling-delay = <1000>;
1905
1906                         thermal-sensors = <&tsens0 0>;
1907
1908                         trips {
1909                                 aoss0_alert0: trip-point0 {
1910                                         temperature = <90000>;
1911                                         hysteresis = <2000>;
1912                                         type = "hot";
1913                                 };
1914                         };
1915                 };
1916
1917                 cluster0-thermal {
1918                         polling-delay-passive = <250>;
1919                         polling-delay = <1000>;
1920
1921                         thermal-sensors = <&tsens0 5>;
1922
1923                         trips {
1924                                 cluster0_alert0: trip-point0 {
1925                                         temperature = <90000>;
1926                                         hysteresis = <2000>;
1927                                         type = "hot";
1928                                 };
1929                                 cluster0_crit: cluster0_crit {
1930                                         temperature = <110000>;
1931                                         hysteresis = <2000>;
1932                                         type = "critical";
1933                                 };
1934                         };
1935                 };
1936
1937                 cluster1-thermal {
1938                         polling-delay-passive = <250>;
1939                         polling-delay = <1000>;
1940
1941                         thermal-sensors = <&tsens0 6>;
1942
1943                         trips {
1944                                 cluster1_alert0: trip-point0 {
1945                                         temperature = <90000>;
1946                                         hysteresis = <2000>;
1947                                         type = "hot";
1948                                 };
1949                                 cluster1_crit: cluster1_crit {
1950                                         temperature = <110000>;
1951                                         hysteresis = <2000>;
1952                                         type = "critical";
1953                                 };
1954                         };
1955                 };
1956
1957                 aoss1-thermal {
1958                         polling-delay-passive = <250>;
1959                         polling-delay = <1000>;
1960
1961                         thermal-sensors = <&tsens1 0>;
1962
1963                         trips {
1964                                 aoss1_alert0: trip-point0 {
1965                                         temperature = <90000>;
1966                                         hysteresis = <2000>;
1967                                         type = "hot";
1968                                 };
1969                         };
1970                 };
1971
1972                 gpu-thermal-top {
1973                         polling-delay-passive = <250>;
1974                         polling-delay = <1000>;
1975
1976                         thermal-sensors = <&tsens1 1>;
1977
1978                         trips {
1979                                 gpu1_alert0: trip-point0 {
1980                                         temperature = <90000>;
1981                                         hysteresis = <1000>;
1982                                         type = "hot";
1983                                 };
1984                         };
1985                 };
1986
1987                 gpu-thermal-bottom {
1988                         polling-delay-passive = <250>;
1989                         polling-delay = <1000>;
1990
1991                         thermal-sensors = <&tsens1 2>;
1992
1993                         trips {
1994                                 gpu2_alert0: trip-point0 {
1995                                         temperature = <90000>;
1996                                         hysteresis = <1000>;
1997                                         type = "hot";
1998                                 };
1999                         };
2000                 };
2001
2002                 nspss1-thermal {
2003                         polling-delay-passive = <250>;
2004                         polling-delay = <1000>;
2005
2006                         thermal-sensors = <&tsens1 3>;
2007
2008                         trips {
2009                                 nspss1_alert0: trip-point0 {
2010                                         temperature = <90000>;
2011                                         hysteresis = <1000>;
2012                                         type = "hot";
2013                                 };
2014                         };
2015                 };
2016
2017                 nspss2-thermal {
2018                         polling-delay-passive = <250>;
2019                         polling-delay = <1000>;
2020
2021                         thermal-sensors = <&tsens1 4>;
2022
2023                         trips {
2024                                 nspss2_alert0: trip-point0 {
2025                                         temperature = <90000>;
2026                                         hysteresis = <1000>;
2027                                         type = "hot";
2028                                 };
2029                         };
2030                 };
2031
2032                 nspss3-thermal {
2033                         polling-delay-passive = <250>;
2034                         polling-delay = <1000>;
2035
2036                         thermal-sensors = <&tsens1 5>;
2037
2038                         trips {
2039                                 nspss3_alert0: trip-point0 {
2040                                         temperature = <90000>;
2041                                         hysteresis = <1000>;
2042                                         type = "hot";
2043                                 };
2044                         };
2045                 };
2046
2047                 video-thermal {
2048                         polling-delay-passive = <250>;
2049                         polling-delay = <1000>;
2050
2051                         thermal-sensors = <&tsens1 6>;
2052
2053                         trips {
2054                                 video_alert0: trip-point0 {
2055                                         temperature = <90000>;
2056                                         hysteresis = <2000>;
2057                                         type = "hot";
2058                                 };
2059                         };
2060                 };
2061
2062                 mem-thermal {
2063                         polling-delay-passive = <250>;
2064                         polling-delay = <1000>;
2065
2066                         thermal-sensors = <&tsens1 7>;
2067
2068                         trips {
2069                                 mem_alert0: trip-point0 {
2070                                         temperature = <90000>;
2071                                         hysteresis = <2000>;
2072                                         type = "hot";
2073                                 };
2074                         };
2075                 };
2076
2077                 modem1-thermal-top {
2078                         polling-delay-passive = <250>;
2079                         polling-delay = <1000>;
2080
2081                         thermal-sensors = <&tsens1 8>;
2082
2083                         trips {
2084                                 modem1_alert0: trip-point0 {
2085                                         temperature = <90000>;
2086                                         hysteresis = <2000>;
2087                                         type = "hot";
2088                                 };
2089                         };
2090                 };
2091
2092                 modem2-thermal-top {
2093                         polling-delay-passive = <250>;
2094                         polling-delay = <1000>;
2095
2096                         thermal-sensors = <&tsens1 9>;
2097
2098                         trips {
2099                                 modem2_alert0: trip-point0 {
2100                                         temperature = <90000>;
2101                                         hysteresis = <2000>;
2102                                         type = "hot";
2103                                 };
2104                         };
2105                 };
2106
2107                 modem3-thermal-top {
2108                         polling-delay-passive = <250>;
2109                         polling-delay = <1000>;
2110
2111                         thermal-sensors = <&tsens1 10>;
2112
2113                         trips {
2114                                 modem3_alert0: trip-point0 {
2115                                         temperature = <90000>;
2116                                         hysteresis = <2000>;
2117                                         type = "hot";
2118                                 };
2119                         };
2120                 };
2121
2122                 modem4-thermal-top {
2123                         polling-delay-passive = <250>;
2124                         polling-delay = <1000>;
2125
2126                         thermal-sensors = <&tsens1 11>;
2127
2128                         trips {
2129                                 modem4_alert0: trip-point0 {
2130                                         temperature = <90000>;
2131                                         hysteresis = <2000>;
2132                                         type = "hot";
2133                                 };
2134                         };
2135                 };
2136
2137                 camera-thermal-top {
2138                         polling-delay-passive = <250>;
2139                         polling-delay = <1000>;
2140
2141                         thermal-sensors = <&tsens1 12>;
2142
2143                         trips {
2144                                 camera1_alert0: trip-point0 {
2145                                         temperature = <90000>;
2146                                         hysteresis = <2000>;
2147                                         type = "hot";
2148                                 };
2149                         };
2150                 };
2151
2152                 camera-thermal-bottom {
2153                         polling-delay-passive = <250>;
2154                         polling-delay = <1000>;
2155
2156                         thermal-sensors = <&tsens1 13>;
2157
2158                         trips {
2159                                 camera2_alert0: trip-point0 {
2160                                         temperature = <90000>;
2161                                         hysteresis = <2000>;
2162                                         type = "hot";
2163                                 };
2164                         };
2165                 };
2166         };
2167
2168         timer {
2169                 compatible = "arm,armv8-timer";
2170                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2171                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2172                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2173                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2174         };
2175 };