arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  12 #include <dt-bindings/interconnect/qcom,sm8250.h>
  13 #include <dt-bindings/mailbox/qcom-ipcc.h>
  14 #include <dt-bindings/power/qcom-aoss-qmp.h>
  15 #include <dt-bindings/power/qcom-rpmpd.h>
  16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 i2c6 = &i2c6;
  33                 i2c7 = &i2c7;
  34                 i2c8 = &i2c8;
  35                 i2c9 = &i2c9;
  36                 i2c10 = &i2c10;
  37                 i2c11 = &i2c11;
  38                 i2c12 = &i2c12;
  39                 i2c13 = &i2c13;
  40                 i2c14 = &i2c14;
  41                 i2c15 = &i2c15;
  42                 i2c16 = &i2c16;
  43                 i2c17 = &i2c17;
  44                 i2c18 = &i2c18;
  45                 i2c19 = &i2c19;
  46                 spi0 = &spi0;
  47                 spi1 = &spi1;
  48                 spi2 = &spi2;
  49                 spi3 = &spi3;
  50                 spi4 = &spi4;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi7 = &spi7;
  54                 spi8 = &spi8;
  55                 spi9 = &spi9;
  56                 spi10 = &spi10;
  57                 spi11 = &spi11;
  58                 spi12 = &spi12;
  59                 spi13 = &spi13;
  60                 spi14 = &spi14;
  61                 spi15 = &spi15;
  62                 spi16 = &spi16;
  63                 spi17 = &spi17;
  64                 spi18 = &spi18;
  65                 spi19 = &spi19;
  66         };
  67
  68         chosen { };
  69
  70         clocks {
  71                 xo_board: xo-board {
  72                         compatible = "fixed-clock";
  73                         #clock-cells = <0>;
  74                         clock-frequency = <38400000>;
  75                         clock-output-names = "xo_board";
  76                 };
  77
  78                 sleep_clk: sleep-clk {
  79                         compatible = "fixed-clock";
  80                         clock-frequency = <32768>;
  81                         #clock-cells = <0>;
  82                 };
  83         };
  84
  85         cpus {
  86                 #address-cells = <2>;
  87                 #size-cells = <0>;
  88
  89                 CPU0: cpu@0 {
  90                         device_type = "cpu";
  91                         compatible = "qcom,kryo485";
  92                         reg = <0x0 0x0>;
  93                         enable-method = "psci";
  94                         next-level-cache = <&L2_0>;
  95                         qcom,freq-domain = <&cpufreq_hw 0>;
  96                         #cooling-cells = <2>;
  97                         L2_0: l2-cache {
  98                                 compatible = "cache";
  99                                 next-level-cache = <&L3_0>;
 100                                 L3_0: l3-cache {
 101                                         compatible = "cache";
 102                                 };
 103                         };
 104                 };
 105
 106                 CPU1: cpu@100 {
 107                         device_type = "cpu";
 108                         compatible = "qcom,kryo485";
 109                         reg = <0x0 0x100>;
 110                         enable-method = "psci";
 111                         next-level-cache = <&L2_100>;
 112                         qcom,freq-domain = <&cpufreq_hw 0>;
 113                         #cooling-cells = <2>;
 114                         L2_100: l2-cache {
 115                                 compatible = "cache";
 116                                 next-level-cache = <&L3_0>;
 117                         };
 118                 };
 119
 120                 CPU2: cpu@200 {
 121                         device_type = "cpu";
 122                         compatible = "qcom,kryo485";
 123                         reg = <0x0 0x200>;
 124                         enable-method = "psci";
 125                         next-level-cache = <&L2_200>;
 126                         qcom,freq-domain = <&cpufreq_hw 0>;
 127                         #cooling-cells = <2>;
 128                         L2_200: l2-cache {
 129                                 compatible = "cache";
 130                                 next-level-cache = <&L3_0>;
 131                         };
 132                 };
 133
 134                 CPU3: cpu@300 {
 135                         device_type = "cpu";
 136                         compatible = "qcom,kryo485";
 137                         reg = <0x0 0x300>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&L2_300>;
 140                         qcom,freq-domain = <&cpufreq_hw 0>;
 141                         #cooling-cells = <2>;
 142                         L2_300: l2-cache {
 143                                 compatible = "cache";
 144                                 next-level-cache = <&L3_0>;
 145                         };
 146                 };
 147
 148                 CPU4: cpu@400 {
 149                         device_type = "cpu";
 150                         compatible = "qcom,kryo485";
 151                         reg = <0x0 0x400>;
 152                         enable-method = "psci";
 153                         next-level-cache = <&L2_400>;
 154                         qcom,freq-domain = <&cpufreq_hw 1>;
 155                         #cooling-cells = <2>;
 156                         L2_400: l2-cache {
 157                                 compatible = "cache";
 158                                 next-level-cache = <&L3_0>;
 159                         };
 160                 };
 161
 162                 CPU5: cpu@500 {
 163                         device_type = "cpu";
 164                         compatible = "qcom,kryo485";
 165                         reg = <0x0 0x500>;
 166                         enable-method = "psci";
 167                         next-level-cache = <&L2_500>;
 168                         qcom,freq-domain = <&cpufreq_hw 1>;
 169                         #cooling-cells = <2>;
 170                         L2_500: l2-cache {
 171                                 compatible = "cache";
 172                                 next-level-cache = <&L3_0>;
 173                         };
 174
 175                 };
 176
 177                 CPU6: cpu@600 {
 178                         device_type = "cpu";
 179                         compatible = "qcom,kryo485";
 180                         reg = <0x0 0x600>;
 181                         enable-method = "psci";
 182                         next-level-cache = <&L2_600>;
 183                         qcom,freq-domain = <&cpufreq_hw 1>;
 184                         #cooling-cells = <2>;
 185                         L2_600: l2-cache {
 186                                 compatible = "cache";
 187                                 next-level-cache = <&L3_0>;
 188                         };
 189                 };
 190
 191                 CPU7: cpu@700 {
 192                         device_type = "cpu";
 193                         compatible = "qcom,kryo485";
 194                         reg = <0x0 0x700>;
 195                         enable-method = "psci";
 196                         next-level-cache = <&L2_700>;
 197                         qcom,freq-domain = <&cpufreq_hw 2>;
 198                         #cooling-cells = <2>;
 199                         L2_700: l2-cache {
 200                                 compatible = "cache";
 201                                 next-level-cache = <&L3_0>;
 202                         };
 203                 };
 204         };
 205
 206         firmware {
 207                 scm: scm {
 208                         compatible = "qcom,scm";
 209                         #reset-cells = <1>;
 210                 };
 211         };
 212
 213         memory@80000000 {
 214                 device_type = "memory";
 215                 /* We expect the bootloader to fill in the size */
 216                 reg = <0x0 0x80000000 0x0 0x0>;
 217         };
 218
 219         mmcx_reg: mmcx-reg {
 220                 compatible = "regulator-fixed-domain";
 221                 power-domains = <&rpmhpd SM8250_MMCX>;
 222                 required-opps = <&rpmhpd_opp_low_svs>;
 223                 regulator-name = "MMCX";
 224         };
 225
 226         pmu {
 227                 compatible = "arm,armv8-pmuv3";
 228                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 229         };
 230
 231         psci {
 232                 compatible = "arm,psci-1.0";
 233                 method = "smc";
 234         };
 235
 236         reserved-memory {
 237                 #address-cells = <2>;
 238                 #size-cells = <2>;
 239                 ranges;
 240
 241                 hyp_mem: memory@80000000 {
 242                         reg = <0x0 0x80000000 0x0 0x600000>;
 243                         no-map;
 244                 };
 245
 246                 xbl_aop_mem: memory@80700000 {
 247                         reg = <0x0 0x80700000 0x0 0x160000>;
 248                         no-map;
 249                 };
 250
 251                 cmd_db: memory@80860000 {
 252                         compatible = "qcom,cmd-db";
 253                         reg = <0x0 0x80860000 0x0 0x20000>;
 254                         no-map;
 255                 };
 256
 257                 smem_mem: memory@80900000 {
 258                         reg = <0x0 0x80900000 0x0 0x200000>;
 259                         no-map;
 260                 };
 261
 262                 removed_mem: memory@80b00000 {
 263                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 264                         no-map;
 265                 };
 266
 267                 camera_mem: memory@86200000 {
 268                         reg = <0x0 0x86200000 0x0 0x500000>;
 269                         no-map;
 270                 };
 271
 272                 wlan_mem: memory@86700000 {
 273                         reg = <0x0 0x86700000 0x0 0x100000>;
 274                         no-map;
 275                 };
 276
 277                 ipa_fw_mem: memory@86800000 {
 278                         reg = <0x0 0x86800000 0x0 0x10000>;
 279                         no-map;
 280                 };
 281
 282                 ipa_gsi_mem: memory@86810000 {
 283                         reg = <0x0 0x86810000 0x0 0xa000>;
 284                         no-map;
 285                 };
 286
 287                 gpu_mem: memory@8681a000 {
 288                         reg = <0x0 0x8681a000 0x0 0x2000>;
 289                         no-map;
 290                 };
 291
 292                 npu_mem: memory@86900000 {
 293                         reg = <0x0 0x86900000 0x0 0x500000>;
 294                         no-map;
 295                 };
 296
 297                 video_mem: memory@86e00000 {
 298                         reg = <0x0 0x86e00000 0x0 0x500000>;
 299                         no-map;
 300                 };
 301
 302                 cvp_mem: memory@87300000 {
 303                         reg = <0x0 0x87300000 0x0 0x500000>;
 304                         no-map;
 305                 };
 306
 307                 cdsp_mem: memory@87800000 {
 308                         reg = <0x0 0x87800000 0x0 0x1400000>;
 309                         no-map;
 310                 };
 311
 312                 slpi_mem: memory@88c00000 {
 313                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 314                         no-map;
 315                 };
 316
 317                 adsp_mem: memory@8a100000 {
 318                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 319                         no-map;
 320                 };
 321
 322                 spss_mem: memory@8be00000 {
 323                         reg = <0x0 0x8be00000 0x0 0x100000>;
 324                         no-map;
 325                 };
 326
 327                 cdsp_secure_heap: memory@8bf00000 {
 328                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 329                         no-map;
 330                 };
 331         };
 332
 333         smem: qcom,smem {
 334                 compatible = "qcom,smem";
 335                 memory-region = <&smem_mem>;
 336                 hwlocks = <&tcsr_mutex 3>;
 337         };
 338
 339         smp2p-adsp {
 340                 compatible = "qcom,smp2p";
 341                 qcom,smem = <443>, <429>;
 342                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 343                                              IPCC_MPROC_SIGNAL_SMP2P
 344                                              IRQ_TYPE_EDGE_RISING>;
 345                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 346                                 IPCC_MPROC_SIGNAL_SMP2P>;
 347
 348                 qcom,local-pid = <0>;
 349                 qcom,remote-pid = <2>;
 350
 351                 smp2p_adsp_out: master-kernel {
 352                         qcom,entry-name = "master-kernel";
 353                         #qcom,smem-state-cells = <1>;
 354                 };
 355
 356                 smp2p_adsp_in: slave-kernel {
 357                         qcom,entry-name = "slave-kernel";
 358                         interrupt-controller;
 359                         #interrupt-cells = <2>;
 360                 };
 361         };
 362
 363         smp2p-cdsp {
 364                 compatible = "qcom,smp2p";
 365                 qcom,smem = <94>, <432>;
 366                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 367                                              IPCC_MPROC_SIGNAL_SMP2P
 368                                              IRQ_TYPE_EDGE_RISING>;
 369                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 370                                 IPCC_MPROC_SIGNAL_SMP2P>;
 371
 372                 qcom,local-pid = <0>;
 373                 qcom,remote-pid = <5>;
 374
 375                 smp2p_cdsp_out: master-kernel {
 376                         qcom,entry-name = "master-kernel";
 377                         #qcom,smem-state-cells = <1>;
 378                 };
 379
 380                 smp2p_cdsp_in: slave-kernel {
 381                         qcom,entry-name = "slave-kernel";
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385         };
 386
 387         smp2p-slpi {
 388                 compatible = "qcom,smp2p";
 389                 qcom,smem = <481>, <430>;
 390                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 391                                              IPCC_MPROC_SIGNAL_SMP2P
 392                                              IRQ_TYPE_EDGE_RISING>;
 393                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 394                                 IPCC_MPROC_SIGNAL_SMP2P>;
 395
 396                 qcom,local-pid = <0>;
 397                 qcom,remote-pid = <3>;
 398
 399                 smp2p_slpi_out: master-kernel {
 400                         qcom,entry-name = "master-kernel";
 401                         #qcom,smem-state-cells = <1>;
 402                 };
 403
 404                 smp2p_slpi_in: slave-kernel {
 405                         qcom,entry-name = "slave-kernel";
 406                         interrupt-controller;
 407                         #interrupt-cells = <2>;
 408                 };
 409         };
 410
 411         soc: soc@0 {
 412                 #address-cells = <2>;
 413                 #size-cells = <2>;
 414                 ranges = <0 0 0 0 0x10 0>;
 415                 dma-ranges = <0 0 0 0 0x10 0>;
 416                 compatible = "simple-bus";
 417
 418                 gcc: clock-controller@100000 {
 419                         compatible = "qcom,gcc-sm8250";
 420                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 421                         #clock-cells = <1>;
 422                         #reset-cells = <1>;
 423                         #power-domain-cells = <1>;
 424                         clock-names = "bi_tcxo",
 425                                       "bi_tcxo_ao",
 426                                       "sleep_clk";
 427                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 428                                  <&rpmhcc RPMH_CXO_CLK_A>,
 429                                  <&sleep_clk>;
 430                 };
 431
 432                 ipcc: mailbox@408000 {
 433                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 434                         reg = <0 0x00408000 0 0x1000>;
 435                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 436                         interrupt-controller;
 437                         #interrupt-cells = <3>;
 438                         #mbox-cells = <2>;
 439                 };
 440
 441                 rng: rng@793000 {
 442                         compatible = "qcom,prng-ee";
 443                         reg = <0 0x00793000 0 0x1000>;
 444                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 445                         clock-names = "core";
 446                 };
 447
 448                 qup_opp_table: qup-opp-table {
 449                         compatible = "operating-points-v2";
 450
 451                         opp-50000000 {
 452                                 opp-hz = /bits/ 64 <50000000>;
 453                                 required-opps = <&rpmhpd_opp_min_svs>;
 454                         };
 455
 456                         opp-75000000 {
 457                                 opp-hz = /bits/ 64 <75000000>;
 458                                 required-opps = <&rpmhpd_opp_low_svs>;
 459                         };
 460
 461                         opp-120000000 {
 462                                 opp-hz = /bits/ 64 <120000000>;
 463                                 required-opps = <&rpmhpd_opp_svs>;
 464                         };
 465                 };
 466
 467                 qupv3_id_2: geniqup@8c0000 {
 468                         compatible = "qcom,geni-se-qup";
 469                         reg = <0x0 0x008c0000 0x0 0x6000>;
 470                         clock-names = "m-ahb", "s-ahb";
 471                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 472                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 473                         #address-cells = <2>;
 474                         #size-cells = <2>;
 475                         iommus = <&apps_smmu 0x63 0x0>;
 476                         ranges;
 477                         status = "disabled";
 478
 479                         i2c14: i2c@880000 {
 480                                 compatible = "qcom,geni-i2c";
 481                                 reg = <0 0x00880000 0 0x4000>;
 482                                 clock-names = "se";
 483                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 484                                 pinctrl-names = "default";
 485                                 pinctrl-0 = <&qup_i2c14_default>;
 486                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 487                                 #address-cells = <1>;
 488                                 #size-cells = <0>;
 489                                 status = "disabled";
 490                         };
 491
 492                         spi14: spi@880000 {
 493                                 compatible = "qcom,geni-spi";
 494                                 reg = <0 0x00880000 0 0x4000>;
 495                                 clock-names = "se";
 496                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 497                                 pinctrl-names = "default";
 498                                 pinctrl-0 = <&qup_spi14_default>;
 499                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 500                                 #address-cells = <1>;
 501                                 #size-cells = <0>;
 502                                 power-domains = <&rpmhpd SM8250_CX>;
 503                                 operating-points-v2 = <&qup_opp_table>;
 504                                 status = "disabled";
 505                         };
 506
 507                         i2c15: i2c@884000 {
 508                                 compatible = "qcom,geni-i2c";
 509                                 reg = <0 0x00884000 0 0x4000>;
 510                                 clock-names = "se";
 511                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 512                                 pinctrl-names = "default";
 513                                 pinctrl-0 = <&qup_i2c15_default>;
 514                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 515                                 #address-cells = <1>;
 516                                 #size-cells = <0>;
 517                                 status = "disabled";
 518                         };
 519
 520                         spi15: spi@884000 {
 521                                 compatible = "qcom,geni-spi";
 522                                 reg = <0 0x00884000 0 0x4000>;
 523                                 clock-names = "se";
 524                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 525                                 pinctrl-names = "default";
 526                                 pinctrl-0 = <&qup_spi15_default>;
 527                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 528                                 #address-cells = <1>;
 529                                 #size-cells = <0>;
 530                                 power-domains = <&rpmhpd SM8250_CX>;
 531                                 operating-points-v2 = <&qup_opp_table>;
 532                                 status = "disabled";
 533                         };
 534
 535                         i2c16: i2c@888000 {
 536                                 compatible = "qcom,geni-i2c";
 537                                 reg = <0 0x00888000 0 0x4000>;
 538                                 clock-names = "se";
 539                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 540                                 pinctrl-names = "default";
 541                                 pinctrl-0 = <&qup_i2c16_default>;
 542                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 543                                 #address-cells = <1>;
 544                                 #size-cells = <0>;
 545                                 status = "disabled";
 546                         };
 547
 548                         spi16: spi@888000 {
 549                                 compatible = "qcom,geni-spi";
 550                                 reg = <0 0x00888000 0 0x4000>;
 551                                 clock-names = "se";
 552                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 553                                 pinctrl-names = "default";
 554                                 pinctrl-0 = <&qup_spi16_default>;
 555                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 556                                 #address-cells = <1>;
 557                                 #size-cells = <0>;
 558                                 power-domains = <&rpmhpd SM8250_CX>;
 559                                 operating-points-v2 = <&qup_opp_table>;
 560                                 status = "disabled";
 561                         };
 562
 563                         i2c17: i2c@88c000 {
 564                                 compatible = "qcom,geni-i2c";
 565                                 reg = <0 0x0088c000 0 0x4000>;
 566                                 clock-names = "se";
 567                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 568                                 pinctrl-names = "default";
 569                                 pinctrl-0 = <&qup_i2c17_default>;
 570                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 571                                 #address-cells = <1>;
 572                                 #size-cells = <0>;
 573                                 status = "disabled";
 574                         };
 575
 576                         spi17: spi@88c000 {
 577                                 compatible = "qcom,geni-spi";
 578                                 reg = <0 0x0088c000 0 0x4000>;
 579                                 clock-names = "se";
 580                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 581                                 pinctrl-names = "default";
 582                                 pinctrl-0 = <&qup_spi17_default>;
 583                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 584                                 #address-cells = <1>;
 585                                 #size-cells = <0>;
 586                                 power-domains = <&rpmhpd SM8250_CX>;
 587                                 operating-points-v2 = <&qup_opp_table>;
 588                                 status = "disabled";
 589                         };
 590
 591                         uart17: serial@88c000 {
 592                                 compatible = "qcom,geni-uart";
 593                                 reg = <0 0x0088c000 0 0x4000>;
 594                                 clock-names = "se";
 595                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 596                                 pinctrl-names = "default";
 597                                 pinctrl-0 = <&qup_uart17_default>;
 598                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 599                                 power-domains = <&rpmhpd SM8250_CX>;
 600                                 operating-points-v2 = <&qup_opp_table>;
 601                                 status = "disabled";
 602                         };
 603
 604                         i2c18: i2c@890000 {
 605                                 compatible = "qcom,geni-i2c";
 606                                 reg = <0 0x00890000 0 0x4000>;
 607                                 clock-names = "se";
 608                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 609                                 pinctrl-names = "default";
 610                                 pinctrl-0 = <&qup_i2c18_default>;
 611                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 612                                 #address-cells = <1>;
 613                                 #size-cells = <0>;
 614                                 status = "disabled";
 615                         };
 616
 617                         spi18: spi@890000 {
 618                                 compatible = "qcom,geni-spi";
 619                                 reg = <0 0x00890000 0 0x4000>;
 620                                 clock-names = "se";
 621                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 622                                 pinctrl-names = "default";
 623                                 pinctrl-0 = <&qup_spi18_default>;
 624                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 625                                 #address-cells = <1>;
 626                                 #size-cells = <0>;
 627                                 power-domains = <&rpmhpd SM8250_CX>;
 628                                 operating-points-v2 = <&qup_opp_table>;
 629                                 status = "disabled";
 630                         };
 631
 632                         uart18: serial@890000 {
 633                                 compatible = "qcom,geni-uart";
 634                                 reg = <0 0x00890000 0 0x4000>;
 635                                 clock-names = "se";
 636                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 637                                 pinctrl-names = "default";
 638                                 pinctrl-0 = <&qup_uart18_default>;
 639                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 640                                 power-domains = <&rpmhpd SM8250_CX>;
 641                                 operating-points-v2 = <&qup_opp_table>;
 642                                 status = "disabled";
 643                         };
 644
 645                         i2c19: i2c@894000 {
 646                                 compatible = "qcom,geni-i2c";
 647                                 reg = <0 0x00894000 0 0x4000>;
 648                                 clock-names = "se";
 649                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 650                                 pinctrl-names = "default";
 651                                 pinctrl-0 = <&qup_i2c19_default>;
 652                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 status = "disabled";
 656                         };
 657
 658                         spi19: spi@894000 {
 659                                 compatible = "qcom,geni-spi";
 660                                 reg = <0 0x00894000 0 0x4000>;
 661                                 clock-names = "se";
 662                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 663                                 pinctrl-names = "default";
 664                                 pinctrl-0 = <&qup_spi19_default>;
 665                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 666                                 #address-cells = <1>;
 667                                 #size-cells = <0>;
 668                                 power-domains = <&rpmhpd SM8250_CX>;
 669                                 operating-points-v2 = <&qup_opp_table>;
 670                                 status = "disabled";
 671                         };
 672                 };
 673
 674                 qupv3_id_0: geniqup@9c0000 {
 675                         compatible = "qcom,geni-se-qup";
 676                         reg = <0x0 0x009c0000 0x0 0x6000>;
 677                         clock-names = "m-ahb", "s-ahb";
 678                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 679                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 680                         #address-cells = <2>;
 681                         #size-cells = <2>;
 682                         iommus = <&apps_smmu 0x5a3 0x0>;
 683                         ranges;
 684                         status = "disabled";
 685
 686                         i2c0: i2c@980000 {
 687                                 compatible = "qcom,geni-i2c";
 688                                 reg = <0 0x00980000 0 0x4000>;
 689                                 clock-names = "se";
 690                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 691                                 pinctrl-names = "default";
 692                                 pinctrl-0 = <&qup_i2c0_default>;
 693                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 694                                 #address-cells = <1>;
 695                                 #size-cells = <0>;
 696                                 status = "disabled";
 697                         };
 698
 699                         spi0: spi@980000 {
 700                                 compatible = "qcom,geni-spi";
 701                                 reg = <0 0x00980000 0 0x4000>;
 702                                 clock-names = "se";
 703                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 704                                 pinctrl-names = "default";
 705                                 pinctrl-0 = <&qup_spi0_default>;
 706                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 707                                 #address-cells = <1>;
 708                                 #size-cells = <0>;
 709                                 power-domains = <&rpmhpd SM8250_CX>;
 710                                 operating-points-v2 = <&qup_opp_table>;
 711                                 status = "disabled";
 712                         };
 713
 714                         i2c1: i2c@984000 {
 715                                 compatible = "qcom,geni-i2c";
 716                                 reg = <0 0x00984000 0 0x4000>;
 717                                 clock-names = "se";
 718                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 719                                 pinctrl-names = "default";
 720                                 pinctrl-0 = <&qup_i2c1_default>;
 721                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 722                                 #address-cells = <1>;
 723                                 #size-cells = <0>;
 724                                 status = "disabled";
 725                         };
 726
 727                         spi1: spi@984000 {
 728                                 compatible = "qcom,geni-spi";
 729                                 reg = <0 0x00984000 0 0x4000>;
 730                                 clock-names = "se";
 731                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 732                                 pinctrl-names = "default";
 733                                 pinctrl-0 = <&qup_spi1_default>;
 734                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 735                                 #address-cells = <1>;
 736                                 #size-cells = <0>;
 737                                 power-domains = <&rpmhpd SM8250_CX>;
 738                                 operating-points-v2 = <&qup_opp_table>;
 739                                 status = "disabled";
 740                         };
 741
 742                         i2c2: i2c@988000 {
 743                                 compatible = "qcom,geni-i2c";
 744                                 reg = <0 0x00988000 0 0x4000>;
 745                                 clock-names = "se";
 746                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 747                                 pinctrl-names = "default";
 748                                 pinctrl-0 = <&qup_i2c2_default>;
 749                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 750                                 #address-cells = <1>;
 751                                 #size-cells = <0>;
 752                                 status = "disabled";
 753                         };
 754
 755                         spi2: spi@988000 {
 756                                 compatible = "qcom,geni-spi";
 757                                 reg = <0 0x00988000 0 0x4000>;
 758                                 clock-names = "se";
 759                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 760                                 pinctrl-names = "default";
 761                                 pinctrl-0 = <&qup_spi2_default>;
 762                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 763                                 #address-cells = <1>;
 764                                 #size-cells = <0>;
 765                                 power-domains = <&rpmhpd SM8250_CX>;
 766                                 operating-points-v2 = <&qup_opp_table>;
 767                                 status = "disabled";
 768                         };
 769
 770                         uart2: serial@988000 {
 771                                 compatible = "qcom,geni-debug-uart";
 772                                 reg = <0 0x00988000 0 0x4000>;
 773                                 clock-names = "se";
 774                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 775                                 pinctrl-names = "default";
 776                                 pinctrl-0 = <&qup_uart2_default>;
 777                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 778                                 power-domains = <&rpmhpd SM8250_CX>;
 779                                 operating-points-v2 = <&qup_opp_table>;
 780                                 status = "disabled";
 781                         };
 782
 783                         i2c3: i2c@98c000 {
 784                                 compatible = "qcom,geni-i2c";
 785                                 reg = <0 0x0098c000 0 0x4000>;
 786                                 clock-names = "se";
 787                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 788                                 pinctrl-names = "default";
 789                                 pinctrl-0 = <&qup_i2c3_default>;
 790                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                                 status = "disabled";
 794                         };
 795
 796                         spi3: spi@98c000 {
 797                                 compatible = "qcom,geni-spi";
 798                                 reg = <0 0x0098c000 0 0x4000>;
 799                                 clock-names = "se";
 800                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 801                                 pinctrl-names = "default";
 802                                 pinctrl-0 = <&qup_spi3_default>;
 803                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806                                 power-domains = <&rpmhpd SM8250_CX>;
 807                                 operating-points-v2 = <&qup_opp_table>;
 808                                 status = "disabled";
 809                         };
 810
 811                         i2c4: i2c@990000 {
 812                                 compatible = "qcom,geni-i2c";
 813                                 reg = <0 0x00990000 0 0x4000>;
 814                                 clock-names = "se";
 815                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 816                                 pinctrl-names = "default";
 817                                 pinctrl-0 = <&qup_i2c4_default>;
 818                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 819                                 #address-cells = <1>;
 820                                 #size-cells = <0>;
 821                                 status = "disabled";
 822                         };
 823
 824                         spi4: spi@990000 {
 825                                 compatible = "qcom,geni-spi";
 826                                 reg = <0 0x00990000 0 0x4000>;
 827                                 clock-names = "se";
 828                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 829                                 pinctrl-names = "default";
 830                                 pinctrl-0 = <&qup_spi4_default>;
 831                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 832                                 #address-cells = <1>;
 833                                 #size-cells = <0>;
 834                                 power-domains = <&rpmhpd SM8250_CX>;
 835                                 operating-points-v2 = <&qup_opp_table>;
 836                                 status = "disabled";
 837                         };
 838
 839                         i2c5: i2c@994000 {
 840                                 compatible = "qcom,geni-i2c";
 841                                 reg = <0 0x00994000 0 0x4000>;
 842                                 clock-names = "se";
 843                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 844                                 pinctrl-names = "default";
 845                                 pinctrl-0 = <&qup_i2c5_default>;
 846                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 847                                 #address-cells = <1>;
 848                                 #size-cells = <0>;
 849                                 status = "disabled";
 850                         };
 851
 852                         spi5: spi@994000 {
 853                                 compatible = "qcom,geni-spi";
 854                                 reg = <0 0x00994000 0 0x4000>;
 855                                 clock-names = "se";
 856                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 857                                 pinctrl-names = "default";
 858                                 pinctrl-0 = <&qup_spi5_default>;
 859                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 860                                 #address-cells = <1>;
 861                                 #size-cells = <0>;
 862                                 power-domains = <&rpmhpd SM8250_CX>;
 863                                 operating-points-v2 = <&qup_opp_table>;
 864                                 status = "disabled";
 865                         };
 866
 867                         i2c6: i2c@998000 {
 868                                 compatible = "qcom,geni-i2c";
 869                                 reg = <0 0x00998000 0 0x4000>;
 870                                 clock-names = "se";
 871                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 872                                 pinctrl-names = "default";
 873                                 pinctrl-0 = <&qup_i2c6_default>;
 874                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 875                                 #address-cells = <1>;
 876                                 #size-cells = <0>;
 877                                 status = "disabled";
 878                         };
 879
 880                         spi6: spi@998000 {
 881                                 compatible = "qcom,geni-spi";
 882                                 reg = <0 0x00998000 0 0x4000>;
 883                                 clock-names = "se";
 884                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 885                                 pinctrl-names = "default";
 886                                 pinctrl-0 = <&qup_spi6_default>;
 887                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 888                                 #address-cells = <1>;
 889                                 #size-cells = <0>;
 890                                 power-domains = <&rpmhpd SM8250_CX>;
 891                                 operating-points-v2 = <&qup_opp_table>;
 892                                 status = "disabled";
 893                         };
 894
 895                         uart6: serial@998000 {
 896                                 compatible = "qcom,geni-uart";
 897                                 reg = <0 0x00998000 0 0x4000>;
 898                                 clock-names = "se";
 899                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 900                                 pinctrl-names = "default";
 901                                 pinctrl-0 = <&qup_uart6_default>;
 902                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 903                                 power-domains = <&rpmhpd SM8250_CX>;
 904                                 operating-points-v2 = <&qup_opp_table>;
 905                                 status = "disabled";
 906                         };
 907
 908                         i2c7: i2c@99c000 {
 909                                 compatible = "qcom,geni-i2c";
 910                                 reg = <0 0x0099c000 0 0x4000>;
 911                                 clock-names = "se";
 912                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 913                                 pinctrl-names = "default";
 914                                 pinctrl-0 = <&qup_i2c7_default>;
 915                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 916                                 #address-cells = <1>;
 917                                 #size-cells = <0>;
 918                                 status = "disabled";
 919                         };
 920
 921                         spi7: spi@99c000 {
 922                                 compatible = "qcom,geni-spi";
 923                                 reg = <0 0x0099c000 0 0x4000>;
 924                                 clock-names = "se";
 925                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 926                                 pinctrl-names = "default";
 927                                 pinctrl-0 = <&qup_spi7_default>;
 928                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 power-domains = <&rpmhpd SM8250_CX>;
 932                                 operating-points-v2 = <&qup_opp_table>;
 933                                 status = "disabled";
 934                         };
 935                 };
 936
 937                 qupv3_id_1: geniqup@ac0000 {
 938                         compatible = "qcom,geni-se-qup";
 939                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 940                         clock-names = "m-ahb", "s-ahb";
 941                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 942                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 943                         #address-cells = <2>;
 944                         #size-cells = <2>;
 945                         iommus = <&apps_smmu 0x43 0x0>;
 946                         ranges;
 947                         status = "disabled";
 948
 949                         i2c8: i2c@a80000 {
 950                                 compatible = "qcom,geni-i2c";
 951                                 reg = <0 0x00a80000 0 0x4000>;
 952                                 clock-names = "se";
 953                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 954                                 pinctrl-names = "default";
 955                                 pinctrl-0 = <&qup_i2c8_default>;
 956                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 957                                 #address-cells = <1>;
 958                                 #size-cells = <0>;
 959                                 status = "disabled";
 960                         };
 961
 962                         spi8: spi@a80000 {
 963                                 compatible = "qcom,geni-spi";
 964                                 reg = <0 0x00a80000 0 0x4000>;
 965                                 clock-names = "se";
 966                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 967                                 pinctrl-names = "default";
 968                                 pinctrl-0 = <&qup_spi8_default>;
 969                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 970                                 #address-cells = <1>;
 971                                 #size-cells = <0>;
 972                                 power-domains = <&rpmhpd SM8250_CX>;
 973                                 operating-points-v2 = <&qup_opp_table>;
 974                                 status = "disabled";
 975                         };
 976
 977                         i2c9: i2c@a84000 {
 978                                 compatible = "qcom,geni-i2c";
 979                                 reg = <0 0x00a84000 0 0x4000>;
 980                                 clock-names = "se";
 981                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 982                                 pinctrl-names = "default";
 983                                 pinctrl-0 = <&qup_i2c9_default>;
 984                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 status = "disabled";
 988                         };
 989
 990                         spi9: spi@a84000 {
 991                                 compatible = "qcom,geni-spi";
 992                                 reg = <0 0x00a84000 0 0x4000>;
 993                                 clock-names = "se";
 994                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 995                                 pinctrl-names = "default";
 996                                 pinctrl-0 = <&qup_spi9_default>;
 997                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 power-domains = <&rpmhpd SM8250_CX>;
1001                                 operating-points-v2 = <&qup_opp_table>;
1002                                 status = "disabled";
1003                         };
1004
1005                         i2c10: i2c@a88000 {
1006                                 compatible = "qcom,geni-i2c";
1007                                 reg = <0 0x00a88000 0 0x4000>;
1008                                 clock-names = "se";
1009                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1010                                 pinctrl-names = "default";
1011                                 pinctrl-0 = <&qup_i2c10_default>;
1012                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015                                 status = "disabled";
1016                         };
1017
1018                         spi10: spi@a88000 {
1019                                 compatible = "qcom,geni-spi";
1020                                 reg = <0 0x00a88000 0 0x4000>;
1021                                 clock-names = "se";
1022                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1023                                 pinctrl-names = "default";
1024                                 pinctrl-0 = <&qup_spi10_default>;
1025                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1026                                 #address-cells = <1>;
1027                                 #size-cells = <0>;
1028                                 power-domains = <&rpmhpd SM8250_CX>;
1029                                 operating-points-v2 = <&qup_opp_table>;
1030                                 status = "disabled";
1031                         };
1032
1033                         i2c11: i2c@a8c000 {
1034                                 compatible = "qcom,geni-i2c";
1035                                 reg = <0 0x00a8c000 0 0x4000>;
1036                                 clock-names = "se";
1037                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1038                                 pinctrl-names = "default";
1039                                 pinctrl-0 = <&qup_i2c11_default>;
1040                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1041                                 #address-cells = <1>;
1042                                 #size-cells = <0>;
1043                                 status = "disabled";
1044                         };
1045
1046                         spi11: spi@a8c000 {
1047                                 compatible = "qcom,geni-spi";
1048                                 reg = <0 0x00a8c000 0 0x4000>;
1049                                 clock-names = "se";
1050                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1051                                 pinctrl-names = "default";
1052                                 pinctrl-0 = <&qup_spi11_default>;
1053                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1054                                 #address-cells = <1>;
1055                                 #size-cells = <0>;
1056                                 power-domains = <&rpmhpd SM8250_CX>;
1057                                 operating-points-v2 = <&qup_opp_table>;
1058                                 status = "disabled";
1059                         };
1060
1061                         i2c12: i2c@a90000 {
1062                                 compatible = "qcom,geni-i2c";
1063                                 reg = <0 0x00a90000 0 0x4000>;
1064                                 clock-names = "se";
1065                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1066                                 pinctrl-names = "default";
1067                                 pinctrl-0 = <&qup_i2c12_default>;
1068                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 status = "disabled";
1072                         };
1073
1074                         spi12: spi@a90000 {
1075                                 compatible = "qcom,geni-spi";
1076                                 reg = <0 0x00a90000 0 0x4000>;
1077                                 clock-names = "se";
1078                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1079                                 pinctrl-names = "default";
1080                                 pinctrl-0 = <&qup_spi12_default>;
1081                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1082                                 #address-cells = <1>;
1083                                 #size-cells = <0>;
1084                                 power-domains = <&rpmhpd SM8250_CX>;
1085                                 operating-points-v2 = <&qup_opp_table>;
1086                                 status = "disabled";
1087                         };
1088
1089                         uart12: serial@a90000 {
1090                                 compatible = "qcom,geni-debug-uart";
1091                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1092                                 clock-names = "se";
1093                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1094                                 pinctrl-names = "default";
1095                                 pinctrl-0 = <&qup_uart12_default>;
1096                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1097                                 power-domains = <&rpmhpd SM8250_CX>;
1098                                 operating-points-v2 = <&qup_opp_table>;
1099                                 status = "disabled";
1100                         };
1101
1102                         i2c13: i2c@a94000 {
1103                                 compatible = "qcom,geni-i2c";
1104                                 reg = <0 0x00a94000 0 0x4000>;
1105                                 clock-names = "se";
1106                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1107                                 pinctrl-names = "default";
1108                                 pinctrl-0 = <&qup_i2c13_default>;
1109                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1110                                 #address-cells = <1>;
1111                                 #size-cells = <0>;
1112                                 status = "disabled";
1113                         };
1114
1115                         spi13: spi@a94000 {
1116                                 compatible = "qcom,geni-spi";
1117                                 reg = <0 0x00a94000 0 0x4000>;
1118                                 clock-names = "se";
1119                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&qup_spi13_default>;
1122                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 power-domains = <&rpmhpd SM8250_CX>;
1126                                 operating-points-v2 = <&qup_opp_table>;
1127                                 status = "disabled";
1128                         };
1129                 };
1130
1131                 config_noc: interconnect@1500000 {
1132                         compatible = "qcom,sm8250-config-noc";
1133                         reg = <0 0x01500000 0 0xa580>;
1134                         #interconnect-cells = <1>;
1135                         qcom,bcm-voters = <&apps_bcm_voter>;
1136                 };
1137
1138                 system_noc: interconnect@1620000 {
1139                         compatible = "qcom,sm8250-system-noc";
1140                         reg = <0 0x01620000 0 0x1c200>;
1141                         #interconnect-cells = <1>;
1142                         qcom,bcm-voters = <&apps_bcm_voter>;
1143                 };
1144
1145                 mc_virt: interconnect@163d000 {
1146                         compatible = "qcom,sm8250-mc-virt";
1147                         reg = <0 0x0163d000 0 0x1000>;
1148                         #interconnect-cells = <1>;
1149                         qcom,bcm-voters = <&apps_bcm_voter>;
1150                 };
1151
1152                 aggre1_noc: interconnect@16e0000 {
1153                         compatible = "qcom,sm8250-aggre1-noc";
1154                         reg = <0 0x016e0000 0 0x1f180>;
1155                         #interconnect-cells = <1>;
1156                         qcom,bcm-voters = <&apps_bcm_voter>;
1157                 };
1158
1159                 aggre2_noc: interconnect@1700000 {
1160                         compatible = "qcom,sm8250-aggre2-noc";
1161                         reg = <0 0x01700000 0 0x33000>;
1162                         #interconnect-cells = <1>;
1163                         qcom,bcm-voters = <&apps_bcm_voter>;
1164                 };
1165
1166                 compute_noc: interconnect@1733000 {
1167                         compatible = "qcom,sm8250-compute-noc";
1168                         reg = <0 0x01733000 0 0xa180>;
1169                         #interconnect-cells = <1>;
1170                         qcom,bcm-voters = <&apps_bcm_voter>;
1171                 };
1172
1173                 mmss_noc: interconnect@1740000 {
1174                         compatible = "qcom,sm8250-mmss-noc";
1175                         reg = <0 0x01740000 0 0x1f080>;
1176                         #interconnect-cells = <1>;
1177                         qcom,bcm-voters = <&apps_bcm_voter>;
1178                 };
1179
1180                 ufs_mem_hc: ufshc@1d84000 {
1181                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1182                                      "jedec,ufs-2.0";
1183                         reg = <0 0x01d84000 0 0x3000>;
1184                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1185                         phys = <&ufs_mem_phy_lanes>;
1186                         phy-names = "ufsphy";
1187                         lanes-per-direction = <2>;
1188                         #reset-cells = <1>;
1189                         resets = <&gcc GCC_UFS_PHY_BCR>;
1190                         reset-names = "rst";
1191
1192                         power-domains = <&gcc UFS_PHY_GDSC>;
1193
1194                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1195
1196                         clock-names =
1197                                 "core_clk",
1198                                 "bus_aggr_clk",
1199                                 "iface_clk",
1200                                 "core_clk_unipro",
1201                                 "ref_clk",
1202                                 "tx_lane0_sync_clk",
1203                                 "rx_lane0_sync_clk",
1204                                 "rx_lane1_sync_clk";
1205                         clocks =
1206                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1207                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1208                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1209                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1210                                 <&rpmhcc RPMH_CXO_CLK>,
1211                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1212                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1213                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1214                         freq-table-hz =
1215                                 <37500000 300000000>,
1216                                 <0 0>,
1217                                 <0 0>,
1218                                 <37500000 300000000>,
1219                                 <0 0>,
1220                                 <0 0>,
1221                                 <0 0>,
1222                                 <0 0>;
1223
1224                         status = "disabled";
1225                 };
1226
1227                 ufs_mem_phy: phy@1d87000 {
1228                         compatible = "qcom,sm8250-qmp-ufs-phy";
1229                         reg = <0 0x01d87000 0 0x1c0>;
1230                         #address-cells = <2>;
1231                         #size-cells = <2>;
1232                         ranges;
1233                         clock-names = "ref",
1234                                       "ref_aux";
1235                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1236                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1237
1238                         resets = <&ufs_mem_hc 0>;
1239                         reset-names = "ufsphy";
1240                         status = "disabled";
1241
1242                         ufs_mem_phy_lanes: lanes@1d87400 {
1243                                 reg = <0 0x01d87400 0 0x108>,
1244                                       <0 0x01d87600 0 0x1e0>,
1245                                       <0 0x01d87c00 0 0x1dc>,
1246                                       <0 0x01d87800 0 0x108>,
1247                                       <0 0x01d87a00 0 0x1e0>;
1248                                 #phy-cells = <0>;
1249                         };
1250                 };
1251
1252                 ipa_virt: interconnect@1e00000 {
1253                         compatible = "qcom,sm8250-ipa-virt";
1254                         reg = <0 0x01e00000 0 0x1000>;
1255                         #interconnect-cells = <1>;
1256                         qcom,bcm-voters = <&apps_bcm_voter>;
1257                 };
1258
1259                 tcsr_mutex: hwlock@1f40000 {
1260                         compatible = "qcom,tcsr-mutex";
1261                         reg = <0x0 0x01f40000 0x0 0x40000>;
1262                         #hwlock-cells = <1>;
1263                 };
1264
1265                 gpu: gpu@3d00000 {
1266                         compatible = "qcom,adreno-650.2",
1267                                      "qcom,adreno";
1268                         #stream-id-cells = <16>;
1269
1270                         reg = <0 0x03d00000 0 0x40000>;
1271                         reg-names = "kgsl_3d0_reg_memory";
1272
1273                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1274
1275                         iommus = <&adreno_smmu 0 0x401>;
1276
1277                         operating-points-v2 = <&gpu_opp_table>;
1278
1279                         qcom,gmu = <&gmu>;
1280
1281                         zap-shader {
1282                                 memory-region = <&gpu_mem>;
1283                         };
1284
1285                         /* note: downstream checks gpu binning for 670 Mhz */
1286                         gpu_opp_table: opp-table {
1287                                 compatible = "operating-points-v2";
1288
1289                                 opp-670000000 {
1290                                         opp-hz = /bits/ 64 <670000000>;
1291                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1292                                 };
1293
1294                                 opp-587000000 {
1295                                         opp-hz = /bits/ 64 <587000000>;
1296                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1297                                 };
1298
1299                                 opp-525000000 {
1300                                         opp-hz = /bits/ 64 <525000000>;
1301                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1302                                 };
1303
1304                                 opp-490000000 {
1305                                         opp-hz = /bits/ 64 <490000000>;
1306                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1307                                 };
1308
1309                                 opp-441600000 {
1310                                         opp-hz = /bits/ 64 <441600000>;
1311                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1312                                 };
1313
1314                                 opp-400000000 {
1315                                         opp-hz = /bits/ 64 <400000000>;
1316                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1317                                 };
1318
1319                                 opp-305000000 {
1320                                         opp-hz = /bits/ 64 <305000000>;
1321                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1322                                 };
1323                         };
1324                 };
1325
1326                 gmu: gmu@3d6a000 {
1327                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1328
1329                         reg = <0 0x03d6a000 0 0x30000>,
1330                               <0 0x3de0000 0 0x10000>,
1331                               <0 0xb290000 0 0x10000>,
1332                               <0 0xb490000 0 0x10000>;
1333                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1334
1335                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1336                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1337                         interrupt-names = "hfi", "gmu";
1338
1339                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1340                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1341                                  <&gpucc GPU_CC_CXO_CLK>,
1342                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1343                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1344                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1345
1346                         power-domains = <&gpucc GPU_CX_GDSC>,
1347                                         <&gpucc GPU_GX_GDSC>;
1348                         power-domain-names = "cx", "gx";
1349
1350                         iommus = <&adreno_smmu 5 0x400>;
1351
1352                         operating-points-v2 = <&gmu_opp_table>;
1353
1354                         gmu_opp_table: opp-table {
1355                                 compatible = "operating-points-v2";
1356
1357                                 opp-200000000 {
1358                                         opp-hz = /bits/ 64 <200000000>;
1359                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1360                                 };
1361                         };
1362                 };
1363
1364                 gpucc: clock-controller@3d90000 {
1365                         compatible = "qcom,sm8250-gpucc";
1366                         reg = <0 0x03d90000 0 0x9000>;
1367                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1368                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1369                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1370                         clock-names = "bi_tcxo",
1371                                       "gcc_gpu_gpll0_clk_src",
1372                                       "gcc_gpu_gpll0_div_clk_src";
1373                         #clock-cells = <1>;
1374                         #reset-cells = <1>;
1375                         #power-domain-cells = <1>;
1376                 };
1377
1378                 adreno_smmu: iommu@3da0000 {
1379                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1380                         reg = <0 0x03da0000 0 0x10000>;
1381                         #iommu-cells = <2>;
1382                         #global-interrupts = <2>;
1383                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1384                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1385                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1386                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1387                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1388                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1389                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1390                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1391                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1392                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1393                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1394                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1395                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1396                         clock-names = "ahb", "bus", "iface";
1397
1398                         power-domains = <&gpucc GPU_CX_GDSC>;
1399                 };
1400
1401                 slpi: remoteproc@5c00000 {
1402                         compatible = "qcom,sm8250-slpi-pas";
1403                         reg = <0 0x05c00000 0 0x4000>;
1404
1405                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1406                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1407                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1408                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1409                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1410                         interrupt-names = "wdog", "fatal", "ready",
1411                                           "handover", "stop-ack";
1412
1413                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1414                         clock-names = "xo";
1415
1416                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1417                                         <&rpmhpd SM8250_LCX>,
1418                                         <&rpmhpd SM8250_LMX>;
1419                         power-domain-names = "load_state", "lcx", "lmx";
1420
1421                         memory-region = <&slpi_mem>;
1422
1423                         qcom,smem-states = <&smp2p_slpi_out 0>;
1424                         qcom,smem-state-names = "stop";
1425
1426                         status = "disabled";
1427
1428                         glink-edge {
1429                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1430                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1431                                                              IRQ_TYPE_EDGE_RISING>;
1432                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1433                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1434
1435                                 label = "slpi";
1436                                 qcom,remote-pid = <3>;
1437
1438                                 fastrpc {
1439                                         compatible = "qcom,fastrpc";
1440                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1441                                         label = "sdsp";
1442                                         #address-cells = <1>;
1443                                         #size-cells = <0>;
1444
1445                                         compute-cb@1 {
1446                                                 compatible = "qcom,fastrpc-compute-cb";
1447                                                 reg = <1>;
1448                                                 iommus = <&apps_smmu 0x0541 0x0>;
1449                                         };
1450
1451                                         compute-cb@2 {
1452                                                 compatible = "qcom,fastrpc-compute-cb";
1453                                                 reg = <2>;
1454                                                 iommus = <&apps_smmu 0x0542 0x0>;
1455                                         };
1456
1457                                         compute-cb@3 {
1458                                                 compatible = "qcom,fastrpc-compute-cb";
1459                                                 reg = <3>;
1460                                                 iommus = <&apps_smmu 0x0543 0x0>;
1461                                                 /* note: shared-cb = <4> in downstream */
1462                                         };
1463                                 };
1464                         };
1465                 };
1466
1467                 cdsp: remoteproc@8300000 {
1468                         compatible = "qcom,sm8250-cdsp-pas";
1469                         reg = <0 0x08300000 0 0x10000>;
1470
1471                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1472                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1473                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1474                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1475                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1476                         interrupt-names = "wdog", "fatal", "ready",
1477                                           "handover", "stop-ack";
1478
1479                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1480                         clock-names = "xo";
1481
1482                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1483                                         <&rpmhpd SM8250_CX>;
1484                         power-domain-names = "load_state", "cx";
1485
1486                         memory-region = <&cdsp_mem>;
1487
1488                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1489                         qcom,smem-state-names = "stop";
1490
1491                         status = "disabled";
1492
1493                         glink-edge {
1494                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1495                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1496                                                              IRQ_TYPE_EDGE_RISING>;
1497                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1498                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1499
1500                                 label = "cdsp";
1501                                 qcom,remote-pid = <5>;
1502
1503                                 fastrpc {
1504                                         compatible = "qcom,fastrpc";
1505                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1506                                         label = "cdsp";
1507                                         #address-cells = <1>;
1508                                         #size-cells = <0>;
1509
1510                                         compute-cb@1 {
1511                                                 compatible = "qcom,fastrpc-compute-cb";
1512                                                 reg = <1>;
1513                                                 iommus = <&apps_smmu 0x1001 0x0460>;
1514                                         };
1515
1516                                         compute-cb@2 {
1517                                                 compatible = "qcom,fastrpc-compute-cb";
1518                                                 reg = <2>;
1519                                                 iommus = <&apps_smmu 0x1002 0x0460>;
1520                                         };
1521
1522                                         compute-cb@3 {
1523                                                 compatible = "qcom,fastrpc-compute-cb";
1524                                                 reg = <3>;
1525                                                 iommus = <&apps_smmu 0x1003 0x0460>;
1526                                         };
1527
1528                                         compute-cb@4 {
1529                                                 compatible = "qcom,fastrpc-compute-cb";
1530                                                 reg = <4>;
1531                                                 iommus = <&apps_smmu 0x1004 0x0460>;
1532                                         };
1533
1534                                         compute-cb@5 {
1535                                                 compatible = "qcom,fastrpc-compute-cb";
1536                                                 reg = <5>;
1537                                                 iommus = <&apps_smmu 0x1005 0x0460>;
1538                                         };
1539
1540                                         compute-cb@6 {
1541                                                 compatible = "qcom,fastrpc-compute-cb";
1542                                                 reg = <6>;
1543                                                 iommus = <&apps_smmu 0x1006 0x0460>;
1544                                         };
1545
1546                                         compute-cb@7 {
1547                                                 compatible = "qcom,fastrpc-compute-cb";
1548                                                 reg = <7>;
1549                                                 iommus = <&apps_smmu 0x1007 0x0460>;
1550                                         };
1551
1552                                         compute-cb@8 {
1553                                                 compatible = "qcom,fastrpc-compute-cb";
1554                                                 reg = <8>;
1555                                                 iommus = <&apps_smmu 0x1008 0x0460>;
1556                                         };
1557
1558                                         /* note: secure cb9 in downstream */
1559                                 };
1560                         };
1561                 };
1562
1563                 usb_1_hsphy: phy@88e3000 {
1564                         compatible = "qcom,sm8250-usb-hs-phy",
1565                                      "qcom,usb-snps-hs-7nm-phy";
1566                         reg = <0 0x088e3000 0 0x400>;
1567                         status = "disabled";
1568                         #phy-cells = <0>;
1569
1570                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1571                         clock-names = "ref";
1572
1573                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1574                 };
1575
1576                 usb_2_hsphy: phy@88e4000 {
1577                         compatible = "qcom,sm8250-usb-hs-phy",
1578                                      "qcom,usb-snps-hs-7nm-phy";
1579                         reg = <0 0x088e4000 0 0x400>;
1580                         status = "disabled";
1581                         #phy-cells = <0>;
1582
1583                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1584                         clock-names = "ref";
1585
1586                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1587                 };
1588
1589                 usb_1_qmpphy: phy@88e9000 {
1590                         compatible = "qcom,sm8250-qmp-usb3-phy";
1591                         reg = <0 0x088e9000 0 0x200>,
1592                               <0 0x088e8000 0 0x20>;
1593                         reg-names = "reg-base", "dp_com";
1594                         status = "disabled";
1595                         #clock-cells = <1>;
1596                         #address-cells = <2>;
1597                         #size-cells = <2>;
1598                         ranges;
1599
1600                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1601                                  <&rpmhcc RPMH_CXO_CLK>,
1602                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1603                         clock-names = "aux", "ref_clk_src", "com_aux";
1604
1605                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1606                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1607                         reset-names = "phy", "common";
1608
1609                         usb_1_ssphy: lanes@88e9200 {
1610                                 reg = <0 0x088e9200 0 0x200>,
1611                                       <0 0x088e9400 0 0x200>,
1612                                       <0 0x088e9c00 0 0x400>,
1613                                       <0 0x088e9600 0 0x200>,
1614                                       <0 0x088e9800 0 0x200>,
1615                                       <0 0x088e9a00 0 0x100>;
1616                                 #phy-cells = <0>;
1617                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1618                                 clock-names = "pipe0";
1619                                 clock-output-names = "usb3_phy_pipe_clk_src";
1620                         };
1621                 };
1622
1623                 usb_2_qmpphy: phy@88eb000 {
1624                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
1625                         reg = <0 0x088eb000 0 0x200>;
1626                         status = "disabled";
1627                         #clock-cells = <1>;
1628                         #address-cells = <2>;
1629                         #size-cells = <2>;
1630                         ranges;
1631
1632                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1633                                  <&rpmhcc RPMH_CXO_CLK>,
1634                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
1635                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1636                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1637
1638                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1639                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
1640                         reset-names = "phy", "common";
1641
1642                         usb_2_ssphy: lane@88eb200 {
1643                                 reg = <0 0x088eb200 0 0x200>,
1644                                       <0 0x088eb400 0 0x200>,
1645                                       <0 0x088eb800 0 0x800>;
1646                                 #phy-cells = <0>;
1647                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1648                                 clock-names = "pipe0";
1649                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1650                         };
1651                 };
1652
1653                 sdhc_2: sdhci@8804000 {
1654                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
1655                         reg = <0 0x08804000 0 0x1000>;
1656
1657                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1658                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1659                         interrupt-names = "hc_irq", "pwr_irq";
1660
1661                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1662                                  <&gcc GCC_SDCC2_APPS_CLK>,
1663                                  <&xo_board>;
1664                         clock-names = "iface", "core", "xo";
1665                         iommus = <&apps_smmu 0x4a0 0x0>;
1666                         qcom,dll-config = <0x0007642c>;
1667                         qcom,ddr-config = <0x80040868>;
1668                         power-domains = <&rpmhpd SM8250_CX>;
1669                         operating-points-v2 = <&sdhc2_opp_table>;
1670
1671                         status = "disabled";
1672
1673                         sdhc2_opp_table: sdhc2-opp-table {
1674                                 compatible = "operating-points-v2";
1675
1676                                 opp-19200000 {
1677                                         opp-hz = /bits/ 64 <19200000>;
1678                                         required-opps = <&rpmhpd_opp_min_svs>;
1679                                 };
1680
1681                                 opp-50000000 {
1682                                         opp-hz = /bits/ 64 <50000000>;
1683                                         required-opps = <&rpmhpd_opp_low_svs>;
1684                                 };
1685
1686                                 opp-100000000 {
1687                                         opp-hz = /bits/ 64 <100000000>;
1688                                         required-opps = <&rpmhpd_opp_svs>;
1689                                 };
1690
1691                                 opp-202000000 {
1692                                         opp-hz = /bits/ 64 <202000000>;
1693                                         required-opps = <&rpmhpd_opp_svs_l1>;
1694                                 };
1695                         };
1696                 };
1697
1698                 dc_noc: interconnect@90c0000 {
1699                         compatible = "qcom,sm8250-dc-noc";
1700                         reg = <0 0x090c0000 0 0x4200>;
1701                         #interconnect-cells = <1>;
1702                         qcom,bcm-voters = <&apps_bcm_voter>;
1703                 };
1704
1705                 gem_noc: interconnect@9100000 {
1706                         compatible = "qcom,sm8250-gem-noc";
1707                         reg = <0 0x09100000 0 0xb4000>;
1708                         #interconnect-cells = <1>;
1709                         qcom,bcm-voters = <&apps_bcm_voter>;
1710                 };
1711
1712                 npu_noc: interconnect@9990000 {
1713                         compatible = "qcom,sm8250-npu-noc";
1714                         reg = <0 0x09990000 0 0x1600>;
1715                         #interconnect-cells = <1>;
1716                         qcom,bcm-voters = <&apps_bcm_voter>;
1717                 };
1718
1719                 usb_1: usb@a6f8800 {
1720                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1721                         reg = <0 0x0a6f8800 0 0x400>;
1722                         status = "disabled";
1723                         #address-cells = <2>;
1724                         #size-cells = <2>;
1725                         ranges;
1726                         dma-ranges;
1727
1728                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1729                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1730                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1731                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1732                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1733                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1734                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1735                                       "sleep", "xo";
1736
1737                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1738                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1739                         assigned-clock-rates = <19200000>, <200000000>;
1740
1741                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1742                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1743                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1744                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1745                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1746                                           "dm_hs_phy_irq", "ss_phy_irq";
1747
1748                         power-domains = <&gcc USB30_PRIM_GDSC>;
1749
1750                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1751
1752                         usb_1_dwc3: dwc3@a600000 {
1753                                 compatible = "snps,dwc3";
1754                                 reg = <0 0x0a600000 0 0xcd00>;
1755                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1756                                 iommus = <&apps_smmu 0x0 0x0>;
1757                                 snps,dis_u2_susphy_quirk;
1758                                 snps,dis_enblslpm_quirk;
1759                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1760                                 phy-names = "usb2-phy", "usb3-phy";
1761                         };
1762                 };
1763
1764                 system-cache-controller@9200000 {
1765                         compatible = "qcom,sm8250-llcc";
1766                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
1767                         reg-names = "llcc_base", "llcc_broadcast_base";
1768                 };
1769
1770                 usb_2: usb@a8f8800 {
1771                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1772                         reg = <0 0x0a8f8800 0 0x400>;
1773                         status = "disabled";
1774                         #address-cells = <2>;
1775                         #size-cells = <2>;
1776                         ranges;
1777                         dma-ranges;
1778
1779                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1780                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1781                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1782                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1783                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1784                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1785                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1786                                       "sleep", "xo";
1787
1788                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1789                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1790                         assigned-clock-rates = <19200000>, <200000000>;
1791
1792                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1793                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1794                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1795                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1796                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1797                                           "dm_hs_phy_irq", "ss_phy_irq";
1798
1799                         power-domains = <&gcc USB30_SEC_GDSC>;
1800
1801                         resets = <&gcc GCC_USB30_SEC_BCR>;
1802
1803                         usb_2_dwc3: dwc3@a800000 {
1804                                 compatible = "snps,dwc3";
1805                                 reg = <0 0x0a800000 0 0xcd00>;
1806                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1807                                 iommus = <&apps_smmu 0x20 0>;
1808                                 snps,dis_u2_susphy_quirk;
1809                                 snps,dis_enblslpm_quirk;
1810                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1811                                 phy-names = "usb2-phy", "usb3-phy";
1812                         };
1813                 };
1814
1815                 mdss: mdss@ae00000 {
1816                         compatible = "qcom,sdm845-mdss";
1817                         reg = <0 0x0ae00000 0 0x1000>;
1818                         reg-names = "mdss";
1819
1820                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
1821                                         <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
1822                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
1823                         interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
1824
1825                         power-domains = <&dispcc MDSS_GDSC>;
1826
1827                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1828                                  <&gcc GCC_DISP_HF_AXI_CLK>,
1829                                  <&gcc GCC_DISP_SF_AXI_CLK>,
1830                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
1831                         clock-names = "iface", "bus", "nrt_bus", "core";
1832
1833                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
1834                         assigned-clock-rates = <460000000>;
1835
1836                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1837                         interrupt-controller;
1838                         #interrupt-cells = <1>;
1839
1840                         iommus = <&apps_smmu 0x820 0x402>;
1841
1842                         status = "disabled";
1843
1844                         #address-cells = <2>;
1845                         #size-cells = <2>;
1846                         ranges;
1847
1848                         mdss_mdp: mdp@ae01000 {
1849                                 compatible = "qcom,sdm845-dpu";
1850                                 reg = <0 0x0ae01000 0 0x8f000>,
1851                                       <0 0x0aeb0000 0 0x2008>;
1852                                 reg-names = "mdp", "vbif";
1853
1854                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1855                                          <&gcc GCC_DISP_HF_AXI_CLK>,
1856                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
1857                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1858                                 clock-names = "iface", "bus", "core", "vsync";
1859
1860                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
1861                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1862                                 assigned-clock-rates = <460000000>,
1863                                                        <19200000>;
1864
1865                                 operating-points-v2 = <&mdp_opp_table>;
1866                                 power-domains = <&rpmhpd SM8250_MMCX>;
1867
1868                                 interrupt-parent = <&mdss>;
1869                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1870
1871                                 status = "disabled";
1872
1873                                 ports {
1874                                         #address-cells = <1>;
1875                                         #size-cells = <0>;
1876
1877                                         port@0 {
1878                                                 reg = <0>;
1879                                                 dpu_intf1_out: endpoint {
1880                                                         remote-endpoint = <&dsi0_in>;
1881                                                 };
1882                                         };
1883
1884                                         port@1 {
1885                                                 reg = <1>;
1886                                                 dpu_intf2_out: endpoint {
1887                                                         remote-endpoint = <&dsi1_in>;
1888                                                 };
1889                                         };
1890                                 };
1891
1892                                 mdp_opp_table: mdp-opp-table {
1893                                         compatible = "operating-points-v2";
1894
1895                                         opp-200000000 {
1896                                                 opp-hz = /bits/ 64 <200000000>;
1897                                                 required-opps = <&rpmhpd_opp_low_svs>;
1898                                         };
1899
1900                                         opp-300000000 {
1901                                                 opp-hz = /bits/ 64 <300000000>;
1902                                                 required-opps = <&rpmhpd_opp_svs>;
1903                                         };
1904
1905                                         opp-345000000 {
1906                                                 opp-hz = /bits/ 64 <345000000>;
1907                                                 required-opps = <&rpmhpd_opp_svs_l1>;
1908                                         };
1909
1910                                         opp-460000000 {
1911                                                 opp-hz = /bits/ 64 <460000000>;
1912                                                 required-opps = <&rpmhpd_opp_nom>;
1913                                         };
1914                                 };
1915                         };
1916
1917                         dsi0: dsi@ae94000 {
1918                                 compatible = "qcom,mdss-dsi-ctrl";
1919                                 reg = <0 0x0ae94000 0 0x400>;
1920                                 reg-names = "dsi_ctrl";
1921
1922                                 interrupt-parent = <&mdss>;
1923                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1924
1925                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1926                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1927                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1928                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1929                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1930                                         <&gcc GCC_DISP_HF_AXI_CLK>;
1931                                 clock-names = "byte",
1932                                               "byte_intf",
1933                                               "pixel",
1934                                               "core",
1935                                               "iface",
1936                                               "bus";
1937
1938                                 operating-points-v2 = <&dsi_opp_table>;
1939                                 power-domains = <&rpmhpd SM8250_MMCX>;
1940
1941                                 phys = <&dsi0_phy>;
1942                                 phy-names = "dsi";
1943
1944                                 status = "disabled";
1945
1946                                 ports {
1947                                         #address-cells = <1>;
1948                                         #size-cells = <0>;
1949
1950                                         port@0 {
1951                                                 reg = <0>;
1952                                                 dsi0_in: endpoint {
1953                                                         remote-endpoint = <&dpu_intf1_out>;
1954                                                 };
1955                                         };
1956
1957                                         port@1 {
1958                                                 reg = <1>;
1959                                                 dsi0_out: endpoint {
1960                                                 };
1961                                         };
1962                                 };
1963                         };
1964
1965                         dsi0_phy: dsi-phy@ae94400 {
1966                                 compatible = "qcom,dsi-phy-7nm";
1967                                 reg = <0 0x0ae94400 0 0x200>,
1968                                       <0 0x0ae94600 0 0x280>,
1969                                       <0 0x0ae94900 0 0x260>;
1970                                 reg-names = "dsi_phy",
1971                                             "dsi_phy_lane",
1972                                             "dsi_pll";
1973
1974                                 #clock-cells = <1>;
1975                                 #phy-cells = <0>;
1976
1977                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1978                                          <&rpmhcc RPMH_CXO_CLK>;
1979                                 clock-names = "iface", "ref";
1980
1981                                 status = "disabled";
1982                         };
1983
1984                         dsi1: dsi@ae96000 {
1985                                 compatible = "qcom,mdss-dsi-ctrl";
1986                                 reg = <0 0x0ae96000 0 0x400>;
1987                                 reg-names = "dsi_ctrl";
1988
1989                                 interrupt-parent = <&mdss>;
1990                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
1991
1992                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
1993                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
1994                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
1995                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
1996                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1997                                          <&gcc GCC_DISP_HF_AXI_CLK>;
1998                                 clock-names = "byte",
1999                                               "byte_intf",
2000                                               "pixel",
2001                                               "core",
2002                                               "iface",
2003                                               "bus";
2004
2005                                 operating-points-v2 = <&dsi_opp_table>;
2006                                 power-domains = <&rpmhpd SM8250_MMCX>;
2007
2008                                 phys = <&dsi1_phy>;
2009                                 phy-names = "dsi";
2010
2011                                 status = "disabled";
2012
2013                                 ports {
2014                                         #address-cells = <1>;
2015                                         #size-cells = <0>;
2016
2017                                         port@0 {
2018                                                 reg = <0>;
2019                                                 dsi1_in: endpoint {
2020                                                         remote-endpoint = <&dpu_intf2_out>;
2021                                                 };
2022                                         };
2023
2024                                         port@1 {
2025                                                 reg = <1>;
2026                                                 dsi1_out: endpoint {
2027                                                 };
2028                                         };
2029                                 };
2030                         };
2031
2032                         dsi1_phy: dsi-phy@ae96400 {
2033                                 compatible = "qcom,dsi-phy-7nm";
2034                                 reg = <0 0x0ae96400 0 0x200>,
2035                                       <0 0x0ae96600 0 0x280>,
2036                                       <0 0x0ae96900 0 0x260>;
2037                                 reg-names = "dsi_phy",
2038                                             "dsi_phy_lane",
2039                                             "dsi_pll";
2040
2041                                 #clock-cells = <1>;
2042                                 #phy-cells = <0>;
2043
2044                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2045                                          <&rpmhcc RPMH_CXO_CLK>;
2046                                 clock-names = "iface", "ref";
2047
2048                                 status = "disabled";
2049
2050                                 dsi_opp_table: dsi-opp-table {
2051                                         compatible = "operating-points-v2";
2052
2053                                         opp-187500000 {
2054                                                 opp-hz = /bits/ 64 <187500000>;
2055                                                 required-opps = <&rpmhpd_opp_low_svs>;
2056                                         };
2057
2058                                         opp-300000000 {
2059                                                 opp-hz = /bits/ 64 <300000000>;
2060                                                 required-opps = <&rpmhpd_opp_svs>;
2061                                         };
2062
2063                                         opp-358000000 {
2064                                                 opp-hz = /bits/ 64 <358000000>;
2065                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2066                                         };
2067                                 };
2068                         };
2069                 };
2070
2071                 dispcc: clock-controller@af00000 {
2072                         compatible = "qcom,sm8250-dispcc";
2073                         reg = <0 0x0af00000 0 0x20000>;
2074                         mmcx-supply = <&mmcx_reg>;
2075                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2076                                  <&dsi0_phy 0>,
2077                                  <&dsi0_phy 1>,
2078                                  <&dsi1_phy 0>,
2079                                  <&dsi1_phy 1>,
2080                                  <0>,
2081                                  <0>,
2082                                  <0>,
2083                                  <0>,
2084                                  <0>,
2085                                  <0>,
2086                                  <0>,
2087                                  <0>,
2088                                  <&sleep_clk>;
2089                         clock-names = "bi_tcxo",
2090                                       "dsi0_phy_pll_out_byteclk",
2091                                       "dsi0_phy_pll_out_dsiclk",
2092                                       "dsi1_phy_pll_out_byteclk",
2093                                       "dsi1_phy_pll_out_dsiclk",
2094                                       "dp_link_clk_divsel_ten",
2095                                       "dp_vco_divided_clk_src_mux",
2096                                       "dptx1_phy_pll_link_clk",
2097                                       "dptx1_phy_pll_vco_div_clk",
2098                                       "dptx2_phy_pll_link_clk",
2099                                       "dptx2_phy_pll_vco_div_clk",
2100                                       "edp_phy_pll_link_clk",
2101                                       "edp_phy_pll_vco_div_clk",
2102                                       "sleep_clk";
2103                         #clock-cells = <1>;
2104                         #reset-cells = <1>;
2105                         #power-domain-cells = <1>;
2106                 };
2107
2108                 pdc: interrupt-controller@b220000 {
2109                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
2110                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2111                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2112                                           <125 63 1>, <126 716 12>;
2113                         #interrupt-cells = <2>;
2114                         interrupt-parent = <&intc>;
2115                         interrupt-controller;
2116                 };
2117
2118                 tsens0: thermal-sensor@c263000 {
2119                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2120                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2121                               <0 0x0c222000 0 0x1ff>; /* SROT */
2122                         #qcom,sensors = <16>;
2123                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2124                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2125                         interrupt-names = "uplow", "critical";
2126                         #thermal-sensor-cells = <1>;
2127                 };
2128
2129                 tsens1: thermal-sensor@c265000 {
2130                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2131                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2132                               <0 0x0c223000 0 0x1ff>; /* SROT */
2133                         #qcom,sensors = <9>;
2134                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2135                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2136                         interrupt-names = "uplow", "critical";
2137                         #thermal-sensor-cells = <1>;
2138                 };
2139
2140                 aoss_qmp: qmp@c300000 {
2141                         compatible = "qcom,sm8250-aoss-qmp";
2142                         reg = <0 0x0c300000 0 0x100000>;
2143                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2144                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
2145                                                      IRQ_TYPE_EDGE_RISING>;
2146                         mboxes = <&ipcc IPCC_CLIENT_AOP
2147                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
2148
2149                         #clock-cells = <0>;
2150                         #power-domain-cells = <1>;
2151                 };
2152
2153                 spmi_bus: spmi@c440000 {
2154                         compatible = "qcom,spmi-pmic-arb";
2155                         reg = <0x0 0x0c440000 0x0 0x0001100>,
2156                               <0x0 0x0c600000 0x0 0x2000000>,
2157                               <0x0 0x0e600000 0x0 0x0100000>,
2158                               <0x0 0x0e700000 0x0 0x00a0000>,
2159                               <0x0 0x0c40a000 0x0 0x0026000>;
2160                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2161                         interrupt-names = "periph_irq";
2162                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2163                         qcom,ee = <0>;
2164                         qcom,channel = <0>;
2165                         #address-cells = <2>;
2166                         #size-cells = <0>;
2167                         interrupt-controller;
2168                         #interrupt-cells = <4>;
2169                 };
2170
2171                 tlmm: pinctrl@f100000 {
2172                         compatible = "qcom,sm8250-pinctrl";
2173                         reg = <0 0x0f100000 0 0x300000>,
2174                               <0 0x0f500000 0 0x300000>,
2175                               <0 0x0f900000 0 0x300000>;
2176                         reg-names = "west", "south", "north";
2177                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2178                         gpio-controller;
2179                         #gpio-cells = <2>;
2180                         interrupt-controller;
2181                         #interrupt-cells = <2>;
2182                         gpio-ranges = <&tlmm 0 0 180>;
2183                         wakeup-parent = <&pdc>;
2184
2185                         qup_i2c0_default: qup-i2c0-default {
2186                                 mux {
2187                                         pins = "gpio28", "gpio29";
2188                                         function = "qup0";
2189                                 };
2190
2191                                 config {
2192                                         pins = "gpio28", "gpio29";
2193                                         drive-strength = <2>;
2194                                         bias-disable;
2195                                 };
2196                         };
2197
2198                         qup_i2c1_default: qup-i2c1-default {
2199                                 pinmux {
2200                                         pins = "gpio4", "gpio5";
2201                                         function = "qup1";
2202                                 };
2203
2204                                 config {
2205                                         pins = "gpio4", "gpio5";
2206                                         drive-strength = <2>;
2207                                         bias-disable;
2208                                 };
2209                         };
2210
2211                         qup_i2c2_default: qup-i2c2-default {
2212                                 mux {
2213                                         pins = "gpio115", "gpio116";
2214                                         function = "qup2";
2215                                 };
2216
2217                                 config {
2218                                         pins = "gpio115", "gpio116";
2219                                         drive-strength = <2>;
2220                                         bias-disable;
2221                                 };
2222                         };
2223
2224                         qup_i2c3_default: qup-i2c3-default {
2225                                 mux {
2226                                         pins = "gpio119", "gpio120";
2227                                         function = "qup3";
2228                                 };
2229
2230                                 config {
2231                                         pins = "gpio119", "gpio120";
2232                                         drive-strength = <2>;
2233                                         bias-disable;
2234                                 };
2235                         };
2236
2237                         qup_i2c4_default: qup-i2c4-default {
2238                                 mux {
2239                                         pins = "gpio8", "gpio9";
2240                                         function = "qup4";
2241                                 };
2242
2243                                 config {
2244                                         pins = "gpio8", "gpio9";
2245                                         drive-strength = <2>;
2246                                         bias-disable;
2247                                 };
2248                         };
2249
2250                         qup_i2c5_default: qup-i2c5-default {
2251                                 mux {
2252                                         pins = "gpio12", "gpio13";
2253                                         function = "qup5";
2254                                 };
2255
2256                                 config {
2257                                         pins = "gpio12", "gpio13";
2258                                         drive-strength = <2>;
2259                                         bias-disable;
2260                                 };
2261                         };
2262
2263                         qup_i2c6_default: qup-i2c6-default {
2264                                 mux {
2265                                         pins = "gpio16", "gpio17";
2266                                         function = "qup6";
2267                                 };
2268
2269                                 config {
2270                                         pins = "gpio16", "gpio17";
2271                                         drive-strength = <2>;
2272                                         bias-disable;
2273                                 };
2274                         };
2275
2276                         qup_i2c7_default: qup-i2c7-default {
2277                                 mux {
2278                                         pins = "gpio20", "gpio21";
2279                                         function = "qup7";
2280                                 };
2281
2282                                 config {
2283                                         pins = "gpio20", "gpio21";
2284                                         drive-strength = <2>;
2285                                         bias-disable;
2286                                 };
2287                         };
2288
2289                         qup_i2c8_default: qup-i2c8-default {
2290                                 mux {
2291                                         pins = "gpio24", "gpio25";
2292                                         function = "qup8";
2293                                 };
2294
2295                                 config {
2296                                         pins = "gpio24", "gpio25";
2297                                         drive-strength = <2>;
2298                                         bias-disable;
2299                                 };
2300                         };
2301
2302                         qup_i2c9_default: qup-i2c9-default {
2303                                 mux {
2304                                         pins = "gpio125", "gpio126";
2305                                         function = "qup9";
2306                                 };
2307
2308                                 config {
2309                                         pins = "gpio125", "gpio126";
2310                                         drive-strength = <2>;
2311                                         bias-disable;
2312                                 };
2313                         };
2314
2315                         qup_i2c10_default: qup-i2c10-default {
2316                                 mux {
2317                                         pins = "gpio129", "gpio130";
2318                                         function = "qup10";
2319                                 };
2320
2321                                 config {
2322                                         pins = "gpio129", "gpio130";
2323                                         drive-strength = <2>;
2324                                         bias-disable;
2325                                 };
2326                         };
2327
2328                         qup_i2c11_default: qup-i2c11-default {
2329                                 mux {
2330                                         pins = "gpio60", "gpio61";
2331                                         function = "qup11";
2332                                 };
2333
2334                                 config {
2335                                         pins = "gpio60", "gpio61";
2336                                         drive-strength = <2>;
2337                                         bias-disable;
2338                                 };
2339                         };
2340
2341                         qup_i2c12_default: qup-i2c12-default {
2342                                 mux {
2343                                         pins = "gpio32", "gpio33";
2344                                         function = "qup12";
2345                                 };
2346
2347                                 config {
2348                                         pins = "gpio32", "gpio33";
2349                                         drive-strength = <2>;
2350                                         bias-disable;
2351                                 };
2352                         };
2353
2354                         qup_i2c13_default: qup-i2c13-default {
2355                                 mux {
2356                                         pins = "gpio36", "gpio37";
2357                                         function = "qup13";
2358                                 };
2359
2360                                 config {
2361                                         pins = "gpio36", "gpio37";
2362                                         drive-strength = <2>;
2363                                         bias-disable;
2364                                 };
2365                         };
2366
2367                         qup_i2c14_default: qup-i2c14-default {
2368                                 mux {
2369                                         pins = "gpio40", "gpio41";
2370                                         function = "qup14";
2371                                 };
2372
2373                                 config {
2374                                         pins = "gpio40", "gpio41";
2375                                         drive-strength = <2>;
2376                                         bias-disable;
2377                                 };
2378                         };
2379
2380                         qup_i2c15_default: qup-i2c15-default {
2381                                 mux {
2382                                         pins = "gpio44", "gpio45";
2383                                         function = "qup15";
2384                                 };
2385
2386                                 config {
2387                                         pins = "gpio44", "gpio45";
2388                                         drive-strength = <2>;
2389                                         bias-disable;
2390                                 };
2391                         };
2392
2393                         qup_i2c16_default: qup-i2c16-default {
2394                                 mux {
2395                                         pins = "gpio48", "gpio49";
2396                                         function = "qup16";
2397                                 };
2398
2399                                 config {
2400                                         pins = "gpio48", "gpio49";
2401                                         drive-strength = <2>;
2402                                         bias-disable;
2403                                 };
2404                         };
2405
2406                         qup_i2c17_default: qup-i2c17-default {
2407                                 mux {
2408                                         pins = "gpio52", "gpio53";
2409                                         function = "qup17";
2410                                 };
2411
2412                                 config {
2413                                         pins = "gpio52", "gpio53";
2414                                         drive-strength = <2>;
2415                                         bias-disable;
2416                                 };
2417                         };
2418
2419                         qup_i2c18_default: qup-i2c18-default {
2420                                 mux {
2421                                         pins = "gpio56", "gpio57";
2422                                         function = "qup18";
2423                                 };
2424
2425                                 config {
2426                                         pins = "gpio56", "gpio57";
2427                                         drive-strength = <2>;
2428                                         bias-disable;
2429                                 };
2430                         };
2431
2432                         qup_i2c19_default: qup-i2c19-default {
2433                                 mux {
2434                                         pins = "gpio0", "gpio1";
2435                                         function = "qup19";
2436                                 };
2437
2438                                 config {
2439                                         pins = "gpio0", "gpio1";
2440                                         drive-strength = <2>;
2441                                         bias-disable;
2442                                 };
2443                         };
2444
2445                         qup_spi0_default: qup-spi0-default {
2446                                 mux {
2447                                         pins = "gpio28", "gpio29",
2448                                                "gpio30", "gpio31";
2449                                         function = "qup0";
2450                                 };
2451
2452                                 config {
2453                                         pins = "gpio28", "gpio29",
2454                                                "gpio30", "gpio31";
2455                                         drive-strength = <6>;
2456                                         bias-disable;
2457                                 };
2458                         };
2459
2460                         qup_spi1_default: qup-spi1-default {
2461                                 mux {
2462                                         pins = "gpio4", "gpio5",
2463                                                "gpio6", "gpio7";
2464                                         function = "qup1";
2465                                 };
2466
2467                                 config {
2468                                         pins = "gpio4", "gpio5",
2469                                                "gpio6", "gpio7";
2470                                         drive-strength = <6>;
2471                                         bias-disable;
2472                                 };
2473                         };
2474
2475                         qup_spi2_default: qup-spi2-default {
2476                                 mux {
2477                                         pins = "gpio115", "gpio116",
2478                                                "gpio117", "gpio118";
2479                                         function = "qup2";
2480                                 };
2481
2482                                 config {
2483                                         pins = "gpio115", "gpio116",
2484                                                "gpio117", "gpio118";
2485                                         drive-strength = <6>;
2486                                         bias-disable;
2487                                 };
2488                         };
2489
2490                         qup_spi3_default: qup-spi3-default {
2491                                 mux {
2492                                         pins = "gpio119", "gpio120",
2493                                                "gpio121", "gpio122";
2494                                         function = "qup3";
2495                                 };
2496
2497                                 config {
2498                                         pins = "gpio119", "gpio120",
2499                                                "gpio121", "gpio122";
2500                                         drive-strength = <6>;
2501                                         bias-disable;
2502                                 };
2503                         };
2504
2505                         qup_spi4_default: qup-spi4-default {
2506                                 mux {
2507                                         pins = "gpio8", "gpio9",
2508                                                "gpio10", "gpio11";
2509                                         function = "qup4";
2510                                 };
2511
2512                                 config {
2513                                         pins = "gpio8", "gpio9",
2514                                                "gpio10", "gpio11";
2515                                         drive-strength = <6>;
2516                                         bias-disable;
2517                                 };
2518                         };
2519
2520                         qup_spi5_default: qup-spi5-default {
2521                                 mux {
2522                                         pins = "gpio12", "gpio13",
2523                                                "gpio14", "gpio15";
2524                                         function = "qup5";
2525                                 };
2526
2527                                 config {
2528                                         pins = "gpio12", "gpio13",
2529                                                "gpio14", "gpio15";
2530                                         drive-strength = <6>;
2531                                         bias-disable;
2532                                 };
2533                         };
2534
2535                         qup_spi6_default: qup-spi6-default {
2536                                 mux {
2537                                         pins = "gpio16", "gpio17",
2538                                                "gpio18", "gpio19";
2539                                         function = "qup6";
2540                                 };
2541
2542                                 config {
2543                                         pins = "gpio16", "gpio17",
2544                                                "gpio18", "gpio19";
2545                                         drive-strength = <6>;
2546                                         bias-disable;
2547                                 };
2548                         };
2549
2550                         qup_spi7_default: qup-spi7-default {
2551                                 mux {
2552                                         pins = "gpio20", "gpio21",
2553                                                "gpio22", "gpio23";
2554                                         function = "qup7";
2555                                 };
2556
2557                                 config {
2558                                         pins = "gpio20", "gpio21",
2559                                                "gpio22", "gpio23";
2560                                         drive-strength = <6>;
2561                                         bias-disable;
2562                                 };
2563                         };
2564
2565                         qup_spi8_default: qup-spi8-default {
2566                                 mux {
2567                                         pins = "gpio24", "gpio25",
2568                                                "gpio26", "gpio27";
2569                                         function = "qup8";
2570                                 };
2571
2572                                 config {
2573                                         pins = "gpio24", "gpio25",
2574                                                "gpio26", "gpio27";
2575                                         drive-strength = <6>;
2576                                         bias-disable;
2577                                 };
2578                         };
2579
2580                         qup_spi9_default: qup-spi9-default {
2581                                 mux {
2582                                         pins = "gpio125", "gpio126",
2583                                                "gpio127", "gpio128";
2584                                         function = "qup9";
2585                                 };
2586
2587                                 config {
2588                                         pins = "gpio125", "gpio126",
2589                                                "gpio127", "gpio128";
2590                                         drive-strength = <6>;
2591                                         bias-disable;
2592                                 };
2593                         };
2594
2595                         qup_spi10_default: qup-spi10-default {
2596                                 mux {
2597                                         pins = "gpio129", "gpio130",
2598                                                "gpio131", "gpio132";
2599                                         function = "qup10";
2600                                 };
2601
2602                                 config {
2603                                         pins = "gpio129", "gpio130",
2604                                                "gpio131", "gpio132";
2605                                         drive-strength = <6>;
2606                                         bias-disable;
2607                                 };
2608                         };
2609
2610                         qup_spi11_default: qup-spi11-default {
2611                                 mux {
2612                                         pins = "gpio60", "gpio61",
2613                                                "gpio62", "gpio63";
2614                                         function = "qup11";
2615                                 };
2616
2617                                 config {
2618                                         pins = "gpio60", "gpio61",
2619                                                "gpio62", "gpio63";
2620                                         drive-strength = <6>;
2621                                         bias-disable;
2622                                 };
2623                         };
2624
2625                         qup_spi12_default: qup-spi12-default {
2626                                 mux {
2627                                         pins = "gpio32", "gpio33",
2628                                                "gpio34", "gpio35";
2629                                         function = "qup12";
2630                                 };
2631
2632                                 config {
2633                                         pins = "gpio32", "gpio33",
2634                                                "gpio34", "gpio35";
2635                                         drive-strength = <6>;
2636                                         bias-disable;
2637                                 };
2638                         };
2639
2640                         qup_spi13_default: qup-spi13-default {
2641                                 mux {
2642                                         pins = "gpio36", "gpio37",
2643                                                "gpio38", "gpio39";
2644                                         function = "qup13";
2645                                 };
2646
2647                                 config {
2648                                         pins = "gpio36", "gpio37",
2649                                                "gpio38", "gpio39";
2650                                         drive-strength = <6>;
2651                                         bias-disable;
2652                                 };
2653                         };
2654
2655                         qup_spi14_default: qup-spi14-default {
2656                                 mux {
2657                                         pins = "gpio40", "gpio41",
2658                                                "gpio42", "gpio43";
2659                                         function = "qup14";
2660                                 };
2661
2662                                 config {
2663                                         pins = "gpio40", "gpio41",
2664                                                "gpio42", "gpio43";
2665                                         drive-strength = <6>;
2666                                         bias-disable;
2667                                 };
2668                         };
2669
2670                         qup_spi15_default: qup-spi15-default {
2671                                 mux {
2672                                         pins = "gpio44", "gpio45",
2673                                                "gpio46", "gpio47";
2674                                         function = "qup15";
2675                                 };
2676
2677                                 config {
2678                                         pins = "gpio44", "gpio45",
2679                                                "gpio46", "gpio47";
2680                                         drive-strength = <6>;
2681                                         bias-disable;
2682                                 };
2683                         };
2684
2685                         qup_spi16_default: qup-spi16-default {
2686                                 mux {
2687                                         pins = "gpio48", "gpio49",
2688                                                "gpio50", "gpio51";
2689                                         function = "qup16";
2690                                 };
2691
2692                                 config {
2693                                         pins = "gpio48", "gpio49",
2694                                                "gpio50", "gpio51";
2695                                         drive-strength = <6>;
2696                                         bias-disable;
2697                                 };
2698                         };
2699
2700                         qup_spi17_default: qup-spi17-default {
2701                                 mux {
2702                                         pins = "gpio52", "gpio53",
2703                                                "gpio54", "gpio55";
2704                                         function = "qup17";
2705                                 };
2706
2707                                 config {
2708                                         pins = "gpio52", "gpio53",
2709                                                "gpio54", "gpio55";
2710                                         drive-strength = <6>;
2711                                         bias-disable;
2712                                 };
2713                         };
2714
2715                         qup_spi18_default: qup-spi18-default {
2716                                 mux {
2717                                         pins = "gpio56", "gpio57",
2718                                                "gpio58", "gpio59";
2719                                         function = "qup18";
2720                                 };
2721
2722                                 config {
2723                                         pins = "gpio56", "gpio57",
2724                                                "gpio58", "gpio59";
2725                                         drive-strength = <6>;
2726                                         bias-disable;
2727                                 };
2728                         };
2729
2730                         qup_spi19_default: qup-spi19-default {
2731                                 mux {
2732                                         pins = "gpio0", "gpio1",
2733                                                "gpio2", "gpio3";
2734                                         function = "qup19";
2735                                 };
2736
2737                                 config {
2738                                         pins = "gpio0", "gpio1",
2739                                                "gpio2", "gpio3";
2740                                         drive-strength = <6>;
2741                                         bias-disable;
2742                                 };
2743                         };
2744
2745                         qup_uart2_default: qup-uart2-default {
2746                                 mux {
2747                                         pins = "gpio117", "gpio118";
2748                                         function = "qup2";
2749                                 };
2750                         };
2751
2752                         qup_uart6_default: qup-uart6-default {
2753                                 mux {
2754                                         pins = "gpio16", "gpio17",
2755                                                 "gpio18", "gpio19";
2756                                         function = "qup6";
2757                                 };
2758                         };
2759
2760                         qup_uart12_default: qup-uart12-default {
2761                                 mux {
2762                                         pins = "gpio34", "gpio35";
2763                                         function = "qup12";
2764                                 };
2765                         };
2766
2767                         qup_uart17_default: qup-uart17-default {
2768                                 mux {
2769                                         pins = "gpio52", "gpio53",
2770                                                 "gpio54", "gpio55";
2771                                         function = "qup17";
2772                                 };
2773                         };
2774
2775                         qup_uart18_default: qup-uart18-default {
2776                                 mux {
2777                                         pins = "gpio58", "gpio59";
2778                                         function = "qup18";
2779                                 };
2780                         };
2781                 };
2782
2783                 apps_smmu: iommu@15000000 {
2784                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2785                         reg = <0 0x15000000 0 0x100000>;
2786                         #iommu-cells = <2>;
2787                         #global-interrupts = <2>;
2788                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2789                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2790                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2791                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2792                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2793                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2794                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2795                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2796                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2797                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2798                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2799                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2800                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2801                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2802                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2803                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2804                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2805                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2806                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2807                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2808                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2809                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2810                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2811                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2812                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2813                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2814                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2815                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2816                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2817                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2818                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2819                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2820                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2821                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2822                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2823                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2824                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2825                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2826                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2827                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2828                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2829                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2830                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2831                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2832                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2833                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2834                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2835                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2836                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2837                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2838                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2839                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2840                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2841                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2842                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2843                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2844                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2845                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2846                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2847                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2848                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2849                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2850                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2851                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2852                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2853                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2854                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2855                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2856                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2857                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2858                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2859                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2860                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2861                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2862                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2863                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2864                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2865                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2866                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2867                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2868                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2869                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2870                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2871                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2872                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2873                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2874                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2875                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2876                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2877                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2878                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2879                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2880                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2881                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2882                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2883                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2884                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
2885                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
2886                 };
2887
2888                 adsp: remoteproc@17300000 {
2889                         compatible = "qcom,sm8250-adsp-pas";
2890                         reg = <0 0x17300000 0 0x100>;
2891
2892                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2893                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2894                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2895                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2896                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2897                         interrupt-names = "wdog", "fatal", "ready",
2898                                           "handover", "stop-ack";
2899
2900                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2901                         clock-names = "xo";
2902
2903                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2904                                         <&rpmhpd SM8250_LCX>,
2905                                         <&rpmhpd SM8250_LMX>;
2906                         power-domain-names = "load_state", "lcx", "lmx";
2907
2908                         memory-region = <&adsp_mem>;
2909
2910                         qcom,smem-states = <&smp2p_adsp_out 0>;
2911                         qcom,smem-state-names = "stop";
2912
2913                         status = "disabled";
2914
2915                         glink-edge {
2916                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2917                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2918                                                              IRQ_TYPE_EDGE_RISING>;
2919                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2920                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2921
2922                                 label = "lpass";
2923                                 qcom,remote-pid = <2>;
2924
2925                                 fastrpc {
2926                                         compatible = "qcom,fastrpc";
2927                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2928                                         label = "adsp";
2929                                         #address-cells = <1>;
2930                                         #size-cells = <0>;
2931
2932                                         compute-cb@3 {
2933                                                 compatible = "qcom,fastrpc-compute-cb";
2934                                                 reg = <3>;
2935                                                 iommus = <&apps_smmu 0x1803 0x0>;
2936                                         };
2937
2938                                         compute-cb@4 {
2939                                                 compatible = "qcom,fastrpc-compute-cb";
2940                                                 reg = <4>;
2941                                                 iommus = <&apps_smmu 0x1804 0x0>;
2942                                         };
2943
2944                                         compute-cb@5 {
2945                                                 compatible = "qcom,fastrpc-compute-cb";
2946                                                 reg = <5>;
2947                                                 iommus = <&apps_smmu 0x1805 0x0>;
2948                                         };
2949                                 };
2950                         };
2951                 };
2952
2953                 intc: interrupt-controller@17a00000 {
2954                         compatible = "arm,gic-v3";
2955                         #interrupt-cells = <3>;
2956                         interrupt-controller;
2957                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2958                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2959                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2960                 };
2961
2962                 watchdog@17c10000 {
2963                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
2964                         reg = <0 0x17c10000 0 0x1000>;
2965                         clocks = <&sleep_clk>;
2966                 };
2967
2968                 timer@17c20000 {
2969                         #address-cells = <2>;
2970                         #size-cells = <2>;
2971                         ranges;
2972                         compatible = "arm,armv7-timer-mem";
2973                         reg = <0x0 0x17c20000 0x0 0x1000>;
2974                         clock-frequency = <19200000>;
2975
2976                         frame@17c21000 {
2977                                 frame-number = <0>;
2978                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2979                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2980                                 reg = <0x0 0x17c21000 0x0 0x1000>,
2981                                       <0x0 0x17c22000 0x0 0x1000>;
2982                         };
2983
2984                         frame@17c23000 {
2985                                 frame-number = <1>;
2986                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2987                                 reg = <0x0 0x17c23000 0x0 0x1000>;
2988                                 status = "disabled";
2989                         };
2990
2991                         frame@17c25000 {
2992                                 frame-number = <2>;
2993                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2994                                 reg = <0x0 0x17c25000 0x0 0x1000>;
2995                                 status = "disabled";
2996                         };
2997
2998                         frame@17c27000 {
2999                                 frame-number = <3>;
3000                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3001                                 reg = <0x0 0x17c27000 0x0 0x1000>;
3002                                 status = "disabled";
3003                         };
3004
3005                         frame@17c29000 {
3006                                 frame-number = <4>;
3007                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3008                                 reg = <0x0 0x17c29000 0x0 0x1000>;
3009                                 status = "disabled";
3010                         };
3011
3012                         frame@17c2b000 {
3013                                 frame-number = <5>;
3014                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3015                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
3016                                 status = "disabled";
3017                         };
3018
3019                         frame@17c2d000 {
3020                                 frame-number = <6>;
3021                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3022                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
3023                                 status = "disabled";
3024                         };
3025                 };
3026
3027                 apps_rsc: rsc@18200000 {
3028                         label = "apps_rsc";
3029                         compatible = "qcom,rpmh-rsc";
3030                         reg = <0x0 0x18200000 0x0 0x10000>,
3031                                 <0x0 0x18210000 0x0 0x10000>,
3032                                 <0x0 0x18220000 0x0 0x10000>;
3033                         reg-names = "drv-0", "drv-1", "drv-2";
3034                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3035                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3036                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3037                         qcom,tcs-offset = <0xd00>;
3038                         qcom,drv-id = <2>;
3039                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3040                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
3041
3042                         rpmhcc: clock-controller {
3043                                 compatible = "qcom,sm8250-rpmh-clk";
3044                                 #clock-cells = <1>;
3045                                 clock-names = "xo";
3046                                 clocks = <&xo_board>;
3047                         };
3048
3049                         rpmhpd: power-controller {
3050                                 compatible = "qcom,sm8250-rpmhpd";
3051                                 #power-domain-cells = <1>;
3052                                 operating-points-v2 = <&rpmhpd_opp_table>;
3053
3054                                 rpmhpd_opp_table: opp-table {
3055                                         compatible = "operating-points-v2";
3056
3057                                         rpmhpd_opp_ret: opp1 {
3058                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3059                                         };
3060
3061                                         rpmhpd_opp_min_svs: opp2 {
3062                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3063                                         };
3064
3065                                         rpmhpd_opp_low_svs: opp3 {
3066                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3067                                         };
3068
3069                                         rpmhpd_opp_svs: opp4 {
3070                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3071                                         };
3072
3073                                         rpmhpd_opp_svs_l1: opp5 {
3074                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3075                                         };
3076
3077                                         rpmhpd_opp_nom: opp6 {
3078                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3079                                         };
3080
3081                                         rpmhpd_opp_nom_l1: opp7 {
3082                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3083                                         };
3084
3085                                         rpmhpd_opp_nom_l2: opp8 {
3086                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3087                                         };
3088
3089                                         rpmhpd_opp_turbo: opp9 {
3090                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3091                                         };
3092
3093                                         rpmhpd_opp_turbo_l1: opp10 {
3094                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3095                                         };
3096                                 };
3097                         };
3098
3099                         apps_bcm_voter: bcm_voter {
3100                                 compatible = "qcom,bcm-voter";
3101                         };
3102                 };
3103
3104                 epss_l3: interconnect@18591000 {
3105                         compatible = "qcom,sm8250-epss-l3";
3106                         reg = <0 0x18590000 0 0x1000>;
3107
3108                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3109                         clock-names = "xo", "alternate";
3110
3111                         #interconnect-cells = <1>;
3112                 };
3113
3114                 cpufreq_hw: cpufreq@18591000 {
3115                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3116                         reg = <0 0x18591000 0 0x1000>,
3117                               <0 0x18592000 0 0x1000>,
3118                               <0 0x18593000 0 0x1000>;
3119                         reg-names = "freq-domain0", "freq-domain1",
3120                                     "freq-domain2";
3121
3122                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3123                         clock-names = "xo", "alternate";
3124
3125                         #freq-domain-cells = <1>;
3126                 };
3127         };
3128
3129         timer {
3130                 compatible = "arm,armv8-timer";
3131                 interrupts = <GIC_PPI 13
3132                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3133                              <GIC_PPI 14
3134                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3135                              <GIC_PPI 11
3136                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3137                              <GIC_PPI 12
3138                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3139         };
3140
3141         thermal-zones {
3142                 cpu0-thermal {
3143                         polling-delay-passive = <250>;
3144                         polling-delay = <1000>;
3145
3146                         thermal-sensors = <&tsens0 1>;
3147
3148                         trips {
3149                                 cpu0_alert0: trip-point0 {
3150                                         temperature = <90000>;
3151                                         hysteresis = <2000>;
3152                                         type = "passive";
3153                                 };
3154
3155                                 cpu0_alert1: trip-point1 {
3156                                         temperature = <95000>;
3157                                         hysteresis = <2000>;
3158                                         type = "passive";
3159                                 };
3160
3161                                 cpu0_crit: cpu_crit {
3162                                         temperature = <110000>;
3163                                         hysteresis = <1000>;
3164                                         type = "critical";
3165                                 };
3166                         };
3167
3168                         cooling-maps {
3169                                 map0 {
3170                                         trip = <&cpu0_alert0>;
3171                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3172                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3173                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3174                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3175                                 };
3176                                 map1 {
3177                                         trip = <&cpu0_alert1>;
3178                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3179                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3180                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3181                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3182                                 };
3183                         };
3184                 };
3185
3186                 cpu1-thermal {
3187                         polling-delay-passive = <250>;
3188                         polling-delay = <1000>;
3189
3190                         thermal-sensors = <&tsens0 2>;
3191
3192                         trips {
3193                                 cpu1_alert0: trip-point0 {
3194                                         temperature = <90000>;
3195                                         hysteresis = <2000>;
3196                                         type = "passive";
3197                                 };
3198
3199                                 cpu1_alert1: trip-point1 {
3200                                         temperature = <95000>;
3201                                         hysteresis = <2000>;
3202                                         type = "passive";
3203                                 };
3204
3205                                 cpu1_crit: cpu_crit {
3206                                         temperature = <110000>;
3207                                         hysteresis = <1000>;
3208                                         type = "critical";
3209                                 };
3210                         };
3211
3212                         cooling-maps {
3213                                 map0 {
3214                                         trip = <&cpu1_alert0>;
3215                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3216                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3217                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3218                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3219                                 };
3220                                 map1 {
3221                                         trip = <&cpu1_alert1>;
3222                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3223                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3224                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3225                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3226                                 };
3227                         };
3228                 };
3229
3230                 cpu2-thermal {
3231                         polling-delay-passive = <250>;
3232                         polling-delay = <1000>;
3233
3234                         thermal-sensors = <&tsens0 3>;
3235
3236                         trips {
3237                                 cpu2_alert0: trip-point0 {
3238                                         temperature = <90000>;
3239                                         hysteresis = <2000>;
3240                                         type = "passive";
3241                                 };
3242
3243                                 cpu2_alert1: trip-point1 {
3244                                         temperature = <95000>;
3245                                         hysteresis = <2000>;
3246                                         type = "passive";
3247                                 };
3248
3249                                 cpu2_crit: cpu_crit {
3250                                         temperature = <110000>;
3251                                         hysteresis = <1000>;
3252                                         type = "critical";
3253                                 };
3254                         };
3255
3256                         cooling-maps {
3257                                 map0 {
3258                                         trip = <&cpu2_alert0>;
3259                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3260                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3261                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3262                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3263                                 };
3264                                 map1 {
3265                                         trip = <&cpu2_alert1>;
3266                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3267                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3268                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3269                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3270                                 };
3271                         };
3272                 };
3273
3274                 cpu3-thermal {
3275                         polling-delay-passive = <250>;
3276                         polling-delay = <1000>;
3277
3278                         thermal-sensors = <&tsens0 4>;
3279
3280                         trips {
3281                                 cpu3_alert0: trip-point0 {
3282                                         temperature = <90000>;
3283                                         hysteresis = <2000>;
3284                                         type = "passive";
3285                                 };
3286
3287                                 cpu3_alert1: trip-point1 {
3288                                         temperature = <95000>;
3289                                         hysteresis = <2000>;
3290                                         type = "passive";
3291                                 };
3292
3293                                 cpu3_crit: cpu_crit {
3294                                         temperature = <110000>;
3295                                         hysteresis = <1000>;
3296                                         type = "critical";
3297                                 };
3298                         };
3299
3300                         cooling-maps {
3301                                 map0 {
3302                                         trip = <&cpu3_alert0>;
3303                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3304                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3305                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3306                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3307                                 };
3308                                 map1 {
3309                                         trip = <&cpu3_alert1>;
3310                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3311                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3312                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3313                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3314                                 };
3315                         };
3316                 };
3317
3318                 cpu4-top-thermal {
3319                         polling-delay-passive = <250>;
3320                         polling-delay = <1000>;
3321
3322                         thermal-sensors = <&tsens0 7>;
3323
3324                         trips {
3325                                 cpu4_top_alert0: trip-point0 {
3326                                         temperature = <90000>;
3327                                         hysteresis = <2000>;
3328                                         type = "passive";
3329                                 };
3330
3331                                 cpu4_top_alert1: trip-point1 {
3332                                         temperature = <95000>;
3333                                         hysteresis = <2000>;
3334                                         type = "passive";
3335                                 };
3336
3337                                 cpu4_top_crit: cpu_crit {
3338                                         temperature = <110000>;
3339                                         hysteresis = <1000>;
3340                                         type = "critical";
3341                                 };
3342                         };
3343
3344                         cooling-maps {
3345                                 map0 {
3346                                         trip = <&cpu4_top_alert0>;
3347                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3348                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3349                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3350                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3351                                 };
3352                                 map1 {
3353                                         trip = <&cpu4_top_alert1>;
3354                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3355                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3356                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3357                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3358                                 };
3359                         };
3360                 };
3361
3362                 cpu5-top-thermal {
3363                         polling-delay-passive = <250>;
3364                         polling-delay = <1000>;
3365
3366                         thermal-sensors = <&tsens0 8>;
3367
3368                         trips {
3369                                 cpu5_top_alert0: trip-point0 {
3370                                         temperature = <90000>;
3371                                         hysteresis = <2000>;
3372                                         type = "passive";
3373                                 };
3374
3375                                 cpu5_top_alert1: trip-point1 {
3376                                         temperature = <95000>;
3377                                         hysteresis = <2000>;
3378                                         type = "passive";
3379                                 };
3380
3381                                 cpu5_top_crit: cpu_crit {
3382                                         temperature = <110000>;
3383                                         hysteresis = <1000>;
3384                                         type = "critical";
3385                                 };
3386                         };
3387
3388                         cooling-maps {
3389                                 map0 {
3390                                         trip = <&cpu5_top_alert0>;
3391                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3392                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3393                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3394                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3395                                 };
3396                                 map1 {
3397                                         trip = <&cpu5_top_alert1>;
3398                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3399                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3400                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3401                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3402                                 };
3403                         };
3404                 };
3405
3406                 cpu6-top-thermal {
3407                         polling-delay-passive = <250>;
3408                         polling-delay = <1000>;
3409
3410                         thermal-sensors = <&tsens0 9>;
3411
3412                         trips {
3413                                 cpu6_top_alert0: trip-point0 {
3414                                         temperature = <90000>;
3415                                         hysteresis = <2000>;
3416                                         type = "passive";
3417                                 };
3418
3419                                 cpu6_top_alert1: trip-point1 {
3420                                         temperature = <95000>;
3421                                         hysteresis = <2000>;
3422                                         type = "passive";
3423                                 };
3424
3425                                 cpu6_top_crit: cpu_crit {
3426                                         temperature = <110000>;
3427                                         hysteresis = <1000>;
3428                                         type = "critical";
3429                                 };
3430                         };
3431
3432                         cooling-maps {
3433                                 map0 {
3434                                         trip = <&cpu6_top_alert0>;
3435                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3436                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3437                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3438                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3439                                 };
3440                                 map1 {
3441                                         trip = <&cpu6_top_alert1>;
3442                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3443                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3444                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3445                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3446                                 };
3447                         };
3448                 };
3449
3450                 cpu7-top-thermal {
3451                         polling-delay-passive = <250>;
3452                         polling-delay = <1000>;
3453
3454                         thermal-sensors = <&tsens0 10>;
3455
3456                         trips {
3457                                 cpu7_top_alert0: trip-point0 {
3458                                         temperature = <90000>;
3459                                         hysteresis = <2000>;
3460                                         type = "passive";
3461                                 };
3462
3463                                 cpu7_top_alert1: trip-point1 {
3464                                         temperature = <95000>;
3465                                         hysteresis = <2000>;
3466                                         type = "passive";
3467                                 };
3468
3469                                 cpu7_top_crit: cpu_crit {
3470                                         temperature = <110000>;
3471                                         hysteresis = <1000>;
3472                                         type = "critical";
3473                                 };
3474                         };
3475
3476                         cooling-maps {
3477                                 map0 {
3478                                         trip = <&cpu7_top_alert0>;
3479                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3480                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3481                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3482                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3483                                 };
3484                                 map1 {
3485                                         trip = <&cpu7_top_alert1>;
3486                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3487                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3488                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3489                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3490                                 };
3491                         };
3492                 };
3493
3494                 cpu4-bottom-thermal {
3495                         polling-delay-passive = <250>;
3496                         polling-delay = <1000>;
3497
3498                         thermal-sensors = <&tsens0 11>;
3499
3500                         trips {
3501                                 cpu4_bottom_alert0: trip-point0 {
3502                                         temperature = <90000>;
3503                                         hysteresis = <2000>;
3504                                         type = "passive";
3505                                 };
3506
3507                                 cpu4_bottom_alert1: trip-point1 {
3508                                         temperature = <95000>;
3509                                         hysteresis = <2000>;
3510                                         type = "passive";
3511                                 };
3512
3513                                 cpu4_bottom_crit: cpu_crit {
3514                                         temperature = <110000>;
3515                                         hysteresis = <1000>;
3516                                         type = "critical";
3517                                 };
3518                         };
3519
3520                         cooling-maps {
3521                                 map0 {
3522                                         trip = <&cpu4_bottom_alert0>;
3523                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3524                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3525                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3526                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3527                                 };
3528                                 map1 {
3529                                         trip = <&cpu4_bottom_alert1>;
3530                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3531                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3532                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3533                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3534                                 };
3535                         };
3536                 };
3537
3538                 cpu5-bottom-thermal {
3539                         polling-delay-passive = <250>;
3540                         polling-delay = <1000>;
3541
3542                         thermal-sensors = <&tsens0 12>;
3543
3544                         trips {
3545                                 cpu5_bottom_alert0: trip-point0 {
3546                                         temperature = <90000>;
3547                                         hysteresis = <2000>;
3548                                         type = "passive";
3549                                 };
3550
3551                                 cpu5_bottom_alert1: trip-point1 {
3552                                         temperature = <95000>;
3553                                         hysteresis = <2000>;
3554                                         type = "passive";
3555                                 };
3556
3557                                 cpu5_bottom_crit: cpu_crit {
3558                                         temperature = <110000>;
3559                                         hysteresis = <1000>;
3560                                         type = "critical";
3561                                 };
3562                         };
3563
3564                         cooling-maps {
3565                                 map0 {
3566                                         trip = <&cpu5_bottom_alert0>;
3567                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3568                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3569                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3570                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3571                                 };
3572                                 map1 {
3573                                         trip = <&cpu5_bottom_alert1>;
3574                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3575                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3576                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3577                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3578                                 };
3579                         };
3580                 };
3581
3582                 cpu6-bottom-thermal {
3583                         polling-delay-passive = <250>;
3584                         polling-delay = <1000>;
3585
3586                         thermal-sensors = <&tsens0 13>;
3587
3588                         trips {
3589                                 cpu6_bottom_alert0: trip-point0 {
3590                                         temperature = <90000>;
3591                                         hysteresis = <2000>;
3592                                         type = "passive";
3593                                 };
3594
3595                                 cpu6_bottom_alert1: trip-point1 {
3596                                         temperature = <95000>;
3597                                         hysteresis = <2000>;
3598                                         type = "passive";
3599                                 };
3600
3601                                 cpu6_bottom_crit: cpu_crit {
3602                                         temperature = <110000>;
3603                                         hysteresis = <1000>;
3604                                         type = "critical";
3605                                 };
3606                         };
3607
3608                         cooling-maps {
3609                                 map0 {
3610                                         trip = <&cpu6_bottom_alert0>;
3611                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3612                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3613                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3614                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3615                                 };
3616                                 map1 {
3617                                         trip = <&cpu6_bottom_alert1>;
3618                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3619                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3620                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3621                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3622                                 };
3623                         };
3624                 };
3625
3626                 cpu7-bottom-thermal {
3627                         polling-delay-passive = <250>;
3628                         polling-delay = <1000>;
3629
3630                         thermal-sensors = <&tsens0 14>;
3631
3632                         trips {
3633                                 cpu7_bottom_alert0: trip-point0 {
3634                                         temperature = <90000>;
3635                                         hysteresis = <2000>;
3636                                         type = "passive";
3637                                 };
3638
3639                                 cpu7_bottom_alert1: trip-point1 {
3640                                         temperature = <95000>;
3641                                         hysteresis = <2000>;
3642                                         type = "passive";
3643                                 };
3644
3645                                 cpu7_bottom_crit: cpu_crit {
3646                                         temperature = <110000>;
3647                                         hysteresis = <1000>;
3648                                         type = "critical";
3649                                 };
3650                         };
3651
3652                         cooling-maps {
3653                                 map0 {
3654                                         trip = <&cpu7_bottom_alert0>;
3655                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3659                                 };
3660                                 map1 {
3661                                         trip = <&cpu7_bottom_alert1>;
3662                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3663                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3664                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3665                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3666                                 };
3667                         };
3668                 };
3669
3670                 aoss0-thermal {
3671                         polling-delay-passive = <250>;
3672                         polling-delay = <1000>;
3673
3674                         thermal-sensors = <&tsens0 0>;
3675
3676                         trips {
3677                                 aoss0_alert0: trip-point0 {
3678                                         temperature = <90000>;
3679                                         hysteresis = <2000>;
3680                                         type = "hot";
3681                                 };
3682                         };
3683                 };
3684
3685                 cluster0-thermal {
3686                         polling-delay-passive = <250>;
3687                         polling-delay = <1000>;
3688
3689                         thermal-sensors = <&tsens0 5>;
3690
3691                         trips {
3692                                 cluster0_alert0: trip-point0 {
3693                                         temperature = <90000>;
3694                                         hysteresis = <2000>;
3695                                         type = "hot";
3696                                 };
3697                                 cluster0_crit: cluster0_crit {
3698                                         temperature = <110000>;
3699                                         hysteresis = <2000>;
3700                                         type = "critical";
3701                                 };
3702                         };
3703                 };
3704
3705                 cluster1-thermal {
3706                         polling-delay-passive = <250>;
3707                         polling-delay = <1000>;
3708
3709                         thermal-sensors = <&tsens0 6>;
3710
3711                         trips {
3712                                 cluster1_alert0: trip-point0 {
3713                                         temperature = <90000>;
3714                                         hysteresis = <2000>;
3715                                         type = "hot";
3716                                 };
3717                                 cluster1_crit: cluster1_crit {
3718                                         temperature = <110000>;
3719                                         hysteresis = <2000>;
3720                                         type = "critical";
3721                                 };
3722                         };
3723                 };
3724
3725                 gpu-thermal-top {
3726                         polling-delay-passive = <250>;
3727                         polling-delay = <1000>;
3728
3729                         thermal-sensors = <&tsens0 15>;
3730
3731                         trips {
3732                                 gpu1_alert0: trip-point0 {
3733                                         temperature = <90000>;
3734                                         hysteresis = <2000>;
3735                                         type = "hot";
3736                                 };
3737                         };
3738                 };
3739
3740                 aoss1-thermal {
3741                         polling-delay-passive = <250>;
3742                         polling-delay = <1000>;
3743
3744                         thermal-sensors = <&tsens1 0>;
3745
3746                         trips {
3747                                 aoss1_alert0: trip-point0 {
3748                                         temperature = <90000>;
3749                                         hysteresis = <2000>;
3750                                         type = "hot";
3751                                 };
3752                         };
3753                 };
3754
3755                 wlan-thermal {
3756                         polling-delay-passive = <250>;
3757                         polling-delay = <1000>;
3758
3759                         thermal-sensors = <&tsens1 1>;
3760
3761                         trips {
3762                                 wlan_alert0: trip-point0 {
3763                                         temperature = <90000>;
3764                                         hysteresis = <2000>;
3765                                         type = "hot";
3766                                 };
3767                         };
3768                 };
3769
3770                 video-thermal {
3771                         polling-delay-passive = <250>;
3772                         polling-delay = <1000>;
3773
3774                         thermal-sensors = <&tsens1 2>;
3775
3776                         trips {
3777                                 video_alert0: trip-point0 {
3778                                         temperature = <90000>;
3779                                         hysteresis = <2000>;
3780                                         type = "hot";
3781                                 };
3782                         };
3783                 };
3784
3785                 mem-thermal {
3786                         polling-delay-passive = <250>;
3787                         polling-delay = <1000>;
3788
3789                         thermal-sensors = <&tsens1 3>;
3790
3791                         trips {
3792                                 mem_alert0: trip-point0 {
3793                                         temperature = <90000>;
3794                                         hysteresis = <2000>;
3795                                         type = "hot";
3796                                 };
3797                         };
3798                 };
3799
3800                 q6-hvx-thermal {
3801                         polling-delay-passive = <250>;
3802                         polling-delay = <1000>;
3803
3804                         thermal-sensors = <&tsens1 4>;
3805
3806                         trips {
3807                                 q6_hvx_alert0: trip-point0 {
3808                                         temperature = <90000>;
3809                                         hysteresis = <2000>;
3810                                         type = "hot";
3811                                 };
3812                         };
3813                 };
3814
3815                 camera-thermal {
3816                         polling-delay-passive = <250>;
3817                         polling-delay = <1000>;
3818
3819                         thermal-sensors = <&tsens1 5>;
3820
3821                         trips {
3822                                 camera_alert0: trip-point0 {
3823                                         temperature = <90000>;
3824                                         hysteresis = <2000>;
3825                                         type = "hot";
3826                                 };
3827                         };
3828                 };
3829
3830                 compute-thermal {
3831                         polling-delay-passive = <250>;
3832                         polling-delay = <1000>;
3833
3834                         thermal-sensors = <&tsens1 6>;
3835
3836                         trips {
3837                                 compute_alert0: trip-point0 {
3838                                         temperature = <90000>;
3839                                         hysteresis = <2000>;
3840                                         type = "hot";
3841                                 };
3842                         };
3843                 };
3844
3845                 npu-thermal {
3846                         polling-delay-passive = <250>;
3847                         polling-delay = <1000>;
3848
3849                         thermal-sensors = <&tsens1 7>;
3850
3851                         trips {
3852                                 npu_alert0: trip-point0 {
3853                                         temperature = <90000>;
3854                                         hysteresis = <2000>;
3855                                         type = "hot";
3856                                 };
3857                         };
3858                 };
3859
3860                 gpu-thermal-bottom {
3861                         polling-delay-passive = <250>;
3862                         polling-delay = <1000>;
3863
3864                         thermal-sensors = <&tsens1 8>;
3865
3866                         trips {
3867                                 gpu2_alert0: trip-point0 {
3868                                         temperature = <90000>;
3869                                         hysteresis = <2000>;
3870                                         type = "hot";
3871                                 };
3872                         };
3873                 };
3874         };
3875 };