1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
70 compatible = "fixed-clock";
72 clock-frequency = <38400000>;
73 clock-output-names = "xo_board";
76 sleep_clk: sleep-clk {
77 compatible = "fixed-clock";
78 clock-frequency = <32768>;
89 compatible = "qcom,kryo485";
91 enable-method = "psci";
92 next-level-cache = <&L2_0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
97 next-level-cache = <&L3_0>;
106 compatible = "qcom,kryo485";
108 enable-method = "psci";
109 next-level-cache = <&L2_100>;
110 qcom,freq-domain = <&cpufreq_hw 0>;
111 #cooling-cells = <2>;
113 compatible = "cache";
114 next-level-cache = <&L3_0>;
120 compatible = "qcom,kryo485";
122 enable-method = "psci";
123 next-level-cache = <&L2_200>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
127 compatible = "cache";
128 next-level-cache = <&L3_0>;
134 compatible = "qcom,kryo485";
136 enable-method = "psci";
137 next-level-cache = <&L2_300>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
139 #cooling-cells = <2>;
141 compatible = "cache";
142 next-level-cache = <&L3_0>;
148 compatible = "qcom,kryo485";
150 enable-method = "psci";
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 #cooling-cells = <2>;
155 compatible = "cache";
156 next-level-cache = <&L3_0>;
162 compatible = "qcom,kryo485";
164 enable-method = "psci";
165 next-level-cache = <&L2_500>;
166 qcom,freq-domain = <&cpufreq_hw 1>;
167 #cooling-cells = <2>;
169 compatible = "cache";
170 next-level-cache = <&L3_0>;
177 compatible = "qcom,kryo485";
179 enable-method = "psci";
180 next-level-cache = <&L2_600>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
184 compatible = "cache";
185 next-level-cache = <&L3_0>;
191 compatible = "qcom,kryo485";
193 enable-method = "psci";
194 next-level-cache = <&L2_700>;
195 qcom,freq-domain = <&cpufreq_hw 2>;
196 #cooling-cells = <2>;
198 compatible = "cache";
199 next-level-cache = <&L3_0>;
206 compatible = "qcom,scm";
212 device_type = "memory";
213 /* We expect the bootloader to fill in the size */
214 reg = <0x0 0x80000000 0x0 0x0>;
218 compatible = "arm,armv8-pmuv3";
219 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
223 compatible = "arm,psci-1.0";
228 #address-cells = <2>;
232 hyp_mem: memory@80000000 {
233 reg = <0x0 0x80000000 0x0 0x600000>;
237 xbl_aop_mem: memory@80700000 {
238 reg = <0x0 0x80700000 0x0 0x160000>;
242 cmd_db: memory@80860000 {
243 compatible = "qcom,cmd-db";
244 reg = <0x0 0x80860000 0x0 0x20000>;
248 smem_mem: memory@80900000 {
249 reg = <0x0 0x80900000 0x0 0x200000>;
253 removed_mem: memory@80b00000 {
254 reg = <0x0 0x80b00000 0x0 0x5300000>;
258 camera_mem: memory@86200000 {
259 reg = <0x0 0x86200000 0x0 0x500000>;
263 wlan_mem: memory@86700000 {
264 reg = <0x0 0x86700000 0x0 0x100000>;
268 ipa_fw_mem: memory@86800000 {
269 reg = <0x0 0x86800000 0x0 0x10000>;
273 ipa_gsi_mem: memory@86810000 {
274 reg = <0x0 0x86810000 0x0 0xa000>;
278 gpu_mem: memory@8681a000 {
279 reg = <0x0 0x8681a000 0x0 0x2000>;
283 npu_mem: memory@86900000 {
284 reg = <0x0 0x86900000 0x0 0x500000>;
288 video_mem: memory@86e00000 {
289 reg = <0x0 0x86e00000 0x0 0x500000>;
293 cvp_mem: memory@87300000 {
294 reg = <0x0 0x87300000 0x0 0x500000>;
298 cdsp_mem: memory@87800000 {
299 reg = <0x0 0x87800000 0x0 0x1400000>;
303 slpi_mem: memory@88c00000 {
304 reg = <0x0 0x88c00000 0x0 0x1500000>;
308 adsp_mem: memory@8a100000 {
309 reg = <0x0 0x8a100000 0x0 0x1d00000>;
313 spss_mem: memory@8be00000 {
314 reg = <0x0 0x8be00000 0x0 0x100000>;
318 cdsp_secure_heap: memory@8bf00000 {
319 reg = <0x0 0x8bf00000 0x0 0x4600000>;
325 compatible = "qcom,smem";
326 memory-region = <&smem_mem>;
327 hwlocks = <&tcsr_mutex 3>;
331 compatible = "qcom,smp2p";
332 qcom,smem = <443>, <429>;
333 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
334 IPCC_MPROC_SIGNAL_SMP2P
335 IRQ_TYPE_EDGE_RISING>;
336 mboxes = <&ipcc IPCC_CLIENT_LPASS
337 IPCC_MPROC_SIGNAL_SMP2P>;
339 qcom,local-pid = <0>;
340 qcom,remote-pid = <2>;
342 smp2p_adsp_out: master-kernel {
343 qcom,entry-name = "master-kernel";
344 #qcom,smem-state-cells = <1>;
347 smp2p_adsp_in: slave-kernel {
348 qcom,entry-name = "slave-kernel";
349 interrupt-controller;
350 #interrupt-cells = <2>;
355 compatible = "qcom,smp2p";
356 qcom,smem = <94>, <432>;
357 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
358 IPCC_MPROC_SIGNAL_SMP2P
359 IRQ_TYPE_EDGE_RISING>;
360 mboxes = <&ipcc IPCC_CLIENT_CDSP
361 IPCC_MPROC_SIGNAL_SMP2P>;
363 qcom,local-pid = <0>;
364 qcom,remote-pid = <5>;
366 smp2p_cdsp_out: master-kernel {
367 qcom,entry-name = "master-kernel";
368 #qcom,smem-state-cells = <1>;
371 smp2p_cdsp_in: slave-kernel {
372 qcom,entry-name = "slave-kernel";
373 interrupt-controller;
374 #interrupt-cells = <2>;
379 compatible = "qcom,smp2p";
380 qcom,smem = <481>, <430>;
381 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
382 IPCC_MPROC_SIGNAL_SMP2P
383 IRQ_TYPE_EDGE_RISING>;
384 mboxes = <&ipcc IPCC_CLIENT_SLPI
385 IPCC_MPROC_SIGNAL_SMP2P>;
387 qcom,local-pid = <0>;
388 qcom,remote-pid = <3>;
390 smp2p_slpi_out: master-kernel {
391 qcom,entry-name = "master-kernel";
392 #qcom,smem-state-cells = <1>;
395 smp2p_slpi_in: slave-kernel {
396 qcom,entry-name = "slave-kernel";
397 interrupt-controller;
398 #interrupt-cells = <2>;
403 #address-cells = <2>;
405 ranges = <0 0 0 0 0x10 0>;
406 dma-ranges = <0 0 0 0 0x10 0>;
407 compatible = "simple-bus";
409 gcc: clock-controller@100000 {
410 compatible = "qcom,gcc-sm8250";
411 reg = <0x0 0x00100000 0x0 0x1f0000>;
414 #power-domain-cells = <1>;
415 clock-names = "bi_tcxo",
418 clocks = <&rpmhcc RPMH_CXO_CLK>,
419 <&rpmhcc RPMH_CXO_CLK_A>,
423 ipcc: mailbox@408000 {
424 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
425 reg = <0 0x00408000 0 0x1000>;
426 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-controller;
428 #interrupt-cells = <3>;
433 compatible = "qcom,prng-ee";
434 reg = <0 0x00793000 0 0x1000>;
435 clocks = <&gcc GCC_PRNG_AHB_CLK>;
436 clock-names = "core";
439 qup_opp_table: qup-opp-table {
440 compatible = "operating-points-v2";
443 opp-hz = /bits/ 64 <50000000>;
444 required-opps = <&rpmhpd_opp_min_svs>;
448 opp-hz = /bits/ 64 <75000000>;
449 required-opps = <&rpmhpd_opp_low_svs>;
453 opp-hz = /bits/ 64 <120000000>;
454 required-opps = <&rpmhpd_opp_svs>;
458 qupv3_id_2: geniqup@8c0000 {
459 compatible = "qcom,geni-se-qup";
460 reg = <0x0 0x008c0000 0x0 0x6000>;
461 clock-names = "m-ahb", "s-ahb";
462 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
463 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
464 #address-cells = <2>;
466 iommus = <&apps_smmu 0x63 0x0>;
471 compatible = "qcom,geni-i2c";
472 reg = <0 0x00880000 0 0x4000>;
474 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&qup_i2c14_default>;
477 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
484 compatible = "qcom,geni-spi";
485 reg = <0 0x00880000 0 0x4000>;
487 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&qup_spi14_default>;
490 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
493 power-domains = <&rpmhpd SM8250_CX>;
494 operating-points-v2 = <&qup_opp_table>;
499 compatible = "qcom,geni-i2c";
500 reg = <0 0x00884000 0 0x4000>;
502 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&qup_i2c15_default>;
505 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
512 compatible = "qcom,geni-spi";
513 reg = <0 0x00884000 0 0x4000>;
515 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&qup_spi15_default>;
518 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
519 #address-cells = <1>;
521 power-domains = <&rpmhpd SM8250_CX>;
522 operating-points-v2 = <&qup_opp_table>;
527 compatible = "qcom,geni-i2c";
528 reg = <0 0x00888000 0 0x4000>;
530 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&qup_i2c16_default>;
533 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
540 compatible = "qcom,geni-spi";
541 reg = <0 0x00888000 0 0x4000>;
543 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&qup_spi16_default>;
546 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
549 power-domains = <&rpmhpd SM8250_CX>;
550 operating-points-v2 = <&qup_opp_table>;
555 compatible = "qcom,geni-i2c";
556 reg = <0 0x0088c000 0 0x4000>;
558 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&qup_i2c17_default>;
561 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
562 #address-cells = <1>;
568 compatible = "qcom,geni-spi";
569 reg = <0 0x0088c000 0 0x4000>;
571 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&qup_spi17_default>;
574 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
575 #address-cells = <1>;
577 power-domains = <&rpmhpd SM8250_CX>;
578 operating-points-v2 = <&qup_opp_table>;
582 uart17: serial@88c000 {
583 compatible = "qcom,geni-uart";
584 reg = <0 0x0088c000 0 0x4000>;
586 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&qup_uart17_default>;
589 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
590 power-domains = <&rpmhpd SM8250_CX>;
591 operating-points-v2 = <&qup_opp_table>;
596 compatible = "qcom,geni-i2c";
597 reg = <0 0x00890000 0 0x4000>;
599 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&qup_i2c18_default>;
602 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
603 #address-cells = <1>;
609 compatible = "qcom,geni-spi";
610 reg = <0 0x00890000 0 0x4000>;
612 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&qup_spi18_default>;
615 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>;
618 power-domains = <&rpmhpd SM8250_CX>;
619 operating-points-v2 = <&qup_opp_table>;
623 uart18: serial@890000 {
624 compatible = "qcom,geni-uart";
625 reg = <0 0x00890000 0 0x4000>;
627 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&qup_uart18_default>;
630 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
631 power-domains = <&rpmhpd SM8250_CX>;
632 operating-points-v2 = <&qup_opp_table>;
637 compatible = "qcom,geni-i2c";
638 reg = <0 0x00894000 0 0x4000>;
640 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&qup_i2c19_default>;
643 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
644 #address-cells = <1>;
650 compatible = "qcom,geni-spi";
651 reg = <0 0x00894000 0 0x4000>;
653 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&qup_spi19_default>;
656 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells = <1>;
659 power-domains = <&rpmhpd SM8250_CX>;
660 operating-points-v2 = <&qup_opp_table>;
665 qupv3_id_0: geniqup@9c0000 {
666 compatible = "qcom,geni-se-qup";
667 reg = <0x0 0x009c0000 0x0 0x6000>;
668 clock-names = "m-ahb", "s-ahb";
669 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
670 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
671 #address-cells = <2>;
673 iommus = <&apps_smmu 0x5a3 0x0>;
678 compatible = "qcom,geni-i2c";
679 reg = <0 0x00980000 0 0x4000>;
681 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&qup_i2c0_default>;
684 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
691 compatible = "qcom,geni-spi";
692 reg = <0 0x00980000 0 0x4000>;
694 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&qup_spi0_default>;
697 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
698 #address-cells = <1>;
700 power-domains = <&rpmhpd SM8250_CX>;
701 operating-points-v2 = <&qup_opp_table>;
706 compatible = "qcom,geni-i2c";
707 reg = <0 0x00984000 0 0x4000>;
709 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&qup_i2c1_default>;
712 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
713 #address-cells = <1>;
719 compatible = "qcom,geni-spi";
720 reg = <0 0x00984000 0 0x4000>;
722 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&qup_spi1_default>;
725 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
726 #address-cells = <1>;
728 power-domains = <&rpmhpd SM8250_CX>;
729 operating-points-v2 = <&qup_opp_table>;
734 compatible = "qcom,geni-i2c";
735 reg = <0 0x00988000 0 0x4000>;
737 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
738 pinctrl-names = "default";
739 pinctrl-0 = <&qup_i2c2_default>;
740 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
741 #address-cells = <1>;
747 compatible = "qcom,geni-spi";
748 reg = <0 0x00988000 0 0x4000>;
750 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&qup_spi2_default>;
753 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
754 #address-cells = <1>;
756 power-domains = <&rpmhpd SM8250_CX>;
757 operating-points-v2 = <&qup_opp_table>;
761 uart2: serial@988000 {
762 compatible = "qcom,geni-debug-uart";
763 reg = <0 0x00988000 0 0x4000>;
765 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&qup_uart2_default>;
768 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
769 power-domains = <&rpmhpd SM8250_CX>;
770 operating-points-v2 = <&qup_opp_table>;
775 compatible = "qcom,geni-i2c";
776 reg = <0 0x0098c000 0 0x4000>;
778 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&qup_i2c3_default>;
781 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
782 #address-cells = <1>;
788 compatible = "qcom,geni-spi";
789 reg = <0 0x0098c000 0 0x4000>;
791 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
792 pinctrl-names = "default";
793 pinctrl-0 = <&qup_spi3_default>;
794 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
795 #address-cells = <1>;
797 power-domains = <&rpmhpd SM8250_CX>;
798 operating-points-v2 = <&qup_opp_table>;
803 compatible = "qcom,geni-i2c";
804 reg = <0 0x00990000 0 0x4000>;
806 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
807 pinctrl-names = "default";
808 pinctrl-0 = <&qup_i2c4_default>;
809 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
810 #address-cells = <1>;
816 compatible = "qcom,geni-spi";
817 reg = <0 0x00990000 0 0x4000>;
819 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
820 pinctrl-names = "default";
821 pinctrl-0 = <&qup_spi4_default>;
822 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
823 #address-cells = <1>;
825 power-domains = <&rpmhpd SM8250_CX>;
826 operating-points-v2 = <&qup_opp_table>;
831 compatible = "qcom,geni-i2c";
832 reg = <0 0x00994000 0 0x4000>;
834 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&qup_i2c5_default>;
837 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
838 #address-cells = <1>;
844 compatible = "qcom,geni-spi";
845 reg = <0 0x00994000 0 0x4000>;
847 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&qup_spi5_default>;
850 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
851 #address-cells = <1>;
853 power-domains = <&rpmhpd SM8250_CX>;
854 operating-points-v2 = <&qup_opp_table>;
859 compatible = "qcom,geni-i2c";
860 reg = <0 0x00998000 0 0x4000>;
862 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
863 pinctrl-names = "default";
864 pinctrl-0 = <&qup_i2c6_default>;
865 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
866 #address-cells = <1>;
872 compatible = "qcom,geni-spi";
873 reg = <0 0x00998000 0 0x4000>;
875 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
876 pinctrl-names = "default";
877 pinctrl-0 = <&qup_spi6_default>;
878 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
879 #address-cells = <1>;
881 power-domains = <&rpmhpd SM8250_CX>;
882 operating-points-v2 = <&qup_opp_table>;
886 uart6: serial@998000 {
887 compatible = "qcom,geni-uart";
888 reg = <0 0x00998000 0 0x4000>;
890 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_uart6_default>;
893 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
894 power-domains = <&rpmhpd SM8250_CX>;
895 operating-points-v2 = <&qup_opp_table>;
900 compatible = "qcom,geni-i2c";
901 reg = <0 0x0099c000 0 0x4000>;
903 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
904 pinctrl-names = "default";
905 pinctrl-0 = <&qup_i2c7_default>;
906 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
907 #address-cells = <1>;
913 compatible = "qcom,geni-spi";
914 reg = <0 0x0099c000 0 0x4000>;
916 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
917 pinctrl-names = "default";
918 pinctrl-0 = <&qup_spi7_default>;
919 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
920 #address-cells = <1>;
922 power-domains = <&rpmhpd SM8250_CX>;
923 operating-points-v2 = <&qup_opp_table>;
928 qupv3_id_1: geniqup@ac0000 {
929 compatible = "qcom,geni-se-qup";
930 reg = <0x0 0x00ac0000 0x0 0x6000>;
931 clock-names = "m-ahb", "s-ahb";
932 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
933 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
934 #address-cells = <2>;
936 iommus = <&apps_smmu 0x43 0x0>;
941 compatible = "qcom,geni-i2c";
942 reg = <0 0x00a80000 0 0x4000>;
944 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c8_default>;
947 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
948 #address-cells = <1>;
954 compatible = "qcom,geni-spi";
955 reg = <0 0x00a80000 0 0x4000>;
957 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
958 pinctrl-names = "default";
959 pinctrl-0 = <&qup_spi8_default>;
960 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
961 #address-cells = <1>;
963 power-domains = <&rpmhpd SM8250_CX>;
964 operating-points-v2 = <&qup_opp_table>;
969 compatible = "qcom,geni-i2c";
970 reg = <0 0x00a84000 0 0x4000>;
972 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_i2c9_default>;
975 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
976 #address-cells = <1>;
982 compatible = "qcom,geni-spi";
983 reg = <0 0x00a84000 0 0x4000>;
985 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&qup_spi9_default>;
988 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
989 #address-cells = <1>;
991 power-domains = <&rpmhpd SM8250_CX>;
992 operating-points-v2 = <&qup_opp_table>;
997 compatible = "qcom,geni-i2c";
998 reg = <0 0x00a88000 0 0x4000>;
1000 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&qup_i2c10_default>;
1003 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1004 #address-cells = <1>;
1006 status = "disabled";
1010 compatible = "qcom,geni-spi";
1011 reg = <0 0x00a88000 0 0x4000>;
1013 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1014 pinctrl-names = "default";
1015 pinctrl-0 = <&qup_spi10_default>;
1016 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1017 #address-cells = <1>;
1019 power-domains = <&rpmhpd SM8250_CX>;
1020 operating-points-v2 = <&qup_opp_table>;
1021 status = "disabled";
1025 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00a8c000 0 0x4000>;
1028 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1029 pinctrl-names = "default";
1030 pinctrl-0 = <&qup_i2c11_default>;
1031 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1032 #address-cells = <1>;
1034 status = "disabled";
1038 compatible = "qcom,geni-spi";
1039 reg = <0 0x00a8c000 0 0x4000>;
1041 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&qup_spi11_default>;
1044 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1045 #address-cells = <1>;
1047 power-domains = <&rpmhpd SM8250_CX>;
1048 operating-points-v2 = <&qup_opp_table>;
1049 status = "disabled";
1053 compatible = "qcom,geni-i2c";
1054 reg = <0 0x00a90000 0 0x4000>;
1056 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1057 pinctrl-names = "default";
1058 pinctrl-0 = <&qup_i2c12_default>;
1059 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1060 #address-cells = <1>;
1062 status = "disabled";
1066 compatible = "qcom,geni-spi";
1067 reg = <0 0x00a90000 0 0x4000>;
1069 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1070 pinctrl-names = "default";
1071 pinctrl-0 = <&qup_spi12_default>;
1072 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1073 #address-cells = <1>;
1075 power-domains = <&rpmhpd SM8250_CX>;
1076 operating-points-v2 = <&qup_opp_table>;
1077 status = "disabled";
1080 uart12: serial@a90000 {
1081 compatible = "qcom,geni-debug-uart";
1082 reg = <0x0 0x00a90000 0x0 0x4000>;
1084 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&qup_uart12_default>;
1087 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1088 power-domains = <&rpmhpd SM8250_CX>;
1089 operating-points-v2 = <&qup_opp_table>;
1090 status = "disabled";
1094 compatible = "qcom,geni-i2c";
1095 reg = <0 0x00a94000 0 0x4000>;
1097 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_i2c13_default>;
1100 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1101 #address-cells = <1>;
1103 status = "disabled";
1107 compatible = "qcom,geni-spi";
1108 reg = <0 0x00a94000 0 0x4000>;
1110 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&qup_spi13_default>;
1113 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1114 #address-cells = <1>;
1116 power-domains = <&rpmhpd SM8250_CX>;
1117 operating-points-v2 = <&qup_opp_table>;
1118 status = "disabled";
1122 config_noc: interconnect@1500000 {
1123 compatible = "qcom,sm8250-config-noc";
1124 reg = <0 0x01500000 0 0xa580>;
1125 #interconnect-cells = <1>;
1126 qcom,bcm-voters = <&apps_bcm_voter>;
1129 system_noc: interconnect@1620000 {
1130 compatible = "qcom,sm8250-system-noc";
1131 reg = <0 0x01620000 0 0x1c200>;
1132 #interconnect-cells = <1>;
1133 qcom,bcm-voters = <&apps_bcm_voter>;
1136 mc_virt: interconnect@163d000 {
1137 compatible = "qcom,sm8250-mc-virt";
1138 reg = <0 0x0163d000 0 0x1000>;
1139 #interconnect-cells = <1>;
1140 qcom,bcm-voters = <&apps_bcm_voter>;
1143 aggre1_noc: interconnect@16e0000 {
1144 compatible = "qcom,sm8250-aggre1-noc";
1145 reg = <0 0x016e0000 0 0x1f180>;
1146 #interconnect-cells = <1>;
1147 qcom,bcm-voters = <&apps_bcm_voter>;
1150 aggre2_noc: interconnect@1700000 {
1151 compatible = "qcom,sm8250-aggre2-noc";
1152 reg = <0 0x01700000 0 0x33000>;
1153 #interconnect-cells = <1>;
1154 qcom,bcm-voters = <&apps_bcm_voter>;
1157 compute_noc: interconnect@1733000 {
1158 compatible = "qcom,sm8250-compute-noc";
1159 reg = <0 0x01733000 0 0xa180>;
1160 #interconnect-cells = <1>;
1161 qcom,bcm-voters = <&apps_bcm_voter>;
1164 mmss_noc: interconnect@1740000 {
1165 compatible = "qcom,sm8250-mmss-noc";
1166 reg = <0 0x01740000 0 0x1f080>;
1167 #interconnect-cells = <1>;
1168 qcom,bcm-voters = <&apps_bcm_voter>;
1171 ufs_mem_hc: ufshc@1d84000 {
1172 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1174 reg = <0 0x01d84000 0 0x3000>;
1175 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1176 phys = <&ufs_mem_phy_lanes>;
1177 phy-names = "ufsphy";
1178 lanes-per-direction = <2>;
1180 resets = <&gcc GCC_UFS_PHY_BCR>;
1181 reset-names = "rst";
1183 power-domains = <&gcc UFS_PHY_GDSC>;
1185 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1193 "tx_lane0_sync_clk",
1194 "rx_lane0_sync_clk",
1195 "rx_lane1_sync_clk";
1197 <&gcc GCC_UFS_PHY_AXI_CLK>,
1198 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1199 <&gcc GCC_UFS_PHY_AHB_CLK>,
1200 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1201 <&rpmhcc RPMH_CXO_CLK>,
1202 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1203 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1204 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1206 <37500000 300000000>,
1209 <37500000 300000000>,
1215 status = "disabled";
1218 ufs_mem_phy: phy@1d87000 {
1219 compatible = "qcom,sm8250-qmp-ufs-phy";
1220 reg = <0 0x01d87000 0 0x1c0>;
1221 #address-cells = <2>;
1224 clock-names = "ref",
1226 clocks = <&rpmhcc RPMH_CXO_CLK>,
1227 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1229 resets = <&ufs_mem_hc 0>;
1230 reset-names = "ufsphy";
1231 status = "disabled";
1233 ufs_mem_phy_lanes: lanes@1d87400 {
1234 reg = <0 0x01d87400 0 0x108>,
1235 <0 0x01d87600 0 0x1e0>,
1236 <0 0x01d87c00 0 0x1dc>,
1237 <0 0x01d87800 0 0x108>,
1238 <0 0x01d87a00 0 0x1e0>;
1243 ipa_virt: interconnect@1e00000 {
1244 compatible = "qcom,sm8250-ipa-virt";
1245 reg = <0 0x01e00000 0 0x1000>;
1246 #interconnect-cells = <1>;
1247 qcom,bcm-voters = <&apps_bcm_voter>;
1250 tcsr_mutex: hwlock@1f40000 {
1251 compatible = "qcom,tcsr-mutex";
1252 reg = <0x0 0x01f40000 0x0 0x40000>;
1253 #hwlock-cells = <1>;
1258 * note: the amd,imageon compatible makes it possible
1259 * to use the drm/msm driver without the display node,
1260 * make sure to remove it when display node is added
1262 compatible = "qcom,adreno-650.2",
1265 #stream-id-cells = <16>;
1267 reg = <0 0x03d00000 0 0x40000>;
1268 reg-names = "kgsl_3d0_reg_memory";
1270 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1272 iommus = <&adreno_smmu 0 0x401>;
1274 operating-points-v2 = <&gpu_opp_table>;
1279 memory-region = <&gpu_mem>;
1282 /* note: downstream checks gpu binning for 670 Mhz */
1283 gpu_opp_table: opp-table {
1284 compatible = "operating-points-v2";
1287 opp-hz = /bits/ 64 <670000000>;
1288 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1292 opp-hz = /bits/ 64 <587000000>;
1293 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1297 opp-hz = /bits/ 64 <525000000>;
1298 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1302 opp-hz = /bits/ 64 <490000000>;
1303 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1307 opp-hz = /bits/ 64 <441600000>;
1308 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1312 opp-hz = /bits/ 64 <400000000>;
1313 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1317 opp-hz = /bits/ 64 <305000000>;
1318 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1324 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1326 reg = <0 0x03d6a000 0 0x30000>,
1327 <0 0x3de0000 0 0x10000>,
1328 <0 0xb290000 0 0x10000>,
1329 <0 0xb490000 0 0x10000>;
1330 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1332 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1334 interrupt-names = "hfi", "gmu";
1336 clocks = <&gpucc GPU_CC_AHB_CLK>,
1337 <&gpucc GPU_CC_CX_GMU_CLK>,
1338 <&gpucc GPU_CC_CXO_CLK>,
1339 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1340 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1343 power-domains = <&gpucc GPU_CX_GDSC>,
1344 <&gpucc GPU_GX_GDSC>;
1345 power-domain-names = "cx", "gx";
1347 iommus = <&adreno_smmu 5 0x400>;
1349 operating-points-v2 = <&gmu_opp_table>;
1351 gmu_opp_table: opp-table {
1352 compatible = "operating-points-v2";
1355 opp-hz = /bits/ 64 <200000000>;
1356 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1361 gpucc: clock-controller@3d90000 {
1362 compatible = "qcom,sm8250-gpucc";
1363 reg = <0 0x03d90000 0 0x9000>;
1364 clocks = <&rpmhcc RPMH_CXO_CLK>,
1365 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1366 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1367 clock-names = "bi_tcxo",
1368 "gcc_gpu_gpll0_clk_src",
1369 "gcc_gpu_gpll0_div_clk_src";
1372 #power-domain-cells = <1>;
1375 adreno_smmu: iommu@3da0000 {
1376 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1377 reg = <0 0x03da0000 0 0x10000>;
1379 #global-interrupts = <2>;
1380 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&gpucc GPU_CC_AHB_CLK>,
1391 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1392 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1393 clock-names = "ahb", "bus", "iface";
1395 power-domains = <&gpucc GPU_CX_GDSC>;
1398 slpi: remoteproc@5c00000 {
1399 compatible = "qcom,sm8250-slpi-pas";
1400 reg = <0 0x05c00000 0 0x4000>;
1402 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1403 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1404 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1405 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1406 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1407 interrupt-names = "wdog", "fatal", "ready",
1408 "handover", "stop-ack";
1410 clocks = <&rpmhcc RPMH_CXO_CLK>;
1413 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1414 <&rpmhpd SM8250_LCX>,
1415 <&rpmhpd SM8250_LMX>;
1416 power-domain-names = "load_state", "lcx", "lmx";
1418 memory-region = <&slpi_mem>;
1420 qcom,smem-states = <&smp2p_slpi_out 0>;
1421 qcom,smem-state-names = "stop";
1423 status = "disabled";
1426 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1427 IPCC_MPROC_SIGNAL_GLINK_QMP
1428 IRQ_TYPE_EDGE_RISING>;
1429 mboxes = <&ipcc IPCC_CLIENT_SLPI
1430 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1433 qcom,remote-pid = <3>;
1436 compatible = "qcom,fastrpc";
1437 qcom,glink-channels = "fastrpcglink-apps-dsp";
1439 #address-cells = <1>;
1443 compatible = "qcom,fastrpc-compute-cb";
1445 iommus = <&apps_smmu 0x0541 0x0>;
1449 compatible = "qcom,fastrpc-compute-cb";
1451 iommus = <&apps_smmu 0x0542 0x0>;
1455 compatible = "qcom,fastrpc-compute-cb";
1457 iommus = <&apps_smmu 0x0543 0x0>;
1458 /* note: shared-cb = <4> in downstream */
1464 cdsp: remoteproc@8300000 {
1465 compatible = "qcom,sm8250-cdsp-pas";
1466 reg = <0 0x08300000 0 0x10000>;
1468 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1469 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1470 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1471 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1472 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1473 interrupt-names = "wdog", "fatal", "ready",
1474 "handover", "stop-ack";
1476 clocks = <&rpmhcc RPMH_CXO_CLK>;
1479 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1480 <&rpmhpd SM8250_CX>;
1481 power-domain-names = "load_state", "cx";
1483 memory-region = <&cdsp_mem>;
1485 qcom,smem-states = <&smp2p_cdsp_out 0>;
1486 qcom,smem-state-names = "stop";
1488 status = "disabled";
1491 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1492 IPCC_MPROC_SIGNAL_GLINK_QMP
1493 IRQ_TYPE_EDGE_RISING>;
1494 mboxes = <&ipcc IPCC_CLIENT_CDSP
1495 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1498 qcom,remote-pid = <5>;
1501 compatible = "qcom,fastrpc";
1502 qcom,glink-channels = "fastrpcglink-apps-dsp";
1504 #address-cells = <1>;
1508 compatible = "qcom,fastrpc-compute-cb";
1510 iommus = <&apps_smmu 0x1001 0x0460>;
1514 compatible = "qcom,fastrpc-compute-cb";
1516 iommus = <&apps_smmu 0x1002 0x0460>;
1520 compatible = "qcom,fastrpc-compute-cb";
1522 iommus = <&apps_smmu 0x1003 0x0460>;
1526 compatible = "qcom,fastrpc-compute-cb";
1528 iommus = <&apps_smmu 0x1004 0x0460>;
1532 compatible = "qcom,fastrpc-compute-cb";
1534 iommus = <&apps_smmu 0x1005 0x0460>;
1538 compatible = "qcom,fastrpc-compute-cb";
1540 iommus = <&apps_smmu 0x1006 0x0460>;
1544 compatible = "qcom,fastrpc-compute-cb";
1546 iommus = <&apps_smmu 0x1007 0x0460>;
1550 compatible = "qcom,fastrpc-compute-cb";
1552 iommus = <&apps_smmu 0x1008 0x0460>;
1555 /* note: secure cb9 in downstream */
1560 usb_1_hsphy: phy@88e3000 {
1561 compatible = "qcom,sm8250-usb-hs-phy",
1562 "qcom,usb-snps-hs-7nm-phy";
1563 reg = <0 0x088e3000 0 0x400>;
1564 status = "disabled";
1567 clocks = <&rpmhcc RPMH_CXO_CLK>;
1568 clock-names = "ref";
1570 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1573 usb_2_hsphy: phy@88e4000 {
1574 compatible = "qcom,sm8250-usb-hs-phy",
1575 "qcom,usb-snps-hs-7nm-phy";
1576 reg = <0 0x088e4000 0 0x400>;
1577 status = "disabled";
1580 clocks = <&rpmhcc RPMH_CXO_CLK>;
1581 clock-names = "ref";
1583 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1586 usb_1_qmpphy: phy@88e9000 {
1587 compatible = "qcom,sm8250-qmp-usb3-phy";
1588 reg = <0 0x088e9000 0 0x200>,
1589 <0 0x088e8000 0 0x20>;
1590 reg-names = "reg-base", "dp_com";
1591 status = "disabled";
1593 #address-cells = <2>;
1597 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1598 <&rpmhcc RPMH_CXO_CLK>,
1599 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1600 clock-names = "aux", "ref_clk_src", "com_aux";
1602 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1603 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1604 reset-names = "phy", "common";
1606 usb_1_ssphy: lanes@88e9200 {
1607 reg = <0 0x088e9200 0 0x200>,
1608 <0 0x088e9400 0 0x200>,
1609 <0 0x088e9c00 0 0x400>,
1610 <0 0x088e9600 0 0x200>,
1611 <0 0x088e9800 0 0x200>,
1612 <0 0x088e9a00 0 0x100>;
1614 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1615 clock-names = "pipe0";
1616 clock-output-names = "usb3_phy_pipe_clk_src";
1620 usb_2_qmpphy: phy@88eb000 {
1621 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
1622 reg = <0 0x088eb000 0 0x200>;
1623 status = "disabled";
1625 #address-cells = <2>;
1629 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1630 <&rpmhcc RPMH_CXO_CLK>,
1631 <&gcc GCC_USB3_SEC_CLKREF_EN>,
1632 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1633 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1635 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1636 <&gcc GCC_USB3_PHY_SEC_BCR>;
1637 reset-names = "phy", "common";
1639 usb_2_ssphy: lane@88eb200 {
1640 reg = <0 0x088eb200 0 0x200>,
1641 <0 0x088eb400 0 0x200>,
1642 <0 0x088eb800 0 0x800>;
1644 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1645 clock-names = "pipe0";
1646 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1650 sdhc_2: sdhci@8804000 {
1651 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
1652 reg = <0 0x08804000 0 0x1000>;
1654 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1656 interrupt-names = "hc_irq", "pwr_irq";
1658 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1659 <&gcc GCC_SDCC2_APPS_CLK>,
1661 clock-names = "iface", "core", "xo";
1662 iommus = <&apps_smmu 0x4a0 0x0>;
1663 qcom,dll-config = <0x0007642c>;
1664 qcom,ddr-config = <0x80040868>;
1665 power-domains = <&rpmhpd SM8250_CX>;
1666 operating-points-v2 = <&sdhc2_opp_table>;
1668 status = "disabled";
1670 sdhc2_opp_table: sdhc2-opp-table {
1671 compatible = "operating-points-v2";
1674 opp-hz = /bits/ 64 <19200000>;
1675 required-opps = <&rpmhpd_opp_min_svs>;
1679 opp-hz = /bits/ 64 <50000000>;
1680 required-opps = <&rpmhpd_opp_low_svs>;
1684 opp-hz = /bits/ 64 <100000000>;
1685 required-opps = <&rpmhpd_opp_svs>;
1689 opp-hz = /bits/ 64 <202000000>;
1690 required-opps = <&rpmhpd_opp_svs_l1>;
1695 dc_noc: interconnect@90c0000 {
1696 compatible = "qcom,sm8250-dc-noc";
1697 reg = <0 0x090c0000 0 0x4200>;
1698 #interconnect-cells = <1>;
1699 qcom,bcm-voters = <&apps_bcm_voter>;
1702 gem_noc: interconnect@9100000 {
1703 compatible = "qcom,sm8250-gem-noc";
1704 reg = <0 0x09100000 0 0xb4000>;
1705 #interconnect-cells = <1>;
1706 qcom,bcm-voters = <&apps_bcm_voter>;
1709 npu_noc: interconnect@9990000 {
1710 compatible = "qcom,sm8250-npu-noc";
1711 reg = <0 0x09990000 0 0x1600>;
1712 #interconnect-cells = <1>;
1713 qcom,bcm-voters = <&apps_bcm_voter>;
1716 usb_1: usb@a6f8800 {
1717 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1718 reg = <0 0x0a6f8800 0 0x400>;
1719 status = "disabled";
1720 #address-cells = <2>;
1725 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1726 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1727 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1728 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1729 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1730 <&gcc GCC_USB3_SEC_CLKREF_EN>;
1731 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1734 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1735 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1736 assigned-clock-rates = <19200000>, <200000000>;
1738 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1739 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1740 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1741 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1742 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1743 "dm_hs_phy_irq", "ss_phy_irq";
1745 power-domains = <&gcc USB30_PRIM_GDSC>;
1747 resets = <&gcc GCC_USB30_PRIM_BCR>;
1749 usb_1_dwc3: dwc3@a600000 {
1750 compatible = "snps,dwc3";
1751 reg = <0 0x0a600000 0 0xcd00>;
1752 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1753 iommus = <&apps_smmu 0x0 0x0>;
1754 snps,dis_u2_susphy_quirk;
1755 snps,dis_enblslpm_quirk;
1756 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1757 phy-names = "usb2-phy", "usb3-phy";
1761 usb_2: usb@a8f8800 {
1762 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1763 reg = <0 0x0a8f8800 0 0x400>;
1764 status = "disabled";
1765 #address-cells = <2>;
1770 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1771 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1772 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1773 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1774 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1775 <&gcc GCC_USB3_SEC_CLKREF_EN>;
1776 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1779 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1780 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1781 assigned-clock-rates = <19200000>, <200000000>;
1783 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1784 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1785 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1786 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1787 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1788 "dm_hs_phy_irq", "ss_phy_irq";
1790 power-domains = <&gcc USB30_SEC_GDSC>;
1792 resets = <&gcc GCC_USB30_SEC_BCR>;
1794 usb_2_dwc3: dwc3@a800000 {
1795 compatible = "snps,dwc3";
1796 reg = <0 0x0a800000 0 0xcd00>;
1797 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1798 iommus = <&apps_smmu 0x20 0>;
1799 snps,dis_u2_susphy_quirk;
1800 snps,dis_enblslpm_quirk;
1801 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1802 phy-names = "usb2-phy", "usb3-phy";
1806 pdc: interrupt-controller@b220000 {
1807 compatible = "qcom,sm8250-pdc", "qcom,pdc";
1808 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1809 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1810 <125 63 1>, <126 716 12>;
1811 #interrupt-cells = <2>;
1812 interrupt-parent = <&intc>;
1813 interrupt-controller;
1816 tsens0: thermal-sensor@c263000 {
1817 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1818 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1819 <0 0x0c222000 0 0x1ff>; /* SROT */
1820 #qcom,sensors = <16>;
1821 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1823 interrupt-names = "uplow", "critical";
1824 #thermal-sensor-cells = <1>;
1827 tsens1: thermal-sensor@c265000 {
1828 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1829 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1830 <0 0x0c223000 0 0x1ff>; /* SROT */
1831 #qcom,sensors = <9>;
1832 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1834 interrupt-names = "uplow", "critical";
1835 #thermal-sensor-cells = <1>;
1838 aoss_qmp: qmp@c300000 {
1839 compatible = "qcom,sm8250-aoss-qmp";
1840 reg = <0 0x0c300000 0 0x100000>;
1841 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1842 IPCC_MPROC_SIGNAL_GLINK_QMP
1843 IRQ_TYPE_EDGE_RISING>;
1844 mboxes = <&ipcc IPCC_CLIENT_AOP
1845 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1848 #power-domain-cells = <1>;
1851 spmi_bus: spmi@c440000 {
1852 compatible = "qcom,spmi-pmic-arb";
1853 reg = <0x0 0x0c440000 0x0 0x0001100>,
1854 <0x0 0x0c600000 0x0 0x2000000>,
1855 <0x0 0x0e600000 0x0 0x0100000>,
1856 <0x0 0x0e700000 0x0 0x00a0000>,
1857 <0x0 0x0c40a000 0x0 0x0026000>;
1858 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1859 interrupt-names = "periph_irq";
1860 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1863 #address-cells = <2>;
1865 interrupt-controller;
1866 #interrupt-cells = <4>;
1869 tlmm: pinctrl@f100000 {
1870 compatible = "qcom,sm8250-pinctrl";
1871 reg = <0 0x0f100000 0 0x300000>,
1872 <0 0x0f500000 0 0x300000>,
1873 <0 0x0f900000 0 0x300000>;
1874 reg-names = "west", "south", "north";
1875 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1878 interrupt-controller;
1879 #interrupt-cells = <2>;
1880 gpio-ranges = <&tlmm 0 0 180>;
1881 wakeup-parent = <&pdc>;
1883 qup_i2c0_default: qup-i2c0-default {
1885 pins = "gpio28", "gpio29";
1890 pins = "gpio28", "gpio29";
1891 drive-strength = <2>;
1896 qup_i2c1_default: qup-i2c1-default {
1898 pins = "gpio4", "gpio5";
1903 pins = "gpio4", "gpio5";
1904 drive-strength = <2>;
1909 qup_i2c2_default: qup-i2c2-default {
1911 pins = "gpio115", "gpio116";
1916 pins = "gpio115", "gpio116";
1917 drive-strength = <2>;
1922 qup_i2c3_default: qup-i2c3-default {
1924 pins = "gpio119", "gpio120";
1929 pins = "gpio119", "gpio120";
1930 drive-strength = <2>;
1935 qup_i2c4_default: qup-i2c4-default {
1937 pins = "gpio8", "gpio9";
1942 pins = "gpio8", "gpio9";
1943 drive-strength = <2>;
1948 qup_i2c5_default: qup-i2c5-default {
1950 pins = "gpio12", "gpio13";
1955 pins = "gpio12", "gpio13";
1956 drive-strength = <2>;
1961 qup_i2c6_default: qup-i2c6-default {
1963 pins = "gpio16", "gpio17";
1968 pins = "gpio16", "gpio17";
1969 drive-strength = <2>;
1974 qup_i2c7_default: qup-i2c7-default {
1976 pins = "gpio20", "gpio21";
1981 pins = "gpio20", "gpio21";
1982 drive-strength = <2>;
1987 qup_i2c8_default: qup-i2c8-default {
1989 pins = "gpio24", "gpio25";
1994 pins = "gpio24", "gpio25";
1995 drive-strength = <2>;
2000 qup_i2c9_default: qup-i2c9-default {
2002 pins = "gpio125", "gpio126";
2007 pins = "gpio125", "gpio126";
2008 drive-strength = <2>;
2013 qup_i2c10_default: qup-i2c10-default {
2015 pins = "gpio129", "gpio130";
2020 pins = "gpio129", "gpio130";
2021 drive-strength = <2>;
2026 qup_i2c11_default: qup-i2c11-default {
2028 pins = "gpio60", "gpio61";
2033 pins = "gpio60", "gpio61";
2034 drive-strength = <2>;
2039 qup_i2c12_default: qup-i2c12-default {
2041 pins = "gpio32", "gpio33";
2046 pins = "gpio32", "gpio33";
2047 drive-strength = <2>;
2052 qup_i2c13_default: qup-i2c13-default {
2054 pins = "gpio36", "gpio37";
2059 pins = "gpio36", "gpio37";
2060 drive-strength = <2>;
2065 qup_i2c14_default: qup-i2c14-default {
2067 pins = "gpio40", "gpio41";
2072 pins = "gpio40", "gpio41";
2073 drive-strength = <2>;
2078 qup_i2c15_default: qup-i2c15-default {
2080 pins = "gpio44", "gpio45";
2085 pins = "gpio44", "gpio45";
2086 drive-strength = <2>;
2091 qup_i2c16_default: qup-i2c16-default {
2093 pins = "gpio48", "gpio49";
2098 pins = "gpio48", "gpio49";
2099 drive-strength = <2>;
2104 qup_i2c17_default: qup-i2c17-default {
2106 pins = "gpio52", "gpio53";
2111 pins = "gpio52", "gpio53";
2112 drive-strength = <2>;
2117 qup_i2c18_default: qup-i2c18-default {
2119 pins = "gpio56", "gpio57";
2124 pins = "gpio56", "gpio57";
2125 drive-strength = <2>;
2130 qup_i2c19_default: qup-i2c19-default {
2132 pins = "gpio0", "gpio1";
2137 pins = "gpio0", "gpio1";
2138 drive-strength = <2>;
2143 qup_spi0_default: qup-spi0-default {
2145 pins = "gpio28", "gpio29",
2151 pins = "gpio28", "gpio29",
2153 drive-strength = <6>;
2158 qup_spi1_default: qup-spi1-default {
2160 pins = "gpio4", "gpio5",
2166 pins = "gpio4", "gpio5",
2168 drive-strength = <6>;
2173 qup_spi2_default: qup-spi2-default {
2175 pins = "gpio115", "gpio116",
2176 "gpio117", "gpio118";
2181 pins = "gpio115", "gpio116",
2182 "gpio117", "gpio118";
2183 drive-strength = <6>;
2188 qup_spi3_default: qup-spi3-default {
2190 pins = "gpio119", "gpio120",
2191 "gpio121", "gpio122";
2196 pins = "gpio119", "gpio120",
2197 "gpio121", "gpio122";
2198 drive-strength = <6>;
2203 qup_spi4_default: qup-spi4-default {
2205 pins = "gpio8", "gpio9",
2211 pins = "gpio8", "gpio9",
2213 drive-strength = <6>;
2218 qup_spi5_default: qup-spi5-default {
2220 pins = "gpio12", "gpio13",
2226 pins = "gpio12", "gpio13",
2228 drive-strength = <6>;
2233 qup_spi6_default: qup-spi6-default {
2235 pins = "gpio16", "gpio17",
2241 pins = "gpio16", "gpio17",
2243 drive-strength = <6>;
2248 qup_spi7_default: qup-spi7-default {
2250 pins = "gpio20", "gpio21",
2256 pins = "gpio20", "gpio21",
2258 drive-strength = <6>;
2263 qup_spi8_default: qup-spi8-default {
2265 pins = "gpio24", "gpio25",
2271 pins = "gpio24", "gpio25",
2273 drive-strength = <6>;
2278 qup_spi9_default: qup-spi9-default {
2280 pins = "gpio125", "gpio126",
2281 "gpio127", "gpio128";
2286 pins = "gpio125", "gpio126",
2287 "gpio127", "gpio128";
2288 drive-strength = <6>;
2293 qup_spi10_default: qup-spi10-default {
2295 pins = "gpio129", "gpio130",
2296 "gpio131", "gpio132";
2301 pins = "gpio129", "gpio130",
2302 "gpio131", "gpio132";
2303 drive-strength = <6>;
2308 qup_spi11_default: qup-spi11-default {
2310 pins = "gpio60", "gpio61",
2316 pins = "gpio60", "gpio61",
2318 drive-strength = <6>;
2323 qup_spi12_default: qup-spi12-default {
2325 pins = "gpio32", "gpio33",
2331 pins = "gpio32", "gpio33",
2333 drive-strength = <6>;
2338 qup_spi13_default: qup-spi13-default {
2340 pins = "gpio36", "gpio37",
2346 pins = "gpio36", "gpio37",
2348 drive-strength = <6>;
2353 qup_spi14_default: qup-spi14-default {
2355 pins = "gpio40", "gpio41",
2361 pins = "gpio40", "gpio41",
2363 drive-strength = <6>;
2368 qup_spi15_default: qup-spi15-default {
2370 pins = "gpio44", "gpio45",
2376 pins = "gpio44", "gpio45",
2378 drive-strength = <6>;
2383 qup_spi16_default: qup-spi16-default {
2385 pins = "gpio48", "gpio49",
2391 pins = "gpio48", "gpio49",
2393 drive-strength = <6>;
2398 qup_spi17_default: qup-spi17-default {
2400 pins = "gpio52", "gpio53",
2406 pins = "gpio52", "gpio53",
2408 drive-strength = <6>;
2413 qup_spi18_default: qup-spi18-default {
2415 pins = "gpio56", "gpio57",
2421 pins = "gpio56", "gpio57",
2423 drive-strength = <6>;
2428 qup_spi19_default: qup-spi19-default {
2430 pins = "gpio0", "gpio1",
2436 pins = "gpio0", "gpio1",
2438 drive-strength = <6>;
2443 qup_uart2_default: qup-uart2-default {
2445 pins = "gpio117", "gpio118";
2450 qup_uart6_default: qup-uart6-default {
2452 pins = "gpio16", "gpio17",
2458 qup_uart12_default: qup-uart12-default {
2460 pins = "gpio34", "gpio35";
2465 qup_uart17_default: qup-uart17-default {
2467 pins = "gpio52", "gpio53",
2473 qup_uart18_default: qup-uart18-default {
2475 pins = "gpio58", "gpio59";
2481 apps_smmu: iommu@15000000 {
2482 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2483 reg = <0 0x15000000 0 0x100000>;
2485 #global-interrupts = <2>;
2486 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2487 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2488 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2489 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2490 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2491 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2492 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2493 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2494 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2495 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2496 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2497 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2498 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2499 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2500 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2501 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2502 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2503 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2504 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2505 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2506 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2507 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2508 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2509 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2510 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2511 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2512 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2513 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2514 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2515 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2516 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2517 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2518 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2519 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2520 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2521 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2522 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2523 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2524 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2525 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2526 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2527 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2528 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2529 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2530 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2531 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2532 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2533 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2534 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2535 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2536 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2537 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2538 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2539 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2540 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2541 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2542 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2543 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2544 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2545 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2546 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2547 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2548 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2549 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2550 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2551 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2552 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2553 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2554 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2555 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2556 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2557 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2558 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2559 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2560 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2561 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2562 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2563 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2564 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2565 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2566 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2567 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2568 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2569 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2570 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2571 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2572 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2573 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2574 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2575 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2578 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2579 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2580 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2581 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
2583 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
2586 adsp: remoteproc@17300000 {
2587 compatible = "qcom,sm8250-adsp-pas";
2588 reg = <0 0x17300000 0 0x100>;
2590 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2591 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2592 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2593 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2594 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2595 interrupt-names = "wdog", "fatal", "ready",
2596 "handover", "stop-ack";
2598 clocks = <&rpmhcc RPMH_CXO_CLK>;
2601 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2602 <&rpmhpd SM8250_LCX>,
2603 <&rpmhpd SM8250_LMX>;
2604 power-domain-names = "load_state", "lcx", "lmx";
2606 memory-region = <&adsp_mem>;
2608 qcom,smem-states = <&smp2p_adsp_out 0>;
2609 qcom,smem-state-names = "stop";
2611 status = "disabled";
2614 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2615 IPCC_MPROC_SIGNAL_GLINK_QMP
2616 IRQ_TYPE_EDGE_RISING>;
2617 mboxes = <&ipcc IPCC_CLIENT_LPASS
2618 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2621 qcom,remote-pid = <2>;
2624 compatible = "qcom,fastrpc";
2625 qcom,glink-channels = "fastrpcglink-apps-dsp";
2627 #address-cells = <1>;
2631 compatible = "qcom,fastrpc-compute-cb";
2633 iommus = <&apps_smmu 0x1803 0x0>;
2637 compatible = "qcom,fastrpc-compute-cb";
2639 iommus = <&apps_smmu 0x1804 0x0>;
2643 compatible = "qcom,fastrpc-compute-cb";
2645 iommus = <&apps_smmu 0x1805 0x0>;
2651 intc: interrupt-controller@17a00000 {
2652 compatible = "arm,gic-v3";
2653 #interrupt-cells = <3>;
2654 interrupt-controller;
2655 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2656 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2657 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2661 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
2662 reg = <0 0x17c10000 0 0x1000>;
2663 clocks = <&sleep_clk>;
2667 #address-cells = <2>;
2670 compatible = "arm,armv7-timer-mem";
2671 reg = <0x0 0x17c20000 0x0 0x1000>;
2672 clock-frequency = <19200000>;
2676 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2677 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2678 reg = <0x0 0x17c21000 0x0 0x1000>,
2679 <0x0 0x17c22000 0x0 0x1000>;
2684 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2685 reg = <0x0 0x17c23000 0x0 0x1000>;
2686 status = "disabled";
2691 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2692 reg = <0x0 0x17c25000 0x0 0x1000>;
2693 status = "disabled";
2698 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2699 reg = <0x0 0x17c27000 0x0 0x1000>;
2700 status = "disabled";
2705 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2706 reg = <0x0 0x17c29000 0x0 0x1000>;
2707 status = "disabled";
2712 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2713 reg = <0x0 0x17c2b000 0x0 0x1000>;
2714 status = "disabled";
2719 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2720 reg = <0x0 0x17c2d000 0x0 0x1000>;
2721 status = "disabled";
2725 apps_rsc: rsc@18200000 {
2727 compatible = "qcom,rpmh-rsc";
2728 reg = <0x0 0x18200000 0x0 0x10000>,
2729 <0x0 0x18210000 0x0 0x10000>,
2730 <0x0 0x18220000 0x0 0x10000>;
2731 reg-names = "drv-0", "drv-1", "drv-2";
2732 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2733 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2734 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2735 qcom,tcs-offset = <0xd00>;
2737 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2738 <WAKE_TCS 3>, <CONTROL_TCS 1>;
2740 rpmhcc: clock-controller {
2741 compatible = "qcom,sm8250-rpmh-clk";
2744 clocks = <&xo_board>;
2747 rpmhpd: power-controller {
2748 compatible = "qcom,sm8250-rpmhpd";
2749 #power-domain-cells = <1>;
2750 operating-points-v2 = <&rpmhpd_opp_table>;
2752 rpmhpd_opp_table: opp-table {
2753 compatible = "operating-points-v2";
2755 rpmhpd_opp_ret: opp1 {
2756 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2759 rpmhpd_opp_min_svs: opp2 {
2760 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2763 rpmhpd_opp_low_svs: opp3 {
2764 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2767 rpmhpd_opp_svs: opp4 {
2768 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2771 rpmhpd_opp_svs_l1: opp5 {
2772 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2775 rpmhpd_opp_nom: opp6 {
2776 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2779 rpmhpd_opp_nom_l1: opp7 {
2780 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2783 rpmhpd_opp_nom_l2: opp8 {
2784 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2787 rpmhpd_opp_turbo: opp9 {
2788 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2791 rpmhpd_opp_turbo_l1: opp10 {
2792 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2797 apps_bcm_voter: bcm_voter {
2798 compatible = "qcom,bcm-voter";
2802 epss_l3: interconnect@18591000 {
2803 compatible = "qcom,sm8250-epss-l3";
2804 reg = <0 0x18590000 0 0x1000>;
2806 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2807 clock-names = "xo", "alternate";
2809 #interconnect-cells = <1>;
2812 cpufreq_hw: cpufreq@18591000 {
2813 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
2814 reg = <0 0x18591000 0 0x1000>,
2815 <0 0x18592000 0 0x1000>,
2816 <0 0x18593000 0 0x1000>;
2817 reg-names = "freq-domain0", "freq-domain1",
2820 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2821 clock-names = "xo", "alternate";
2823 #freq-domain-cells = <1>;
2828 compatible = "arm,armv8-timer";
2829 interrupts = <GIC_PPI 13
2830 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2832 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2834 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2836 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2841 polling-delay-passive = <250>;
2842 polling-delay = <1000>;
2844 thermal-sensors = <&tsens0 1>;
2847 cpu0_alert0: trip-point0 {
2848 temperature = <90000>;
2849 hysteresis = <2000>;
2853 cpu0_alert1: trip-point1 {
2854 temperature = <95000>;
2855 hysteresis = <2000>;
2859 cpu0_crit: cpu_crit {
2860 temperature = <110000>;
2861 hysteresis = <1000>;
2868 trip = <&cpu0_alert0>;
2869 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2870 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2871 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2872 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2875 trip = <&cpu0_alert1>;
2876 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2877 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2878 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2879 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2885 polling-delay-passive = <250>;
2886 polling-delay = <1000>;
2888 thermal-sensors = <&tsens0 2>;
2891 cpu1_alert0: trip-point0 {
2892 temperature = <90000>;
2893 hysteresis = <2000>;
2897 cpu1_alert1: trip-point1 {
2898 temperature = <95000>;
2899 hysteresis = <2000>;
2903 cpu1_crit: cpu_crit {
2904 temperature = <110000>;
2905 hysteresis = <1000>;
2912 trip = <&cpu1_alert0>;
2913 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2914 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2915 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2916 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2919 trip = <&cpu1_alert1>;
2920 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2921 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2922 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2923 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2929 polling-delay-passive = <250>;
2930 polling-delay = <1000>;
2932 thermal-sensors = <&tsens0 3>;
2935 cpu2_alert0: trip-point0 {
2936 temperature = <90000>;
2937 hysteresis = <2000>;
2941 cpu2_alert1: trip-point1 {
2942 temperature = <95000>;
2943 hysteresis = <2000>;
2947 cpu2_crit: cpu_crit {
2948 temperature = <110000>;
2949 hysteresis = <1000>;
2956 trip = <&cpu2_alert0>;
2957 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2958 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2959 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2960 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2963 trip = <&cpu2_alert1>;
2964 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2965 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2966 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2967 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2973 polling-delay-passive = <250>;
2974 polling-delay = <1000>;
2976 thermal-sensors = <&tsens0 4>;
2979 cpu3_alert0: trip-point0 {
2980 temperature = <90000>;
2981 hysteresis = <2000>;
2985 cpu3_alert1: trip-point1 {
2986 temperature = <95000>;
2987 hysteresis = <2000>;
2991 cpu3_crit: cpu_crit {
2992 temperature = <110000>;
2993 hysteresis = <1000>;
3000 trip = <&cpu3_alert0>;
3001 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3002 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3003 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3004 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3007 trip = <&cpu3_alert1>;
3008 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3009 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3010 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3011 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3017 polling-delay-passive = <250>;
3018 polling-delay = <1000>;
3020 thermal-sensors = <&tsens0 7>;
3023 cpu4_top_alert0: trip-point0 {
3024 temperature = <90000>;
3025 hysteresis = <2000>;
3029 cpu4_top_alert1: trip-point1 {
3030 temperature = <95000>;
3031 hysteresis = <2000>;
3035 cpu4_top_crit: cpu_crit {
3036 temperature = <110000>;
3037 hysteresis = <1000>;
3044 trip = <&cpu4_top_alert0>;
3045 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3046 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3047 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3048 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3051 trip = <&cpu4_top_alert1>;
3052 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3053 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3054 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3055 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3061 polling-delay-passive = <250>;
3062 polling-delay = <1000>;
3064 thermal-sensors = <&tsens0 8>;
3067 cpu5_top_alert0: trip-point0 {
3068 temperature = <90000>;
3069 hysteresis = <2000>;
3073 cpu5_top_alert1: trip-point1 {
3074 temperature = <95000>;
3075 hysteresis = <2000>;
3079 cpu5_top_crit: cpu_crit {
3080 temperature = <110000>;
3081 hysteresis = <1000>;
3088 trip = <&cpu5_top_alert0>;
3089 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3090 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3091 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3092 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3095 trip = <&cpu5_top_alert1>;
3096 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3097 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3098 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3099 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3105 polling-delay-passive = <250>;
3106 polling-delay = <1000>;
3108 thermal-sensors = <&tsens0 9>;
3111 cpu6_top_alert0: trip-point0 {
3112 temperature = <90000>;
3113 hysteresis = <2000>;
3117 cpu6_top_alert1: trip-point1 {
3118 temperature = <95000>;
3119 hysteresis = <2000>;
3123 cpu6_top_crit: cpu_crit {
3124 temperature = <110000>;
3125 hysteresis = <1000>;
3132 trip = <&cpu6_top_alert0>;
3133 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3134 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3135 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3136 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3139 trip = <&cpu6_top_alert1>;
3140 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3141 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3142 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3143 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3149 polling-delay-passive = <250>;
3150 polling-delay = <1000>;
3152 thermal-sensors = <&tsens0 10>;
3155 cpu7_top_alert0: trip-point0 {
3156 temperature = <90000>;
3157 hysteresis = <2000>;
3161 cpu7_top_alert1: trip-point1 {
3162 temperature = <95000>;
3163 hysteresis = <2000>;
3167 cpu7_top_crit: cpu_crit {
3168 temperature = <110000>;
3169 hysteresis = <1000>;
3176 trip = <&cpu7_top_alert0>;
3177 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3178 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3179 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3180 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3183 trip = <&cpu7_top_alert1>;
3184 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3185 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3186 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3187 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3192 cpu4-bottom-thermal {
3193 polling-delay-passive = <250>;
3194 polling-delay = <1000>;
3196 thermal-sensors = <&tsens0 11>;
3199 cpu4_bottom_alert0: trip-point0 {
3200 temperature = <90000>;
3201 hysteresis = <2000>;
3205 cpu4_bottom_alert1: trip-point1 {
3206 temperature = <95000>;
3207 hysteresis = <2000>;
3211 cpu4_bottom_crit: cpu_crit {
3212 temperature = <110000>;
3213 hysteresis = <1000>;
3220 trip = <&cpu4_bottom_alert0>;
3221 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3222 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3223 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3224 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3227 trip = <&cpu4_bottom_alert1>;
3228 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3229 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3230 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3231 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3236 cpu5-bottom-thermal {
3237 polling-delay-passive = <250>;
3238 polling-delay = <1000>;
3240 thermal-sensors = <&tsens0 12>;
3243 cpu5_bottom_alert0: trip-point0 {
3244 temperature = <90000>;
3245 hysteresis = <2000>;
3249 cpu5_bottom_alert1: trip-point1 {
3250 temperature = <95000>;
3251 hysteresis = <2000>;
3255 cpu5_bottom_crit: cpu_crit {
3256 temperature = <110000>;
3257 hysteresis = <1000>;
3264 trip = <&cpu5_bottom_alert0>;
3265 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3266 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3267 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3268 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3271 trip = <&cpu5_bottom_alert1>;
3272 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3273 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3274 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3275 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3280 cpu6-bottom-thermal {
3281 polling-delay-passive = <250>;
3282 polling-delay = <1000>;
3284 thermal-sensors = <&tsens0 13>;
3287 cpu6_bottom_alert0: trip-point0 {
3288 temperature = <90000>;
3289 hysteresis = <2000>;
3293 cpu6_bottom_alert1: trip-point1 {
3294 temperature = <95000>;
3295 hysteresis = <2000>;
3299 cpu6_bottom_crit: cpu_crit {
3300 temperature = <110000>;
3301 hysteresis = <1000>;
3308 trip = <&cpu6_bottom_alert0>;
3309 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3310 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3311 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3312 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3315 trip = <&cpu6_bottom_alert1>;
3316 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3317 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3318 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3319 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3324 cpu7-bottom-thermal {
3325 polling-delay-passive = <250>;
3326 polling-delay = <1000>;
3328 thermal-sensors = <&tsens0 14>;
3331 cpu7_bottom_alert0: trip-point0 {
3332 temperature = <90000>;
3333 hysteresis = <2000>;
3337 cpu7_bottom_alert1: trip-point1 {
3338 temperature = <95000>;
3339 hysteresis = <2000>;
3343 cpu7_bottom_crit: cpu_crit {
3344 temperature = <110000>;
3345 hysteresis = <1000>;
3352 trip = <&cpu7_bottom_alert0>;
3353 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3354 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3355 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3356 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3359 trip = <&cpu7_bottom_alert1>;
3360 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3361 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3362 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3363 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3369 polling-delay-passive = <250>;
3370 polling-delay = <1000>;
3372 thermal-sensors = <&tsens0 0>;
3375 aoss0_alert0: trip-point0 {
3376 temperature = <90000>;
3377 hysteresis = <2000>;
3384 polling-delay-passive = <250>;
3385 polling-delay = <1000>;
3387 thermal-sensors = <&tsens0 5>;
3390 cluster0_alert0: trip-point0 {
3391 temperature = <90000>;
3392 hysteresis = <2000>;
3395 cluster0_crit: cluster0_crit {
3396 temperature = <110000>;
3397 hysteresis = <2000>;
3404 polling-delay-passive = <250>;
3405 polling-delay = <1000>;
3407 thermal-sensors = <&tsens0 6>;
3410 cluster1_alert0: trip-point0 {
3411 temperature = <90000>;
3412 hysteresis = <2000>;
3415 cluster1_crit: cluster1_crit {
3416 temperature = <110000>;
3417 hysteresis = <2000>;
3424 polling-delay-passive = <250>;
3425 polling-delay = <1000>;
3427 thermal-sensors = <&tsens0 15>;
3430 gpu1_alert0: trip-point0 {
3431 temperature = <90000>;
3432 hysteresis = <2000>;
3439 polling-delay-passive = <250>;
3440 polling-delay = <1000>;
3442 thermal-sensors = <&tsens1 0>;
3445 aoss1_alert0: trip-point0 {
3446 temperature = <90000>;
3447 hysteresis = <2000>;
3454 polling-delay-passive = <250>;
3455 polling-delay = <1000>;
3457 thermal-sensors = <&tsens1 1>;
3460 wlan_alert0: trip-point0 {
3461 temperature = <90000>;
3462 hysteresis = <2000>;
3469 polling-delay-passive = <250>;
3470 polling-delay = <1000>;
3472 thermal-sensors = <&tsens1 2>;
3475 video_alert0: trip-point0 {
3476 temperature = <90000>;
3477 hysteresis = <2000>;
3484 polling-delay-passive = <250>;
3485 polling-delay = <1000>;
3487 thermal-sensors = <&tsens1 3>;
3490 mem_alert0: trip-point0 {
3491 temperature = <90000>;
3492 hysteresis = <2000>;
3499 polling-delay-passive = <250>;
3500 polling-delay = <1000>;
3502 thermal-sensors = <&tsens1 4>;
3505 q6_hvx_alert0: trip-point0 {
3506 temperature = <90000>;
3507 hysteresis = <2000>;
3514 polling-delay-passive = <250>;
3515 polling-delay = <1000>;
3517 thermal-sensors = <&tsens1 5>;
3520 camera_alert0: trip-point0 {
3521 temperature = <90000>;
3522 hysteresis = <2000>;
3529 polling-delay-passive = <250>;
3530 polling-delay = <1000>;
3532 thermal-sensors = <&tsens1 6>;
3535 compute_alert0: trip-point0 {
3536 temperature = <90000>;
3537 hysteresis = <2000>;
3544 polling-delay-passive = <250>;
3545 polling-delay = <1000>;
3547 thermal-sensors = <&tsens1 7>;
3550 npu_alert0: trip-point0 {
3551 temperature = <90000>;
3552 hysteresis = <2000>;
3558 gpu-thermal-bottom {
3559 polling-delay-passive = <250>;
3560 polling-delay = <1000>;
3562 thermal-sensors = <&tsens1 8>;
3565 gpu2_alert0: trip-point0 {
3566 temperature = <90000>;
3567 hysteresis = <2000>;