arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  12 #include <dt-bindings/interconnect/qcom,sm8250.h>
  13 #include <dt-bindings/mailbox/qcom-ipcc.h>
  14 #include <dt-bindings/power/qcom-aoss-qmp.h>
  15 #include <dt-bindings/power/qcom-rpmpd.h>
  16 #include <dt-bindings/soc/qcom,apr.h>
  17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  18 #include <dt-bindings/sound/qcom,q6afe.h>
  19 #include <dt-bindings/thermal/thermal.h>
  20
  21 / {
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 i2c0 = &i2c0;
  29                 i2c1 = &i2c1;
  30                 i2c2 = &i2c2;
  31                 i2c3 = &i2c3;
  32                 i2c4 = &i2c4;
  33                 i2c5 = &i2c5;
  34                 i2c6 = &i2c6;
  35                 i2c7 = &i2c7;
  36                 i2c8 = &i2c8;
  37                 i2c9 = &i2c9;
  38                 i2c10 = &i2c10;
  39                 i2c11 = &i2c11;
  40                 i2c12 = &i2c12;
  41                 i2c13 = &i2c13;
  42                 i2c14 = &i2c14;
  43                 i2c15 = &i2c15;
  44                 i2c16 = &i2c16;
  45                 i2c17 = &i2c17;
  46                 i2c18 = &i2c18;
  47                 i2c19 = &i2c19;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi2 = &spi2;
  51                 spi3 = &spi3;
  52                 spi4 = &spi4;
  53                 spi5 = &spi5;
  54                 spi6 = &spi6;
  55                 spi7 = &spi7;
  56                 spi8 = &spi8;
  57                 spi9 = &spi9;
  58                 spi10 = &spi10;
  59                 spi11 = &spi11;
  60                 spi12 = &spi12;
  61                 spi13 = &spi13;
  62                 spi14 = &spi14;
  63                 spi15 = &spi15;
  64                 spi16 = &spi16;
  65                 spi17 = &spi17;
  66                 spi18 = &spi18;
  67                 spi19 = &spi19;
  68         };
  69
  70         chosen { };
  71
  72         clocks {
  73                 xo_board: xo-board {
  74                         compatible = "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <38400000>;
  77                         clock-output-names = "xo_board";
  78                 };
  79
  80                 sleep_clk: sleep-clk {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                         #clock-cells = <0>;
  84                 };
  85         };
  86
  87         cpus {
  88                 #address-cells = <2>;
  89                 #size-cells = <0>;
  90
  91                 CPU0: cpu@0 {
  92                         device_type = "cpu";
  93                         compatible = "qcom,kryo485";
  94                         reg = <0x0 0x0>;
  95                         enable-method = "psci";
  96                         capacity-dmips-mhz = <448>;
  97                         dynamic-power-coefficient = <205>;
  98                         next-level-cache = <&L2_0>;
  99                         qcom,freq-domain = <&cpufreq_hw 0>;
 100                         #cooling-cells = <2>;
 101                         L2_0: l2-cache {
 102                                 compatible = "cache";
 103                                 next-level-cache = <&L3_0>;
 104                                 L3_0: l3-cache {
 105                                         compatible = "cache";
 106                                 };
 107                         };
 108                 };
 109
 110                 CPU1: cpu@100 {
 111                         device_type = "cpu";
 112                         compatible = "qcom,kryo485";
 113                         reg = <0x0 0x100>;
 114                         enable-method = "psci";
 115                         capacity-dmips-mhz = <448>;
 116                         dynamic-power-coefficient = <205>;
 117                         next-level-cache = <&L2_100>;
 118                         qcom,freq-domain = <&cpufreq_hw 0>;
 119                         #cooling-cells = <2>;
 120                         L2_100: l2-cache {
 121                                 compatible = "cache";
 122                                 next-level-cache = <&L3_0>;
 123                         };
 124                 };
 125
 126                 CPU2: cpu@200 {
 127                         device_type = "cpu";
 128                         compatible = "qcom,kryo485";
 129                         reg = <0x0 0x200>;
 130                         enable-method = "psci";
 131                         capacity-dmips-mhz = <448>;
 132                         dynamic-power-coefficient = <205>;
 133                         next-level-cache = <&L2_200>;
 134                         qcom,freq-domain = <&cpufreq_hw 0>;
 135                         #cooling-cells = <2>;
 136                         L2_200: l2-cache {
 137                                 compatible = "cache";
 138                                 next-level-cache = <&L3_0>;
 139                         };
 140                 };
 141
 142                 CPU3: cpu@300 {
 143                         device_type = "cpu";
 144                         compatible = "qcom,kryo485";
 145                         reg = <0x0 0x300>;
 146                         enable-method = "psci";
 147                         capacity-dmips-mhz = <448>;
 148                         dynamic-power-coefficient = <205>;
 149                         next-level-cache = <&L2_300>;
 150                         qcom,freq-domain = <&cpufreq_hw 0>;
 151                         #cooling-cells = <2>;
 152                         L2_300: l2-cache {
 153                                 compatible = "cache";
 154                                 next-level-cache = <&L3_0>;
 155                         };
 156                 };
 157
 158                 CPU4: cpu@400 {
 159                         device_type = "cpu";
 160                         compatible = "qcom,kryo485";
 161                         reg = <0x0 0x400>;
 162                         enable-method = "psci";
 163                         capacity-dmips-mhz = <1024>;
 164                         dynamic-power-coefficient = <379>;
 165                         next-level-cache = <&L2_400>;
 166                         qcom,freq-domain = <&cpufreq_hw 1>;
 167                         #cooling-cells = <2>;
 168                         L2_400: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU5: cpu@500 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo485";
 177                         reg = <0x0 0x500>;
 178                         enable-method = "psci";
 179                         capacity-dmips-mhz = <1024>;
 180                         dynamic-power-coefficient = <379>;
 181                         next-level-cache = <&L2_500>;
 182                         qcom,freq-domain = <&cpufreq_hw 1>;
 183                         #cooling-cells = <2>;
 184                         L2_500: l2-cache {
 185                                 compatible = "cache";
 186                                 next-level-cache = <&L3_0>;
 187                         };
 188
 189                 };
 190
 191                 CPU6: cpu@600 {
 192                         device_type = "cpu";
 193                         compatible = "qcom,kryo485";
 194                         reg = <0x0 0x600>;
 195                         enable-method = "psci";
 196                         capacity-dmips-mhz = <1024>;
 197                         dynamic-power-coefficient = <379>;
 198                         next-level-cache = <&L2_600>;
 199                         qcom,freq-domain = <&cpufreq_hw 1>;
 200                         #cooling-cells = <2>;
 201                         L2_600: l2-cache {
 202                                 compatible = "cache";
 203                                 next-level-cache = <&L3_0>;
 204                         };
 205                 };
 206
 207                 CPU7: cpu@700 {
 208                         device_type = "cpu";
 209                         compatible = "qcom,kryo485";
 210                         reg = <0x0 0x700>;
 211                         enable-method = "psci";
 212                         capacity-dmips-mhz = <1024>;
 213                         dynamic-power-coefficient = <444>;
 214                         next-level-cache = <&L2_700>;
 215                         qcom,freq-domain = <&cpufreq_hw 2>;
 216                         #cooling-cells = <2>;
 217                         L2_700: l2-cache {
 218                                 compatible = "cache";
 219                                 next-level-cache = <&L3_0>;
 220                         };
 221                 };
 222
 223                 cpu-map {
 224                         cluster0 {
 225                                 core0 {
 226                                         cpu = <&CPU0>;
 227                                 };
 228
 229                                 core1 {
 230                                         cpu = <&CPU1>;
 231                                 };
 232
 233                                 core2 {
 234                                         cpu = <&CPU2>;
 235                                 };
 236
 237                                 core3 {
 238                                         cpu = <&CPU3>;
 239                                 };
 240
 241                                 core4 {
 242                                         cpu = <&CPU4>;
 243                                 };
 244
 245                                 core5 {
 246                                         cpu = <&CPU5>;
 247                                 };
 248
 249                                 core6 {
 250                                         cpu = <&CPU6>;
 251                                 };
 252
 253                                 core7 {
 254                                         cpu = <&CPU7>;
 255                                 };
 256                         };
 257                 };
 258         };
 259
 260         firmware {
 261                 scm: scm {
 262                         compatible = "qcom,scm";
 263                         #reset-cells = <1>;
 264                 };
 265         };
 266
 267         memory@80000000 {
 268                 device_type = "memory";
 269                 /* We expect the bootloader to fill in the size */
 270                 reg = <0x0 0x80000000 0x0 0x0>;
 271         };
 272
 273         mmcx_reg: mmcx-reg {
 274                 compatible = "regulator-fixed-domain";
 275                 power-domains = <&rpmhpd SM8250_MMCX>;
 276                 required-opps = <&rpmhpd_opp_low_svs>;
 277                 regulator-name = "MMCX";
 278         };
 279
 280         pmu {
 281                 compatible = "arm,armv8-pmuv3";
 282                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 283         };
 284
 285         psci {
 286                 compatible = "arm,psci-1.0";
 287                 method = "smc";
 288         };
 289
 290         reserved-memory {
 291                 #address-cells = <2>;
 292                 #size-cells = <2>;
 293                 ranges;
 294
 295                 hyp_mem: memory@80000000 {
 296                         reg = <0x0 0x80000000 0x0 0x600000>;
 297                         no-map;
 298                 };
 299
 300                 xbl_aop_mem: memory@80700000 {
 301                         reg = <0x0 0x80700000 0x0 0x160000>;
 302                         no-map;
 303                 };
 304
 305                 cmd_db: memory@80860000 {
 306                         compatible = "qcom,cmd-db";
 307                         reg = <0x0 0x80860000 0x0 0x20000>;
 308                         no-map;
 309                 };
 310
 311                 smem_mem: memory@80900000 {
 312                         reg = <0x0 0x80900000 0x0 0x200000>;
 313                         no-map;
 314                 };
 315
 316                 removed_mem: memory@80b00000 {
 317                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 318                         no-map;
 319                 };
 320
 321                 camera_mem: memory@86200000 {
 322                         reg = <0x0 0x86200000 0x0 0x500000>;
 323                         no-map;
 324                 };
 325
 326                 wlan_mem: memory@86700000 {
 327                         reg = <0x0 0x86700000 0x0 0x100000>;
 328                         no-map;
 329                 };
 330
 331                 ipa_fw_mem: memory@86800000 {
 332                         reg = <0x0 0x86800000 0x0 0x10000>;
 333                         no-map;
 334                 };
 335
 336                 ipa_gsi_mem: memory@86810000 {
 337                         reg = <0x0 0x86810000 0x0 0xa000>;
 338                         no-map;
 339                 };
 340
 341                 gpu_mem: memory@8681a000 {
 342                         reg = <0x0 0x8681a000 0x0 0x2000>;
 343                         no-map;
 344                 };
 345
 346                 npu_mem: memory@86900000 {
 347                         reg = <0x0 0x86900000 0x0 0x500000>;
 348                         no-map;
 349                 };
 350
 351                 video_mem: memory@86e00000 {
 352                         reg = <0x0 0x86e00000 0x0 0x500000>;
 353                         no-map;
 354                 };
 355
 356                 cvp_mem: memory@87300000 {
 357                         reg = <0x0 0x87300000 0x0 0x500000>;
 358                         no-map;
 359                 };
 360
 361                 cdsp_mem: memory@87800000 {
 362                         reg = <0x0 0x87800000 0x0 0x1400000>;
 363                         no-map;
 364                 };
 365
 366                 slpi_mem: memory@88c00000 {
 367                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 368                         no-map;
 369                 };
 370
 371                 adsp_mem: memory@8a100000 {
 372                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 373                         no-map;
 374                 };
 375
 376                 spss_mem: memory@8be00000 {
 377                         reg = <0x0 0x8be00000 0x0 0x100000>;
 378                         no-map;
 379                 };
 380
 381                 cdsp_secure_heap: memory@8bf00000 {
 382                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 383                         no-map;
 384                 };
 385         };
 386
 387         smem {
 388                 compatible = "qcom,smem";
 389                 memory-region = <&smem_mem>;
 390                 hwlocks = <&tcsr_mutex 3>;
 391         };
 392
 393         smp2p-adsp {
 394                 compatible = "qcom,smp2p";
 395                 qcom,smem = <443>, <429>;
 396                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 397                                              IPCC_MPROC_SIGNAL_SMP2P
 398                                              IRQ_TYPE_EDGE_RISING>;
 399                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 400                                 IPCC_MPROC_SIGNAL_SMP2P>;
 401
 402                 qcom,local-pid = <0>;
 403                 qcom,remote-pid = <2>;
 404
 405                 smp2p_adsp_out: master-kernel {
 406                         qcom,entry-name = "master-kernel";
 407                         #qcom,smem-state-cells = <1>;
 408                 };
 409
 410                 smp2p_adsp_in: slave-kernel {
 411                         qcom,entry-name = "slave-kernel";
 412                         interrupt-controller;
 413                         #interrupt-cells = <2>;
 414                 };
 415         };
 416
 417         smp2p-cdsp {
 418                 compatible = "qcom,smp2p";
 419                 qcom,smem = <94>, <432>;
 420                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 421                                              IPCC_MPROC_SIGNAL_SMP2P
 422                                              IRQ_TYPE_EDGE_RISING>;
 423                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 424                                 IPCC_MPROC_SIGNAL_SMP2P>;
 425
 426                 qcom,local-pid = <0>;
 427                 qcom,remote-pid = <5>;
 428
 429                 smp2p_cdsp_out: master-kernel {
 430                         qcom,entry-name = "master-kernel";
 431                         #qcom,smem-state-cells = <1>;
 432                 };
 433
 434                 smp2p_cdsp_in: slave-kernel {
 435                         qcom,entry-name = "slave-kernel";
 436                         interrupt-controller;
 437                         #interrupt-cells = <2>;
 438                 };
 439         };
 440
 441         smp2p-slpi {
 442                 compatible = "qcom,smp2p";
 443                 qcom,smem = <481>, <430>;
 444                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 445                                              IPCC_MPROC_SIGNAL_SMP2P
 446                                              IRQ_TYPE_EDGE_RISING>;
 447                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 448                                 IPCC_MPROC_SIGNAL_SMP2P>;
 449
 450                 qcom,local-pid = <0>;
 451                 qcom,remote-pid = <3>;
 452
 453                 smp2p_slpi_out: master-kernel {
 454                         qcom,entry-name = "master-kernel";
 455                         #qcom,smem-state-cells = <1>;
 456                 };
 457
 458                 smp2p_slpi_in: slave-kernel {
 459                         qcom,entry-name = "slave-kernel";
 460                         interrupt-controller;
 461                         #interrupt-cells = <2>;
 462                 };
 463         };
 464
 465         soc: soc@0 {
 466                 #address-cells = <2>;
 467                 #size-cells = <2>;
 468                 ranges = <0 0 0 0 0x10 0>;
 469                 dma-ranges = <0 0 0 0 0x10 0>;
 470                 compatible = "simple-bus";
 471
 472                 gcc: clock-controller@100000 {
 473                         compatible = "qcom,gcc-sm8250";
 474                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 475                         #clock-cells = <1>;
 476                         #reset-cells = <1>;
 477                         #power-domain-cells = <1>;
 478                         clock-names = "bi_tcxo",
 479                                       "bi_tcxo_ao",
 480                                       "sleep_clk";
 481                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 482                                  <&rpmhcc RPMH_CXO_CLK_A>,
 483                                  <&sleep_clk>;
 484                 };
 485
 486                 ipcc: mailbox@408000 {
 487                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 488                         reg = <0 0x00408000 0 0x1000>;
 489                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 490                         interrupt-controller;
 491                         #interrupt-cells = <3>;
 492                         #mbox-cells = <2>;
 493                 };
 494
 495                 rng: rng@793000 {
 496                         compatible = "qcom,prng-ee";
 497                         reg = <0 0x00793000 0 0x1000>;
 498                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 499                         clock-names = "core";
 500                 };
 501
 502                 qup_opp_table: qup-opp-table {
 503                         compatible = "operating-points-v2";
 504
 505                         opp-50000000 {
 506                                 opp-hz = /bits/ 64 <50000000>;
 507                                 required-opps = <&rpmhpd_opp_min_svs>;
 508                         };
 509
 510                         opp-75000000 {
 511                                 opp-hz = /bits/ 64 <75000000>;
 512                                 required-opps = <&rpmhpd_opp_low_svs>;
 513                         };
 514
 515                         opp-120000000 {
 516                                 opp-hz = /bits/ 64 <120000000>;
 517                                 required-opps = <&rpmhpd_opp_svs>;
 518                         };
 519                 };
 520
 521                 qupv3_id_2: geniqup@8c0000 {
 522                         compatible = "qcom,geni-se-qup";
 523                         reg = <0x0 0x008c0000 0x0 0x6000>;
 524                         clock-names = "m-ahb", "s-ahb";
 525                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 526                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 527                         #address-cells = <2>;
 528                         #size-cells = <2>;
 529                         iommus = <&apps_smmu 0x63 0x0>;
 530                         ranges;
 531                         status = "disabled";
 532
 533                         i2c14: i2c@880000 {
 534                                 compatible = "qcom,geni-i2c";
 535                                 reg = <0 0x00880000 0 0x4000>;
 536                                 clock-names = "se";
 537                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 538                                 pinctrl-names = "default";
 539                                 pinctrl-0 = <&qup_i2c14_default>;
 540                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 541                                 #address-cells = <1>;
 542                                 #size-cells = <0>;
 543                                 status = "disabled";
 544                         };
 545
 546                         spi14: spi@880000 {
 547                                 compatible = "qcom,geni-spi";
 548                                 reg = <0 0x00880000 0 0x4000>;
 549                                 clock-names = "se";
 550                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 551                                 pinctrl-names = "default";
 552                                 pinctrl-0 = <&qup_spi14_default>;
 553                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 554                                 #address-cells = <1>;
 555                                 #size-cells = <0>;
 556                                 power-domains = <&rpmhpd SM8250_CX>;
 557                                 operating-points-v2 = <&qup_opp_table>;
 558                                 status = "disabled";
 559                         };
 560
 561                         i2c15: i2c@884000 {
 562                                 compatible = "qcom,geni-i2c";
 563                                 reg = <0 0x00884000 0 0x4000>;
 564                                 clock-names = "se";
 565                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 566                                 pinctrl-names = "default";
 567                                 pinctrl-0 = <&qup_i2c15_default>;
 568                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 569                                 #address-cells = <1>;
 570                                 #size-cells = <0>;
 571                                 status = "disabled";
 572                         };
 573
 574                         spi15: spi@884000 {
 575                                 compatible = "qcom,geni-spi";
 576                                 reg = <0 0x00884000 0 0x4000>;
 577                                 clock-names = "se";
 578                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 579                                 pinctrl-names = "default";
 580                                 pinctrl-0 = <&qup_spi15_default>;
 581                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 582                                 #address-cells = <1>;
 583                                 #size-cells = <0>;
 584                                 power-domains = <&rpmhpd SM8250_CX>;
 585                                 operating-points-v2 = <&qup_opp_table>;
 586                                 status = "disabled";
 587                         };
 588
 589                         i2c16: i2c@888000 {
 590                                 compatible = "qcom,geni-i2c";
 591                                 reg = <0 0x00888000 0 0x4000>;
 592                                 clock-names = "se";
 593                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 594                                 pinctrl-names = "default";
 595                                 pinctrl-0 = <&qup_i2c16_default>;
 596                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 597                                 #address-cells = <1>;
 598                                 #size-cells = <0>;
 599                                 status = "disabled";
 600                         };
 601
 602                         spi16: spi@888000 {
 603                                 compatible = "qcom,geni-spi";
 604                                 reg = <0 0x00888000 0 0x4000>;
 605                                 clock-names = "se";
 606                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 607                                 pinctrl-names = "default";
 608                                 pinctrl-0 = <&qup_spi16_default>;
 609                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 610                                 #address-cells = <1>;
 611                                 #size-cells = <0>;
 612                                 power-domains = <&rpmhpd SM8250_CX>;
 613                                 operating-points-v2 = <&qup_opp_table>;
 614                                 status = "disabled";
 615                         };
 616
 617                         i2c17: i2c@88c000 {
 618                                 compatible = "qcom,geni-i2c";
 619                                 reg = <0 0x0088c000 0 0x4000>;
 620                                 clock-names = "se";
 621                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 622                                 pinctrl-names = "default";
 623                                 pinctrl-0 = <&qup_i2c17_default>;
 624                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 625                                 #address-cells = <1>;
 626                                 #size-cells = <0>;
 627                                 status = "disabled";
 628                         };
 629
 630                         spi17: spi@88c000 {
 631                                 compatible = "qcom,geni-spi";
 632                                 reg = <0 0x0088c000 0 0x4000>;
 633                                 clock-names = "se";
 634                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 635                                 pinctrl-names = "default";
 636                                 pinctrl-0 = <&qup_spi17_default>;
 637                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 638                                 #address-cells = <1>;
 639                                 #size-cells = <0>;
 640                                 power-domains = <&rpmhpd SM8250_CX>;
 641                                 operating-points-v2 = <&qup_opp_table>;
 642                                 status = "disabled";
 643                         };
 644
 645                         uart17: serial@88c000 {
 646                                 compatible = "qcom,geni-uart";
 647                                 reg = <0 0x0088c000 0 0x4000>;
 648                                 clock-names = "se";
 649                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 650                                 pinctrl-names = "default";
 651                                 pinctrl-0 = <&qup_uart17_default>;
 652                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 653                                 power-domains = <&rpmhpd SM8250_CX>;
 654                                 operating-points-v2 = <&qup_opp_table>;
 655                                 status = "disabled";
 656                         };
 657
 658                         i2c18: i2c@890000 {
 659                                 compatible = "qcom,geni-i2c";
 660                                 reg = <0 0x00890000 0 0x4000>;
 661                                 clock-names = "se";
 662                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 663                                 pinctrl-names = "default";
 664                                 pinctrl-0 = <&qup_i2c18_default>;
 665                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 666                                 #address-cells = <1>;
 667                                 #size-cells = <0>;
 668                                 status = "disabled";
 669                         };
 670
 671                         spi18: spi@890000 {
 672                                 compatible = "qcom,geni-spi";
 673                                 reg = <0 0x00890000 0 0x4000>;
 674                                 clock-names = "se";
 675                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 676                                 pinctrl-names = "default";
 677                                 pinctrl-0 = <&qup_spi18_default>;
 678                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 679                                 #address-cells = <1>;
 680                                 #size-cells = <0>;
 681                                 power-domains = <&rpmhpd SM8250_CX>;
 682                                 operating-points-v2 = <&qup_opp_table>;
 683                                 status = "disabled";
 684                         };
 685
 686                         uart18: serial@890000 {
 687                                 compatible = "qcom,geni-uart";
 688                                 reg = <0 0x00890000 0 0x4000>;
 689                                 clock-names = "se";
 690                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 691                                 pinctrl-names = "default";
 692                                 pinctrl-0 = <&qup_uart18_default>;
 693                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 694                                 power-domains = <&rpmhpd SM8250_CX>;
 695                                 operating-points-v2 = <&qup_opp_table>;
 696                                 status = "disabled";
 697                         };
 698
 699                         i2c19: i2c@894000 {
 700                                 compatible = "qcom,geni-i2c";
 701                                 reg = <0 0x00894000 0 0x4000>;
 702                                 clock-names = "se";
 703                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 704                                 pinctrl-names = "default";
 705                                 pinctrl-0 = <&qup_i2c19_default>;
 706                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 707                                 #address-cells = <1>;
 708                                 #size-cells = <0>;
 709                                 status = "disabled";
 710                         };
 711
 712                         spi19: spi@894000 {
 713                                 compatible = "qcom,geni-spi";
 714                                 reg = <0 0x00894000 0 0x4000>;
 715                                 clock-names = "se";
 716                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 717                                 pinctrl-names = "default";
 718                                 pinctrl-0 = <&qup_spi19_default>;
 719                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 720                                 #address-cells = <1>;
 721                                 #size-cells = <0>;
 722                                 power-domains = <&rpmhpd SM8250_CX>;
 723                                 operating-points-v2 = <&qup_opp_table>;
 724                                 status = "disabled";
 725                         };
 726                 };
 727
 728                 qupv3_id_0: geniqup@9c0000 {
 729                         compatible = "qcom,geni-se-qup";
 730                         reg = <0x0 0x009c0000 0x0 0x6000>;
 731                         clock-names = "m-ahb", "s-ahb";
 732                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 733                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 734                         #address-cells = <2>;
 735                         #size-cells = <2>;
 736                         iommus = <&apps_smmu 0x5a3 0x0>;
 737                         ranges;
 738                         status = "disabled";
 739
 740                         i2c0: i2c@980000 {
 741                                 compatible = "qcom,geni-i2c";
 742                                 reg = <0 0x00980000 0 0x4000>;
 743                                 clock-names = "se";
 744                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 745                                 pinctrl-names = "default";
 746                                 pinctrl-0 = <&qup_i2c0_default>;
 747                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 748                                 #address-cells = <1>;
 749                                 #size-cells = <0>;
 750                                 status = "disabled";
 751                         };
 752
 753                         spi0: spi@980000 {
 754                                 compatible = "qcom,geni-spi";
 755                                 reg = <0 0x00980000 0 0x4000>;
 756                                 clock-names = "se";
 757                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 758                                 pinctrl-names = "default";
 759                                 pinctrl-0 = <&qup_spi0_default>;
 760                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 761                                 #address-cells = <1>;
 762                                 #size-cells = <0>;
 763                                 power-domains = <&rpmhpd SM8250_CX>;
 764                                 operating-points-v2 = <&qup_opp_table>;
 765                                 status = "disabled";
 766                         };
 767
 768                         i2c1: i2c@984000 {
 769                                 compatible = "qcom,geni-i2c";
 770                                 reg = <0 0x00984000 0 0x4000>;
 771                                 clock-names = "se";
 772                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 773                                 pinctrl-names = "default";
 774                                 pinctrl-0 = <&qup_i2c1_default>;
 775                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 776                                 #address-cells = <1>;
 777                                 #size-cells = <0>;
 778                                 status = "disabled";
 779                         };
 780
 781                         spi1: spi@984000 {
 782                                 compatible = "qcom,geni-spi";
 783                                 reg = <0 0x00984000 0 0x4000>;
 784                                 clock-names = "se";
 785                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 786                                 pinctrl-names = "default";
 787                                 pinctrl-0 = <&qup_spi1_default>;
 788                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 789                                 #address-cells = <1>;
 790                                 #size-cells = <0>;
 791                                 power-domains = <&rpmhpd SM8250_CX>;
 792                                 operating-points-v2 = <&qup_opp_table>;
 793                                 status = "disabled";
 794                         };
 795
 796                         i2c2: i2c@988000 {
 797                                 compatible = "qcom,geni-i2c";
 798                                 reg = <0 0x00988000 0 0x4000>;
 799                                 clock-names = "se";
 800                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 801                                 pinctrl-names = "default";
 802                                 pinctrl-0 = <&qup_i2c2_default>;
 803                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806                                 status = "disabled";
 807                         };
 808
 809                         spi2: spi@988000 {
 810                                 compatible = "qcom,geni-spi";
 811                                 reg = <0 0x00988000 0 0x4000>;
 812                                 clock-names = "se";
 813                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 814                                 pinctrl-names = "default";
 815                                 pinctrl-0 = <&qup_spi2_default>;
 816                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 817                                 #address-cells = <1>;
 818                                 #size-cells = <0>;
 819                                 power-domains = <&rpmhpd SM8250_CX>;
 820                                 operating-points-v2 = <&qup_opp_table>;
 821                                 status = "disabled";
 822                         };
 823
 824                         uart2: serial@988000 {
 825                                 compatible = "qcom,geni-debug-uart";
 826                                 reg = <0 0x00988000 0 0x4000>;
 827                                 clock-names = "se";
 828                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 829                                 pinctrl-names = "default";
 830                                 pinctrl-0 = <&qup_uart2_default>;
 831                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 832                                 power-domains = <&rpmhpd SM8250_CX>;
 833                                 operating-points-v2 = <&qup_opp_table>;
 834                                 status = "disabled";
 835                         };
 836
 837                         i2c3: i2c@98c000 {
 838                                 compatible = "qcom,geni-i2c";
 839                                 reg = <0 0x0098c000 0 0x4000>;
 840                                 clock-names = "se";
 841                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 842                                 pinctrl-names = "default";
 843                                 pinctrl-0 = <&qup_i2c3_default>;
 844                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 845                                 #address-cells = <1>;
 846                                 #size-cells = <0>;
 847                                 status = "disabled";
 848                         };
 849
 850                         spi3: spi@98c000 {
 851                                 compatible = "qcom,geni-spi";
 852                                 reg = <0 0x0098c000 0 0x4000>;
 853                                 clock-names = "se";
 854                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 855                                 pinctrl-names = "default";
 856                                 pinctrl-0 = <&qup_spi3_default>;
 857                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 858                                 #address-cells = <1>;
 859                                 #size-cells = <0>;
 860                                 power-domains = <&rpmhpd SM8250_CX>;
 861                                 operating-points-v2 = <&qup_opp_table>;
 862                                 status = "disabled";
 863                         };
 864
 865                         i2c4: i2c@990000 {
 866                                 compatible = "qcom,geni-i2c";
 867                                 reg = <0 0x00990000 0 0x4000>;
 868                                 clock-names = "se";
 869                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 870                                 pinctrl-names = "default";
 871                                 pinctrl-0 = <&qup_i2c4_default>;
 872                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 873                                 #address-cells = <1>;
 874                                 #size-cells = <0>;
 875                                 status = "disabled";
 876                         };
 877
 878                         spi4: spi@990000 {
 879                                 compatible = "qcom,geni-spi";
 880                                 reg = <0 0x00990000 0 0x4000>;
 881                                 clock-names = "se";
 882                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 883                                 pinctrl-names = "default";
 884                                 pinctrl-0 = <&qup_spi4_default>;
 885                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 886                                 #address-cells = <1>;
 887                                 #size-cells = <0>;
 888                                 power-domains = <&rpmhpd SM8250_CX>;
 889                                 operating-points-v2 = <&qup_opp_table>;
 890                                 status = "disabled";
 891                         };
 892
 893                         i2c5: i2c@994000 {
 894                                 compatible = "qcom,geni-i2c";
 895                                 reg = <0 0x00994000 0 0x4000>;
 896                                 clock-names = "se";
 897                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 898                                 pinctrl-names = "default";
 899                                 pinctrl-0 = <&qup_i2c5_default>;
 900                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 status = "disabled";
 904                         };
 905
 906                         spi5: spi@994000 {
 907                                 compatible = "qcom,geni-spi";
 908                                 reg = <0 0x00994000 0 0x4000>;
 909                                 clock-names = "se";
 910                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 911                                 pinctrl-names = "default";
 912                                 pinctrl-0 = <&qup_spi5_default>;
 913                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 914                                 #address-cells = <1>;
 915                                 #size-cells = <0>;
 916                                 power-domains = <&rpmhpd SM8250_CX>;
 917                                 operating-points-v2 = <&qup_opp_table>;
 918                                 status = "disabled";
 919                         };
 920
 921                         i2c6: i2c@998000 {
 922                                 compatible = "qcom,geni-i2c";
 923                                 reg = <0 0x00998000 0 0x4000>;
 924                                 clock-names = "se";
 925                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 926                                 pinctrl-names = "default";
 927                                 pinctrl-0 = <&qup_i2c6_default>;
 928                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 status = "disabled";
 932                         };
 933
 934                         spi6: spi@998000 {
 935                                 compatible = "qcom,geni-spi";
 936                                 reg = <0 0x00998000 0 0x4000>;
 937                                 clock-names = "se";
 938                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 939                                 pinctrl-names = "default";
 940                                 pinctrl-0 = <&qup_spi6_default>;
 941                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 942                                 #address-cells = <1>;
 943                                 #size-cells = <0>;
 944                                 power-domains = <&rpmhpd SM8250_CX>;
 945                                 operating-points-v2 = <&qup_opp_table>;
 946                                 status = "disabled";
 947                         };
 948
 949                         uart6: serial@998000 {
 950                                 compatible = "qcom,geni-uart";
 951                                 reg = <0 0x00998000 0 0x4000>;
 952                                 clock-names = "se";
 953                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 954                                 pinctrl-names = "default";
 955                                 pinctrl-0 = <&qup_uart6_default>;
 956                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 957                                 power-domains = <&rpmhpd SM8250_CX>;
 958                                 operating-points-v2 = <&qup_opp_table>;
 959                                 status = "disabled";
 960                         };
 961
 962                         i2c7: i2c@99c000 {
 963                                 compatible = "qcom,geni-i2c";
 964                                 reg = <0 0x0099c000 0 0x4000>;
 965                                 clock-names = "se";
 966                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 967                                 pinctrl-names = "default";
 968                                 pinctrl-0 = <&qup_i2c7_default>;
 969                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 970                                 #address-cells = <1>;
 971                                 #size-cells = <0>;
 972                                 status = "disabled";
 973                         };
 974
 975                         spi7: spi@99c000 {
 976                                 compatible = "qcom,geni-spi";
 977                                 reg = <0 0x0099c000 0 0x4000>;
 978                                 clock-names = "se";
 979                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 980                                 pinctrl-names = "default";
 981                                 pinctrl-0 = <&qup_spi7_default>;
 982                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 983                                 #address-cells = <1>;
 984                                 #size-cells = <0>;
 985                                 power-domains = <&rpmhpd SM8250_CX>;
 986                                 operating-points-v2 = <&qup_opp_table>;
 987                                 status = "disabled";
 988                         };
 989                 };
 990
 991                 qupv3_id_1: geniqup@ac0000 {
 992                         compatible = "qcom,geni-se-qup";
 993                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 994                         clock-names = "m-ahb", "s-ahb";
 995                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 996                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 997                         #address-cells = <2>;
 998                         #size-cells = <2>;
 999                         iommus = <&apps_smmu 0x43 0x0>;
1000                         ranges;
1001                         status = "disabled";
1002
1003                         i2c8: i2c@a80000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0 0x00a80000 0 0x4000>;
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&qup_i2c8_default>;
1010                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 status = "disabled";
1014                         };
1015
1016                         spi8: spi@a80000 {
1017                                 compatible = "qcom,geni-spi";
1018                                 reg = <0 0x00a80000 0 0x4000>;
1019                                 clock-names = "se";
1020                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1021                                 pinctrl-names = "default";
1022                                 pinctrl-0 = <&qup_spi8_default>;
1023                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 power-domains = <&rpmhpd SM8250_CX>;
1027                                 operating-points-v2 = <&qup_opp_table>;
1028                                 status = "disabled";
1029                         };
1030
1031                         i2c9: i2c@a84000 {
1032                                 compatible = "qcom,geni-i2c";
1033                                 reg = <0 0x00a84000 0 0x4000>;
1034                                 clock-names = "se";
1035                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1036                                 pinctrl-names = "default";
1037                                 pinctrl-0 = <&qup_i2c9_default>;
1038                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1039                                 #address-cells = <1>;
1040                                 #size-cells = <0>;
1041                                 status = "disabled";
1042                         };
1043
1044                         spi9: spi@a84000 {
1045                                 compatible = "qcom,geni-spi";
1046                                 reg = <0 0x00a84000 0 0x4000>;
1047                                 clock-names = "se";
1048                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1049                                 pinctrl-names = "default";
1050                                 pinctrl-0 = <&qup_spi9_default>;
1051                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1052                                 #address-cells = <1>;
1053                                 #size-cells = <0>;
1054                                 power-domains = <&rpmhpd SM8250_CX>;
1055                                 operating-points-v2 = <&qup_opp_table>;
1056                                 status = "disabled";
1057                         };
1058
1059                         i2c10: i2c@a88000 {
1060                                 compatible = "qcom,geni-i2c";
1061                                 reg = <0 0x00a88000 0 0x4000>;
1062                                 clock-names = "se";
1063                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1064                                 pinctrl-names = "default";
1065                                 pinctrl-0 = <&qup_i2c10_default>;
1066                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1067                                 #address-cells = <1>;
1068                                 #size-cells = <0>;
1069                                 status = "disabled";
1070                         };
1071
1072                         spi10: spi@a88000 {
1073                                 compatible = "qcom,geni-spi";
1074                                 reg = <0 0x00a88000 0 0x4000>;
1075                                 clock-names = "se";
1076                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1077                                 pinctrl-names = "default";
1078                                 pinctrl-0 = <&qup_spi10_default>;
1079                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1080                                 #address-cells = <1>;
1081                                 #size-cells = <0>;
1082                                 power-domains = <&rpmhpd SM8250_CX>;
1083                                 operating-points-v2 = <&qup_opp_table>;
1084                                 status = "disabled";
1085                         };
1086
1087                         i2c11: i2c@a8c000 {
1088                                 compatible = "qcom,geni-i2c";
1089                                 reg = <0 0x00a8c000 0 0x4000>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1092                                 pinctrl-names = "default";
1093                                 pinctrl-0 = <&qup_i2c11_default>;
1094                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 status = "disabled";
1098                         };
1099
1100                         spi11: spi@a8c000 {
1101                                 compatible = "qcom,geni-spi";
1102                                 reg = <0 0x00a8c000 0 0x4000>;
1103                                 clock-names = "se";
1104                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1105                                 pinctrl-names = "default";
1106                                 pinctrl-0 = <&qup_spi11_default>;
1107                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1108                                 #address-cells = <1>;
1109                                 #size-cells = <0>;
1110                                 power-domains = <&rpmhpd SM8250_CX>;
1111                                 operating-points-v2 = <&qup_opp_table>;
1112                                 status = "disabled";
1113                         };
1114
1115                         i2c12: i2c@a90000 {
1116                                 compatible = "qcom,geni-i2c";
1117                                 reg = <0 0x00a90000 0 0x4000>;
1118                                 clock-names = "se";
1119                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&qup_i2c12_default>;
1122                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 status = "disabled";
1126                         };
1127
1128                         spi12: spi@a90000 {
1129                                 compatible = "qcom,geni-spi";
1130                                 reg = <0 0x00a90000 0 0x4000>;
1131                                 clock-names = "se";
1132                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1133                                 pinctrl-names = "default";
1134                                 pinctrl-0 = <&qup_spi12_default>;
1135                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 power-domains = <&rpmhpd SM8250_CX>;
1139                                 operating-points-v2 = <&qup_opp_table>;
1140                                 status = "disabled";
1141                         };
1142
1143                         uart12: serial@a90000 {
1144                                 compatible = "qcom,geni-debug-uart";
1145                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1146                                 clock-names = "se";
1147                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1148                                 pinctrl-names = "default";
1149                                 pinctrl-0 = <&qup_uart12_default>;
1150                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1151                                 power-domains = <&rpmhpd SM8250_CX>;
1152                                 operating-points-v2 = <&qup_opp_table>;
1153                                 status = "disabled";
1154                         };
1155
1156                         i2c13: i2c@a94000 {
1157                                 compatible = "qcom,geni-i2c";
1158                                 reg = <0 0x00a94000 0 0x4000>;
1159                                 clock-names = "se";
1160                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1161                                 pinctrl-names = "default";
1162                                 pinctrl-0 = <&qup_i2c13_default>;
1163                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1164                                 #address-cells = <1>;
1165                                 #size-cells = <0>;
1166                                 status = "disabled";
1167                         };
1168
1169                         spi13: spi@a94000 {
1170                                 compatible = "qcom,geni-spi";
1171                                 reg = <0 0x00a94000 0 0x4000>;
1172                                 clock-names = "se";
1173                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1174                                 pinctrl-names = "default";
1175                                 pinctrl-0 = <&qup_spi13_default>;
1176                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1177                                 #address-cells = <1>;
1178                                 #size-cells = <0>;
1179                                 power-domains = <&rpmhpd SM8250_CX>;
1180                                 operating-points-v2 = <&qup_opp_table>;
1181                                 status = "disabled";
1182                         };
1183                 };
1184
1185                 config_noc: interconnect@1500000 {
1186                         compatible = "qcom,sm8250-config-noc";
1187                         reg = <0 0x01500000 0 0xa580>;
1188                         #interconnect-cells = <1>;
1189                         qcom,bcm-voters = <&apps_bcm_voter>;
1190                 };
1191
1192                 system_noc: interconnect@1620000 {
1193                         compatible = "qcom,sm8250-system-noc";
1194                         reg = <0 0x01620000 0 0x1c200>;
1195                         #interconnect-cells = <1>;
1196                         qcom,bcm-voters = <&apps_bcm_voter>;
1197                 };
1198
1199                 mc_virt: interconnect@163d000 {
1200                         compatible = "qcom,sm8250-mc-virt";
1201                         reg = <0 0x0163d000 0 0x1000>;
1202                         #interconnect-cells = <1>;
1203                         qcom,bcm-voters = <&apps_bcm_voter>;
1204                 };
1205
1206                 aggre1_noc: interconnect@16e0000 {
1207                         compatible = "qcom,sm8250-aggre1-noc";
1208                         reg = <0 0x016e0000 0 0x1f180>;
1209                         #interconnect-cells = <1>;
1210                         qcom,bcm-voters = <&apps_bcm_voter>;
1211                 };
1212
1213                 aggre2_noc: interconnect@1700000 {
1214                         compatible = "qcom,sm8250-aggre2-noc";
1215                         reg = <0 0x01700000 0 0x33000>;
1216                         #interconnect-cells = <1>;
1217                         qcom,bcm-voters = <&apps_bcm_voter>;
1218                 };
1219
1220                 compute_noc: interconnect@1733000 {
1221                         compatible = "qcom,sm8250-compute-noc";
1222                         reg = <0 0x01733000 0 0xa180>;
1223                         #interconnect-cells = <1>;
1224                         qcom,bcm-voters = <&apps_bcm_voter>;
1225                 };
1226
1227                 mmss_noc: interconnect@1740000 {
1228                         compatible = "qcom,sm8250-mmss-noc";
1229                         reg = <0 0x01740000 0 0x1f080>;
1230                         #interconnect-cells = <1>;
1231                         qcom,bcm-voters = <&apps_bcm_voter>;
1232                 };
1233
1234                 pcie0: pci@1c00000 {
1235                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1236                         reg = <0 0x01c00000 0 0x3000>,
1237                               <0 0x60000000 0 0xf1d>,
1238                               <0 0x60000f20 0 0xa8>,
1239                               <0 0x60001000 0 0x1000>,
1240                               <0 0x60100000 0 0x100000>;
1241                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1242                         device_type = "pci";
1243                         linux,pci-domain = <0>;
1244                         bus-range = <0x00 0xff>;
1245                         num-lanes = <1>;
1246
1247                         #address-cells = <3>;
1248                         #size-cells = <2>;
1249
1250                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1251                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1252
1253                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1254                         interrupt-names = "msi";
1255                         #interrupt-cells = <1>;
1256                         interrupt-map-mask = <0 0 0 0x7>;
1257                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1258                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1259                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1260                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1261
1262                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1263                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1264                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1265                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1266                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1267                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1268                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1269                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1270                         clock-names = "pipe",
1271                                       "aux",
1272                                       "cfg",
1273                                       "bus_master",
1274                                       "bus_slave",
1275                                       "slave_q2a",
1276                                       "tbu",
1277                                       "ddrss_sf_tbu";
1278
1279                         iommus = <&apps_smmu 0x1c00 0x7f>;
1280                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1281                                     <0x100 &apps_smmu 0x1c01 0x1>;
1282
1283                         resets = <&gcc GCC_PCIE_0_BCR>;
1284                         reset-names = "pci";
1285
1286                         power-domains = <&gcc PCIE_0_GDSC>;
1287
1288                         phys = <&pcie0_lane>;
1289                         phy-names = "pciephy";
1290
1291                         status = "disabled";
1292                 };
1293
1294                 pcie0_phy: phy@1c06000 {
1295                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1296                         reg = <0 0x01c06000 0 0x1c0>;
1297                         #address-cells = <2>;
1298                         #size-cells = <2>;
1299                         ranges;
1300                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1301                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1302                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1303                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1304                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1305
1306                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1307                         reset-names = "phy";
1308
1309                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1310                         assigned-clock-rates = <100000000>;
1311
1312                         status = "disabled";
1313
1314                         pcie0_lane: lanes@1c06200 {
1315                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1316                                       <0 0x1c06400 0 0x200>, /* rx */
1317                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1318                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1319                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1320                                 clock-names = "pipe0";
1321
1322                                 #phy-cells = <0>;
1323                                 clock-output-names = "pcie_0_pipe_clk";
1324                         };
1325                 };
1326
1327                 pcie1: pci@1c08000 {
1328                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1329                         reg = <0 0x01c08000 0 0x3000>,
1330                               <0 0x40000000 0 0xf1d>,
1331                               <0 0x40000f20 0 0xa8>,
1332                               <0 0x40001000 0 0x1000>,
1333                               <0 0x40100000 0 0x100000>;
1334                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1335                         device_type = "pci";
1336                         linux,pci-domain = <1>;
1337                         bus-range = <0x00 0xff>;
1338                         num-lanes = <2>;
1339
1340                         #address-cells = <3>;
1341                         #size-cells = <2>;
1342
1343                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1344                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1345
1346                         interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
1347                         interrupt-names = "msi";
1348                         #interrupt-cells = <1>;
1349                         interrupt-map-mask = <0 0 0 0x7>;
1350                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1351                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1352                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1353                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1354
1355                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1356                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1357                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1358                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1359                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1360                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1361                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1362                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1363                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1364                         clock-names = "pipe",
1365                                       "aux",
1366                                       "cfg",
1367                                       "bus_master",
1368                                       "bus_slave",
1369                                       "slave_q2a",
1370                                       "ref",
1371                                       "tbu",
1372                                       "ddrss_sf_tbu";
1373
1374                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1375                         assigned-clock-rates = <19200000>;
1376
1377                         iommus = <&apps_smmu 0x1c80 0x7f>;
1378                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1379                                     <0x100 &apps_smmu 0x1c81 0x1>;
1380
1381                         resets = <&gcc GCC_PCIE_1_BCR>;
1382                         reset-names = "pci";
1383
1384                         power-domains = <&gcc PCIE_1_GDSC>;
1385
1386                         phys = <&pcie1_lane>;
1387                         phy-names = "pciephy";
1388
1389                         status = "disabled";
1390                 };
1391
1392                 pcie1_phy: phy@1c0e000 {
1393                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1394                         reg = <0 0x01c0e000 0 0x1c0>;
1395                         #address-cells = <2>;
1396                         #size-cells = <2>;
1397                         ranges;
1398                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1399                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1400                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1401                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1402                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1403
1404                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1405                         reset-names = "phy";
1406
1407                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1408                         assigned-clock-rates = <100000000>;
1409
1410                         status = "disabled";
1411
1412                         pcie1_lane: lanes@1c0e200 {
1413                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1414                                       <0 0x1c0e400 0 0x200>, /* rx0 */
1415                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
1416                                       <0 0x1c0e600 0 0x170>, /* tx1 */
1417                                       <0 0x1c0e800 0 0x200>, /* rx1 */
1418                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1419                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1420                                 clock-names = "pipe0";
1421
1422                                 #phy-cells = <0>;
1423                                 clock-output-names = "pcie_1_pipe_clk";
1424                         };
1425                 };
1426
1427                 pcie2: pci@1c10000 {
1428                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1429                         reg = <0 0x01c10000 0 0x3000>,
1430                               <0 0x64000000 0 0xf1d>,
1431                               <0 0x64000f20 0 0xa8>,
1432                               <0 0x64001000 0 0x1000>,
1433                               <0 0x64100000 0 0x100000>;
1434                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1435                         device_type = "pci";
1436                         linux,pci-domain = <2>;
1437                         bus-range = <0x00 0xff>;
1438                         num-lanes = <2>;
1439
1440                         #address-cells = <3>;
1441                         #size-cells = <2>;
1442
1443                         ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
1444                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
1445
1446                         interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
1447                         interrupt-names = "msi";
1448                         #interrupt-cells = <1>;
1449                         interrupt-map-mask = <0 0 0 0x7>;
1450                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1451                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1452                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1453                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1454
1455                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1456                                  <&gcc GCC_PCIE_2_AUX_CLK>,
1457                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1458                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1459                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1460                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1461                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1462                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1463                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1464                         clock-names = "pipe",
1465                                       "aux",
1466                                       "cfg",
1467                                       "bus_master",
1468                                       "bus_slave",
1469                                       "slave_q2a",
1470                                       "ref",
1471                                       "tbu",
1472                                       "ddrss_sf_tbu";
1473
1474                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1475                         assigned-clock-rates = <19200000>;
1476
1477                         iommus = <&apps_smmu 0x1d00 0x7f>;
1478                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
1479                                     <0x100 &apps_smmu 0x1d01 0x1>;
1480
1481                         resets = <&gcc GCC_PCIE_2_BCR>;
1482                         reset-names = "pci";
1483
1484                         power-domains = <&gcc PCIE_2_GDSC>;
1485
1486                         phys = <&pcie2_lane>;
1487                         phy-names = "pciephy";
1488
1489                         status = "disabled";
1490                 };
1491
1492                 pcie2_phy: phy@1c16000 {
1493                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1494                         reg = <0 0x1c16000 0 0x1c0>;
1495                         #address-cells = <2>;
1496                         #size-cells = <2>;
1497                         ranges;
1498                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1499                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1500                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1501                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1502                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1503
1504                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1505                         reset-names = "phy";
1506
1507                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1508                         assigned-clock-rates = <100000000>;
1509
1510                         status = "disabled";
1511
1512                         pcie2_lane: lanes@1c0e200 {
1513                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1514                                       <0 0x1c16400 0 0x200>, /* rx0 */
1515                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
1516                                       <0 0x1c16600 0 0x170>, /* tx1 */
1517                                       <0 0x1c16800 0 0x200>, /* rx1 */
1518                                       <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1519                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1520                                 clock-names = "pipe0";
1521
1522                                 #phy-cells = <0>;
1523                                 clock-output-names = "pcie_2_pipe_clk";
1524                         };
1525                 };
1526
1527                 ufs_mem_hc: ufshc@1d84000 {
1528                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1529                                      "jedec,ufs-2.0";
1530                         reg = <0 0x01d84000 0 0x3000>;
1531                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1532                         phys = <&ufs_mem_phy_lanes>;
1533                         phy-names = "ufsphy";
1534                         lanes-per-direction = <2>;
1535                         #reset-cells = <1>;
1536                         resets = <&gcc GCC_UFS_PHY_BCR>;
1537                         reset-names = "rst";
1538
1539                         power-domains = <&gcc UFS_PHY_GDSC>;
1540
1541                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1542
1543                         clock-names =
1544                                 "core_clk",
1545                                 "bus_aggr_clk",
1546                                 "iface_clk",
1547                                 "core_clk_unipro",
1548                                 "ref_clk",
1549                                 "tx_lane0_sync_clk",
1550                                 "rx_lane0_sync_clk",
1551                                 "rx_lane1_sync_clk";
1552                         clocks =
1553                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1554                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1555                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1556                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1557                                 <&rpmhcc RPMH_CXO_CLK>,
1558                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1559                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1560                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1561                         freq-table-hz =
1562                                 <37500000 300000000>,
1563                                 <0 0>,
1564                                 <0 0>,
1565                                 <37500000 300000000>,
1566                                 <0 0>,
1567                                 <0 0>,
1568                                 <0 0>,
1569                                 <0 0>;
1570
1571                         status = "disabled";
1572                 };
1573
1574                 ufs_mem_phy: phy@1d87000 {
1575                         compatible = "qcom,sm8250-qmp-ufs-phy";
1576                         reg = <0 0x01d87000 0 0x1c0>;
1577                         #address-cells = <2>;
1578                         #size-cells = <2>;
1579                         ranges;
1580                         clock-names = "ref",
1581                                       "ref_aux";
1582                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1583                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1584
1585                         resets = <&ufs_mem_hc 0>;
1586                         reset-names = "ufsphy";
1587                         status = "disabled";
1588
1589                         ufs_mem_phy_lanes: lanes@1d87400 {
1590                                 reg = <0 0x01d87400 0 0x108>,
1591                                       <0 0x01d87600 0 0x1e0>,
1592                                       <0 0x01d87c00 0 0x1dc>,
1593                                       <0 0x01d87800 0 0x108>,
1594                                       <0 0x01d87a00 0 0x1e0>;
1595                                 #phy-cells = <0>;
1596                         };
1597                 };
1598
1599                 ipa_virt: interconnect@1e00000 {
1600                         compatible = "qcom,sm8250-ipa-virt";
1601                         reg = <0 0x01e00000 0 0x1000>;
1602                         #interconnect-cells = <1>;
1603                         qcom,bcm-voters = <&apps_bcm_voter>;
1604                 };
1605
1606                 tcsr_mutex: hwlock@1f40000 {
1607                         compatible = "qcom,tcsr-mutex";
1608                         reg = <0x0 0x01f40000 0x0 0x40000>;
1609                         #hwlock-cells = <1>;
1610                 };
1611
1612                 wsamacro: codec@3240000 {
1613                         compatible = "qcom,sm8250-lpass-wsa-macro";
1614                         reg = <0 0x03240000 0 0x1000>;
1615                         clocks = <&audiocc 1>,
1616                                  <&audiocc 0>,
1617                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1618                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1619                                  <&aoncc 0>,
1620                                  <&vamacro>;
1621
1622                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1623
1624                         #clock-cells = <0>;
1625                         clock-frequency = <9600000>;
1626                         clock-output-names = "mclk";
1627                         #sound-dai-cells = <1>;
1628
1629                         pinctrl-names = "default";
1630                         pinctrl-0 = <&wsa_swr_active>;
1631                 };
1632
1633                 swr0: soundwire-controller@3250000 {
1634                         reg = <0 0x03250000 0 0x2000>;
1635                         compatible = "qcom,soundwire-v1.5.1";
1636                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1637                         clocks = <&wsamacro>;
1638                         clock-names = "iface";
1639
1640                         qcom,din-ports = <2>;
1641                         qcom,dout-ports = <6>;
1642
1643                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1644                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1645                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1646                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1647
1648                         #sound-dai-cells = <1>;
1649                         #address-cells = <2>;
1650                         #size-cells = <0>;
1651                 };
1652
1653                 audiocc: clock-controller@3300000 {
1654                         compatible = "qcom,sm8250-lpass-audiocc";
1655                         reg = <0 0x03300000 0 0x30000>;
1656                         #clock-cells = <1>;
1657                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1658                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1659                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1660                         clock-names = "core", "audio", "bus";
1661                 };
1662
1663                 vamacro: codec@3370000 {
1664                         compatible = "qcom,sm8250-lpass-va-macro";
1665                         reg = <0 0x03370000 0 0x1000>;
1666                         clocks = <&aoncc 0>,
1667                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1668                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1669
1670                         clock-names = "mclk", "macro", "dcodec";
1671
1672                         #clock-cells = <0>;
1673                         clock-frequency = <9600000>;
1674                         clock-output-names = "fsgen";
1675                         #sound-dai-cells = <1>;
1676                 };
1677
1678                 aoncc: clock-controller@3380000 {
1679                         compatible = "qcom,sm8250-lpass-aoncc";
1680                         reg = <0 0x03380000 0 0x40000>;
1681                         #clock-cells = <1>;
1682                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1683                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1684                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1685                         clock-names = "core", "audio", "bus";
1686                 };
1687
1688                 lpass_tlmm: pinctrl@33c0000{
1689                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1690                         reg = <0 0x033c0000 0x0 0x20000>,
1691                               <0 0x03550000 0x0 0x10000>;
1692                         gpio-controller;
1693                         #gpio-cells = <2>;
1694                         gpio-ranges = <&lpass_tlmm 0 0 14>;
1695
1696                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1697                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1698                         clock-names = "core", "audio";
1699
1700                         wsa_swr_active: wsa-swr-active-pins {
1701                                 clk {
1702                                         pins = "gpio10";
1703                                         function = "wsa_swr_clk";
1704                                         drive-strength = <2>;
1705                                         slew-rate = <1>;
1706                                         bias-disable;
1707                                 };
1708
1709                                 data {
1710                                         pins = "gpio11";
1711                                         function = "wsa_swr_data";
1712                                         drive-strength = <2>;
1713                                         slew-rate = <1>;
1714                                         bias-bus-hold;
1715
1716                                 };
1717                         };
1718
1719                         wsa_swr_sleep: wsa-swr-sleep-pins {
1720                                 clk {
1721                                         pins = "gpio10";
1722                                         function = "wsa_swr_clk";
1723                                         drive-strength = <2>;
1724                                         input-enable;
1725                                         bias-pull-down;
1726                                 };
1727
1728                                 data {
1729                                         pins = "gpio11";
1730                                         function = "wsa_swr_data";
1731                                         drive-strength = <2>;
1732                                         input-enable;
1733                                         bias-pull-down;
1734
1735                                 };
1736                         };
1737
1738                         dmic01_active: dmic01-active-pins {
1739                                 clk {
1740                                         pins = "gpio6";
1741                                         function = "dmic1_clk";
1742                                         drive-strength = <8>;
1743                                         output-high;
1744                                 };
1745                                 data {
1746                                         pins = "gpio7";
1747                                         function = "dmic1_data";
1748                                         drive-strength = <8>;
1749                                         input-enable;
1750                                 };
1751                         };
1752
1753                         dmic01_sleep: dmic01-sleep-pins {
1754                                 clk {
1755                                         pins = "gpio6";
1756                                         function = "dmic1_clk";
1757                                         drive-strength = <2>;
1758                                         bias-disable;
1759                                         output-low;
1760                                 };
1761
1762                                 data {
1763                                         pins = "gpio7";
1764                                         function = "dmic1_data";
1765                                         drive-strength = <2>;
1766                                         pull-down;
1767                                         input-enable;
1768                                 };
1769                         };
1770                 };
1771
1772                 gpu: gpu@3d00000 {
1773                         compatible = "qcom,adreno-650.2",
1774                                      "qcom,adreno";
1775                         #stream-id-cells = <16>;
1776
1777                         reg = <0 0x03d00000 0 0x40000>;
1778                         reg-names = "kgsl_3d0_reg_memory";
1779
1780                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1781
1782                         iommus = <&adreno_smmu 0 0x401>;
1783
1784                         operating-points-v2 = <&gpu_opp_table>;
1785
1786                         qcom,gmu = <&gmu>;
1787
1788                         zap-shader {
1789                                 memory-region = <&gpu_mem>;
1790                         };
1791
1792                         /* note: downstream checks gpu binning for 670 Mhz */
1793                         gpu_opp_table: opp-table {
1794                                 compatible = "operating-points-v2";
1795
1796                                 opp-670000000 {
1797                                         opp-hz = /bits/ 64 <670000000>;
1798                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1799                                 };
1800
1801                                 opp-587000000 {
1802                                         opp-hz = /bits/ 64 <587000000>;
1803                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1804                                 };
1805
1806                                 opp-525000000 {
1807                                         opp-hz = /bits/ 64 <525000000>;
1808                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1809                                 };
1810
1811                                 opp-490000000 {
1812                                         opp-hz = /bits/ 64 <490000000>;
1813                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1814                                 };
1815
1816                                 opp-441600000 {
1817                                         opp-hz = /bits/ 64 <441600000>;
1818                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1819                                 };
1820
1821                                 opp-400000000 {
1822                                         opp-hz = /bits/ 64 <400000000>;
1823                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1824                                 };
1825
1826                                 opp-305000000 {
1827                                         opp-hz = /bits/ 64 <305000000>;
1828                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1829                                 };
1830                         };
1831                 };
1832
1833                 gmu: gmu@3d6a000 {
1834                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1835
1836                         reg = <0 0x03d6a000 0 0x30000>,
1837                               <0 0x3de0000 0 0x10000>,
1838                               <0 0xb290000 0 0x10000>,
1839                               <0 0xb490000 0 0x10000>;
1840                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1841
1842                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1843                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1844                         interrupt-names = "hfi", "gmu";
1845
1846                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1847                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1848                                  <&gpucc GPU_CC_CXO_CLK>,
1849                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1850                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1851                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1852
1853                         power-domains = <&gpucc GPU_CX_GDSC>,
1854                                         <&gpucc GPU_GX_GDSC>;
1855                         power-domain-names = "cx", "gx";
1856
1857                         iommus = <&adreno_smmu 5 0x400>;
1858
1859                         operating-points-v2 = <&gmu_opp_table>;
1860
1861                         gmu_opp_table: opp-table {
1862                                 compatible = "operating-points-v2";
1863
1864                                 opp-200000000 {
1865                                         opp-hz = /bits/ 64 <200000000>;
1866                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1867                                 };
1868                         };
1869                 };
1870
1871                 gpucc: clock-controller@3d90000 {
1872                         compatible = "qcom,sm8250-gpucc";
1873                         reg = <0 0x03d90000 0 0x9000>;
1874                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1875                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1876                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1877                         clock-names = "bi_tcxo",
1878                                       "gcc_gpu_gpll0_clk_src",
1879                                       "gcc_gpu_gpll0_div_clk_src";
1880                         #clock-cells = <1>;
1881                         #reset-cells = <1>;
1882                         #power-domain-cells = <1>;
1883                 };
1884
1885                 adreno_smmu: iommu@3da0000 {
1886                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1887                         reg = <0 0x03da0000 0 0x10000>;
1888                         #iommu-cells = <2>;
1889                         #global-interrupts = <2>;
1890                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1891                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1892                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1893                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1894                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1895                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1896                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1897                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1898                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1899                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1900                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1901                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1902                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1903                         clock-names = "ahb", "bus", "iface";
1904
1905                         power-domains = <&gpucc GPU_CX_GDSC>;
1906                 };
1907
1908                 slpi: remoteproc@5c00000 {
1909                         compatible = "qcom,sm8250-slpi-pas";
1910                         reg = <0 0x05c00000 0 0x4000>;
1911
1912                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1913                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1914                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1915                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1916                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1917                         interrupt-names = "wdog", "fatal", "ready",
1918                                           "handover", "stop-ack";
1919
1920                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1921                         clock-names = "xo";
1922
1923                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1924                                         <&rpmhpd SM8250_LCX>,
1925                                         <&rpmhpd SM8250_LMX>;
1926                         power-domain-names = "load_state", "lcx", "lmx";
1927
1928                         memory-region = <&slpi_mem>;
1929
1930                         qcom,smem-states = <&smp2p_slpi_out 0>;
1931                         qcom,smem-state-names = "stop";
1932
1933                         status = "disabled";
1934
1935                         glink-edge {
1936                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1937                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1938                                                              IRQ_TYPE_EDGE_RISING>;
1939                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1940                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1941
1942                                 label = "slpi";
1943                                 qcom,remote-pid = <3>;
1944
1945                                 fastrpc {
1946                                         compatible = "qcom,fastrpc";
1947                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1948                                         label = "sdsp";
1949                                         #address-cells = <1>;
1950                                         #size-cells = <0>;
1951
1952                                         compute-cb@1 {
1953                                                 compatible = "qcom,fastrpc-compute-cb";
1954                                                 reg = <1>;
1955                                                 iommus = <&apps_smmu 0x0541 0x0>;
1956                                         };
1957
1958                                         compute-cb@2 {
1959                                                 compatible = "qcom,fastrpc-compute-cb";
1960                                                 reg = <2>;
1961                                                 iommus = <&apps_smmu 0x0542 0x0>;
1962                                         };
1963
1964                                         compute-cb@3 {
1965                                                 compatible = "qcom,fastrpc-compute-cb";
1966                                                 reg = <3>;
1967                                                 iommus = <&apps_smmu 0x0543 0x0>;
1968                                                 /* note: shared-cb = <4> in downstream */
1969                                         };
1970                                 };
1971                         };
1972                 };
1973
1974                 cdsp: remoteproc@8300000 {
1975                         compatible = "qcom,sm8250-cdsp-pas";
1976                         reg = <0 0x08300000 0 0x10000>;
1977
1978                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1979                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1980                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1981                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1982                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1983                         interrupt-names = "wdog", "fatal", "ready",
1984                                           "handover", "stop-ack";
1985
1986                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1987                         clock-names = "xo";
1988
1989                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1990                                         <&rpmhpd SM8250_CX>;
1991                         power-domain-names = "load_state", "cx";
1992
1993                         memory-region = <&cdsp_mem>;
1994
1995                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1996                         qcom,smem-state-names = "stop";
1997
1998                         status = "disabled";
1999
2000                         glink-edge {
2001                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2002                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2003                                                              IRQ_TYPE_EDGE_RISING>;
2004                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2005                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2006
2007                                 label = "cdsp";
2008                                 qcom,remote-pid = <5>;
2009
2010                                 fastrpc {
2011                                         compatible = "qcom,fastrpc";
2012                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2013                                         label = "cdsp";
2014                                         #address-cells = <1>;
2015                                         #size-cells = <0>;
2016
2017                                         compute-cb@1 {
2018                                                 compatible = "qcom,fastrpc-compute-cb";
2019                                                 reg = <1>;
2020                                                 iommus = <&apps_smmu 0x1001 0x0460>;
2021                                         };
2022
2023                                         compute-cb@2 {
2024                                                 compatible = "qcom,fastrpc-compute-cb";
2025                                                 reg = <2>;
2026                                                 iommus = <&apps_smmu 0x1002 0x0460>;
2027                                         };
2028
2029                                         compute-cb@3 {
2030                                                 compatible = "qcom,fastrpc-compute-cb";
2031                                                 reg = <3>;
2032                                                 iommus = <&apps_smmu 0x1003 0x0460>;
2033                                         };
2034
2035                                         compute-cb@4 {
2036                                                 compatible = "qcom,fastrpc-compute-cb";
2037                                                 reg = <4>;
2038                                                 iommus = <&apps_smmu 0x1004 0x0460>;
2039                                         };
2040
2041                                         compute-cb@5 {
2042                                                 compatible = "qcom,fastrpc-compute-cb";
2043                                                 reg = <5>;
2044                                                 iommus = <&apps_smmu 0x1005 0x0460>;
2045                                         };
2046
2047                                         compute-cb@6 {
2048                                                 compatible = "qcom,fastrpc-compute-cb";
2049                                                 reg = <6>;
2050                                                 iommus = <&apps_smmu 0x1006 0x0460>;
2051                                         };
2052
2053                                         compute-cb@7 {
2054                                                 compatible = "qcom,fastrpc-compute-cb";
2055                                                 reg = <7>;
2056                                                 iommus = <&apps_smmu 0x1007 0x0460>;
2057                                         };
2058
2059                                         compute-cb@8 {
2060                                                 compatible = "qcom,fastrpc-compute-cb";
2061                                                 reg = <8>;
2062                                                 iommus = <&apps_smmu 0x1008 0x0460>;
2063                                         };
2064
2065                                         /* note: secure cb9 in downstream */
2066                                 };
2067                         };
2068                 };
2069
2070                 sound: sound {
2071                 };
2072
2073                 usb_1_hsphy: phy@88e3000 {
2074                         compatible = "qcom,sm8250-usb-hs-phy",
2075                                      "qcom,usb-snps-hs-7nm-phy";
2076                         reg = <0 0x088e3000 0 0x400>;
2077                         status = "disabled";
2078                         #phy-cells = <0>;
2079
2080                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2081                         clock-names = "ref";
2082
2083                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2084                 };
2085
2086                 usb_2_hsphy: phy@88e4000 {
2087                         compatible = "qcom,sm8250-usb-hs-phy",
2088                                      "qcom,usb-snps-hs-7nm-phy";
2089                         reg = <0 0x088e4000 0 0x400>;
2090                         status = "disabled";
2091                         #phy-cells = <0>;
2092
2093                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2094                         clock-names = "ref";
2095
2096                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2097                 };
2098
2099                 usb_1_qmpphy: phy@88e9000 {
2100                         compatible = "qcom,sm8250-qmp-usb3-phy";
2101                         reg = <0 0x088e9000 0 0x200>,
2102                               <0 0x088e8000 0 0x20>;
2103                         reg-names = "reg-base", "dp_com";
2104                         status = "disabled";
2105                         #clock-cells = <1>;
2106                         #address-cells = <2>;
2107                         #size-cells = <2>;
2108                         ranges;
2109
2110                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2111                                  <&rpmhcc RPMH_CXO_CLK>,
2112                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2113                         clock-names = "aux", "ref_clk_src", "com_aux";
2114
2115                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2116                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2117                         reset-names = "phy", "common";
2118
2119                         usb_1_ssphy: lanes@88e9200 {
2120                                 reg = <0 0x088e9200 0 0x200>,
2121                                       <0 0x088e9400 0 0x200>,
2122                                       <0 0x088e9c00 0 0x400>,
2123                                       <0 0x088e9600 0 0x200>,
2124                                       <0 0x088e9800 0 0x200>,
2125                                       <0 0x088e9a00 0 0x100>;
2126                                 #phy-cells = <0>;
2127                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2128                                 clock-names = "pipe0";
2129                                 clock-output-names = "usb3_phy_pipe_clk_src";
2130                         };
2131                 };
2132
2133                 usb_2_qmpphy: phy@88eb000 {
2134                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2135                         reg = <0 0x088eb000 0 0x200>;
2136                         status = "disabled";
2137                         #clock-cells = <1>;
2138                         #address-cells = <2>;
2139                         #size-cells = <2>;
2140                         ranges;
2141
2142                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2143                                  <&rpmhcc RPMH_CXO_CLK>,
2144                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2145                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2146                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2147
2148                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2149                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2150                         reset-names = "phy", "common";
2151
2152                         usb_2_ssphy: lane@88eb200 {
2153                                 reg = <0 0x088eb200 0 0x200>,
2154                                       <0 0x088eb400 0 0x200>,
2155                                       <0 0x088eb800 0 0x800>;
2156                                 #phy-cells = <0>;
2157                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2158                                 clock-names = "pipe0";
2159                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2160                         };
2161                 };
2162
2163                 sdhc_2: sdhci@8804000 {
2164                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2165                         reg = <0 0x08804000 0 0x1000>;
2166
2167                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2168                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2169                         interrupt-names = "hc_irq", "pwr_irq";
2170
2171                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2172                                  <&gcc GCC_SDCC2_APPS_CLK>,
2173                                  <&rpmhcc RPMH_CXO_CLK>;
2174                         clock-names = "iface", "core", "xo";
2175                         iommus = <&apps_smmu 0x4a0 0x0>;
2176                         qcom,dll-config = <0x0007642c>;
2177                         qcom,ddr-config = <0x80040868>;
2178                         power-domains = <&rpmhpd SM8250_CX>;
2179                         operating-points-v2 = <&sdhc2_opp_table>;
2180
2181                         status = "disabled";
2182
2183                         sdhc2_opp_table: sdhc2-opp-table {
2184                                 compatible = "operating-points-v2";
2185
2186                                 opp-19200000 {
2187                                         opp-hz = /bits/ 64 <19200000>;
2188                                         required-opps = <&rpmhpd_opp_min_svs>;
2189                                 };
2190
2191                                 opp-50000000 {
2192                                         opp-hz = /bits/ 64 <50000000>;
2193                                         required-opps = <&rpmhpd_opp_low_svs>;
2194                                 };
2195
2196                                 opp-100000000 {
2197                                         opp-hz = /bits/ 64 <100000000>;
2198                                         required-opps = <&rpmhpd_opp_svs>;
2199                                 };
2200
2201                                 opp-202000000 {
2202                                         opp-hz = /bits/ 64 <202000000>;
2203                                         required-opps = <&rpmhpd_opp_svs_l1>;
2204                                 };
2205                         };
2206                 };
2207
2208                 dc_noc: interconnect@90c0000 {
2209                         compatible = "qcom,sm8250-dc-noc";
2210                         reg = <0 0x090c0000 0 0x4200>;
2211                         #interconnect-cells = <1>;
2212                         qcom,bcm-voters = <&apps_bcm_voter>;
2213                 };
2214
2215                 gem_noc: interconnect@9100000 {
2216                         compatible = "qcom,sm8250-gem-noc";
2217                         reg = <0 0x09100000 0 0xb4000>;
2218                         #interconnect-cells = <1>;
2219                         qcom,bcm-voters = <&apps_bcm_voter>;
2220                 };
2221
2222                 npu_noc: interconnect@9990000 {
2223                         compatible = "qcom,sm8250-npu-noc";
2224                         reg = <0 0x09990000 0 0x1600>;
2225                         #interconnect-cells = <1>;
2226                         qcom,bcm-voters = <&apps_bcm_voter>;
2227                 };
2228
2229                 usb_1: usb@a6f8800 {
2230                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2231                         reg = <0 0x0a6f8800 0 0x400>;
2232                         status = "disabled";
2233                         #address-cells = <2>;
2234                         #size-cells = <2>;
2235                         ranges;
2236                         dma-ranges;
2237
2238                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2239                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2240                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2241                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2242                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2243                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2244                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2245                                       "sleep", "xo";
2246
2247                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2248                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2249                         assigned-clock-rates = <19200000>, <200000000>;
2250
2251                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2252                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2253                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2254                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2255                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2256                                           "dm_hs_phy_irq", "ss_phy_irq";
2257
2258                         power-domains = <&gcc USB30_PRIM_GDSC>;
2259
2260                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2261
2262                         usb_1_dwc3: dwc3@a600000 {
2263                                 compatible = "snps,dwc3";
2264                                 reg = <0 0x0a600000 0 0xcd00>;
2265                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2266                                 iommus = <&apps_smmu 0x0 0x0>;
2267                                 snps,dis_u2_susphy_quirk;
2268                                 snps,dis_enblslpm_quirk;
2269                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2270                                 phy-names = "usb2-phy", "usb3-phy";
2271                         };
2272                 };
2273
2274                 system-cache-controller@9200000 {
2275                         compatible = "qcom,sm8250-llcc";
2276                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2277                         reg-names = "llcc_base", "llcc_broadcast_base";
2278                 };
2279
2280                 usb_2: usb@a8f8800 {
2281                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2282                         reg = <0 0x0a8f8800 0 0x400>;
2283                         status = "disabled";
2284                         #address-cells = <2>;
2285                         #size-cells = <2>;
2286                         ranges;
2287                         dma-ranges;
2288
2289                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2290                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2291                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2292                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2293                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2294                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2295                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2296                                       "sleep", "xo";
2297
2298                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2299                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2300                         assigned-clock-rates = <19200000>, <200000000>;
2301
2302                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2303                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2304                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2305                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2306                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2307                                           "dm_hs_phy_irq", "ss_phy_irq";
2308
2309                         power-domains = <&gcc USB30_SEC_GDSC>;
2310
2311                         resets = <&gcc GCC_USB30_SEC_BCR>;
2312
2313                         usb_2_dwc3: dwc3@a800000 {
2314                                 compatible = "snps,dwc3";
2315                                 reg = <0 0x0a800000 0 0xcd00>;
2316                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2317                                 iommus = <&apps_smmu 0x20 0>;
2318                                 snps,dis_u2_susphy_quirk;
2319                                 snps,dis_enblslpm_quirk;
2320                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2321                                 phy-names = "usb2-phy", "usb3-phy";
2322                         };
2323                 };
2324
2325                 mdss: mdss@ae00000 {
2326                         compatible = "qcom,sdm845-mdss";
2327                         reg = <0 0x0ae00000 0 0x1000>;
2328                         reg-names = "mdss";
2329
2330                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
2331                                         <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
2332                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
2333                         interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
2334
2335                         power-domains = <&dispcc MDSS_GDSC>;
2336
2337                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2338                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2339                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2340                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2341                         clock-names = "iface", "bus", "nrt_bus", "core";
2342
2343                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2344                         assigned-clock-rates = <460000000>;
2345
2346                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2347                         interrupt-controller;
2348                         #interrupt-cells = <1>;
2349
2350                         iommus = <&apps_smmu 0x820 0x402>;
2351
2352                         status = "disabled";
2353
2354                         #address-cells = <2>;
2355                         #size-cells = <2>;
2356                         ranges;
2357
2358                         mdss_mdp: mdp@ae01000 {
2359                                 compatible = "qcom,sdm845-dpu";
2360                                 reg = <0 0x0ae01000 0 0x8f000>,
2361                                       <0 0x0aeb0000 0 0x2008>;
2362                                 reg-names = "mdp", "vbif";
2363
2364                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2365                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2366                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2367                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2368                                 clock-names = "iface", "bus", "core", "vsync";
2369
2370                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2371                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2372                                 assigned-clock-rates = <460000000>,
2373                                                        <19200000>;
2374
2375                                 operating-points-v2 = <&mdp_opp_table>;
2376                                 power-domains = <&rpmhpd SM8250_MMCX>;
2377
2378                                 interrupt-parent = <&mdss>;
2379                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2380
2381                                 status = "disabled";
2382
2383                                 ports {
2384                                         #address-cells = <1>;
2385                                         #size-cells = <0>;
2386
2387                                         port@0 {
2388                                                 reg = <0>;
2389                                                 dpu_intf1_out: endpoint {
2390                                                         remote-endpoint = <&dsi0_in>;
2391                                                 };
2392                                         };
2393
2394                                         port@1 {
2395                                                 reg = <1>;
2396                                                 dpu_intf2_out: endpoint {
2397                                                         remote-endpoint = <&dsi1_in>;
2398                                                 };
2399                                         };
2400                                 };
2401
2402                                 mdp_opp_table: mdp-opp-table {
2403                                         compatible = "operating-points-v2";
2404
2405                                         opp-200000000 {
2406                                                 opp-hz = /bits/ 64 <200000000>;
2407                                                 required-opps = <&rpmhpd_opp_low_svs>;
2408                                         };
2409
2410                                         opp-300000000 {
2411                                                 opp-hz = /bits/ 64 <300000000>;
2412                                                 required-opps = <&rpmhpd_opp_svs>;
2413                                         };
2414
2415                                         opp-345000000 {
2416                                                 opp-hz = /bits/ 64 <345000000>;
2417                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2418                                         };
2419
2420                                         opp-460000000 {
2421                                                 opp-hz = /bits/ 64 <460000000>;
2422                                                 required-opps = <&rpmhpd_opp_nom>;
2423                                         };
2424                                 };
2425                         };
2426
2427                         dsi0: dsi@ae94000 {
2428                                 compatible = "qcom,mdss-dsi-ctrl";
2429                                 reg = <0 0x0ae94000 0 0x400>;
2430                                 reg-names = "dsi_ctrl";
2431
2432                                 interrupt-parent = <&mdss>;
2433                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2434
2435                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2436                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2437                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2438                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2439                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2440                                         <&gcc GCC_DISP_HF_AXI_CLK>;
2441                                 clock-names = "byte",
2442                                               "byte_intf",
2443                                               "pixel",
2444                                               "core",
2445                                               "iface",
2446                                               "bus";
2447
2448                                 operating-points-v2 = <&dsi_opp_table>;
2449                                 power-domains = <&rpmhpd SM8250_MMCX>;
2450
2451                                 phys = <&dsi0_phy>;
2452                                 phy-names = "dsi";
2453
2454                                 status = "disabled";
2455
2456                                 ports {
2457                                         #address-cells = <1>;
2458                                         #size-cells = <0>;
2459
2460                                         port@0 {
2461                                                 reg = <0>;
2462                                                 dsi0_in: endpoint {
2463                                                         remote-endpoint = <&dpu_intf1_out>;
2464                                                 };
2465                                         };
2466
2467                                         port@1 {
2468                                                 reg = <1>;
2469                                                 dsi0_out: endpoint {
2470                                                 };
2471                                         };
2472                                 };
2473                         };
2474
2475                         dsi0_phy: dsi-phy@ae94400 {
2476                                 compatible = "qcom,dsi-phy-7nm";
2477                                 reg = <0 0x0ae94400 0 0x200>,
2478                                       <0 0x0ae94600 0 0x280>,
2479                                       <0 0x0ae94900 0 0x260>;
2480                                 reg-names = "dsi_phy",
2481                                             "dsi_phy_lane",
2482                                             "dsi_pll";
2483
2484                                 #clock-cells = <1>;
2485                                 #phy-cells = <0>;
2486
2487                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2488                                          <&rpmhcc RPMH_CXO_CLK>;
2489                                 clock-names = "iface", "ref";
2490
2491                                 status = "disabled";
2492                         };
2493
2494                         dsi1: dsi@ae96000 {
2495                                 compatible = "qcom,mdss-dsi-ctrl";
2496                                 reg = <0 0x0ae96000 0 0x400>;
2497                                 reg-names = "dsi_ctrl";
2498
2499                                 interrupt-parent = <&mdss>;
2500                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2501
2502                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2503                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2504                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2505                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2506                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2507                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2508                                 clock-names = "byte",
2509                                               "byte_intf",
2510                                               "pixel",
2511                                               "core",
2512                                               "iface",
2513                                               "bus";
2514
2515                                 operating-points-v2 = <&dsi_opp_table>;
2516                                 power-domains = <&rpmhpd SM8250_MMCX>;
2517
2518                                 phys = <&dsi1_phy>;
2519                                 phy-names = "dsi";
2520
2521                                 status = "disabled";
2522
2523                                 ports {
2524                                         #address-cells = <1>;
2525                                         #size-cells = <0>;
2526
2527                                         port@0 {
2528                                                 reg = <0>;
2529                                                 dsi1_in: endpoint {
2530                                                         remote-endpoint = <&dpu_intf2_out>;
2531                                                 };
2532                                         };
2533
2534                                         port@1 {
2535                                                 reg = <1>;
2536                                                 dsi1_out: endpoint {
2537                                                 };
2538                                         };
2539                                 };
2540                         };
2541
2542                         dsi1_phy: dsi-phy@ae96400 {
2543                                 compatible = "qcom,dsi-phy-7nm";
2544                                 reg = <0 0x0ae96400 0 0x200>,
2545                                       <0 0x0ae96600 0 0x280>,
2546                                       <0 0x0ae96900 0 0x260>;
2547                                 reg-names = "dsi_phy",
2548                                             "dsi_phy_lane",
2549                                             "dsi_pll";
2550
2551                                 #clock-cells = <1>;
2552                                 #phy-cells = <0>;
2553
2554                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2555                                          <&rpmhcc RPMH_CXO_CLK>;
2556                                 clock-names = "iface", "ref";
2557
2558                                 status = "disabled";
2559
2560                                 dsi_opp_table: dsi-opp-table {
2561                                         compatible = "operating-points-v2";
2562
2563                                         opp-187500000 {
2564                                                 opp-hz = /bits/ 64 <187500000>;
2565                                                 required-opps = <&rpmhpd_opp_low_svs>;
2566                                         };
2567
2568                                         opp-300000000 {
2569                                                 opp-hz = /bits/ 64 <300000000>;
2570                                                 required-opps = <&rpmhpd_opp_svs>;
2571                                         };
2572
2573                                         opp-358000000 {
2574                                                 opp-hz = /bits/ 64 <358000000>;
2575                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2576                                         };
2577                                 };
2578                         };
2579                 };
2580
2581                 dispcc: clock-controller@af00000 {
2582                         compatible = "qcom,sm8250-dispcc";
2583                         reg = <0 0x0af00000 0 0x20000>;
2584                         mmcx-supply = <&mmcx_reg>;
2585                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2586                                  <&dsi0_phy 0>,
2587                                  <&dsi0_phy 1>,
2588                                  <&dsi1_phy 0>,
2589                                  <&dsi1_phy 1>,
2590                                  <0>,
2591                                  <0>,
2592                                  <0>,
2593                                  <0>,
2594                                  <0>,
2595                                  <0>,
2596                                  <0>,
2597                                  <0>,
2598                                  <&sleep_clk>;
2599                         clock-names = "bi_tcxo",
2600                                       "dsi0_phy_pll_out_byteclk",
2601                                       "dsi0_phy_pll_out_dsiclk",
2602                                       "dsi1_phy_pll_out_byteclk",
2603                                       "dsi1_phy_pll_out_dsiclk",
2604                                       "dp_link_clk_divsel_ten",
2605                                       "dp_vco_divided_clk_src_mux",
2606                                       "dptx1_phy_pll_link_clk",
2607                                       "dptx1_phy_pll_vco_div_clk",
2608                                       "dptx2_phy_pll_link_clk",
2609                                       "dptx2_phy_pll_vco_div_clk",
2610                                       "edp_phy_pll_link_clk",
2611                                       "edp_phy_pll_vco_div_clk",
2612                                       "sleep_clk";
2613                         #clock-cells = <1>;
2614                         #reset-cells = <1>;
2615                         #power-domain-cells = <1>;
2616                 };
2617
2618                 pdc: interrupt-controller@b220000 {
2619                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
2620                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2621                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2622                                           <125 63 1>, <126 716 12>;
2623                         #interrupt-cells = <2>;
2624                         interrupt-parent = <&intc>;
2625                         interrupt-controller;
2626                 };
2627
2628                 tsens0: thermal-sensor@c263000 {
2629                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2630                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2631                               <0 0x0c222000 0 0x1ff>; /* SROT */
2632                         #qcom,sensors = <16>;
2633                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2634                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2635                         interrupt-names = "uplow", "critical";
2636                         #thermal-sensor-cells = <1>;
2637                 };
2638
2639                 tsens1: thermal-sensor@c265000 {
2640                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2641                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2642                               <0 0x0c223000 0 0x1ff>; /* SROT */
2643                         #qcom,sensors = <9>;
2644                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2645                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2646                         interrupt-names = "uplow", "critical";
2647                         #thermal-sensor-cells = <1>;
2648                 };
2649
2650                 aoss_qmp: power-controller@c300000 {
2651                         compatible = "qcom,sm8250-aoss-qmp";
2652                         reg = <0 0x0c300000 0 0x100000>;
2653                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2654                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
2655                                                      IRQ_TYPE_EDGE_RISING>;
2656                         mboxes = <&ipcc IPCC_CLIENT_AOP
2657                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
2658
2659                         #clock-cells = <0>;
2660                         #power-domain-cells = <1>;
2661                 };
2662
2663                 spmi_bus: spmi@c440000 {
2664                         compatible = "qcom,spmi-pmic-arb";
2665                         reg = <0x0 0x0c440000 0x0 0x0001100>,
2666                               <0x0 0x0c600000 0x0 0x2000000>,
2667                               <0x0 0x0e600000 0x0 0x0100000>,
2668                               <0x0 0x0e700000 0x0 0x00a0000>,
2669                               <0x0 0x0c40a000 0x0 0x0026000>;
2670                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2671                         interrupt-names = "periph_irq";
2672                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2673                         qcom,ee = <0>;
2674                         qcom,channel = <0>;
2675                         #address-cells = <2>;
2676                         #size-cells = <0>;
2677                         interrupt-controller;
2678                         #interrupt-cells = <4>;
2679                 };
2680
2681                 tlmm: pinctrl@f100000 {
2682                         compatible = "qcom,sm8250-pinctrl";
2683                         reg = <0 0x0f100000 0 0x300000>,
2684                               <0 0x0f500000 0 0x300000>,
2685                               <0 0x0f900000 0 0x300000>;
2686                         reg-names = "west", "south", "north";
2687                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2688                         gpio-controller;
2689                         #gpio-cells = <2>;
2690                         interrupt-controller;
2691                         #interrupt-cells = <2>;
2692                         gpio-ranges = <&tlmm 0 0 181>;
2693                         wakeup-parent = <&pdc>;
2694
2695                         pri_mi2s_active: pri-mi2s-active {
2696                                 sclk {
2697                                         pins = "gpio138";
2698                                         function = "mi2s0_sck";
2699                                         drive-strength = <8>;
2700                                         bias-disable;
2701                                 };
2702
2703                                 ws {
2704                                         pins = "gpio141";
2705                                         function = "mi2s0_ws";
2706                                         drive-strength = <8>;
2707                                         output-high;
2708                                 };
2709
2710                                 data0 {
2711                                         pins = "gpio139";
2712                                         function = "mi2s0_data0";
2713                                         drive-strength = <8>;
2714                                         bias-disable;
2715                                         output-high;
2716                                 };
2717
2718                                 data1 {
2719                                         pins = "gpio140";
2720                                         function = "mi2s0_data1";
2721                                         drive-strength = <8>;
2722                                         output-high;
2723                                 };
2724                         };
2725
2726                         qup_i2c0_default: qup-i2c0-default {
2727                                 mux {
2728                                         pins = "gpio28", "gpio29";
2729                                         function = "qup0";
2730                                 };
2731
2732                                 config {
2733                                         pins = "gpio28", "gpio29";
2734                                         drive-strength = <2>;
2735                                         bias-disable;
2736                                 };
2737                         };
2738
2739                         qup_i2c1_default: qup-i2c1-default {
2740                                 pinmux {
2741                                         pins = "gpio4", "gpio5";
2742                                         function = "qup1";
2743                                 };
2744
2745                                 config {
2746                                         pins = "gpio4", "gpio5";
2747                                         drive-strength = <2>;
2748                                         bias-disable;
2749                                 };
2750                         };
2751
2752                         qup_i2c2_default: qup-i2c2-default {
2753                                 mux {
2754                                         pins = "gpio115", "gpio116";
2755                                         function = "qup2";
2756                                 };
2757
2758                                 config {
2759                                         pins = "gpio115", "gpio116";
2760                                         drive-strength = <2>;
2761                                         bias-disable;
2762                                 };
2763                         };
2764
2765                         qup_i2c3_default: qup-i2c3-default {
2766                                 mux {
2767                                         pins = "gpio119", "gpio120";
2768                                         function = "qup3";
2769                                 };
2770
2771                                 config {
2772                                         pins = "gpio119", "gpio120";
2773                                         drive-strength = <2>;
2774                                         bias-disable;
2775                                 };
2776                         };
2777
2778                         qup_i2c4_default: qup-i2c4-default {
2779                                 mux {
2780                                         pins = "gpio8", "gpio9";
2781                                         function = "qup4";
2782                                 };
2783
2784                                 config {
2785                                         pins = "gpio8", "gpio9";
2786                                         drive-strength = <2>;
2787                                         bias-disable;
2788                                 };
2789                         };
2790
2791                         qup_i2c5_default: qup-i2c5-default {
2792                                 mux {
2793                                         pins = "gpio12", "gpio13";
2794                                         function = "qup5";
2795                                 };
2796
2797                                 config {
2798                                         pins = "gpio12", "gpio13";
2799                                         drive-strength = <2>;
2800                                         bias-disable;
2801                                 };
2802                         };
2803
2804                         qup_i2c6_default: qup-i2c6-default {
2805                                 mux {
2806                                         pins = "gpio16", "gpio17";
2807                                         function = "qup6";
2808                                 };
2809
2810                                 config {
2811                                         pins = "gpio16", "gpio17";
2812                                         drive-strength = <2>;
2813                                         bias-disable;
2814                                 };
2815                         };
2816
2817                         qup_i2c7_default: qup-i2c7-default {
2818                                 mux {
2819                                         pins = "gpio20", "gpio21";
2820                                         function = "qup7";
2821                                 };
2822
2823                                 config {
2824                                         pins = "gpio20", "gpio21";
2825                                         drive-strength = <2>;
2826                                         bias-disable;
2827                                 };
2828                         };
2829
2830                         qup_i2c8_default: qup-i2c8-default {
2831                                 mux {
2832                                         pins = "gpio24", "gpio25";
2833                                         function = "qup8";
2834                                 };
2835
2836                                 config {
2837                                         pins = "gpio24", "gpio25";
2838                                         drive-strength = <2>;
2839                                         bias-disable;
2840                                 };
2841                         };
2842
2843                         qup_i2c9_default: qup-i2c9-default {
2844                                 mux {
2845                                         pins = "gpio125", "gpio126";
2846                                         function = "qup9";
2847                                 };
2848
2849                                 config {
2850                                         pins = "gpio125", "gpio126";
2851                                         drive-strength = <2>;
2852                                         bias-disable;
2853                                 };
2854                         };
2855
2856                         qup_i2c10_default: qup-i2c10-default {
2857                                 mux {
2858                                         pins = "gpio129", "gpio130";
2859                                         function = "qup10";
2860                                 };
2861
2862                                 config {
2863                                         pins = "gpio129", "gpio130";
2864                                         drive-strength = <2>;
2865                                         bias-disable;
2866                                 };
2867                         };
2868
2869                         qup_i2c11_default: qup-i2c11-default {
2870                                 mux {
2871                                         pins = "gpio60", "gpio61";
2872                                         function = "qup11";
2873                                 };
2874
2875                                 config {
2876                                         pins = "gpio60", "gpio61";
2877                                         drive-strength = <2>;
2878                                         bias-disable;
2879                                 };
2880                         };
2881
2882                         qup_i2c12_default: qup-i2c12-default {
2883                                 mux {
2884                                         pins = "gpio32", "gpio33";
2885                                         function = "qup12";
2886                                 };
2887
2888                                 config {
2889                                         pins = "gpio32", "gpio33";
2890                                         drive-strength = <2>;
2891                                         bias-disable;
2892                                 };
2893                         };
2894
2895                         qup_i2c13_default: qup-i2c13-default {
2896                                 mux {
2897                                         pins = "gpio36", "gpio37";
2898                                         function = "qup13";
2899                                 };
2900
2901                                 config {
2902                                         pins = "gpio36", "gpio37";
2903                                         drive-strength = <2>;
2904                                         bias-disable;
2905                                 };
2906                         };
2907
2908                         qup_i2c14_default: qup-i2c14-default {
2909                                 mux {
2910                                         pins = "gpio40", "gpio41";
2911                                         function = "qup14";
2912                                 };
2913
2914                                 config {
2915                                         pins = "gpio40", "gpio41";
2916                                         drive-strength = <2>;
2917                                         bias-disable;
2918                                 };
2919                         };
2920
2921                         qup_i2c15_default: qup-i2c15-default {
2922                                 mux {
2923                                         pins = "gpio44", "gpio45";
2924                                         function = "qup15";
2925                                 };
2926
2927                                 config {
2928                                         pins = "gpio44", "gpio45";
2929                                         drive-strength = <2>;
2930                                         bias-disable;
2931                                 };
2932                         };
2933
2934                         qup_i2c16_default: qup-i2c16-default {
2935                                 mux {
2936                                         pins = "gpio48", "gpio49";
2937                                         function = "qup16";
2938                                 };
2939
2940                                 config {
2941                                         pins = "gpio48", "gpio49";
2942                                         drive-strength = <2>;
2943                                         bias-disable;
2944                                 };
2945                         };
2946
2947                         qup_i2c17_default: qup-i2c17-default {
2948                                 mux {
2949                                         pins = "gpio52", "gpio53";
2950                                         function = "qup17";
2951                                 };
2952
2953                                 config {
2954                                         pins = "gpio52", "gpio53";
2955                                         drive-strength = <2>;
2956                                         bias-disable;
2957                                 };
2958                         };
2959
2960                         qup_i2c18_default: qup-i2c18-default {
2961                                 mux {
2962                                         pins = "gpio56", "gpio57";
2963                                         function = "qup18";
2964                                 };
2965
2966                                 config {
2967                                         pins = "gpio56", "gpio57";
2968                                         drive-strength = <2>;
2969                                         bias-disable;
2970                                 };
2971                         };
2972
2973                         qup_i2c19_default: qup-i2c19-default {
2974                                 mux {
2975                                         pins = "gpio0", "gpio1";
2976                                         function = "qup19";
2977                                 };
2978
2979                                 config {
2980                                         pins = "gpio0", "gpio1";
2981                                         drive-strength = <2>;
2982                                         bias-disable;
2983                                 };
2984                         };
2985
2986                         qup_spi0_default: qup-spi0-default {
2987                                 pins = "gpio28", "gpio29",
2988                                        "gpio30", "gpio31";
2989                                 function = "qup0";
2990                         };
2991
2992                         qup_spi1_default: qup-spi1-default {
2993                                 pins = "gpio4", "gpio5",
2994                                        "gpio6", "gpio7";
2995                                 function = "qup1";
2996                         };
2997
2998                         qup_spi2_default: qup-spi2-default {
2999                                 pins = "gpio115", "gpio116",
3000                                        "gpio117", "gpio118";
3001                                 function = "qup2";
3002                         };
3003
3004                         qup_spi3_default: qup-spi3-default {
3005                                 pins = "gpio119", "gpio120",
3006                                        "gpio121", "gpio122";
3007                                 function = "qup3";
3008                         };
3009
3010                         qup_spi4_default: qup-spi4-default {
3011                                 pins = "gpio8", "gpio9",
3012                                        "gpio10", "gpio11";
3013                                 function = "qup4";
3014                         };
3015
3016                         qup_spi5_default: qup-spi5-default {
3017                                 pins = "gpio12", "gpio13",
3018                                        "gpio14", "gpio15";
3019                                 function = "qup5";
3020                         };
3021
3022                         qup_spi6_default: qup-spi6-default {
3023                                 pins = "gpio16", "gpio17",
3024                                        "gpio18", "gpio19";
3025                                 function = "qup6";
3026                         };
3027
3028                         qup_spi7_default: qup-spi7-default {
3029                                 pins = "gpio20", "gpio21",
3030                                        "gpio22", "gpio23";
3031                                 function = "qup7";
3032                         };
3033
3034                         qup_spi8_default: qup-spi8-default {
3035                                 pins = "gpio24", "gpio25",
3036                                        "gpio26", "gpio27";
3037                                 function = "qup8";
3038                         };
3039
3040                         qup_spi9_default: qup-spi9-default {
3041                                 pins = "gpio125", "gpio126",
3042                                        "gpio127", "gpio128";
3043                                 function = "qup9";
3044                         };
3045
3046                         qup_spi10_default: qup-spi10-default {
3047                                 pins = "gpio129", "gpio130",
3048                                        "gpio131", "gpio132";
3049                                 function = "qup10";
3050                         };
3051
3052                         qup_spi11_default: qup-spi11-default {
3053                                 pins = "gpio60", "gpio61",
3054                                        "gpio62", "gpio63";
3055                                 function = "qup11";
3056                         };
3057
3058                         qup_spi12_default: qup-spi12-default {
3059                                 pins = "gpio32", "gpio33",
3060                                        "gpio34", "gpio35";
3061                                 function = "qup12";
3062                         };
3063
3064                         qup_spi13_default: qup-spi13-default {
3065                                 pins = "gpio36", "gpio37",
3066                                        "gpio38", "gpio39";
3067                                 function = "qup13";
3068                         };
3069
3070                         qup_spi14_default: qup-spi14-default {
3071                                 pins = "gpio40", "gpio41",
3072                                        "gpio42", "gpio43";
3073                                 function = "qup14";
3074                         };
3075
3076                         qup_spi15_default: qup-spi15-default {
3077                                 pins = "gpio44", "gpio45",
3078                                        "gpio46", "gpio47";
3079                                 function = "qup15";
3080                         };
3081
3082                         qup_spi16_default: qup-spi16-default {
3083                                 pins = "gpio48", "gpio49",
3084                                        "gpio50", "gpio51";
3085                                 function = "qup16";
3086                         };
3087
3088                         qup_spi17_default: qup-spi17-default {
3089                                 pins = "gpio52", "gpio53",
3090                                        "gpio54", "gpio55";
3091                                 function = "qup17";
3092                         };
3093
3094                         qup_spi18_default: qup-spi18-default {
3095                                 pins = "gpio56", "gpio57",
3096                                        "gpio58", "gpio59";
3097                                 function = "qup18";
3098                         };
3099
3100                         qup_spi19_default: qup-spi19-default {
3101                                 pins = "gpio0", "gpio1",
3102                                        "gpio2", "gpio3";
3103                                 function = "qup19";
3104                         };
3105
3106                         qup_uart2_default: qup-uart2-default {
3107                                 mux {
3108                                         pins = "gpio117", "gpio118";
3109                                         function = "qup2";
3110                                 };
3111                         };
3112
3113                         qup_uart6_default: qup-uart6-default {
3114                                 mux {
3115                                         pins = "gpio16", "gpio17",
3116                                                 "gpio18", "gpio19";
3117                                         function = "qup6";
3118                                 };
3119                         };
3120
3121                         qup_uart12_default: qup-uart12-default {
3122                                 mux {
3123                                         pins = "gpio34", "gpio35";
3124                                         function = "qup12";
3125                                 };
3126                         };
3127
3128                         qup_uart17_default: qup-uart17-default {
3129                                 mux {
3130                                         pins = "gpio52", "gpio53",
3131                                                 "gpio54", "gpio55";
3132                                         function = "qup17";
3133                                 };
3134                         };
3135
3136                         qup_uart18_default: qup-uart18-default {
3137                                 mux {
3138                                         pins = "gpio58", "gpio59";
3139                                         function = "qup18";
3140                                 };
3141                         };
3142
3143                         tert_mi2s_active: tert-mi2s-active {
3144                                 sck {
3145                                         pins = "gpio133";
3146                                         function = "mi2s2_sck";
3147                                         drive-strength = <8>;
3148                                         bias-disable;
3149                                 };
3150
3151                                 data0 {
3152                                         pins = "gpio134";
3153                                         function = "mi2s2_data0";
3154                                         drive-strength = <8>;
3155                                         bias-disable;
3156                                         output-high;
3157                                 };
3158
3159                                 ws {
3160                                         pins = "gpio135";
3161                                         function = "mi2s2_ws";
3162                                         drive-strength = <8>;
3163                                         output-high;
3164                                 };
3165                         };
3166                 };
3167
3168                 apps_smmu: iommu@15000000 {
3169                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3170                         reg = <0 0x15000000 0 0x100000>;
3171                         #iommu-cells = <2>;
3172                         #global-interrupts = <2>;
3173                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3174                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3175                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3176                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3177                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3178                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3179                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3180                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3181                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3182                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3183                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3184                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3185                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3186                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3187                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3188                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3189                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3190                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3191                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3192                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3193                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3194                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3195                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3196                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3197                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3198                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3199                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3200                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3201                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3202                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3203                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3204                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3205                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3206                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3207                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3208                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3209                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3210                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3211                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3212                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3213                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3214                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3215                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3216                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3217                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3218                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3219                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3220                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3221                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3222                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3223                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3224                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3225                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3226                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3227                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3228                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3229                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3230                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3231                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3232                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3233                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3234                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3235                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3236                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3237                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3238                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3239                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3240                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3241                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3242                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3243                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3244                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3245                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3246                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3247                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3248                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3249                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3250                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3251                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3252                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3253                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3254                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3255                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3256                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3257                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3258                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3259                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3260                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3261                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3262                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3263                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3264                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3265                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3266                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3267                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3268                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3269                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3270                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3271                 };
3272
3273                 adsp: remoteproc@17300000 {
3274                         compatible = "qcom,sm8250-adsp-pas";
3275                         reg = <0 0x17300000 0 0x100>;
3276
3277                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3278                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3279                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3280                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3281                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3282                         interrupt-names = "wdog", "fatal", "ready",
3283                                           "handover", "stop-ack";
3284
3285                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3286                         clock-names = "xo";
3287
3288                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3289                                         <&rpmhpd SM8250_LCX>,
3290                                         <&rpmhpd SM8250_LMX>;
3291                         power-domain-names = "load_state", "lcx", "lmx";
3292
3293                         memory-region = <&adsp_mem>;
3294
3295                         qcom,smem-states = <&smp2p_adsp_out 0>;
3296                         qcom,smem-state-names = "stop";
3297
3298                         status = "disabled";
3299
3300                         glink-edge {
3301                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3302                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3303                                                              IRQ_TYPE_EDGE_RISING>;
3304                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
3305                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3306
3307                                 label = "lpass";
3308                                 qcom,remote-pid = <2>;
3309
3310                                 apr {
3311                                         compatible = "qcom,apr-v2";
3312                                         qcom,glink-channels = "apr_audio_svc";
3313                                         qcom,apr-domain = <APR_DOMAIN_ADSP>;
3314                                         #address-cells = <1>;
3315                                         #size-cells = <0>;
3316
3317                                         apr-service@3 {
3318                                                 reg = <APR_SVC_ADSP_CORE>;
3319                                                 compatible = "qcom,q6core";
3320                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3321                                         };
3322
3323                                         q6afe: apr-service@4 {
3324                                                 compatible = "qcom,q6afe";
3325                                                 reg = <APR_SVC_AFE>;
3326                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3327                                                 q6afedai: dais {
3328                                                         compatible = "qcom,q6afe-dais";
3329                                                         #address-cells = <1>;
3330                                                         #size-cells = <0>;
3331                                                         #sound-dai-cells = <1>;
3332                                                 };
3333
3334                                                 q6afecc: cc {
3335                                                         compatible = "qcom,q6afe-clocks";
3336                                                         #clock-cells = <2>;
3337                                                 };
3338                                         };
3339
3340                                         q6asm: apr-service@7 {
3341                                                 compatible = "qcom,q6asm";
3342                                                 reg = <APR_SVC_ASM>;
3343                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3344                                                 q6asmdai: dais {
3345                                                         compatible = "qcom,q6asm-dais";
3346                                                         #address-cells = <1>;
3347                                                         #size-cells = <0>;
3348                                                         #sound-dai-cells = <1>;
3349                                                         iommus = <&apps_smmu 0x1801 0x0>;
3350                                                 };
3351                                         };
3352
3353                                         q6adm: apr-service@8 {
3354                                                 compatible = "qcom,q6adm";
3355                                                 reg = <APR_SVC_ADM>;
3356                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3357                                                 q6routing: routing {
3358                                                         compatible = "qcom,q6adm-routing";
3359                                                         #sound-dai-cells = <0>;
3360                                                 };
3361                                         };
3362                                 };
3363
3364                                 fastrpc {
3365                                         compatible = "qcom,fastrpc";
3366                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3367                                         label = "adsp";
3368                                         #address-cells = <1>;
3369                                         #size-cells = <0>;
3370
3371                                         compute-cb@3 {
3372                                                 compatible = "qcom,fastrpc-compute-cb";
3373                                                 reg = <3>;
3374                                                 iommus = <&apps_smmu 0x1803 0x0>;
3375                                         };
3376
3377                                         compute-cb@4 {
3378                                                 compatible = "qcom,fastrpc-compute-cb";
3379                                                 reg = <4>;
3380                                                 iommus = <&apps_smmu 0x1804 0x0>;
3381                                         };
3382
3383                                         compute-cb@5 {
3384                                                 compatible = "qcom,fastrpc-compute-cb";
3385                                                 reg = <5>;
3386                                                 iommus = <&apps_smmu 0x1805 0x0>;
3387                                         };
3388                                 };
3389                         };
3390                 };
3391
3392                 intc: interrupt-controller@17a00000 {
3393                         compatible = "arm,gic-v3";
3394                         #interrupt-cells = <3>;
3395                         interrupt-controller;
3396                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3397                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3398                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3399                 };
3400
3401                 watchdog@17c10000 {
3402                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3403                         reg = <0 0x17c10000 0 0x1000>;
3404                         clocks = <&sleep_clk>;
3405                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3406                 };
3407
3408                 timer@17c20000 {
3409                         #address-cells = <2>;
3410                         #size-cells = <2>;
3411                         ranges;
3412                         compatible = "arm,armv7-timer-mem";
3413                         reg = <0x0 0x17c20000 0x0 0x1000>;
3414                         clock-frequency = <19200000>;
3415
3416                         frame@17c21000 {
3417                                 frame-number = <0>;
3418                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3419                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3420                                 reg = <0x0 0x17c21000 0x0 0x1000>,
3421                                       <0x0 0x17c22000 0x0 0x1000>;
3422                         };
3423
3424                         frame@17c23000 {
3425                                 frame-number = <1>;
3426                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3427                                 reg = <0x0 0x17c23000 0x0 0x1000>;
3428                                 status = "disabled";
3429                         };
3430
3431                         frame@17c25000 {
3432                                 frame-number = <2>;
3433                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3434                                 reg = <0x0 0x17c25000 0x0 0x1000>;
3435                                 status = "disabled";
3436                         };
3437
3438                         frame@17c27000 {
3439                                 frame-number = <3>;
3440                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3441                                 reg = <0x0 0x17c27000 0x0 0x1000>;
3442                                 status = "disabled";
3443                         };
3444
3445                         frame@17c29000 {
3446                                 frame-number = <4>;
3447                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3448                                 reg = <0x0 0x17c29000 0x0 0x1000>;
3449                                 status = "disabled";
3450                         };
3451
3452                         frame@17c2b000 {
3453                                 frame-number = <5>;
3454                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3455                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
3456                                 status = "disabled";
3457                         };
3458
3459                         frame@17c2d000 {
3460                                 frame-number = <6>;
3461                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3462                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
3463                                 status = "disabled";
3464                         };
3465                 };
3466
3467                 apps_rsc: rsc@18200000 {
3468                         label = "apps_rsc";
3469                         compatible = "qcom,rpmh-rsc";
3470                         reg = <0x0 0x18200000 0x0 0x10000>,
3471                                 <0x0 0x18210000 0x0 0x10000>,
3472                                 <0x0 0x18220000 0x0 0x10000>;
3473                         reg-names = "drv-0", "drv-1", "drv-2";
3474                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3475                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3476                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3477                         qcom,tcs-offset = <0xd00>;
3478                         qcom,drv-id = <2>;
3479                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3480                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
3481
3482                         rpmhcc: clock-controller {
3483                                 compatible = "qcom,sm8250-rpmh-clk";
3484                                 #clock-cells = <1>;
3485                                 clock-names = "xo";
3486                                 clocks = <&xo_board>;
3487                         };
3488
3489                         rpmhpd: power-controller {
3490                                 compatible = "qcom,sm8250-rpmhpd";
3491                                 #power-domain-cells = <1>;
3492                                 operating-points-v2 = <&rpmhpd_opp_table>;
3493
3494                                 rpmhpd_opp_table: opp-table {
3495                                         compatible = "operating-points-v2";
3496
3497                                         rpmhpd_opp_ret: opp1 {
3498                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3499                                         };
3500
3501                                         rpmhpd_opp_min_svs: opp2 {
3502                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3503                                         };
3504
3505                                         rpmhpd_opp_low_svs: opp3 {
3506                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3507                                         };
3508
3509                                         rpmhpd_opp_svs: opp4 {
3510                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3511                                         };
3512
3513                                         rpmhpd_opp_svs_l1: opp5 {
3514                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3515                                         };
3516
3517                                         rpmhpd_opp_nom: opp6 {
3518                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3519                                         };
3520
3521                                         rpmhpd_opp_nom_l1: opp7 {
3522                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3523                                         };
3524
3525                                         rpmhpd_opp_nom_l2: opp8 {
3526                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3527                                         };
3528
3529                                         rpmhpd_opp_turbo: opp9 {
3530                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3531                                         };
3532
3533                                         rpmhpd_opp_turbo_l1: opp10 {
3534                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3535                                         };
3536                                 };
3537                         };
3538
3539                         apps_bcm_voter: bcm_voter {
3540                                 compatible = "qcom,bcm-voter";
3541                         };
3542                 };
3543
3544                 epss_l3: interconnect@18591000 {
3545                         compatible = "qcom,sm8250-epss-l3";
3546                         reg = <0 0x18590000 0 0x1000>;
3547
3548                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3549                         clock-names = "xo", "alternate";
3550
3551                         #interconnect-cells = <1>;
3552                 };
3553
3554                 cpufreq_hw: cpufreq@18591000 {
3555                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3556                         reg = <0 0x18591000 0 0x1000>,
3557                               <0 0x18592000 0 0x1000>,
3558                               <0 0x18593000 0 0x1000>;
3559                         reg-names = "freq-domain0", "freq-domain1",
3560                                     "freq-domain2";
3561
3562                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3563                         clock-names = "xo", "alternate";
3564
3565                         #freq-domain-cells = <1>;
3566                 };
3567         };
3568
3569         timer {
3570                 compatible = "arm,armv8-timer";
3571                 interrupts = <GIC_PPI 13
3572                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3573                              <GIC_PPI 14
3574                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3575                              <GIC_PPI 11
3576                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3577                              <GIC_PPI 10
3578                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3579         };
3580
3581         thermal-zones {
3582                 cpu0-thermal {
3583                         polling-delay-passive = <250>;
3584                         polling-delay = <1000>;
3585
3586                         thermal-sensors = <&tsens0 1>;
3587
3588                         trips {
3589                                 cpu0_alert0: trip-point0 {
3590                                         temperature = <90000>;
3591                                         hysteresis = <2000>;
3592                                         type = "passive";
3593                                 };
3594
3595                                 cpu0_alert1: trip-point1 {
3596                                         temperature = <95000>;
3597                                         hysteresis = <2000>;
3598                                         type = "passive";
3599                                 };
3600
3601                                 cpu0_crit: cpu_crit {
3602                                         temperature = <110000>;
3603                                         hysteresis = <1000>;
3604                                         type = "critical";
3605                                 };
3606                         };
3607
3608                         cooling-maps {
3609                                 map0 {
3610                                         trip = <&cpu0_alert0>;
3611                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3612                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3613                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3614                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3615                                 };
3616                                 map1 {
3617                                         trip = <&cpu0_alert1>;
3618                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3619                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3620                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3621                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3622                                 };
3623                         };
3624                 };
3625
3626                 cpu1-thermal {
3627                         polling-delay-passive = <250>;
3628                         polling-delay = <1000>;
3629
3630                         thermal-sensors = <&tsens0 2>;
3631
3632                         trips {
3633                                 cpu1_alert0: trip-point0 {
3634                                         temperature = <90000>;
3635                                         hysteresis = <2000>;
3636                                         type = "passive";
3637                                 };
3638
3639                                 cpu1_alert1: trip-point1 {
3640                                         temperature = <95000>;
3641                                         hysteresis = <2000>;
3642                                         type = "passive";
3643                                 };
3644
3645                                 cpu1_crit: cpu_crit {
3646                                         temperature = <110000>;
3647                                         hysteresis = <1000>;
3648                                         type = "critical";
3649                                 };
3650                         };
3651
3652                         cooling-maps {
3653                                 map0 {
3654                                         trip = <&cpu1_alert0>;
3655                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3659                                 };
3660                                 map1 {
3661                                         trip = <&cpu1_alert1>;
3662                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3663                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3664                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3665                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3666                                 };
3667                         };
3668                 };
3669
3670                 cpu2-thermal {
3671                         polling-delay-passive = <250>;
3672                         polling-delay = <1000>;
3673
3674                         thermal-sensors = <&tsens0 3>;
3675
3676                         trips {
3677                                 cpu2_alert0: trip-point0 {
3678                                         temperature = <90000>;
3679                                         hysteresis = <2000>;
3680                                         type = "passive";
3681                                 };
3682
3683                                 cpu2_alert1: trip-point1 {
3684                                         temperature = <95000>;
3685                                         hysteresis = <2000>;
3686                                         type = "passive";
3687                                 };
3688
3689                                 cpu2_crit: cpu_crit {
3690                                         temperature = <110000>;
3691                                         hysteresis = <1000>;
3692                                         type = "critical";
3693                                 };
3694                         };
3695
3696                         cooling-maps {
3697                                 map0 {
3698                                         trip = <&cpu2_alert0>;
3699                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3700                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3701                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3702                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3703                                 };
3704                                 map1 {
3705                                         trip = <&cpu2_alert1>;
3706                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3707                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3708                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3709                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3710                                 };
3711                         };
3712                 };
3713
3714                 cpu3-thermal {
3715                         polling-delay-passive = <250>;
3716                         polling-delay = <1000>;
3717
3718                         thermal-sensors = <&tsens0 4>;
3719
3720                         trips {
3721                                 cpu3_alert0: trip-point0 {
3722                                         temperature = <90000>;
3723                                         hysteresis = <2000>;
3724                                         type = "passive";
3725                                 };
3726
3727                                 cpu3_alert1: trip-point1 {
3728                                         temperature = <95000>;
3729                                         hysteresis = <2000>;
3730                                         type = "passive";
3731                                 };
3732
3733                                 cpu3_crit: cpu_crit {
3734                                         temperature = <110000>;
3735                                         hysteresis = <1000>;
3736                                         type = "critical";
3737                                 };
3738                         };
3739
3740                         cooling-maps {
3741                                 map0 {
3742                                         trip = <&cpu3_alert0>;
3743                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3744                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3745                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3746                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3747                                 };
3748                                 map1 {
3749                                         trip = <&cpu3_alert1>;
3750                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3751                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3752                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3753                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3754                                 };
3755                         };
3756                 };
3757
3758                 cpu4-top-thermal {
3759                         polling-delay-passive = <250>;
3760                         polling-delay = <1000>;
3761
3762                         thermal-sensors = <&tsens0 7>;
3763
3764                         trips {
3765                                 cpu4_top_alert0: trip-point0 {
3766                                         temperature = <90000>;
3767                                         hysteresis = <2000>;
3768                                         type = "passive";
3769                                 };
3770
3771                                 cpu4_top_alert1: trip-point1 {
3772                                         temperature = <95000>;
3773                                         hysteresis = <2000>;
3774                                         type = "passive";
3775                                 };
3776
3777                                 cpu4_top_crit: cpu_crit {
3778                                         temperature = <110000>;
3779                                         hysteresis = <1000>;
3780                                         type = "critical";
3781                                 };
3782                         };
3783
3784                         cooling-maps {
3785                                 map0 {
3786                                         trip = <&cpu4_top_alert0>;
3787                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3788                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3789                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3790                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3791                                 };
3792                                 map1 {
3793                                         trip = <&cpu4_top_alert1>;
3794                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3795                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3796                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3797                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3798                                 };
3799                         };
3800                 };
3801
3802                 cpu5-top-thermal {
3803                         polling-delay-passive = <250>;
3804                         polling-delay = <1000>;
3805
3806                         thermal-sensors = <&tsens0 8>;
3807
3808                         trips {
3809                                 cpu5_top_alert0: trip-point0 {
3810                                         temperature = <90000>;
3811                                         hysteresis = <2000>;
3812                                         type = "passive";
3813                                 };
3814
3815                                 cpu5_top_alert1: trip-point1 {
3816                                         temperature = <95000>;
3817                                         hysteresis = <2000>;
3818                                         type = "passive";
3819                                 };
3820
3821                                 cpu5_top_crit: cpu_crit {
3822                                         temperature = <110000>;
3823                                         hysteresis = <1000>;
3824                                         type = "critical";
3825                                 };
3826                         };
3827
3828                         cooling-maps {
3829                                 map0 {
3830                                         trip = <&cpu5_top_alert0>;
3831                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3832                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3834                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3835                                 };
3836                                 map1 {
3837                                         trip = <&cpu5_top_alert1>;
3838                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3839                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3840                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3841                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3842                                 };
3843                         };
3844                 };
3845
3846                 cpu6-top-thermal {
3847                         polling-delay-passive = <250>;
3848                         polling-delay = <1000>;
3849
3850                         thermal-sensors = <&tsens0 9>;
3851
3852                         trips {
3853                                 cpu6_top_alert0: trip-point0 {
3854                                         temperature = <90000>;
3855                                         hysteresis = <2000>;
3856                                         type = "passive";
3857                                 };
3858
3859                                 cpu6_top_alert1: trip-point1 {
3860                                         temperature = <95000>;
3861                                         hysteresis = <2000>;
3862                                         type = "passive";
3863                                 };
3864
3865                                 cpu6_top_crit: cpu_crit {
3866                                         temperature = <110000>;
3867                                         hysteresis = <1000>;
3868                                         type = "critical";
3869                                 };
3870                         };
3871
3872                         cooling-maps {
3873                                 map0 {
3874                                         trip = <&cpu6_top_alert0>;
3875                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3876                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3877                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3878                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3879                                 };
3880                                 map1 {
3881                                         trip = <&cpu6_top_alert1>;
3882                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3883                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3884                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3886                                 };
3887                         };
3888                 };
3889
3890                 cpu7-top-thermal {
3891                         polling-delay-passive = <250>;
3892                         polling-delay = <1000>;
3893
3894                         thermal-sensors = <&tsens0 10>;
3895
3896                         trips {
3897                                 cpu7_top_alert0: trip-point0 {
3898                                         temperature = <90000>;
3899                                         hysteresis = <2000>;
3900                                         type = "passive";
3901                                 };
3902
3903                                 cpu7_top_alert1: trip-point1 {
3904                                         temperature = <95000>;
3905                                         hysteresis = <2000>;
3906                                         type = "passive";
3907                                 };
3908
3909                                 cpu7_top_crit: cpu_crit {
3910                                         temperature = <110000>;
3911                                         hysteresis = <1000>;
3912                                         type = "critical";
3913                                 };
3914                         };
3915
3916                         cooling-maps {
3917                                 map0 {
3918                                         trip = <&cpu7_top_alert0>;
3919                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3920                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3921                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3922                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3923                                 };
3924                                 map1 {
3925                                         trip = <&cpu7_top_alert1>;
3926                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3927                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3928                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3929                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3930                                 };
3931                         };
3932                 };
3933
3934                 cpu4-bottom-thermal {
3935                         polling-delay-passive = <250>;
3936                         polling-delay = <1000>;
3937
3938                         thermal-sensors = <&tsens0 11>;
3939
3940                         trips {
3941                                 cpu4_bottom_alert0: trip-point0 {
3942                                         temperature = <90000>;
3943                                         hysteresis = <2000>;
3944                                         type = "passive";
3945                                 };
3946
3947                                 cpu4_bottom_alert1: trip-point1 {
3948                                         temperature = <95000>;
3949                                         hysteresis = <2000>;
3950                                         type = "passive";
3951                                 };
3952
3953                                 cpu4_bottom_crit: cpu_crit {
3954                                         temperature = <110000>;
3955                                         hysteresis = <1000>;
3956                                         type = "critical";
3957                                 };
3958                         };
3959
3960                         cooling-maps {
3961                                 map0 {
3962                                         trip = <&cpu4_bottom_alert0>;
3963                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3964                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3965                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3966                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3967                                 };
3968                                 map1 {
3969                                         trip = <&cpu4_bottom_alert1>;
3970                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3971                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3972                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3973                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3974                                 };
3975                         };
3976                 };
3977
3978                 cpu5-bottom-thermal {
3979                         polling-delay-passive = <250>;
3980                         polling-delay = <1000>;
3981
3982                         thermal-sensors = <&tsens0 12>;
3983
3984                         trips {
3985                                 cpu5_bottom_alert0: trip-point0 {
3986                                         temperature = <90000>;
3987                                         hysteresis = <2000>;
3988                                         type = "passive";
3989                                 };
3990
3991                                 cpu5_bottom_alert1: trip-point1 {
3992                                         temperature = <95000>;
3993                                         hysteresis = <2000>;
3994                                         type = "passive";
3995                                 };
3996
3997                                 cpu5_bottom_crit: cpu_crit {
3998                                         temperature = <110000>;
3999                                         hysteresis = <1000>;
4000                                         type = "critical";
4001                                 };
4002                         };
4003
4004                         cooling-maps {
4005                                 map0 {
4006                                         trip = <&cpu5_bottom_alert0>;
4007                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4008                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4009                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4010                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4011                                 };
4012                                 map1 {
4013                                         trip = <&cpu5_bottom_alert1>;
4014                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4015                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4016                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4017                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4018                                 };
4019                         };
4020                 };
4021
4022                 cpu6-bottom-thermal {
4023                         polling-delay-passive = <250>;
4024                         polling-delay = <1000>;
4025
4026                         thermal-sensors = <&tsens0 13>;
4027
4028                         trips {
4029                                 cpu6_bottom_alert0: trip-point0 {
4030                                         temperature = <90000>;
4031                                         hysteresis = <2000>;
4032                                         type = "passive";
4033                                 };
4034
4035                                 cpu6_bottom_alert1: trip-point1 {
4036                                         temperature = <95000>;
4037                                         hysteresis = <2000>;
4038                                         type = "passive";
4039                                 };
4040
4041                                 cpu6_bottom_crit: cpu_crit {
4042                                         temperature = <110000>;
4043                                         hysteresis = <1000>;
4044                                         type = "critical";
4045                                 };
4046                         };
4047
4048                         cooling-maps {
4049                                 map0 {
4050                                         trip = <&cpu6_bottom_alert0>;
4051                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4052                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4053                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4054                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4055                                 };
4056                                 map1 {
4057                                         trip = <&cpu6_bottom_alert1>;
4058                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4059                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4060                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4061                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4062                                 };
4063                         };
4064                 };
4065
4066                 cpu7-bottom-thermal {
4067                         polling-delay-passive = <250>;
4068                         polling-delay = <1000>;
4069
4070                         thermal-sensors = <&tsens0 14>;
4071
4072                         trips {
4073                                 cpu7_bottom_alert0: trip-point0 {
4074                                         temperature = <90000>;
4075                                         hysteresis = <2000>;
4076                                         type = "passive";
4077                                 };
4078
4079                                 cpu7_bottom_alert1: trip-point1 {
4080                                         temperature = <95000>;
4081                                         hysteresis = <2000>;
4082                                         type = "passive";
4083                                 };
4084
4085                                 cpu7_bottom_crit: cpu_crit {
4086                                         temperature = <110000>;
4087                                         hysteresis = <1000>;
4088                                         type = "critical";
4089                                 };
4090                         };
4091
4092                         cooling-maps {
4093                                 map0 {
4094                                         trip = <&cpu7_bottom_alert0>;
4095                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4096                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4097                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4098                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4099                                 };
4100                                 map1 {
4101                                         trip = <&cpu7_bottom_alert1>;
4102                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4103                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4104                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4105                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4106                                 };
4107                         };
4108                 };
4109
4110                 aoss0-thermal {
4111                         polling-delay-passive = <250>;
4112                         polling-delay = <1000>;
4113
4114                         thermal-sensors = <&tsens0 0>;
4115
4116                         trips {
4117                                 aoss0_alert0: trip-point0 {
4118                                         temperature = <90000>;
4119                                         hysteresis = <2000>;
4120                                         type = "hot";
4121                                 };
4122                         };
4123                 };
4124
4125                 cluster0-thermal {
4126                         polling-delay-passive = <250>;
4127                         polling-delay = <1000>;
4128
4129                         thermal-sensors = <&tsens0 5>;
4130
4131                         trips {
4132                                 cluster0_alert0: trip-point0 {
4133                                         temperature = <90000>;
4134                                         hysteresis = <2000>;
4135                                         type = "hot";
4136                                 };
4137                                 cluster0_crit: cluster0_crit {
4138                                         temperature = <110000>;
4139                                         hysteresis = <2000>;
4140                                         type = "critical";
4141                                 };
4142                         };
4143                 };
4144
4145                 cluster1-thermal {
4146                         polling-delay-passive = <250>;
4147                         polling-delay = <1000>;
4148
4149                         thermal-sensors = <&tsens0 6>;
4150
4151                         trips {
4152                                 cluster1_alert0: trip-point0 {
4153                                         temperature = <90000>;
4154                                         hysteresis = <2000>;
4155                                         type = "hot";
4156                                 };
4157                                 cluster1_crit: cluster1_crit {
4158                                         temperature = <110000>;
4159                                         hysteresis = <2000>;
4160                                         type = "critical";
4161                                 };
4162                         };
4163                 };
4164
4165                 gpu-thermal-top {
4166                         polling-delay-passive = <250>;
4167                         polling-delay = <1000>;
4168
4169                         thermal-sensors = <&tsens0 15>;
4170
4171                         trips {
4172                                 gpu1_alert0: trip-point0 {
4173                                         temperature = <90000>;
4174                                         hysteresis = <2000>;
4175                                         type = "hot";
4176                                 };
4177                         };
4178                 };
4179
4180                 aoss1-thermal {
4181                         polling-delay-passive = <250>;
4182                         polling-delay = <1000>;
4183
4184                         thermal-sensors = <&tsens1 0>;
4185
4186                         trips {
4187                                 aoss1_alert0: trip-point0 {
4188                                         temperature = <90000>;
4189                                         hysteresis = <2000>;
4190                                         type = "hot";
4191                                 };
4192                         };
4193                 };
4194
4195                 wlan-thermal {
4196                         polling-delay-passive = <250>;
4197                         polling-delay = <1000>;
4198
4199                         thermal-sensors = <&tsens1 1>;
4200
4201                         trips {
4202                                 wlan_alert0: trip-point0 {
4203                                         temperature = <90000>;
4204                                         hysteresis = <2000>;
4205                                         type = "hot";
4206                                 };
4207                         };
4208                 };
4209
4210                 video-thermal {
4211                         polling-delay-passive = <250>;
4212                         polling-delay = <1000>;
4213
4214                         thermal-sensors = <&tsens1 2>;
4215
4216                         trips {
4217                                 video_alert0: trip-point0 {
4218                                         temperature = <90000>;
4219                                         hysteresis = <2000>;
4220                                         type = "hot";
4221                                 };
4222                         };
4223                 };
4224
4225                 mem-thermal {
4226                         polling-delay-passive = <250>;
4227                         polling-delay = <1000>;
4228
4229                         thermal-sensors = <&tsens1 3>;
4230
4231                         trips {
4232                                 mem_alert0: trip-point0 {
4233                                         temperature = <90000>;
4234                                         hysteresis = <2000>;
4235                                         type = "hot";
4236                                 };
4237                         };
4238                 };
4239
4240                 q6-hvx-thermal {
4241                         polling-delay-passive = <250>;
4242                         polling-delay = <1000>;
4243
4244                         thermal-sensors = <&tsens1 4>;
4245
4246                         trips {
4247                                 q6_hvx_alert0: trip-point0 {
4248                                         temperature = <90000>;
4249                                         hysteresis = <2000>;
4250                                         type = "hot";
4251                                 };
4252                         };
4253                 };
4254
4255                 camera-thermal {
4256                         polling-delay-passive = <250>;
4257                         polling-delay = <1000>;
4258
4259                         thermal-sensors = <&tsens1 5>;
4260
4261                         trips {
4262                                 camera_alert0: trip-point0 {
4263                                         temperature = <90000>;
4264                                         hysteresis = <2000>;
4265                                         type = "hot";
4266                                 };
4267                         };
4268                 };
4269
4270                 compute-thermal {
4271                         polling-delay-passive = <250>;
4272                         polling-delay = <1000>;
4273
4274                         thermal-sensors = <&tsens1 6>;
4275
4276                         trips {
4277                                 compute_alert0: trip-point0 {
4278                                         temperature = <90000>;
4279                                         hysteresis = <2000>;
4280                                         type = "hot";
4281                                 };
4282                         };
4283                 };
4284
4285                 npu-thermal {
4286                         polling-delay-passive = <250>;
4287                         polling-delay = <1000>;
4288
4289                         thermal-sensors = <&tsens1 7>;
4290
4291                         trips {
4292                                 npu_alert0: trip-point0 {
4293                                         temperature = <90000>;
4294                                         hysteresis = <2000>;
4295                                         type = "hot";
4296                                 };
4297                         };
4298                 };
4299
4300                 gpu-thermal-bottom {
4301                         polling-delay-passive = <250>;
4302                         polling-delay = <1000>;
4303
4304                         thermal-sensors = <&tsens1 8>;
4305
4306                         trips {
4307                                 gpu2_alert0: trip-point0 {
4308                                         temperature = <90000>;
4309                                         hysteresis = <2000>;
4310                                         type = "hot";
4311                                 };
4312                         };
4313                 };
4314         };
4315 };