arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  12 #include <dt-bindings/interconnect/qcom,sm8250.h>
  13 #include <dt-bindings/mailbox/qcom-ipcc.h>
  14 #include <dt-bindings/power/qcom-aoss-qmp.h>
  15 #include <dt-bindings/power/qcom-rpmpd.h>
  16 #include <dt-bindings/soc/qcom,apr.h>
  17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  18 #include <dt-bindings/sound/qcom,q6afe.h>
  19 #include <dt-bindings/thermal/thermal.h>
  20
  21 / {
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 i2c0 = &i2c0;
  29                 i2c1 = &i2c1;
  30                 i2c2 = &i2c2;
  31                 i2c3 = &i2c3;
  32                 i2c4 = &i2c4;
  33                 i2c5 = &i2c5;
  34                 i2c6 = &i2c6;
  35                 i2c7 = &i2c7;
  36                 i2c8 = &i2c8;
  37                 i2c9 = &i2c9;
  38                 i2c10 = &i2c10;
  39                 i2c11 = &i2c11;
  40                 i2c12 = &i2c12;
  41                 i2c13 = &i2c13;
  42                 i2c14 = &i2c14;
  43                 i2c15 = &i2c15;
  44                 i2c16 = &i2c16;
  45                 i2c17 = &i2c17;
  46                 i2c18 = &i2c18;
  47                 i2c19 = &i2c19;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi2 = &spi2;
  51                 spi3 = &spi3;
  52                 spi4 = &spi4;
  53                 spi5 = &spi5;
  54                 spi6 = &spi6;
  55                 spi7 = &spi7;
  56                 spi8 = &spi8;
  57                 spi9 = &spi9;
  58                 spi10 = &spi10;
  59                 spi11 = &spi11;
  60                 spi12 = &spi12;
  61                 spi13 = &spi13;
  62                 spi14 = &spi14;
  63                 spi15 = &spi15;
  64                 spi16 = &spi16;
  65                 spi17 = &spi17;
  66                 spi18 = &spi18;
  67                 spi19 = &spi19;
  68         };
  69
  70         chosen { };
  71
  72         clocks {
  73                 xo_board: xo-board {
  74                         compatible = "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <38400000>;
  77                         clock-output-names = "xo_board";
  78                 };
  79
  80                 sleep_clk: sleep-clk {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                         #clock-cells = <0>;
  84                 };
  85         };
  86
  87         cpus {
  88                 #address-cells = <2>;
  89                 #size-cells = <0>;
  90
  91                 CPU0: cpu@0 {
  92                         device_type = "cpu";
  93                         compatible = "qcom,kryo485";
  94                         reg = <0x0 0x0>;
  95                         enable-method = "psci";
  96                         next-level-cache = <&L2_0>;
  97                         qcom,freq-domain = <&cpufreq_hw 0>;
  98                         #cooling-cells = <2>;
  99                         L2_0: l2-cache {
 100                                 compatible = "cache";
 101                                 next-level-cache = <&L3_0>;
 102                                 L3_0: l3-cache {
 103                                         compatible = "cache";
 104                                 };
 105                         };
 106                 };
 107
 108                 CPU1: cpu@100 {
 109                         device_type = "cpu";
 110                         compatible = "qcom,kryo485";
 111                         reg = <0x0 0x100>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&L2_100>;
 114                         qcom,freq-domain = <&cpufreq_hw 0>;
 115                         #cooling-cells = <2>;
 116                         L2_100: l2-cache {
 117                                 compatible = "cache";
 118                                 next-level-cache = <&L3_0>;
 119                         };
 120                 };
 121
 122                 CPU2: cpu@200 {
 123                         device_type = "cpu";
 124                         compatible = "qcom,kryo485";
 125                         reg = <0x0 0x200>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&L2_200>;
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         #cooling-cells = <2>;
 130                         L2_200: l2-cache {
 131                                 compatible = "cache";
 132                                 next-level-cache = <&L3_0>;
 133                         };
 134                 };
 135
 136                 CPU3: cpu@300 {
 137                         device_type = "cpu";
 138                         compatible = "qcom,kryo485";
 139                         reg = <0x0 0x300>;
 140                         enable-method = "psci";
 141                         next-level-cache = <&L2_300>;
 142                         qcom,freq-domain = <&cpufreq_hw 0>;
 143                         #cooling-cells = <2>;
 144                         L2_300: l2-cache {
 145                                 compatible = "cache";
 146                                 next-level-cache = <&L3_0>;
 147                         };
 148                 };
 149
 150                 CPU4: cpu@400 {
 151                         device_type = "cpu";
 152                         compatible = "qcom,kryo485";
 153                         reg = <0x0 0x400>;
 154                         enable-method = "psci";
 155                         next-level-cache = <&L2_400>;
 156                         qcom,freq-domain = <&cpufreq_hw 1>;
 157                         #cooling-cells = <2>;
 158                         L2_400: l2-cache {
 159                                 compatible = "cache";
 160                                 next-level-cache = <&L3_0>;
 161                         };
 162                 };
 163
 164                 CPU5: cpu@500 {
 165                         device_type = "cpu";
 166                         compatible = "qcom,kryo485";
 167                         reg = <0x0 0x500>;
 168                         enable-method = "psci";
 169                         next-level-cache = <&L2_500>;
 170                         qcom,freq-domain = <&cpufreq_hw 1>;
 171                         #cooling-cells = <2>;
 172                         L2_500: l2-cache {
 173                                 compatible = "cache";
 174                                 next-level-cache = <&L3_0>;
 175                         };
 176
 177                 };
 178
 179                 CPU6: cpu@600 {
 180                         device_type = "cpu";
 181                         compatible = "qcom,kryo485";
 182                         reg = <0x0 0x600>;
 183                         enable-method = "psci";
 184                         next-level-cache = <&L2_600>;
 185                         qcom,freq-domain = <&cpufreq_hw 1>;
 186                         #cooling-cells = <2>;
 187                         L2_600: l2-cache {
 188                                 compatible = "cache";
 189                                 next-level-cache = <&L3_0>;
 190                         };
 191                 };
 192
 193                 CPU7: cpu@700 {
 194                         device_type = "cpu";
 195                         compatible = "qcom,kryo485";
 196                         reg = <0x0 0x700>;
 197                         enable-method = "psci";
 198                         next-level-cache = <&L2_700>;
 199                         qcom,freq-domain = <&cpufreq_hw 2>;
 200                         #cooling-cells = <2>;
 201                         L2_700: l2-cache {
 202                                 compatible = "cache";
 203                                 next-level-cache = <&L3_0>;
 204                         };
 205                 };
 206         };
 207
 208         firmware {
 209                 scm: scm {
 210                         compatible = "qcom,scm";
 211                         #reset-cells = <1>;
 212                 };
 213         };
 214
 215         memory@80000000 {
 216                 device_type = "memory";
 217                 /* We expect the bootloader to fill in the size */
 218                 reg = <0x0 0x80000000 0x0 0x0>;
 219         };
 220
 221         mmcx_reg: mmcx-reg {
 222                 compatible = "regulator-fixed-domain";
 223                 power-domains = <&rpmhpd SM8250_MMCX>;
 224                 required-opps = <&rpmhpd_opp_low_svs>;
 225                 regulator-name = "MMCX";
 226         };
 227
 228         pmu {
 229                 compatible = "arm,armv8-pmuv3";
 230                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 231         };
 232
 233         psci {
 234                 compatible = "arm,psci-1.0";
 235                 method = "smc";
 236         };
 237
 238         reserved-memory {
 239                 #address-cells = <2>;
 240                 #size-cells = <2>;
 241                 ranges;
 242
 243                 hyp_mem: memory@80000000 {
 244                         reg = <0x0 0x80000000 0x0 0x600000>;
 245                         no-map;
 246                 };
 247
 248                 xbl_aop_mem: memory@80700000 {
 249                         reg = <0x0 0x80700000 0x0 0x160000>;
 250                         no-map;
 251                 };
 252
 253                 cmd_db: memory@80860000 {
 254                         compatible = "qcom,cmd-db";
 255                         reg = <0x0 0x80860000 0x0 0x20000>;
 256                         no-map;
 257                 };
 258
 259                 smem_mem: memory@80900000 {
 260                         reg = <0x0 0x80900000 0x0 0x200000>;
 261                         no-map;
 262                 };
 263
 264                 removed_mem: memory@80b00000 {
 265                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 266                         no-map;
 267                 };
 268
 269                 camera_mem: memory@86200000 {
 270                         reg = <0x0 0x86200000 0x0 0x500000>;
 271                         no-map;
 272                 };
 273
 274                 wlan_mem: memory@86700000 {
 275                         reg = <0x0 0x86700000 0x0 0x100000>;
 276                         no-map;
 277                 };
 278
 279                 ipa_fw_mem: memory@86800000 {
 280                         reg = <0x0 0x86800000 0x0 0x10000>;
 281                         no-map;
 282                 };
 283
 284                 ipa_gsi_mem: memory@86810000 {
 285                         reg = <0x0 0x86810000 0x0 0xa000>;
 286                         no-map;
 287                 };
 288
 289                 gpu_mem: memory@8681a000 {
 290                         reg = <0x0 0x8681a000 0x0 0x2000>;
 291                         no-map;
 292                 };
 293
 294                 npu_mem: memory@86900000 {
 295                         reg = <0x0 0x86900000 0x0 0x500000>;
 296                         no-map;
 297                 };
 298
 299                 video_mem: memory@86e00000 {
 300                         reg = <0x0 0x86e00000 0x0 0x500000>;
 301                         no-map;
 302                 };
 303
 304                 cvp_mem: memory@87300000 {
 305                         reg = <0x0 0x87300000 0x0 0x500000>;
 306                         no-map;
 307                 };
 308
 309                 cdsp_mem: memory@87800000 {
 310                         reg = <0x0 0x87800000 0x0 0x1400000>;
 311                         no-map;
 312                 };
 313
 314                 slpi_mem: memory@88c00000 {
 315                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 316                         no-map;
 317                 };
 318
 319                 adsp_mem: memory@8a100000 {
 320                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 321                         no-map;
 322                 };
 323
 324                 spss_mem: memory@8be00000 {
 325                         reg = <0x0 0x8be00000 0x0 0x100000>;
 326                         no-map;
 327                 };
 328
 329                 cdsp_secure_heap: memory@8bf00000 {
 330                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 331                         no-map;
 332                 };
 333         };
 334
 335         smem: qcom,smem {
 336                 compatible = "qcom,smem";
 337                 memory-region = <&smem_mem>;
 338                 hwlocks = <&tcsr_mutex 3>;
 339         };
 340
 341         smp2p-adsp {
 342                 compatible = "qcom,smp2p";
 343                 qcom,smem = <443>, <429>;
 344                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 345                                              IPCC_MPROC_SIGNAL_SMP2P
 346                                              IRQ_TYPE_EDGE_RISING>;
 347                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 348                                 IPCC_MPROC_SIGNAL_SMP2P>;
 349
 350                 qcom,local-pid = <0>;
 351                 qcom,remote-pid = <2>;
 352
 353                 smp2p_adsp_out: master-kernel {
 354                         qcom,entry-name = "master-kernel";
 355                         #qcom,smem-state-cells = <1>;
 356                 };
 357
 358                 smp2p_adsp_in: slave-kernel {
 359                         qcom,entry-name = "slave-kernel";
 360                         interrupt-controller;
 361                         #interrupt-cells = <2>;
 362                 };
 363         };
 364
 365         smp2p-cdsp {
 366                 compatible = "qcom,smp2p";
 367                 qcom,smem = <94>, <432>;
 368                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 369                                              IPCC_MPROC_SIGNAL_SMP2P
 370                                              IRQ_TYPE_EDGE_RISING>;
 371                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 372                                 IPCC_MPROC_SIGNAL_SMP2P>;
 373
 374                 qcom,local-pid = <0>;
 375                 qcom,remote-pid = <5>;
 376
 377                 smp2p_cdsp_out: master-kernel {
 378                         qcom,entry-name = "master-kernel";
 379                         #qcom,smem-state-cells = <1>;
 380                 };
 381
 382                 smp2p_cdsp_in: slave-kernel {
 383                         qcom,entry-name = "slave-kernel";
 384                         interrupt-controller;
 385                         #interrupt-cells = <2>;
 386                 };
 387         };
 388
 389         smp2p-slpi {
 390                 compatible = "qcom,smp2p";
 391                 qcom,smem = <481>, <430>;
 392                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 393                                              IPCC_MPROC_SIGNAL_SMP2P
 394                                              IRQ_TYPE_EDGE_RISING>;
 395                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 396                                 IPCC_MPROC_SIGNAL_SMP2P>;
 397
 398                 qcom,local-pid = <0>;
 399                 qcom,remote-pid = <3>;
 400
 401                 smp2p_slpi_out: master-kernel {
 402                         qcom,entry-name = "master-kernel";
 403                         #qcom,smem-state-cells = <1>;
 404                 };
 405
 406                 smp2p_slpi_in: slave-kernel {
 407                         qcom,entry-name = "slave-kernel";
 408                         interrupt-controller;
 409                         #interrupt-cells = <2>;
 410                 };
 411         };
 412
 413         soc: soc@0 {
 414                 #address-cells = <2>;
 415                 #size-cells = <2>;
 416                 ranges = <0 0 0 0 0x10 0>;
 417                 dma-ranges = <0 0 0 0 0x10 0>;
 418                 compatible = "simple-bus";
 419
 420                 gcc: clock-controller@100000 {
 421                         compatible = "qcom,gcc-sm8250";
 422                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 423                         #clock-cells = <1>;
 424                         #reset-cells = <1>;
 425                         #power-domain-cells = <1>;
 426                         clock-names = "bi_tcxo",
 427                                       "bi_tcxo_ao",
 428                                       "sleep_clk";
 429                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 430                                  <&rpmhcc RPMH_CXO_CLK_A>,
 431                                  <&sleep_clk>;
 432                 };
 433
 434                 ipcc: mailbox@408000 {
 435                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 436                         reg = <0 0x00408000 0 0x1000>;
 437                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 438                         interrupt-controller;
 439                         #interrupt-cells = <3>;
 440                         #mbox-cells = <2>;
 441                 };
 442
 443                 rng: rng@793000 {
 444                         compatible = "qcom,prng-ee";
 445                         reg = <0 0x00793000 0 0x1000>;
 446                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 447                         clock-names = "core";
 448                 };
 449
 450                 qup_opp_table: qup-opp-table {
 451                         compatible = "operating-points-v2";
 452
 453                         opp-50000000 {
 454                                 opp-hz = /bits/ 64 <50000000>;
 455                                 required-opps = <&rpmhpd_opp_min_svs>;
 456                         };
 457
 458                         opp-75000000 {
 459                                 opp-hz = /bits/ 64 <75000000>;
 460                                 required-opps = <&rpmhpd_opp_low_svs>;
 461                         };
 462
 463                         opp-120000000 {
 464                                 opp-hz = /bits/ 64 <120000000>;
 465                                 required-opps = <&rpmhpd_opp_svs>;
 466                         };
 467                 };
 468
 469                 qupv3_id_2: geniqup@8c0000 {
 470                         compatible = "qcom,geni-se-qup";
 471                         reg = <0x0 0x008c0000 0x0 0x6000>;
 472                         clock-names = "m-ahb", "s-ahb";
 473                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 474                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 475                         #address-cells = <2>;
 476                         #size-cells = <2>;
 477                         iommus = <&apps_smmu 0x63 0x0>;
 478                         ranges;
 479                         status = "disabled";
 480
 481                         i2c14: i2c@880000 {
 482                                 compatible = "qcom,geni-i2c";
 483                                 reg = <0 0x00880000 0 0x4000>;
 484                                 clock-names = "se";
 485                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 486                                 pinctrl-names = "default";
 487                                 pinctrl-0 = <&qup_i2c14_default>;
 488                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 489                                 #address-cells = <1>;
 490                                 #size-cells = <0>;
 491                                 status = "disabled";
 492                         };
 493
 494                         spi14: spi@880000 {
 495                                 compatible = "qcom,geni-spi";
 496                                 reg = <0 0x00880000 0 0x4000>;
 497                                 clock-names = "se";
 498                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 499                                 pinctrl-names = "default";
 500                                 pinctrl-0 = <&qup_spi14_default>;
 501                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 502                                 #address-cells = <1>;
 503                                 #size-cells = <0>;
 504                                 power-domains = <&rpmhpd SM8250_CX>;
 505                                 operating-points-v2 = <&qup_opp_table>;
 506                                 status = "disabled";
 507                         };
 508
 509                         i2c15: i2c@884000 {
 510                                 compatible = "qcom,geni-i2c";
 511                                 reg = <0 0x00884000 0 0x4000>;
 512                                 clock-names = "se";
 513                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 514                                 pinctrl-names = "default";
 515                                 pinctrl-0 = <&qup_i2c15_default>;
 516                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 517                                 #address-cells = <1>;
 518                                 #size-cells = <0>;
 519                                 status = "disabled";
 520                         };
 521
 522                         spi15: spi@884000 {
 523                                 compatible = "qcom,geni-spi";
 524                                 reg = <0 0x00884000 0 0x4000>;
 525                                 clock-names = "se";
 526                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 527                                 pinctrl-names = "default";
 528                                 pinctrl-0 = <&qup_spi15_default>;
 529                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 530                                 #address-cells = <1>;
 531                                 #size-cells = <0>;
 532                                 power-domains = <&rpmhpd SM8250_CX>;
 533                                 operating-points-v2 = <&qup_opp_table>;
 534                                 status = "disabled";
 535                         };
 536
 537                         i2c16: i2c@888000 {
 538                                 compatible = "qcom,geni-i2c";
 539                                 reg = <0 0x00888000 0 0x4000>;
 540                                 clock-names = "se";
 541                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 542                                 pinctrl-names = "default";
 543                                 pinctrl-0 = <&qup_i2c16_default>;
 544                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 545                                 #address-cells = <1>;
 546                                 #size-cells = <0>;
 547                                 status = "disabled";
 548                         };
 549
 550                         spi16: spi@888000 {
 551                                 compatible = "qcom,geni-spi";
 552                                 reg = <0 0x00888000 0 0x4000>;
 553                                 clock-names = "se";
 554                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 555                                 pinctrl-names = "default";
 556                                 pinctrl-0 = <&qup_spi16_default>;
 557                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 power-domains = <&rpmhpd SM8250_CX>;
 561                                 operating-points-v2 = <&qup_opp_table>;
 562                                 status = "disabled";
 563                         };
 564
 565                         i2c17: i2c@88c000 {
 566                                 compatible = "qcom,geni-i2c";
 567                                 reg = <0 0x0088c000 0 0x4000>;
 568                                 clock-names = "se";
 569                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 570                                 pinctrl-names = "default";
 571                                 pinctrl-0 = <&qup_i2c17_default>;
 572                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 573                                 #address-cells = <1>;
 574                                 #size-cells = <0>;
 575                                 status = "disabled";
 576                         };
 577
 578                         spi17: spi@88c000 {
 579                                 compatible = "qcom,geni-spi";
 580                                 reg = <0 0x0088c000 0 0x4000>;
 581                                 clock-names = "se";
 582                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 583                                 pinctrl-names = "default";
 584                                 pinctrl-0 = <&qup_spi17_default>;
 585                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 586                                 #address-cells = <1>;
 587                                 #size-cells = <0>;
 588                                 power-domains = <&rpmhpd SM8250_CX>;
 589                                 operating-points-v2 = <&qup_opp_table>;
 590                                 status = "disabled";
 591                         };
 592
 593                         uart17: serial@88c000 {
 594                                 compatible = "qcom,geni-uart";
 595                                 reg = <0 0x0088c000 0 0x4000>;
 596                                 clock-names = "se";
 597                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 598                                 pinctrl-names = "default";
 599                                 pinctrl-0 = <&qup_uart17_default>;
 600                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 601                                 power-domains = <&rpmhpd SM8250_CX>;
 602                                 operating-points-v2 = <&qup_opp_table>;
 603                                 status = "disabled";
 604                         };
 605
 606                         i2c18: i2c@890000 {
 607                                 compatible = "qcom,geni-i2c";
 608                                 reg = <0 0x00890000 0 0x4000>;
 609                                 clock-names = "se";
 610                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 611                                 pinctrl-names = "default";
 612                                 pinctrl-0 = <&qup_i2c18_default>;
 613                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 614                                 #address-cells = <1>;
 615                                 #size-cells = <0>;
 616                                 status = "disabled";
 617                         };
 618
 619                         spi18: spi@890000 {
 620                                 compatible = "qcom,geni-spi";
 621                                 reg = <0 0x00890000 0 0x4000>;
 622                                 clock-names = "se";
 623                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 624                                 pinctrl-names = "default";
 625                                 pinctrl-0 = <&qup_spi18_default>;
 626                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 627                                 #address-cells = <1>;
 628                                 #size-cells = <0>;
 629                                 power-domains = <&rpmhpd SM8250_CX>;
 630                                 operating-points-v2 = <&qup_opp_table>;
 631                                 status = "disabled";
 632                         };
 633
 634                         uart18: serial@890000 {
 635                                 compatible = "qcom,geni-uart";
 636                                 reg = <0 0x00890000 0 0x4000>;
 637                                 clock-names = "se";
 638                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 639                                 pinctrl-names = "default";
 640                                 pinctrl-0 = <&qup_uart18_default>;
 641                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 642                                 power-domains = <&rpmhpd SM8250_CX>;
 643                                 operating-points-v2 = <&qup_opp_table>;
 644                                 status = "disabled";
 645                         };
 646
 647                         i2c19: i2c@894000 {
 648                                 compatible = "qcom,geni-i2c";
 649                                 reg = <0 0x00894000 0 0x4000>;
 650                                 clock-names = "se";
 651                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 652                                 pinctrl-names = "default";
 653                                 pinctrl-0 = <&qup_i2c19_default>;
 654                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 655                                 #address-cells = <1>;
 656                                 #size-cells = <0>;
 657                                 status = "disabled";
 658                         };
 659
 660                         spi19: spi@894000 {
 661                                 compatible = "qcom,geni-spi";
 662                                 reg = <0 0x00894000 0 0x4000>;
 663                                 clock-names = "se";
 664                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 665                                 pinctrl-names = "default";
 666                                 pinctrl-0 = <&qup_spi19_default>;
 667                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 668                                 #address-cells = <1>;
 669                                 #size-cells = <0>;
 670                                 power-domains = <&rpmhpd SM8250_CX>;
 671                                 operating-points-v2 = <&qup_opp_table>;
 672                                 status = "disabled";
 673                         };
 674                 };
 675
 676                 qupv3_id_0: geniqup@9c0000 {
 677                         compatible = "qcom,geni-se-qup";
 678                         reg = <0x0 0x009c0000 0x0 0x6000>;
 679                         clock-names = "m-ahb", "s-ahb";
 680                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 681                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 682                         #address-cells = <2>;
 683                         #size-cells = <2>;
 684                         iommus = <&apps_smmu 0x5a3 0x0>;
 685                         ranges;
 686                         status = "disabled";
 687
 688                         i2c0: i2c@980000 {
 689                                 compatible = "qcom,geni-i2c";
 690                                 reg = <0 0x00980000 0 0x4000>;
 691                                 clock-names = "se";
 692                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 693                                 pinctrl-names = "default";
 694                                 pinctrl-0 = <&qup_i2c0_default>;
 695                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 696                                 #address-cells = <1>;
 697                                 #size-cells = <0>;
 698                                 status = "disabled";
 699                         };
 700
 701                         spi0: spi@980000 {
 702                                 compatible = "qcom,geni-spi";
 703                                 reg = <0 0x00980000 0 0x4000>;
 704                                 clock-names = "se";
 705                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 706                                 pinctrl-names = "default";
 707                                 pinctrl-0 = <&qup_spi0_default>;
 708                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 709                                 #address-cells = <1>;
 710                                 #size-cells = <0>;
 711                                 power-domains = <&rpmhpd SM8250_CX>;
 712                                 operating-points-v2 = <&qup_opp_table>;
 713                                 status = "disabled";
 714                         };
 715
 716                         i2c1: i2c@984000 {
 717                                 compatible = "qcom,geni-i2c";
 718                                 reg = <0 0x00984000 0 0x4000>;
 719                                 clock-names = "se";
 720                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 721                                 pinctrl-names = "default";
 722                                 pinctrl-0 = <&qup_i2c1_default>;
 723                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 status = "disabled";
 727                         };
 728
 729                         spi1: spi@984000 {
 730                                 compatible = "qcom,geni-spi";
 731                                 reg = <0 0x00984000 0 0x4000>;
 732                                 clock-names = "se";
 733                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 734                                 pinctrl-names = "default";
 735                                 pinctrl-0 = <&qup_spi1_default>;
 736                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 737                                 #address-cells = <1>;
 738                                 #size-cells = <0>;
 739                                 power-domains = <&rpmhpd SM8250_CX>;
 740                                 operating-points-v2 = <&qup_opp_table>;
 741                                 status = "disabled";
 742                         };
 743
 744                         i2c2: i2c@988000 {
 745                                 compatible = "qcom,geni-i2c";
 746                                 reg = <0 0x00988000 0 0x4000>;
 747                                 clock-names = "se";
 748                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 749                                 pinctrl-names = "default";
 750                                 pinctrl-0 = <&qup_i2c2_default>;
 751                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 752                                 #address-cells = <1>;
 753                                 #size-cells = <0>;
 754                                 status = "disabled";
 755                         };
 756
 757                         spi2: spi@988000 {
 758                                 compatible = "qcom,geni-spi";
 759                                 reg = <0 0x00988000 0 0x4000>;
 760                                 clock-names = "se";
 761                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 762                                 pinctrl-names = "default";
 763                                 pinctrl-0 = <&qup_spi2_default>;
 764                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 765                                 #address-cells = <1>;
 766                                 #size-cells = <0>;
 767                                 power-domains = <&rpmhpd SM8250_CX>;
 768                                 operating-points-v2 = <&qup_opp_table>;
 769                                 status = "disabled";
 770                         };
 771
 772                         uart2: serial@988000 {
 773                                 compatible = "qcom,geni-debug-uart";
 774                                 reg = <0 0x00988000 0 0x4000>;
 775                                 clock-names = "se";
 776                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 777                                 pinctrl-names = "default";
 778                                 pinctrl-0 = <&qup_uart2_default>;
 779                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 780                                 power-domains = <&rpmhpd SM8250_CX>;
 781                                 operating-points-v2 = <&qup_opp_table>;
 782                                 status = "disabled";
 783                         };
 784
 785                         i2c3: i2c@98c000 {
 786                                 compatible = "qcom,geni-i2c";
 787                                 reg = <0 0x0098c000 0 0x4000>;
 788                                 clock-names = "se";
 789                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 790                                 pinctrl-names = "default";
 791                                 pinctrl-0 = <&qup_i2c3_default>;
 792                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795                                 status = "disabled";
 796                         };
 797
 798                         spi3: spi@98c000 {
 799                                 compatible = "qcom,geni-spi";
 800                                 reg = <0 0x0098c000 0 0x4000>;
 801                                 clock-names = "se";
 802                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 803                                 pinctrl-names = "default";
 804                                 pinctrl-0 = <&qup_spi3_default>;
 805                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 806                                 #address-cells = <1>;
 807                                 #size-cells = <0>;
 808                                 power-domains = <&rpmhpd SM8250_CX>;
 809                                 operating-points-v2 = <&qup_opp_table>;
 810                                 status = "disabled";
 811                         };
 812
 813                         i2c4: i2c@990000 {
 814                                 compatible = "qcom,geni-i2c";
 815                                 reg = <0 0x00990000 0 0x4000>;
 816                                 clock-names = "se";
 817                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 818                                 pinctrl-names = "default";
 819                                 pinctrl-0 = <&qup_i2c4_default>;
 820                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 821                                 #address-cells = <1>;
 822                                 #size-cells = <0>;
 823                                 status = "disabled";
 824                         };
 825
 826                         spi4: spi@990000 {
 827                                 compatible = "qcom,geni-spi";
 828                                 reg = <0 0x00990000 0 0x4000>;
 829                                 clock-names = "se";
 830                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 831                                 pinctrl-names = "default";
 832                                 pinctrl-0 = <&qup_spi4_default>;
 833                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836                                 power-domains = <&rpmhpd SM8250_CX>;
 837                                 operating-points-v2 = <&qup_opp_table>;
 838                                 status = "disabled";
 839                         };
 840
 841                         i2c5: i2c@994000 {
 842                                 compatible = "qcom,geni-i2c";
 843                                 reg = <0 0x00994000 0 0x4000>;
 844                                 clock-names = "se";
 845                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 846                                 pinctrl-names = "default";
 847                                 pinctrl-0 = <&qup_i2c5_default>;
 848                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 849                                 #address-cells = <1>;
 850                                 #size-cells = <0>;
 851                                 status = "disabled";
 852                         };
 853
 854                         spi5: spi@994000 {
 855                                 compatible = "qcom,geni-spi";
 856                                 reg = <0 0x00994000 0 0x4000>;
 857                                 clock-names = "se";
 858                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 859                                 pinctrl-names = "default";
 860                                 pinctrl-0 = <&qup_spi5_default>;
 861                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 862                                 #address-cells = <1>;
 863                                 #size-cells = <0>;
 864                                 power-domains = <&rpmhpd SM8250_CX>;
 865                                 operating-points-v2 = <&qup_opp_table>;
 866                                 status = "disabled";
 867                         };
 868
 869                         i2c6: i2c@998000 {
 870                                 compatible = "qcom,geni-i2c";
 871                                 reg = <0 0x00998000 0 0x4000>;
 872                                 clock-names = "se";
 873                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 874                                 pinctrl-names = "default";
 875                                 pinctrl-0 = <&qup_i2c6_default>;
 876                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 877                                 #address-cells = <1>;
 878                                 #size-cells = <0>;
 879                                 status = "disabled";
 880                         };
 881
 882                         spi6: spi@998000 {
 883                                 compatible = "qcom,geni-spi";
 884                                 reg = <0 0x00998000 0 0x4000>;
 885                                 clock-names = "se";
 886                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 887                                 pinctrl-names = "default";
 888                                 pinctrl-0 = <&qup_spi6_default>;
 889                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 890                                 #address-cells = <1>;
 891                                 #size-cells = <0>;
 892                                 power-domains = <&rpmhpd SM8250_CX>;
 893                                 operating-points-v2 = <&qup_opp_table>;
 894                                 status = "disabled";
 895                         };
 896
 897                         uart6: serial@998000 {
 898                                 compatible = "qcom,geni-uart";
 899                                 reg = <0 0x00998000 0 0x4000>;
 900                                 clock-names = "se";
 901                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 902                                 pinctrl-names = "default";
 903                                 pinctrl-0 = <&qup_uart6_default>;
 904                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 905                                 power-domains = <&rpmhpd SM8250_CX>;
 906                                 operating-points-v2 = <&qup_opp_table>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c7: i2c@99c000 {
 911                                 compatible = "qcom,geni-i2c";
 912                                 reg = <0 0x0099c000 0 0x4000>;
 913                                 clock-names = "se";
 914                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 915                                 pinctrl-names = "default";
 916                                 pinctrl-0 = <&qup_i2c7_default>;
 917                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 918                                 #address-cells = <1>;
 919                                 #size-cells = <0>;
 920                                 status = "disabled";
 921                         };
 922
 923                         spi7: spi@99c000 {
 924                                 compatible = "qcom,geni-spi";
 925                                 reg = <0 0x0099c000 0 0x4000>;
 926                                 clock-names = "se";
 927                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 928                                 pinctrl-names = "default";
 929                                 pinctrl-0 = <&qup_spi7_default>;
 930                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 931                                 #address-cells = <1>;
 932                                 #size-cells = <0>;
 933                                 power-domains = <&rpmhpd SM8250_CX>;
 934                                 operating-points-v2 = <&qup_opp_table>;
 935                                 status = "disabled";
 936                         };
 937                 };
 938
 939                 qupv3_id_1: geniqup@ac0000 {
 940                         compatible = "qcom,geni-se-qup";
 941                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 942                         clock-names = "m-ahb", "s-ahb";
 943                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 944                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 945                         #address-cells = <2>;
 946                         #size-cells = <2>;
 947                         iommus = <&apps_smmu 0x43 0x0>;
 948                         ranges;
 949                         status = "disabled";
 950
 951                         i2c8: i2c@a80000 {
 952                                 compatible = "qcom,geni-i2c";
 953                                 reg = <0 0x00a80000 0 0x4000>;
 954                                 clock-names = "se";
 955                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 956                                 pinctrl-names = "default";
 957                                 pinctrl-0 = <&qup_i2c8_default>;
 958                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 959                                 #address-cells = <1>;
 960                                 #size-cells = <0>;
 961                                 status = "disabled";
 962                         };
 963
 964                         spi8: spi@a80000 {
 965                                 compatible = "qcom,geni-spi";
 966                                 reg = <0 0x00a80000 0 0x4000>;
 967                                 clock-names = "se";
 968                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 969                                 pinctrl-names = "default";
 970                                 pinctrl-0 = <&qup_spi8_default>;
 971                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                                 power-domains = <&rpmhpd SM8250_CX>;
 975                                 operating-points-v2 = <&qup_opp_table>;
 976                                 status = "disabled";
 977                         };
 978
 979                         i2c9: i2c@a84000 {
 980                                 compatible = "qcom,geni-i2c";
 981                                 reg = <0 0x00a84000 0 0x4000>;
 982                                 clock-names = "se";
 983                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 984                                 pinctrl-names = "default";
 985                                 pinctrl-0 = <&qup_i2c9_default>;
 986                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989                                 status = "disabled";
 990                         };
 991
 992                         spi9: spi@a84000 {
 993                                 compatible = "qcom,geni-spi";
 994                                 reg = <0 0x00a84000 0 0x4000>;
 995                                 clock-names = "se";
 996                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 997                                 pinctrl-names = "default";
 998                                 pinctrl-0 = <&qup_spi9_default>;
 999                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002                                 power-domains = <&rpmhpd SM8250_CX>;
1003                                 operating-points-v2 = <&qup_opp_table>;
1004                                 status = "disabled";
1005                         };
1006
1007                         i2c10: i2c@a88000 {
1008                                 compatible = "qcom,geni-i2c";
1009                                 reg = <0 0x00a88000 0 0x4000>;
1010                                 clock-names = "se";
1011                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1012                                 pinctrl-names = "default";
1013                                 pinctrl-0 = <&qup_i2c10_default>;
1014                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017                                 status = "disabled";
1018                         };
1019
1020                         spi10: spi@a88000 {
1021                                 compatible = "qcom,geni-spi";
1022                                 reg = <0 0x00a88000 0 0x4000>;
1023                                 clock-names = "se";
1024                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1025                                 pinctrl-names = "default";
1026                                 pinctrl-0 = <&qup_spi10_default>;
1027                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1028                                 #address-cells = <1>;
1029                                 #size-cells = <0>;
1030                                 power-domains = <&rpmhpd SM8250_CX>;
1031                                 operating-points-v2 = <&qup_opp_table>;
1032                                 status = "disabled";
1033                         };
1034
1035                         i2c11: i2c@a8c000 {
1036                                 compatible = "qcom,geni-i2c";
1037                                 reg = <0 0x00a8c000 0 0x4000>;
1038                                 clock-names = "se";
1039                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_i2c11_default>;
1042                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 status = "disabled";
1046                         };
1047
1048                         spi11: spi@a8c000 {
1049                                 compatible = "qcom,geni-spi";
1050                                 reg = <0 0x00a8c000 0 0x4000>;
1051                                 clock-names = "se";
1052                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1053                                 pinctrl-names = "default";
1054                                 pinctrl-0 = <&qup_spi11_default>;
1055                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1056                                 #address-cells = <1>;
1057                                 #size-cells = <0>;
1058                                 power-domains = <&rpmhpd SM8250_CX>;
1059                                 operating-points-v2 = <&qup_opp_table>;
1060                                 status = "disabled";
1061                         };
1062
1063                         i2c12: i2c@a90000 {
1064                                 compatible = "qcom,geni-i2c";
1065                                 reg = <0 0x00a90000 0 0x4000>;
1066                                 clock-names = "se";
1067                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1068                                 pinctrl-names = "default";
1069                                 pinctrl-0 = <&qup_i2c12_default>;
1070                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1071                                 #address-cells = <1>;
1072                                 #size-cells = <0>;
1073                                 status = "disabled";
1074                         };
1075
1076                         spi12: spi@a90000 {
1077                                 compatible = "qcom,geni-spi";
1078                                 reg = <0 0x00a90000 0 0x4000>;
1079                                 clock-names = "se";
1080                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1081                                 pinctrl-names = "default";
1082                                 pinctrl-0 = <&qup_spi12_default>;
1083                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1084                                 #address-cells = <1>;
1085                                 #size-cells = <0>;
1086                                 power-domains = <&rpmhpd SM8250_CX>;
1087                                 operating-points-v2 = <&qup_opp_table>;
1088                                 status = "disabled";
1089                         };
1090
1091                         uart12: serial@a90000 {
1092                                 compatible = "qcom,geni-debug-uart";
1093                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1094                                 clock-names = "se";
1095                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1096                                 pinctrl-names = "default";
1097                                 pinctrl-0 = <&qup_uart12_default>;
1098                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1099                                 power-domains = <&rpmhpd SM8250_CX>;
1100                                 operating-points-v2 = <&qup_opp_table>;
1101                                 status = "disabled";
1102                         };
1103
1104                         i2c13: i2c@a94000 {
1105                                 compatible = "qcom,geni-i2c";
1106                                 reg = <0 0x00a94000 0 0x4000>;
1107                                 clock-names = "se";
1108                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1109                                 pinctrl-names = "default";
1110                                 pinctrl-0 = <&qup_i2c13_default>;
1111                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1112                                 #address-cells = <1>;
1113                                 #size-cells = <0>;
1114                                 status = "disabled";
1115                         };
1116
1117                         spi13: spi@a94000 {
1118                                 compatible = "qcom,geni-spi";
1119                                 reg = <0 0x00a94000 0 0x4000>;
1120                                 clock-names = "se";
1121                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1122                                 pinctrl-names = "default";
1123                                 pinctrl-0 = <&qup_spi13_default>;
1124                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1125                                 #address-cells = <1>;
1126                                 #size-cells = <0>;
1127                                 power-domains = <&rpmhpd SM8250_CX>;
1128                                 operating-points-v2 = <&qup_opp_table>;
1129                                 status = "disabled";
1130                         };
1131                 };
1132
1133                 config_noc: interconnect@1500000 {
1134                         compatible = "qcom,sm8250-config-noc";
1135                         reg = <0 0x01500000 0 0xa580>;
1136                         #interconnect-cells = <1>;
1137                         qcom,bcm-voters = <&apps_bcm_voter>;
1138                 };
1139
1140                 system_noc: interconnect@1620000 {
1141                         compatible = "qcom,sm8250-system-noc";
1142                         reg = <0 0x01620000 0 0x1c200>;
1143                         #interconnect-cells = <1>;
1144                         qcom,bcm-voters = <&apps_bcm_voter>;
1145                 };
1146
1147                 mc_virt: interconnect@163d000 {
1148                         compatible = "qcom,sm8250-mc-virt";
1149                         reg = <0 0x0163d000 0 0x1000>;
1150                         #interconnect-cells = <1>;
1151                         qcom,bcm-voters = <&apps_bcm_voter>;
1152                 };
1153
1154                 aggre1_noc: interconnect@16e0000 {
1155                         compatible = "qcom,sm8250-aggre1-noc";
1156                         reg = <0 0x016e0000 0 0x1f180>;
1157                         #interconnect-cells = <1>;
1158                         qcom,bcm-voters = <&apps_bcm_voter>;
1159                 };
1160
1161                 aggre2_noc: interconnect@1700000 {
1162                         compatible = "qcom,sm8250-aggre2-noc";
1163                         reg = <0 0x01700000 0 0x33000>;
1164                         #interconnect-cells = <1>;
1165                         qcom,bcm-voters = <&apps_bcm_voter>;
1166                 };
1167
1168                 compute_noc: interconnect@1733000 {
1169                         compatible = "qcom,sm8250-compute-noc";
1170                         reg = <0 0x01733000 0 0xa180>;
1171                         #interconnect-cells = <1>;
1172                         qcom,bcm-voters = <&apps_bcm_voter>;
1173                 };
1174
1175                 mmss_noc: interconnect@1740000 {
1176                         compatible = "qcom,sm8250-mmss-noc";
1177                         reg = <0 0x01740000 0 0x1f080>;
1178                         #interconnect-cells = <1>;
1179                         qcom,bcm-voters = <&apps_bcm_voter>;
1180                 };
1181
1182                 ufs_mem_hc: ufshc@1d84000 {
1183                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1184                                      "jedec,ufs-2.0";
1185                         reg = <0 0x01d84000 0 0x3000>;
1186                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1187                         phys = <&ufs_mem_phy_lanes>;
1188                         phy-names = "ufsphy";
1189                         lanes-per-direction = <2>;
1190                         #reset-cells = <1>;
1191                         resets = <&gcc GCC_UFS_PHY_BCR>;
1192                         reset-names = "rst";
1193
1194                         power-domains = <&gcc UFS_PHY_GDSC>;
1195
1196                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1197
1198                         clock-names =
1199                                 "core_clk",
1200                                 "bus_aggr_clk",
1201                                 "iface_clk",
1202                                 "core_clk_unipro",
1203                                 "ref_clk",
1204                                 "tx_lane0_sync_clk",
1205                                 "rx_lane0_sync_clk",
1206                                 "rx_lane1_sync_clk";
1207                         clocks =
1208                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1209                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1210                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1211                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1212                                 <&rpmhcc RPMH_CXO_CLK>,
1213                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1214                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1215                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1216                         freq-table-hz =
1217                                 <37500000 300000000>,
1218                                 <0 0>,
1219                                 <0 0>,
1220                                 <37500000 300000000>,
1221                                 <0 0>,
1222                                 <0 0>,
1223                                 <0 0>,
1224                                 <0 0>;
1225
1226                         status = "disabled";
1227                 };
1228
1229                 ufs_mem_phy: phy@1d87000 {
1230                         compatible = "qcom,sm8250-qmp-ufs-phy";
1231                         reg = <0 0x01d87000 0 0x1c0>;
1232                         #address-cells = <2>;
1233                         #size-cells = <2>;
1234                         ranges;
1235                         clock-names = "ref",
1236                                       "ref_aux";
1237                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1238                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1239
1240                         resets = <&ufs_mem_hc 0>;
1241                         reset-names = "ufsphy";
1242                         status = "disabled";
1243
1244                         ufs_mem_phy_lanes: lanes@1d87400 {
1245                                 reg = <0 0x01d87400 0 0x108>,
1246                                       <0 0x01d87600 0 0x1e0>,
1247                                       <0 0x01d87c00 0 0x1dc>,
1248                                       <0 0x01d87800 0 0x108>,
1249                                       <0 0x01d87a00 0 0x1e0>;
1250                                 #phy-cells = <0>;
1251                         };
1252                 };
1253
1254                 ipa_virt: interconnect@1e00000 {
1255                         compatible = "qcom,sm8250-ipa-virt";
1256                         reg = <0 0x01e00000 0 0x1000>;
1257                         #interconnect-cells = <1>;
1258                         qcom,bcm-voters = <&apps_bcm_voter>;
1259                 };
1260
1261                 tcsr_mutex: hwlock@1f40000 {
1262                         compatible = "qcom,tcsr-mutex";
1263                         reg = <0x0 0x01f40000 0x0 0x40000>;
1264                         #hwlock-cells = <1>;
1265                 };
1266
1267                 audiocc: clock-controller@3300000 {
1268                         compatible = "qcom,sm8250-lpass-audiocc";
1269                         reg = <0 0x03300000 0 0x30000>;
1270                         #clock-cells = <1>;
1271                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1272                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1273                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1274                         clock-names = "core", "audio", "bus";
1275                 };
1276
1277                 aoncc: clock-controller@3380000 {
1278                         compatible = "qcom,sm8250-lpass-aoncc";
1279                         reg = <0 0x03380000 0 0x40000>;
1280                         #clock-cells = <1>;
1281                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1282                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1283                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1284                         clock-names = "core", "audio", "bus";
1285                 };
1286
1287                 gpu: gpu@3d00000 {
1288                         compatible = "qcom,adreno-650.2",
1289                                      "qcom,adreno";
1290                         #stream-id-cells = <16>;
1291
1292                         reg = <0 0x03d00000 0 0x40000>;
1293                         reg-names = "kgsl_3d0_reg_memory";
1294
1295                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1296
1297                         iommus = <&adreno_smmu 0 0x401>;
1298
1299                         operating-points-v2 = <&gpu_opp_table>;
1300
1301                         qcom,gmu = <&gmu>;
1302
1303                         zap-shader {
1304                                 memory-region = <&gpu_mem>;
1305                         };
1306
1307                         /* note: downstream checks gpu binning for 670 Mhz */
1308                         gpu_opp_table: opp-table {
1309                                 compatible = "operating-points-v2";
1310
1311                                 opp-670000000 {
1312                                         opp-hz = /bits/ 64 <670000000>;
1313                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1314                                 };
1315
1316                                 opp-587000000 {
1317                                         opp-hz = /bits/ 64 <587000000>;
1318                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1319                                 };
1320
1321                                 opp-525000000 {
1322                                         opp-hz = /bits/ 64 <525000000>;
1323                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1324                                 };
1325
1326                                 opp-490000000 {
1327                                         opp-hz = /bits/ 64 <490000000>;
1328                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1329                                 };
1330
1331                                 opp-441600000 {
1332                                         opp-hz = /bits/ 64 <441600000>;
1333                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1334                                 };
1335
1336                                 opp-400000000 {
1337                                         opp-hz = /bits/ 64 <400000000>;
1338                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1339                                 };
1340
1341                                 opp-305000000 {
1342                                         opp-hz = /bits/ 64 <305000000>;
1343                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1344                                 };
1345                         };
1346                 };
1347
1348                 gmu: gmu@3d6a000 {
1349                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1350
1351                         reg = <0 0x03d6a000 0 0x30000>,
1352                               <0 0x3de0000 0 0x10000>,
1353                               <0 0xb290000 0 0x10000>,
1354                               <0 0xb490000 0 0x10000>;
1355                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1356
1357                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1358                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1359                         interrupt-names = "hfi", "gmu";
1360
1361                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1362                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1363                                  <&gpucc GPU_CC_CXO_CLK>,
1364                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1365                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1366                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1367
1368                         power-domains = <&gpucc GPU_CX_GDSC>,
1369                                         <&gpucc GPU_GX_GDSC>;
1370                         power-domain-names = "cx", "gx";
1371
1372                         iommus = <&adreno_smmu 5 0x400>;
1373
1374                         operating-points-v2 = <&gmu_opp_table>;
1375
1376                         gmu_opp_table: opp-table {
1377                                 compatible = "operating-points-v2";
1378
1379                                 opp-200000000 {
1380                                         opp-hz = /bits/ 64 <200000000>;
1381                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1382                                 };
1383                         };
1384                 };
1385
1386                 gpucc: clock-controller@3d90000 {
1387                         compatible = "qcom,sm8250-gpucc";
1388                         reg = <0 0x03d90000 0 0x9000>;
1389                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1390                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1391                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1392                         clock-names = "bi_tcxo",
1393                                       "gcc_gpu_gpll0_clk_src",
1394                                       "gcc_gpu_gpll0_div_clk_src";
1395                         #clock-cells = <1>;
1396                         #reset-cells = <1>;
1397                         #power-domain-cells = <1>;
1398                 };
1399
1400                 adreno_smmu: iommu@3da0000 {
1401                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1402                         reg = <0 0x03da0000 0 0x10000>;
1403                         #iommu-cells = <2>;
1404                         #global-interrupts = <2>;
1405                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1406                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1407                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1408                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1409                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1410                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1411                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1412                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1413                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1414                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1415                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1416                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1417                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1418                         clock-names = "ahb", "bus", "iface";
1419
1420                         power-domains = <&gpucc GPU_CX_GDSC>;
1421                 };
1422
1423                 slpi: remoteproc@5c00000 {
1424                         compatible = "qcom,sm8250-slpi-pas";
1425                         reg = <0 0x05c00000 0 0x4000>;
1426
1427                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1428                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1429                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1430                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1431                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1432                         interrupt-names = "wdog", "fatal", "ready",
1433                                           "handover", "stop-ack";
1434
1435                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1436                         clock-names = "xo";
1437
1438                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1439                                         <&rpmhpd SM8250_LCX>,
1440                                         <&rpmhpd SM8250_LMX>;
1441                         power-domain-names = "load_state", "lcx", "lmx";
1442
1443                         memory-region = <&slpi_mem>;
1444
1445                         qcom,smem-states = <&smp2p_slpi_out 0>;
1446                         qcom,smem-state-names = "stop";
1447
1448                         status = "disabled";
1449
1450                         glink-edge {
1451                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1452                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1453                                                              IRQ_TYPE_EDGE_RISING>;
1454                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1455                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1456
1457                                 label = "slpi";
1458                                 qcom,remote-pid = <3>;
1459
1460                                 fastrpc {
1461                                         compatible = "qcom,fastrpc";
1462                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1463                                         label = "sdsp";
1464                                         #address-cells = <1>;
1465                                         #size-cells = <0>;
1466
1467                                         compute-cb@1 {
1468                                                 compatible = "qcom,fastrpc-compute-cb";
1469                                                 reg = <1>;
1470                                                 iommus = <&apps_smmu 0x0541 0x0>;
1471                                         };
1472
1473                                         compute-cb@2 {
1474                                                 compatible = "qcom,fastrpc-compute-cb";
1475                                                 reg = <2>;
1476                                                 iommus = <&apps_smmu 0x0542 0x0>;
1477                                         };
1478
1479                                         compute-cb@3 {
1480                                                 compatible = "qcom,fastrpc-compute-cb";
1481                                                 reg = <3>;
1482                                                 iommus = <&apps_smmu 0x0543 0x0>;
1483                                                 /* note: shared-cb = <4> in downstream */
1484                                         };
1485                                 };
1486                         };
1487                 };
1488
1489                 cdsp: remoteproc@8300000 {
1490                         compatible = "qcom,sm8250-cdsp-pas";
1491                         reg = <0 0x08300000 0 0x10000>;
1492
1493                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1494                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1495                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1496                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1497                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1498                         interrupt-names = "wdog", "fatal", "ready",
1499                                           "handover", "stop-ack";
1500
1501                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1502                         clock-names = "xo";
1503
1504                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1505                                         <&rpmhpd SM8250_CX>;
1506                         power-domain-names = "load_state", "cx";
1507
1508                         memory-region = <&cdsp_mem>;
1509
1510                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1511                         qcom,smem-state-names = "stop";
1512
1513                         status = "disabled";
1514
1515                         glink-edge {
1516                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1517                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1518                                                              IRQ_TYPE_EDGE_RISING>;
1519                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1520                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1521
1522                                 label = "cdsp";
1523                                 qcom,remote-pid = <5>;
1524
1525                                 fastrpc {
1526                                         compatible = "qcom,fastrpc";
1527                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1528                                         label = "cdsp";
1529                                         #address-cells = <1>;
1530                                         #size-cells = <0>;
1531
1532                                         compute-cb@1 {
1533                                                 compatible = "qcom,fastrpc-compute-cb";
1534                                                 reg = <1>;
1535                                                 iommus = <&apps_smmu 0x1001 0x0460>;
1536                                         };
1537
1538                                         compute-cb@2 {
1539                                                 compatible = "qcom,fastrpc-compute-cb";
1540                                                 reg = <2>;
1541                                                 iommus = <&apps_smmu 0x1002 0x0460>;
1542                                         };
1543
1544                                         compute-cb@3 {
1545                                                 compatible = "qcom,fastrpc-compute-cb";
1546                                                 reg = <3>;
1547                                                 iommus = <&apps_smmu 0x1003 0x0460>;
1548                                         };
1549
1550                                         compute-cb@4 {
1551                                                 compatible = "qcom,fastrpc-compute-cb";
1552                                                 reg = <4>;
1553                                                 iommus = <&apps_smmu 0x1004 0x0460>;
1554                                         };
1555
1556                                         compute-cb@5 {
1557                                                 compatible = "qcom,fastrpc-compute-cb";
1558                                                 reg = <5>;
1559                                                 iommus = <&apps_smmu 0x1005 0x0460>;
1560                                         };
1561
1562                                         compute-cb@6 {
1563                                                 compatible = "qcom,fastrpc-compute-cb";
1564                                                 reg = <6>;
1565                                                 iommus = <&apps_smmu 0x1006 0x0460>;
1566                                         };
1567
1568                                         compute-cb@7 {
1569                                                 compatible = "qcom,fastrpc-compute-cb";
1570                                                 reg = <7>;
1571                                                 iommus = <&apps_smmu 0x1007 0x0460>;
1572                                         };
1573
1574                                         compute-cb@8 {
1575                                                 compatible = "qcom,fastrpc-compute-cb";
1576                                                 reg = <8>;
1577                                                 iommus = <&apps_smmu 0x1008 0x0460>;
1578                                         };
1579
1580                                         /* note: secure cb9 in downstream */
1581                                 };
1582                         };
1583                 };
1584
1585                 usb_1_hsphy: phy@88e3000 {
1586                         compatible = "qcom,sm8250-usb-hs-phy",
1587                                      "qcom,usb-snps-hs-7nm-phy";
1588                         reg = <0 0x088e3000 0 0x400>;
1589                         status = "disabled";
1590                         #phy-cells = <0>;
1591
1592                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1593                         clock-names = "ref";
1594
1595                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1596                 };
1597
1598                 usb_2_hsphy: phy@88e4000 {
1599                         compatible = "qcom,sm8250-usb-hs-phy",
1600                                      "qcom,usb-snps-hs-7nm-phy";
1601                         reg = <0 0x088e4000 0 0x400>;
1602                         status = "disabled";
1603                         #phy-cells = <0>;
1604
1605                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1606                         clock-names = "ref";
1607
1608                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1609                 };
1610
1611                 usb_1_qmpphy: phy@88e9000 {
1612                         compatible = "qcom,sm8250-qmp-usb3-phy";
1613                         reg = <0 0x088e9000 0 0x200>,
1614                               <0 0x088e8000 0 0x20>;
1615                         reg-names = "reg-base", "dp_com";
1616                         status = "disabled";
1617                         #clock-cells = <1>;
1618                         #address-cells = <2>;
1619                         #size-cells = <2>;
1620                         ranges;
1621
1622                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1623                                  <&rpmhcc RPMH_CXO_CLK>,
1624                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1625                         clock-names = "aux", "ref_clk_src", "com_aux";
1626
1627                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1628                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1629                         reset-names = "phy", "common";
1630
1631                         usb_1_ssphy: lanes@88e9200 {
1632                                 reg = <0 0x088e9200 0 0x200>,
1633                                       <0 0x088e9400 0 0x200>,
1634                                       <0 0x088e9c00 0 0x400>,
1635                                       <0 0x088e9600 0 0x200>,
1636                                       <0 0x088e9800 0 0x200>,
1637                                       <0 0x088e9a00 0 0x100>;
1638                                 #phy-cells = <0>;
1639                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1640                                 clock-names = "pipe0";
1641                                 clock-output-names = "usb3_phy_pipe_clk_src";
1642                         };
1643                 };
1644
1645                 usb_2_qmpphy: phy@88eb000 {
1646                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
1647                         reg = <0 0x088eb000 0 0x200>;
1648                         status = "disabled";
1649                         #clock-cells = <1>;
1650                         #address-cells = <2>;
1651                         #size-cells = <2>;
1652                         ranges;
1653
1654                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1655                                  <&rpmhcc RPMH_CXO_CLK>,
1656                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
1657                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1658                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1659
1660                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1661                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
1662                         reset-names = "phy", "common";
1663
1664                         usb_2_ssphy: lane@88eb200 {
1665                                 reg = <0 0x088eb200 0 0x200>,
1666                                       <0 0x088eb400 0 0x200>,
1667                                       <0 0x088eb800 0 0x800>;
1668                                 #phy-cells = <0>;
1669                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1670                                 clock-names = "pipe0";
1671                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1672                         };
1673                 };
1674
1675                 sdhc_2: sdhci@8804000 {
1676                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
1677                         reg = <0 0x08804000 0 0x1000>;
1678
1679                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1680                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1681                         interrupt-names = "hc_irq", "pwr_irq";
1682
1683                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1684                                  <&gcc GCC_SDCC2_APPS_CLK>,
1685                                  <&xo_board>;
1686                         clock-names = "iface", "core", "xo";
1687                         iommus = <&apps_smmu 0x4a0 0x0>;
1688                         qcom,dll-config = <0x0007642c>;
1689                         qcom,ddr-config = <0x80040868>;
1690                         power-domains = <&rpmhpd SM8250_CX>;
1691                         operating-points-v2 = <&sdhc2_opp_table>;
1692
1693                         status = "disabled";
1694
1695                         sdhc2_opp_table: sdhc2-opp-table {
1696                                 compatible = "operating-points-v2";
1697
1698                                 opp-19200000 {
1699                                         opp-hz = /bits/ 64 <19200000>;
1700                                         required-opps = <&rpmhpd_opp_min_svs>;
1701                                 };
1702
1703                                 opp-50000000 {
1704                                         opp-hz = /bits/ 64 <50000000>;
1705                                         required-opps = <&rpmhpd_opp_low_svs>;
1706                                 };
1707
1708                                 opp-100000000 {
1709                                         opp-hz = /bits/ 64 <100000000>;
1710                                         required-opps = <&rpmhpd_opp_svs>;
1711                                 };
1712
1713                                 opp-202000000 {
1714                                         opp-hz = /bits/ 64 <202000000>;
1715                                         required-opps = <&rpmhpd_opp_svs_l1>;
1716                                 };
1717                         };
1718                 };
1719
1720                 dc_noc: interconnect@90c0000 {
1721                         compatible = "qcom,sm8250-dc-noc";
1722                         reg = <0 0x090c0000 0 0x4200>;
1723                         #interconnect-cells = <1>;
1724                         qcom,bcm-voters = <&apps_bcm_voter>;
1725                 };
1726
1727                 gem_noc: interconnect@9100000 {
1728                         compatible = "qcom,sm8250-gem-noc";
1729                         reg = <0 0x09100000 0 0xb4000>;
1730                         #interconnect-cells = <1>;
1731                         qcom,bcm-voters = <&apps_bcm_voter>;
1732                 };
1733
1734                 npu_noc: interconnect@9990000 {
1735                         compatible = "qcom,sm8250-npu-noc";
1736                         reg = <0 0x09990000 0 0x1600>;
1737                         #interconnect-cells = <1>;
1738                         qcom,bcm-voters = <&apps_bcm_voter>;
1739                 };
1740
1741                 usb_1: usb@a6f8800 {
1742                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1743                         reg = <0 0x0a6f8800 0 0x400>;
1744                         status = "disabled";
1745                         #address-cells = <2>;
1746                         #size-cells = <2>;
1747                         ranges;
1748                         dma-ranges;
1749
1750                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1751                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1752                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1753                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1754                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1755                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1756                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1757                                       "sleep", "xo";
1758
1759                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1760                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1761                         assigned-clock-rates = <19200000>, <200000000>;
1762
1763                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1764                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1765                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1766                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1767                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1768                                           "dm_hs_phy_irq", "ss_phy_irq";
1769
1770                         power-domains = <&gcc USB30_PRIM_GDSC>;
1771
1772                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1773
1774                         usb_1_dwc3: dwc3@a600000 {
1775                                 compatible = "snps,dwc3";
1776                                 reg = <0 0x0a600000 0 0xcd00>;
1777                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1778                                 iommus = <&apps_smmu 0x0 0x0>;
1779                                 snps,dis_u2_susphy_quirk;
1780                                 snps,dis_enblslpm_quirk;
1781                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1782                                 phy-names = "usb2-phy", "usb3-phy";
1783                         };
1784                 };
1785
1786                 system-cache-controller@9200000 {
1787                         compatible = "qcom,sm8250-llcc";
1788                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
1789                         reg-names = "llcc_base", "llcc_broadcast_base";
1790                 };
1791
1792                 usb_2: usb@a8f8800 {
1793                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1794                         reg = <0 0x0a8f8800 0 0x400>;
1795                         status = "disabled";
1796                         #address-cells = <2>;
1797                         #size-cells = <2>;
1798                         ranges;
1799                         dma-ranges;
1800
1801                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1802                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1803                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1804                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1805                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1806                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1807                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1808                                       "sleep", "xo";
1809
1810                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1811                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1812                         assigned-clock-rates = <19200000>, <200000000>;
1813
1814                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1815                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1816                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1817                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1818                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1819                                           "dm_hs_phy_irq", "ss_phy_irq";
1820
1821                         power-domains = <&gcc USB30_SEC_GDSC>;
1822
1823                         resets = <&gcc GCC_USB30_SEC_BCR>;
1824
1825                         usb_2_dwc3: dwc3@a800000 {
1826                                 compatible = "snps,dwc3";
1827                                 reg = <0 0x0a800000 0 0xcd00>;
1828                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1829                                 iommus = <&apps_smmu 0x20 0>;
1830                                 snps,dis_u2_susphy_quirk;
1831                                 snps,dis_enblslpm_quirk;
1832                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1833                                 phy-names = "usb2-phy", "usb3-phy";
1834                         };
1835                 };
1836
1837                 mdss: mdss@ae00000 {
1838                         compatible = "qcom,sdm845-mdss";
1839                         reg = <0 0x0ae00000 0 0x1000>;
1840                         reg-names = "mdss";
1841
1842                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
1843                                         <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
1844                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
1845                         interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
1846
1847                         power-domains = <&dispcc MDSS_GDSC>;
1848
1849                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1850                                  <&gcc GCC_DISP_HF_AXI_CLK>,
1851                                  <&gcc GCC_DISP_SF_AXI_CLK>,
1852                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
1853                         clock-names = "iface", "bus", "nrt_bus", "core";
1854
1855                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
1856                         assigned-clock-rates = <460000000>;
1857
1858                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1859                         interrupt-controller;
1860                         #interrupt-cells = <1>;
1861
1862                         iommus = <&apps_smmu 0x820 0x402>;
1863
1864                         status = "disabled";
1865
1866                         #address-cells = <2>;
1867                         #size-cells = <2>;
1868                         ranges;
1869
1870                         mdss_mdp: mdp@ae01000 {
1871                                 compatible = "qcom,sdm845-dpu";
1872                                 reg = <0 0x0ae01000 0 0x8f000>,
1873                                       <0 0x0aeb0000 0 0x2008>;
1874                                 reg-names = "mdp", "vbif";
1875
1876                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1877                                          <&gcc GCC_DISP_HF_AXI_CLK>,
1878                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
1879                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1880                                 clock-names = "iface", "bus", "core", "vsync";
1881
1882                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
1883                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1884                                 assigned-clock-rates = <460000000>,
1885                                                        <19200000>;
1886
1887                                 operating-points-v2 = <&mdp_opp_table>;
1888                                 power-domains = <&rpmhpd SM8250_MMCX>;
1889
1890                                 interrupt-parent = <&mdss>;
1891                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1892
1893                                 status = "disabled";
1894
1895                                 ports {
1896                                         #address-cells = <1>;
1897                                         #size-cells = <0>;
1898
1899                                         port@0 {
1900                                                 reg = <0>;
1901                                                 dpu_intf1_out: endpoint {
1902                                                         remote-endpoint = <&dsi0_in>;
1903                                                 };
1904                                         };
1905
1906                                         port@1 {
1907                                                 reg = <1>;
1908                                                 dpu_intf2_out: endpoint {
1909                                                         remote-endpoint = <&dsi1_in>;
1910                                                 };
1911                                         };
1912                                 };
1913
1914                                 mdp_opp_table: mdp-opp-table {
1915                                         compatible = "operating-points-v2";
1916
1917                                         opp-200000000 {
1918                                                 opp-hz = /bits/ 64 <200000000>;
1919                                                 required-opps = <&rpmhpd_opp_low_svs>;
1920                                         };
1921
1922                                         opp-300000000 {
1923                                                 opp-hz = /bits/ 64 <300000000>;
1924                                                 required-opps = <&rpmhpd_opp_svs>;
1925                                         };
1926
1927                                         opp-345000000 {
1928                                                 opp-hz = /bits/ 64 <345000000>;
1929                                                 required-opps = <&rpmhpd_opp_svs_l1>;
1930                                         };
1931
1932                                         opp-460000000 {
1933                                                 opp-hz = /bits/ 64 <460000000>;
1934                                                 required-opps = <&rpmhpd_opp_nom>;
1935                                         };
1936                                 };
1937                         };
1938
1939                         dsi0: dsi@ae94000 {
1940                                 compatible = "qcom,mdss-dsi-ctrl";
1941                                 reg = <0 0x0ae94000 0 0x400>;
1942                                 reg-names = "dsi_ctrl";
1943
1944                                 interrupt-parent = <&mdss>;
1945                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1946
1947                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1948                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1949                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1950                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1951                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1952                                         <&gcc GCC_DISP_HF_AXI_CLK>;
1953                                 clock-names = "byte",
1954                                               "byte_intf",
1955                                               "pixel",
1956                                               "core",
1957                                               "iface",
1958                                               "bus";
1959
1960                                 operating-points-v2 = <&dsi_opp_table>;
1961                                 power-domains = <&rpmhpd SM8250_MMCX>;
1962
1963                                 phys = <&dsi0_phy>;
1964                                 phy-names = "dsi";
1965
1966                                 status = "disabled";
1967
1968                                 ports {
1969                                         #address-cells = <1>;
1970                                         #size-cells = <0>;
1971
1972                                         port@0 {
1973                                                 reg = <0>;
1974                                                 dsi0_in: endpoint {
1975                                                         remote-endpoint = <&dpu_intf1_out>;
1976                                                 };
1977                                         };
1978
1979                                         port@1 {
1980                                                 reg = <1>;
1981                                                 dsi0_out: endpoint {
1982                                                 };
1983                                         };
1984                                 };
1985                         };
1986
1987                         dsi0_phy: dsi-phy@ae94400 {
1988                                 compatible = "qcom,dsi-phy-7nm";
1989                                 reg = <0 0x0ae94400 0 0x200>,
1990                                       <0 0x0ae94600 0 0x280>,
1991                                       <0 0x0ae94900 0 0x260>;
1992                                 reg-names = "dsi_phy",
1993                                             "dsi_phy_lane",
1994                                             "dsi_pll";
1995
1996                                 #clock-cells = <1>;
1997                                 #phy-cells = <0>;
1998
1999                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2000                                          <&rpmhcc RPMH_CXO_CLK>;
2001                                 clock-names = "iface", "ref";
2002
2003                                 status = "disabled";
2004                         };
2005
2006                         dsi1: dsi@ae96000 {
2007                                 compatible = "qcom,mdss-dsi-ctrl";
2008                                 reg = <0 0x0ae96000 0 0x400>;
2009                                 reg-names = "dsi_ctrl";
2010
2011                                 interrupt-parent = <&mdss>;
2012                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2013
2014                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2015                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2016                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2017                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2018                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2019                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2020                                 clock-names = "byte",
2021                                               "byte_intf",
2022                                               "pixel",
2023                                               "core",
2024                                               "iface",
2025                                               "bus";
2026
2027                                 operating-points-v2 = <&dsi_opp_table>;
2028                                 power-domains = <&rpmhpd SM8250_MMCX>;
2029
2030                                 phys = <&dsi1_phy>;
2031                                 phy-names = "dsi";
2032
2033                                 status = "disabled";
2034
2035                                 ports {
2036                                         #address-cells = <1>;
2037                                         #size-cells = <0>;
2038
2039                                         port@0 {
2040                                                 reg = <0>;
2041                                                 dsi1_in: endpoint {
2042                                                         remote-endpoint = <&dpu_intf2_out>;
2043                                                 };
2044                                         };
2045
2046                                         port@1 {
2047                                                 reg = <1>;
2048                                                 dsi1_out: endpoint {
2049                                                 };
2050                                         };
2051                                 };
2052                         };
2053
2054                         dsi1_phy: dsi-phy@ae96400 {
2055                                 compatible = "qcom,dsi-phy-7nm";
2056                                 reg = <0 0x0ae96400 0 0x200>,
2057                                       <0 0x0ae96600 0 0x280>,
2058                                       <0 0x0ae96900 0 0x260>;
2059                                 reg-names = "dsi_phy",
2060                                             "dsi_phy_lane",
2061                                             "dsi_pll";
2062
2063                                 #clock-cells = <1>;
2064                                 #phy-cells = <0>;
2065
2066                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2067                                          <&rpmhcc RPMH_CXO_CLK>;
2068                                 clock-names = "iface", "ref";
2069
2070                                 status = "disabled";
2071
2072                                 dsi_opp_table: dsi-opp-table {
2073                                         compatible = "operating-points-v2";
2074
2075                                         opp-187500000 {
2076                                                 opp-hz = /bits/ 64 <187500000>;
2077                                                 required-opps = <&rpmhpd_opp_low_svs>;
2078                                         };
2079
2080                                         opp-300000000 {
2081                                                 opp-hz = /bits/ 64 <300000000>;
2082                                                 required-opps = <&rpmhpd_opp_svs>;
2083                                         };
2084
2085                                         opp-358000000 {
2086                                                 opp-hz = /bits/ 64 <358000000>;
2087                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2088                                         };
2089                                 };
2090                         };
2091                 };
2092
2093                 dispcc: clock-controller@af00000 {
2094                         compatible = "qcom,sm8250-dispcc";
2095                         reg = <0 0x0af00000 0 0x20000>;
2096                         mmcx-supply = <&mmcx_reg>;
2097                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2098                                  <&dsi0_phy 0>,
2099                                  <&dsi0_phy 1>,
2100                                  <&dsi1_phy 0>,
2101                                  <&dsi1_phy 1>,
2102                                  <0>,
2103                                  <0>,
2104                                  <0>,
2105                                  <0>,
2106                                  <0>,
2107                                  <0>,
2108                                  <0>,
2109                                  <0>,
2110                                  <&sleep_clk>;
2111                         clock-names = "bi_tcxo",
2112                                       "dsi0_phy_pll_out_byteclk",
2113                                       "dsi0_phy_pll_out_dsiclk",
2114                                       "dsi1_phy_pll_out_byteclk",
2115                                       "dsi1_phy_pll_out_dsiclk",
2116                                       "dp_link_clk_divsel_ten",
2117                                       "dp_vco_divided_clk_src_mux",
2118                                       "dptx1_phy_pll_link_clk",
2119                                       "dptx1_phy_pll_vco_div_clk",
2120                                       "dptx2_phy_pll_link_clk",
2121                                       "dptx2_phy_pll_vco_div_clk",
2122                                       "edp_phy_pll_link_clk",
2123                                       "edp_phy_pll_vco_div_clk",
2124                                       "sleep_clk";
2125                         #clock-cells = <1>;
2126                         #reset-cells = <1>;
2127                         #power-domain-cells = <1>;
2128                 };
2129
2130                 pdc: interrupt-controller@b220000 {
2131                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
2132                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2133                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2134                                           <125 63 1>, <126 716 12>;
2135                         #interrupt-cells = <2>;
2136                         interrupt-parent = <&intc>;
2137                         interrupt-controller;
2138                 };
2139
2140                 tsens0: thermal-sensor@c263000 {
2141                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2142                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2143                               <0 0x0c222000 0 0x1ff>; /* SROT */
2144                         #qcom,sensors = <16>;
2145                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2146                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2147                         interrupt-names = "uplow", "critical";
2148                         #thermal-sensor-cells = <1>;
2149                 };
2150
2151                 tsens1: thermal-sensor@c265000 {
2152                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2153                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2154                               <0 0x0c223000 0 0x1ff>; /* SROT */
2155                         #qcom,sensors = <9>;
2156                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2157                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2158                         interrupt-names = "uplow", "critical";
2159                         #thermal-sensor-cells = <1>;
2160                 };
2161
2162                 aoss_qmp: qmp@c300000 {
2163                         compatible = "qcom,sm8250-aoss-qmp";
2164                         reg = <0 0x0c300000 0 0x100000>;
2165                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2166                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
2167                                                      IRQ_TYPE_EDGE_RISING>;
2168                         mboxes = <&ipcc IPCC_CLIENT_AOP
2169                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
2170
2171                         #clock-cells = <0>;
2172                         #power-domain-cells = <1>;
2173                 };
2174
2175                 spmi_bus: spmi@c440000 {
2176                         compatible = "qcom,spmi-pmic-arb";
2177                         reg = <0x0 0x0c440000 0x0 0x0001100>,
2178                               <0x0 0x0c600000 0x0 0x2000000>,
2179                               <0x0 0x0e600000 0x0 0x0100000>,
2180                               <0x0 0x0e700000 0x0 0x00a0000>,
2181                               <0x0 0x0c40a000 0x0 0x0026000>;
2182                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2183                         interrupt-names = "periph_irq";
2184                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2185                         qcom,ee = <0>;
2186                         qcom,channel = <0>;
2187                         #address-cells = <2>;
2188                         #size-cells = <0>;
2189                         interrupt-controller;
2190                         #interrupt-cells = <4>;
2191                 };
2192
2193                 tlmm: pinctrl@f100000 {
2194                         compatible = "qcom,sm8250-pinctrl";
2195                         reg = <0 0x0f100000 0 0x300000>,
2196                               <0 0x0f500000 0 0x300000>,
2197                               <0 0x0f900000 0 0x300000>;
2198                         reg-names = "west", "south", "north";
2199                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2200                         gpio-controller;
2201                         #gpio-cells = <2>;
2202                         interrupt-controller;
2203                         #interrupt-cells = <2>;
2204                         gpio-ranges = <&tlmm 0 0 180>;
2205                         wakeup-parent = <&pdc>;
2206
2207                         qup_i2c0_default: qup-i2c0-default {
2208                                 mux {
2209                                         pins = "gpio28", "gpio29";
2210                                         function = "qup0";
2211                                 };
2212
2213                                 config {
2214                                         pins = "gpio28", "gpio29";
2215                                         drive-strength = <2>;
2216                                         bias-disable;
2217                                 };
2218                         };
2219
2220                         qup_i2c1_default: qup-i2c1-default {
2221                                 pinmux {
2222                                         pins = "gpio4", "gpio5";
2223                                         function = "qup1";
2224                                 };
2225
2226                                 config {
2227                                         pins = "gpio4", "gpio5";
2228                                         drive-strength = <2>;
2229                                         bias-disable;
2230                                 };
2231                         };
2232
2233                         qup_i2c2_default: qup-i2c2-default {
2234                                 mux {
2235                                         pins = "gpio115", "gpio116";
2236                                         function = "qup2";
2237                                 };
2238
2239                                 config {
2240                                         pins = "gpio115", "gpio116";
2241                                         drive-strength = <2>;
2242                                         bias-disable;
2243                                 };
2244                         };
2245
2246                         qup_i2c3_default: qup-i2c3-default {
2247                                 mux {
2248                                         pins = "gpio119", "gpio120";
2249                                         function = "qup3";
2250                                 };
2251
2252                                 config {
2253                                         pins = "gpio119", "gpio120";
2254                                         drive-strength = <2>;
2255                                         bias-disable;
2256                                 };
2257                         };
2258
2259                         qup_i2c4_default: qup-i2c4-default {
2260                                 mux {
2261                                         pins = "gpio8", "gpio9";
2262                                         function = "qup4";
2263                                 };
2264
2265                                 config {
2266                                         pins = "gpio8", "gpio9";
2267                                         drive-strength = <2>;
2268                                         bias-disable;
2269                                 };
2270                         };
2271
2272                         qup_i2c5_default: qup-i2c5-default {
2273                                 mux {
2274                                         pins = "gpio12", "gpio13";
2275                                         function = "qup5";
2276                                 };
2277
2278                                 config {
2279                                         pins = "gpio12", "gpio13";
2280                                         drive-strength = <2>;
2281                                         bias-disable;
2282                                 };
2283                         };
2284
2285                         qup_i2c6_default: qup-i2c6-default {
2286                                 mux {
2287                                         pins = "gpio16", "gpio17";
2288                                         function = "qup6";
2289                                 };
2290
2291                                 config {
2292                                         pins = "gpio16", "gpio17";
2293                                         drive-strength = <2>;
2294                                         bias-disable;
2295                                 };
2296                         };
2297
2298                         qup_i2c7_default: qup-i2c7-default {
2299                                 mux {
2300                                         pins = "gpio20", "gpio21";
2301                                         function = "qup7";
2302                                 };
2303
2304                                 config {
2305                                         pins = "gpio20", "gpio21";
2306                                         drive-strength = <2>;
2307                                         bias-disable;
2308                                 };
2309                         };
2310
2311                         qup_i2c8_default: qup-i2c8-default {
2312                                 mux {
2313                                         pins = "gpio24", "gpio25";
2314                                         function = "qup8";
2315                                 };
2316
2317                                 config {
2318                                         pins = "gpio24", "gpio25";
2319                                         drive-strength = <2>;
2320                                         bias-disable;
2321                                 };
2322                         };
2323
2324                         qup_i2c9_default: qup-i2c9-default {
2325                                 mux {
2326                                         pins = "gpio125", "gpio126";
2327                                         function = "qup9";
2328                                 };
2329
2330                                 config {
2331                                         pins = "gpio125", "gpio126";
2332                                         drive-strength = <2>;
2333                                         bias-disable;
2334                                 };
2335                         };
2336
2337                         qup_i2c10_default: qup-i2c10-default {
2338                                 mux {
2339                                         pins = "gpio129", "gpio130";
2340                                         function = "qup10";
2341                                 };
2342
2343                                 config {
2344                                         pins = "gpio129", "gpio130";
2345                                         drive-strength = <2>;
2346                                         bias-disable;
2347                                 };
2348                         };
2349
2350                         qup_i2c11_default: qup-i2c11-default {
2351                                 mux {
2352                                         pins = "gpio60", "gpio61";
2353                                         function = "qup11";
2354                                 };
2355
2356                                 config {
2357                                         pins = "gpio60", "gpio61";
2358                                         drive-strength = <2>;
2359                                         bias-disable;
2360                                 };
2361                         };
2362
2363                         qup_i2c12_default: qup-i2c12-default {
2364                                 mux {
2365                                         pins = "gpio32", "gpio33";
2366                                         function = "qup12";
2367                                 };
2368
2369                                 config {
2370                                         pins = "gpio32", "gpio33";
2371                                         drive-strength = <2>;
2372                                         bias-disable;
2373                                 };
2374                         };
2375
2376                         qup_i2c13_default: qup-i2c13-default {
2377                                 mux {
2378                                         pins = "gpio36", "gpio37";
2379                                         function = "qup13";
2380                                 };
2381
2382                                 config {
2383                                         pins = "gpio36", "gpio37";
2384                                         drive-strength = <2>;
2385                                         bias-disable;
2386                                 };
2387                         };
2388
2389                         qup_i2c14_default: qup-i2c14-default {
2390                                 mux {
2391                                         pins = "gpio40", "gpio41";
2392                                         function = "qup14";
2393                                 };
2394
2395                                 config {
2396                                         pins = "gpio40", "gpio41";
2397                                         drive-strength = <2>;
2398                                         bias-disable;
2399                                 };
2400                         };
2401
2402                         qup_i2c15_default: qup-i2c15-default {
2403                                 mux {
2404                                         pins = "gpio44", "gpio45";
2405                                         function = "qup15";
2406                                 };
2407
2408                                 config {
2409                                         pins = "gpio44", "gpio45";
2410                                         drive-strength = <2>;
2411                                         bias-disable;
2412                                 };
2413                         };
2414
2415                         qup_i2c16_default: qup-i2c16-default {
2416                                 mux {
2417                                         pins = "gpio48", "gpio49";
2418                                         function = "qup16";
2419                                 };
2420
2421                                 config {
2422                                         pins = "gpio48", "gpio49";
2423                                         drive-strength = <2>;
2424                                         bias-disable;
2425                                 };
2426                         };
2427
2428                         qup_i2c17_default: qup-i2c17-default {
2429                                 mux {
2430                                         pins = "gpio52", "gpio53";
2431                                         function = "qup17";
2432                                 };
2433
2434                                 config {
2435                                         pins = "gpio52", "gpio53";
2436                                         drive-strength = <2>;
2437                                         bias-disable;
2438                                 };
2439                         };
2440
2441                         qup_i2c18_default: qup-i2c18-default {
2442                                 mux {
2443                                         pins = "gpio56", "gpio57";
2444                                         function = "qup18";
2445                                 };
2446
2447                                 config {
2448                                         pins = "gpio56", "gpio57";
2449                                         drive-strength = <2>;
2450                                         bias-disable;
2451                                 };
2452                         };
2453
2454                         qup_i2c19_default: qup-i2c19-default {
2455                                 mux {
2456                                         pins = "gpio0", "gpio1";
2457                                         function = "qup19";
2458                                 };
2459
2460                                 config {
2461                                         pins = "gpio0", "gpio1";
2462                                         drive-strength = <2>;
2463                                         bias-disable;
2464                                 };
2465                         };
2466
2467                         qup_spi0_default: qup-spi0-default {
2468                                 mux {
2469                                         pins = "gpio28", "gpio29",
2470                                                "gpio30", "gpio31";
2471                                         function = "qup0";
2472                                 };
2473
2474                                 config {
2475                                         pins = "gpio28", "gpio29",
2476                                                "gpio30", "gpio31";
2477                                         drive-strength = <6>;
2478                                         bias-disable;
2479                                 };
2480                         };
2481
2482                         qup_spi1_default: qup-spi1-default {
2483                                 mux {
2484                                         pins = "gpio4", "gpio5",
2485                                                "gpio6", "gpio7";
2486                                         function = "qup1";
2487                                 };
2488
2489                                 config {
2490                                         pins = "gpio4", "gpio5",
2491                                                "gpio6", "gpio7";
2492                                         drive-strength = <6>;
2493                                         bias-disable;
2494                                 };
2495                         };
2496
2497                         qup_spi2_default: qup-spi2-default {
2498                                 mux {
2499                                         pins = "gpio115", "gpio116",
2500                                                "gpio117", "gpio118";
2501                                         function = "qup2";
2502                                 };
2503
2504                                 config {
2505                                         pins = "gpio115", "gpio116",
2506                                                "gpio117", "gpio118";
2507                                         drive-strength = <6>;
2508                                         bias-disable;
2509                                 };
2510                         };
2511
2512                         qup_spi3_default: qup-spi3-default {
2513                                 mux {
2514                                         pins = "gpio119", "gpio120",
2515                                                "gpio121", "gpio122";
2516                                         function = "qup3";
2517                                 };
2518
2519                                 config {
2520                                         pins = "gpio119", "gpio120",
2521                                                "gpio121", "gpio122";
2522                                         drive-strength = <6>;
2523                                         bias-disable;
2524                                 };
2525                         };
2526
2527                         qup_spi4_default: qup-spi4-default {
2528                                 mux {
2529                                         pins = "gpio8", "gpio9",
2530                                                "gpio10", "gpio11";
2531                                         function = "qup4";
2532                                 };
2533
2534                                 config {
2535                                         pins = "gpio8", "gpio9",
2536                                                "gpio10", "gpio11";
2537                                         drive-strength = <6>;
2538                                         bias-disable;
2539                                 };
2540                         };
2541
2542                         qup_spi5_default: qup-spi5-default {
2543                                 mux {
2544                                         pins = "gpio12", "gpio13",
2545                                                "gpio14", "gpio15";
2546                                         function = "qup5";
2547                                 };
2548
2549                                 config {
2550                                         pins = "gpio12", "gpio13",
2551                                                "gpio14", "gpio15";
2552                                         drive-strength = <6>;
2553                                         bias-disable;
2554                                 };
2555                         };
2556
2557                         qup_spi6_default: qup-spi6-default {
2558                                 mux {
2559                                         pins = "gpio16", "gpio17",
2560                                                "gpio18", "gpio19";
2561                                         function = "qup6";
2562                                 };
2563
2564                                 config {
2565                                         pins = "gpio16", "gpio17",
2566                                                "gpio18", "gpio19";
2567                                         drive-strength = <6>;
2568                                         bias-disable;
2569                                 };
2570                         };
2571
2572                         qup_spi7_default: qup-spi7-default {
2573                                 mux {
2574                                         pins = "gpio20", "gpio21",
2575                                                "gpio22", "gpio23";
2576                                         function = "qup7";
2577                                 };
2578
2579                                 config {
2580                                         pins = "gpio20", "gpio21",
2581                                                "gpio22", "gpio23";
2582                                         drive-strength = <6>;
2583                                         bias-disable;
2584                                 };
2585                         };
2586
2587                         qup_spi8_default: qup-spi8-default {
2588                                 mux {
2589                                         pins = "gpio24", "gpio25",
2590                                                "gpio26", "gpio27";
2591                                         function = "qup8";
2592                                 };
2593
2594                                 config {
2595                                         pins = "gpio24", "gpio25",
2596                                                "gpio26", "gpio27";
2597                                         drive-strength = <6>;
2598                                         bias-disable;
2599                                 };
2600                         };
2601
2602                         qup_spi9_default: qup-spi9-default {
2603                                 mux {
2604                                         pins = "gpio125", "gpio126",
2605                                                "gpio127", "gpio128";
2606                                         function = "qup9";
2607                                 };
2608
2609                                 config {
2610                                         pins = "gpio125", "gpio126",
2611                                                "gpio127", "gpio128";
2612                                         drive-strength = <6>;
2613                                         bias-disable;
2614                                 };
2615                         };
2616
2617                         qup_spi10_default: qup-spi10-default {
2618                                 mux {
2619                                         pins = "gpio129", "gpio130",
2620                                                "gpio131", "gpio132";
2621                                         function = "qup10";
2622                                 };
2623
2624                                 config {
2625                                         pins = "gpio129", "gpio130",
2626                                                "gpio131", "gpio132";
2627                                         drive-strength = <6>;
2628                                         bias-disable;
2629                                 };
2630                         };
2631
2632                         qup_spi11_default: qup-spi11-default {
2633                                 mux {
2634                                         pins = "gpio60", "gpio61",
2635                                                "gpio62", "gpio63";
2636                                         function = "qup11";
2637                                 };
2638
2639                                 config {
2640                                         pins = "gpio60", "gpio61",
2641                                                "gpio62", "gpio63";
2642                                         drive-strength = <6>;
2643                                         bias-disable;
2644                                 };
2645                         };
2646
2647                         qup_spi12_default: qup-spi12-default {
2648                                 mux {
2649                                         pins = "gpio32", "gpio33",
2650                                                "gpio34", "gpio35";
2651                                         function = "qup12";
2652                                 };
2653
2654                                 config {
2655                                         pins = "gpio32", "gpio33",
2656                                                "gpio34", "gpio35";
2657                                         drive-strength = <6>;
2658                                         bias-disable;
2659                                 };
2660                         };
2661
2662                         qup_spi13_default: qup-spi13-default {
2663                                 mux {
2664                                         pins = "gpio36", "gpio37",
2665                                                "gpio38", "gpio39";
2666                                         function = "qup13";
2667                                 };
2668
2669                                 config {
2670                                         pins = "gpio36", "gpio37",
2671                                                "gpio38", "gpio39";
2672                                         drive-strength = <6>;
2673                                         bias-disable;
2674                                 };
2675                         };
2676
2677                         qup_spi14_default: qup-spi14-default {
2678                                 mux {
2679                                         pins = "gpio40", "gpio41",
2680                                                "gpio42", "gpio43";
2681                                         function = "qup14";
2682                                 };
2683
2684                                 config {
2685                                         pins = "gpio40", "gpio41",
2686                                                "gpio42", "gpio43";
2687                                         drive-strength = <6>;
2688                                         bias-disable;
2689                                 };
2690                         };
2691
2692                         qup_spi15_default: qup-spi15-default {
2693                                 mux {
2694                                         pins = "gpio44", "gpio45",
2695                                                "gpio46", "gpio47";
2696                                         function = "qup15";
2697                                 };
2698
2699                                 config {
2700                                         pins = "gpio44", "gpio45",
2701                                                "gpio46", "gpio47";
2702                                         drive-strength = <6>;
2703                                         bias-disable;
2704                                 };
2705                         };
2706
2707                         qup_spi16_default: qup-spi16-default {
2708                                 mux {
2709                                         pins = "gpio48", "gpio49",
2710                                                "gpio50", "gpio51";
2711                                         function = "qup16";
2712                                 };
2713
2714                                 config {
2715                                         pins = "gpio48", "gpio49",
2716                                                "gpio50", "gpio51";
2717                                         drive-strength = <6>;
2718                                         bias-disable;
2719                                 };
2720                         };
2721
2722                         qup_spi17_default: qup-spi17-default {
2723                                 mux {
2724                                         pins = "gpio52", "gpio53",
2725                                                "gpio54", "gpio55";
2726                                         function = "qup17";
2727                                 };
2728
2729                                 config {
2730                                         pins = "gpio52", "gpio53",
2731                                                "gpio54", "gpio55";
2732                                         drive-strength = <6>;
2733                                         bias-disable;
2734                                 };
2735                         };
2736
2737                         qup_spi18_default: qup-spi18-default {
2738                                 mux {
2739                                         pins = "gpio56", "gpio57",
2740                                                "gpio58", "gpio59";
2741                                         function = "qup18";
2742                                 };
2743
2744                                 config {
2745                                         pins = "gpio56", "gpio57",
2746                                                "gpio58", "gpio59";
2747                                         drive-strength = <6>;
2748                                         bias-disable;
2749                                 };
2750                         };
2751
2752                         qup_spi19_default: qup-spi19-default {
2753                                 mux {
2754                                         pins = "gpio0", "gpio1",
2755                                                "gpio2", "gpio3";
2756                                         function = "qup19";
2757                                 };
2758
2759                                 config {
2760                                         pins = "gpio0", "gpio1",
2761                                                "gpio2", "gpio3";
2762                                         drive-strength = <6>;
2763                                         bias-disable;
2764                                 };
2765                         };
2766
2767                         qup_uart2_default: qup-uart2-default {
2768                                 mux {
2769                                         pins = "gpio117", "gpio118";
2770                                         function = "qup2";
2771                                 };
2772                         };
2773
2774                         qup_uart6_default: qup-uart6-default {
2775                                 mux {
2776                                         pins = "gpio16", "gpio17",
2777                                                 "gpio18", "gpio19";
2778                                         function = "qup6";
2779                                 };
2780                         };
2781
2782                         qup_uart12_default: qup-uart12-default {
2783                                 mux {
2784                                         pins = "gpio34", "gpio35";
2785                                         function = "qup12";
2786                                 };
2787                         };
2788
2789                         qup_uart17_default: qup-uart17-default {
2790                                 mux {
2791                                         pins = "gpio52", "gpio53",
2792                                                 "gpio54", "gpio55";
2793                                         function = "qup17";
2794                                 };
2795                         };
2796
2797                         qup_uart18_default: qup-uart18-default {
2798                                 mux {
2799                                         pins = "gpio58", "gpio59";
2800                                         function = "qup18";
2801                                 };
2802                         };
2803                 };
2804
2805                 apps_smmu: iommu@15000000 {
2806                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2807                         reg = <0 0x15000000 0 0x100000>;
2808                         #iommu-cells = <2>;
2809                         #global-interrupts = <2>;
2810                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2811                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2812                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2813                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2814                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2815                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2816                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2817                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2818                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2819                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2820                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2821                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2822                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2823                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2824                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2825                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2826                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2827                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2828                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2829                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2830                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2831                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2832                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2833                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2834                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2835                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2836                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2837                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2838                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2839                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2840                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2841                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2842                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2843                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2844                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2845                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2846                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2847                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2848                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2849                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2850                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2851                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2852                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2853                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2854                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2855                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2856                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2857                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2858                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2859                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2860                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2861                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2862                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2863                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2864                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2865                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2866                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2867                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2868                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2869                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2870                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2871                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2872                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2873                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2874                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2875                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2876                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2877                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2878                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2879                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2880                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2881                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2882                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2883                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2884                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2885                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2886                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2887                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2888                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2889                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2890                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2891                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2892                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2893                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2894                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2895                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2896                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2897                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2898                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2899                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2900                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2901                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2902                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2903                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2904                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2905                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2906                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
2907                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
2908                 };
2909
2910                 adsp: remoteproc@17300000 {
2911                         compatible = "qcom,sm8250-adsp-pas";
2912                         reg = <0 0x17300000 0 0x100>;
2913
2914                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2915                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2916                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2917                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2918                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2919                         interrupt-names = "wdog", "fatal", "ready",
2920                                           "handover", "stop-ack";
2921
2922                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2923                         clock-names = "xo";
2924
2925                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2926                                         <&rpmhpd SM8250_LCX>,
2927                                         <&rpmhpd SM8250_LMX>;
2928                         power-domain-names = "load_state", "lcx", "lmx";
2929
2930                         memory-region = <&adsp_mem>;
2931
2932                         qcom,smem-states = <&smp2p_adsp_out 0>;
2933                         qcom,smem-state-names = "stop";
2934
2935                         status = "disabled";
2936
2937                         glink-edge {
2938                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2939                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2940                                                              IRQ_TYPE_EDGE_RISING>;
2941                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2942                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2943
2944                                 label = "lpass";
2945                                 qcom,remote-pid = <2>;
2946
2947                                 apr {
2948                                         compatible = "qcom,apr-v2";
2949                                         qcom,glink-channels = "apr_audio_svc";
2950                                         qcom,apr-domain = <APR_DOMAIN_ADSP>;
2951                                         #address-cells = <1>;
2952                                         #size-cells = <0>;
2953
2954                                         apr-service@3 {
2955                                                 reg = <APR_SVC_ADSP_CORE>;
2956                                                 compatible = "qcom,q6core";
2957                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
2958                                         };
2959
2960                                         q6afe: apr-service@4 {
2961                                                 compatible = "qcom,q6afe";
2962                                                 reg = <APR_SVC_AFE>;
2963                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
2964                                                 q6afedai: dais {
2965                                                         compatible = "qcom,q6afe-dais";
2966                                                         #address-cells = <1>;
2967                                                         #size-cells = <0>;
2968                                                         #sound-dai-cells = <1>;
2969                                                 };
2970
2971                                                 q6afecc: cc {
2972                                                         compatible = "qcom,q6afe-clocks";
2973                                                         #clock-cells = <2>;
2974                                                 };
2975                                         };
2976
2977                                         q6asm: apr-service@7 {
2978                                                 compatible = "qcom,q6asm";
2979                                                 reg = <APR_SVC_ASM>;
2980                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
2981                                                 q6asmdai: dais {
2982                                                         compatible = "qcom,q6asm-dais";
2983                                                         #address-cells = <1>;
2984                                                         #size-cells = <0>;
2985                                                         #sound-dai-cells = <1>;
2986                                                         iommus = <&apps_smmu 0x1801 0x0>;
2987                                                 };
2988                                         };
2989
2990                                         q6adm: apr-service@8 {
2991                                                 compatible = "qcom,q6adm";
2992                                                 reg = <APR_SVC_ADM>;
2993                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
2994                                                 q6routing: routing {
2995                                                         compatible = "qcom,q6adm-routing";
2996                                                         #sound-dai-cells = <0>;
2997                                                 };
2998                                         };
2999                                 };
3000
3001                                 fastrpc {
3002                                         compatible = "qcom,fastrpc";
3003                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3004                                         label = "adsp";
3005                                         #address-cells = <1>;
3006                                         #size-cells = <0>;
3007
3008                                         compute-cb@3 {
3009                                                 compatible = "qcom,fastrpc-compute-cb";
3010                                                 reg = <3>;
3011                                                 iommus = <&apps_smmu 0x1803 0x0>;
3012                                         };
3013
3014                                         compute-cb@4 {
3015                                                 compatible = "qcom,fastrpc-compute-cb";
3016                                                 reg = <4>;
3017                                                 iommus = <&apps_smmu 0x1804 0x0>;
3018                                         };
3019
3020                                         compute-cb@5 {
3021                                                 compatible = "qcom,fastrpc-compute-cb";
3022                                                 reg = <5>;
3023                                                 iommus = <&apps_smmu 0x1805 0x0>;
3024                                         };
3025                                 };
3026                         };
3027                 };
3028
3029                 intc: interrupt-controller@17a00000 {
3030                         compatible = "arm,gic-v3";
3031                         #interrupt-cells = <3>;
3032                         interrupt-controller;
3033                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3034                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3035                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3036                 };
3037
3038                 watchdog@17c10000 {
3039                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3040                         reg = <0 0x17c10000 0 0x1000>;
3041                         clocks = <&sleep_clk>;
3042                 };
3043
3044                 timer@17c20000 {
3045                         #address-cells = <2>;
3046                         #size-cells = <2>;
3047                         ranges;
3048                         compatible = "arm,armv7-timer-mem";
3049                         reg = <0x0 0x17c20000 0x0 0x1000>;
3050                         clock-frequency = <19200000>;
3051
3052                         frame@17c21000 {
3053                                 frame-number = <0>;
3054                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3055                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3056                                 reg = <0x0 0x17c21000 0x0 0x1000>,
3057                                       <0x0 0x17c22000 0x0 0x1000>;
3058                         };
3059
3060                         frame@17c23000 {
3061                                 frame-number = <1>;
3062                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3063                                 reg = <0x0 0x17c23000 0x0 0x1000>;
3064                                 status = "disabled";
3065                         };
3066
3067                         frame@17c25000 {
3068                                 frame-number = <2>;
3069                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3070                                 reg = <0x0 0x17c25000 0x0 0x1000>;
3071                                 status = "disabled";
3072                         };
3073
3074                         frame@17c27000 {
3075                                 frame-number = <3>;
3076                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3077                                 reg = <0x0 0x17c27000 0x0 0x1000>;
3078                                 status = "disabled";
3079                         };
3080
3081                         frame@17c29000 {
3082                                 frame-number = <4>;
3083                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3084                                 reg = <0x0 0x17c29000 0x0 0x1000>;
3085                                 status = "disabled";
3086                         };
3087
3088                         frame@17c2b000 {
3089                                 frame-number = <5>;
3090                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3091                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
3092                                 status = "disabled";
3093                         };
3094
3095                         frame@17c2d000 {
3096                                 frame-number = <6>;
3097                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3098                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
3099                                 status = "disabled";
3100                         };
3101                 };
3102
3103                 apps_rsc: rsc@18200000 {
3104                         label = "apps_rsc";
3105                         compatible = "qcom,rpmh-rsc";
3106                         reg = <0x0 0x18200000 0x0 0x10000>,
3107                                 <0x0 0x18210000 0x0 0x10000>,
3108                                 <0x0 0x18220000 0x0 0x10000>;
3109                         reg-names = "drv-0", "drv-1", "drv-2";
3110                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3111                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3112                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3113                         qcom,tcs-offset = <0xd00>;
3114                         qcom,drv-id = <2>;
3115                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3116                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
3117
3118                         rpmhcc: clock-controller {
3119                                 compatible = "qcom,sm8250-rpmh-clk";
3120                                 #clock-cells = <1>;
3121                                 clock-names = "xo";
3122                                 clocks = <&xo_board>;
3123                         };
3124
3125                         rpmhpd: power-controller {
3126                                 compatible = "qcom,sm8250-rpmhpd";
3127                                 #power-domain-cells = <1>;
3128                                 operating-points-v2 = <&rpmhpd_opp_table>;
3129
3130                                 rpmhpd_opp_table: opp-table {
3131                                         compatible = "operating-points-v2";
3132
3133                                         rpmhpd_opp_ret: opp1 {
3134                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3135                                         };
3136
3137                                         rpmhpd_opp_min_svs: opp2 {
3138                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3139                                         };
3140
3141                                         rpmhpd_opp_low_svs: opp3 {
3142                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3143                                         };
3144
3145                                         rpmhpd_opp_svs: opp4 {
3146                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3147                                         };
3148
3149                                         rpmhpd_opp_svs_l1: opp5 {
3150                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3151                                         };
3152
3153                                         rpmhpd_opp_nom: opp6 {
3154                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3155                                         };
3156
3157                                         rpmhpd_opp_nom_l1: opp7 {
3158                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3159                                         };
3160
3161                                         rpmhpd_opp_nom_l2: opp8 {
3162                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3163                                         };
3164
3165                                         rpmhpd_opp_turbo: opp9 {
3166                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3167                                         };
3168
3169                                         rpmhpd_opp_turbo_l1: opp10 {
3170                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3171                                         };
3172                                 };
3173                         };
3174
3175                         apps_bcm_voter: bcm_voter {
3176                                 compatible = "qcom,bcm-voter";
3177                         };
3178                 };
3179
3180                 epss_l3: interconnect@18591000 {
3181                         compatible = "qcom,sm8250-epss-l3";
3182                         reg = <0 0x18590000 0 0x1000>;
3183
3184                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3185                         clock-names = "xo", "alternate";
3186
3187                         #interconnect-cells = <1>;
3188                 };
3189
3190                 cpufreq_hw: cpufreq@18591000 {
3191                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3192                         reg = <0 0x18591000 0 0x1000>,
3193                               <0 0x18592000 0 0x1000>,
3194                               <0 0x18593000 0 0x1000>;
3195                         reg-names = "freq-domain0", "freq-domain1",
3196                                     "freq-domain2";
3197
3198                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3199                         clock-names = "xo", "alternate";
3200
3201                         #freq-domain-cells = <1>;
3202                 };
3203         };
3204
3205         timer {
3206                 compatible = "arm,armv8-timer";
3207                 interrupts = <GIC_PPI 13
3208                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3209                              <GIC_PPI 14
3210                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3211                              <GIC_PPI 11
3212                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3213                              <GIC_PPI 12
3214                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3215         };
3216
3217         thermal-zones {
3218                 cpu0-thermal {
3219                         polling-delay-passive = <250>;
3220                         polling-delay = <1000>;
3221
3222                         thermal-sensors = <&tsens0 1>;
3223
3224                         trips {
3225                                 cpu0_alert0: trip-point0 {
3226                                         temperature = <90000>;
3227                                         hysteresis = <2000>;
3228                                         type = "passive";
3229                                 };
3230
3231                                 cpu0_alert1: trip-point1 {
3232                                         temperature = <95000>;
3233                                         hysteresis = <2000>;
3234                                         type = "passive";
3235                                 };
3236
3237                                 cpu0_crit: cpu_crit {
3238                                         temperature = <110000>;
3239                                         hysteresis = <1000>;
3240                                         type = "critical";
3241                                 };
3242                         };
3243
3244                         cooling-maps {
3245                                 map0 {
3246                                         trip = <&cpu0_alert0>;
3247                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3248                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3249                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3250                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3251                                 };
3252                                 map1 {
3253                                         trip = <&cpu0_alert1>;
3254                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3255                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3256                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3257                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3258                                 };
3259                         };
3260                 };
3261
3262                 cpu1-thermal {
3263                         polling-delay-passive = <250>;
3264                         polling-delay = <1000>;
3265
3266                         thermal-sensors = <&tsens0 2>;
3267
3268                         trips {
3269                                 cpu1_alert0: trip-point0 {
3270                                         temperature = <90000>;
3271                                         hysteresis = <2000>;
3272                                         type = "passive";
3273                                 };
3274
3275                                 cpu1_alert1: trip-point1 {
3276                                         temperature = <95000>;
3277                                         hysteresis = <2000>;
3278                                         type = "passive";
3279                                 };
3280
3281                                 cpu1_crit: cpu_crit {
3282                                         temperature = <110000>;
3283                                         hysteresis = <1000>;
3284                                         type = "critical";
3285                                 };
3286                         };
3287
3288                         cooling-maps {
3289                                 map0 {
3290                                         trip = <&cpu1_alert0>;
3291                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3292                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3293                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3294                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3295                                 };
3296                                 map1 {
3297                                         trip = <&cpu1_alert1>;
3298                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3299                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3300                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3301                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3302                                 };
3303                         };
3304                 };
3305
3306                 cpu2-thermal {
3307                         polling-delay-passive = <250>;
3308                         polling-delay = <1000>;
3309
3310                         thermal-sensors = <&tsens0 3>;
3311
3312                         trips {
3313                                 cpu2_alert0: trip-point0 {
3314                                         temperature = <90000>;
3315                                         hysteresis = <2000>;
3316                                         type = "passive";
3317                                 };
3318
3319                                 cpu2_alert1: trip-point1 {
3320                                         temperature = <95000>;
3321                                         hysteresis = <2000>;
3322                                         type = "passive";
3323                                 };
3324
3325                                 cpu2_crit: cpu_crit {
3326                                         temperature = <110000>;
3327                                         hysteresis = <1000>;
3328                                         type = "critical";
3329                                 };
3330                         };
3331
3332                         cooling-maps {
3333                                 map0 {
3334                                         trip = <&cpu2_alert0>;
3335                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3336                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3337                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3338                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3339                                 };
3340                                 map1 {
3341                                         trip = <&cpu2_alert1>;
3342                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3343                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3344                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3345                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3346                                 };
3347                         };
3348                 };
3349
3350                 cpu3-thermal {
3351                         polling-delay-passive = <250>;
3352                         polling-delay = <1000>;
3353
3354                         thermal-sensors = <&tsens0 4>;
3355
3356                         trips {
3357                                 cpu3_alert0: trip-point0 {
3358                                         temperature = <90000>;
3359                                         hysteresis = <2000>;
3360                                         type = "passive";
3361                                 };
3362
3363                                 cpu3_alert1: trip-point1 {
3364                                         temperature = <95000>;
3365                                         hysteresis = <2000>;
3366                                         type = "passive";
3367                                 };
3368
3369                                 cpu3_crit: cpu_crit {
3370                                         temperature = <110000>;
3371                                         hysteresis = <1000>;
3372                                         type = "critical";
3373                                 };
3374                         };
3375
3376                         cooling-maps {
3377                                 map0 {
3378                                         trip = <&cpu3_alert0>;
3379                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3380                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3381                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3382                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3383                                 };
3384                                 map1 {
3385                                         trip = <&cpu3_alert1>;
3386                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3387                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3388                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3389                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3390                                 };
3391                         };
3392                 };
3393
3394                 cpu4-top-thermal {
3395                         polling-delay-passive = <250>;
3396                         polling-delay = <1000>;
3397
3398                         thermal-sensors = <&tsens0 7>;
3399
3400                         trips {
3401                                 cpu4_top_alert0: trip-point0 {
3402                                         temperature = <90000>;
3403                                         hysteresis = <2000>;
3404                                         type = "passive";
3405                                 };
3406
3407                                 cpu4_top_alert1: trip-point1 {
3408                                         temperature = <95000>;
3409                                         hysteresis = <2000>;
3410                                         type = "passive";
3411                                 };
3412
3413                                 cpu4_top_crit: cpu_crit {
3414                                         temperature = <110000>;
3415                                         hysteresis = <1000>;
3416                                         type = "critical";
3417                                 };
3418                         };
3419
3420                         cooling-maps {
3421                                 map0 {
3422                                         trip = <&cpu4_top_alert0>;
3423                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3424                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3425                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3426                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3427                                 };
3428                                 map1 {
3429                                         trip = <&cpu4_top_alert1>;
3430                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3431                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3432                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3433                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3434                                 };
3435                         };
3436                 };
3437
3438                 cpu5-top-thermal {
3439                         polling-delay-passive = <250>;
3440                         polling-delay = <1000>;
3441
3442                         thermal-sensors = <&tsens0 8>;
3443
3444                         trips {
3445                                 cpu5_top_alert0: trip-point0 {
3446                                         temperature = <90000>;
3447                                         hysteresis = <2000>;
3448                                         type = "passive";
3449                                 };
3450
3451                                 cpu5_top_alert1: trip-point1 {
3452                                         temperature = <95000>;
3453                                         hysteresis = <2000>;
3454                                         type = "passive";
3455                                 };
3456
3457                                 cpu5_top_crit: cpu_crit {
3458                                         temperature = <110000>;
3459                                         hysteresis = <1000>;
3460                                         type = "critical";
3461                                 };
3462                         };
3463
3464                         cooling-maps {
3465                                 map0 {
3466                                         trip = <&cpu5_top_alert0>;
3467                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3468                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3469                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3470                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3471                                 };
3472                                 map1 {
3473                                         trip = <&cpu5_top_alert1>;
3474                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3475                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3476                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3477                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3478                                 };
3479                         };
3480                 };
3481
3482                 cpu6-top-thermal {
3483                         polling-delay-passive = <250>;
3484                         polling-delay = <1000>;
3485
3486                         thermal-sensors = <&tsens0 9>;
3487
3488                         trips {
3489                                 cpu6_top_alert0: trip-point0 {
3490                                         temperature = <90000>;
3491                                         hysteresis = <2000>;
3492                                         type = "passive";
3493                                 };
3494
3495                                 cpu6_top_alert1: trip-point1 {
3496                                         temperature = <95000>;
3497                                         hysteresis = <2000>;
3498                                         type = "passive";
3499                                 };
3500
3501                                 cpu6_top_crit: cpu_crit {
3502                                         temperature = <110000>;
3503                                         hysteresis = <1000>;
3504                                         type = "critical";
3505                                 };
3506                         };
3507
3508                         cooling-maps {
3509                                 map0 {
3510                                         trip = <&cpu6_top_alert0>;
3511                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3512                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3513                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3514                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3515                                 };
3516                                 map1 {
3517                                         trip = <&cpu6_top_alert1>;
3518                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3519                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3520                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3521                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3522                                 };
3523                         };
3524                 };
3525
3526                 cpu7-top-thermal {
3527                         polling-delay-passive = <250>;
3528                         polling-delay = <1000>;
3529
3530                         thermal-sensors = <&tsens0 10>;
3531
3532                         trips {
3533                                 cpu7_top_alert0: trip-point0 {
3534                                         temperature = <90000>;
3535                                         hysteresis = <2000>;
3536                                         type = "passive";
3537                                 };
3538
3539                                 cpu7_top_alert1: trip-point1 {
3540                                         temperature = <95000>;
3541                                         hysteresis = <2000>;
3542                                         type = "passive";
3543                                 };
3544
3545                                 cpu7_top_crit: cpu_crit {
3546                                         temperature = <110000>;
3547                                         hysteresis = <1000>;
3548                                         type = "critical";
3549                                 };
3550                         };
3551
3552                         cooling-maps {
3553                                 map0 {
3554                                         trip = <&cpu7_top_alert0>;
3555                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3556                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3557                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3558                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3559                                 };
3560                                 map1 {
3561                                         trip = <&cpu7_top_alert1>;
3562                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3563                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3564                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3565                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3566                                 };
3567                         };
3568                 };
3569
3570                 cpu4-bottom-thermal {
3571                         polling-delay-passive = <250>;
3572                         polling-delay = <1000>;
3573
3574                         thermal-sensors = <&tsens0 11>;
3575
3576                         trips {
3577                                 cpu4_bottom_alert0: trip-point0 {
3578                                         temperature = <90000>;
3579                                         hysteresis = <2000>;
3580                                         type = "passive";
3581                                 };
3582
3583                                 cpu4_bottom_alert1: trip-point1 {
3584                                         temperature = <95000>;
3585                                         hysteresis = <2000>;
3586                                         type = "passive";
3587                                 };
3588
3589                                 cpu4_bottom_crit: cpu_crit {
3590                                         temperature = <110000>;
3591                                         hysteresis = <1000>;
3592                                         type = "critical";
3593                                 };
3594                         };
3595
3596                         cooling-maps {
3597                                 map0 {
3598                                         trip = <&cpu4_bottom_alert0>;
3599                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3600                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3601                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3602                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3603                                 };
3604                                 map1 {
3605                                         trip = <&cpu4_bottom_alert1>;
3606                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3607                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3608                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3609                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3610                                 };
3611                         };
3612                 };
3613
3614                 cpu5-bottom-thermal {
3615                         polling-delay-passive = <250>;
3616                         polling-delay = <1000>;
3617
3618                         thermal-sensors = <&tsens0 12>;
3619
3620                         trips {
3621                                 cpu5_bottom_alert0: trip-point0 {
3622                                         temperature = <90000>;
3623                                         hysteresis = <2000>;
3624                                         type = "passive";
3625                                 };
3626
3627                                 cpu5_bottom_alert1: trip-point1 {
3628                                         temperature = <95000>;
3629                                         hysteresis = <2000>;
3630                                         type = "passive";
3631                                 };
3632
3633                                 cpu5_bottom_crit: cpu_crit {
3634                                         temperature = <110000>;
3635                                         hysteresis = <1000>;
3636                                         type = "critical";
3637                                 };
3638                         };
3639
3640                         cooling-maps {
3641                                 map0 {
3642                                         trip = <&cpu5_bottom_alert0>;
3643                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3644                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3646                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3647                                 };
3648                                 map1 {
3649                                         trip = <&cpu5_bottom_alert1>;
3650                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3651                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3652                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3653                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3654                                 };
3655                         };
3656                 };
3657
3658                 cpu6-bottom-thermal {
3659                         polling-delay-passive = <250>;
3660                         polling-delay = <1000>;
3661
3662                         thermal-sensors = <&tsens0 13>;
3663
3664                         trips {
3665                                 cpu6_bottom_alert0: trip-point0 {
3666                                         temperature = <90000>;
3667                                         hysteresis = <2000>;
3668                                         type = "passive";
3669                                 };
3670
3671                                 cpu6_bottom_alert1: trip-point1 {
3672                                         temperature = <95000>;
3673                                         hysteresis = <2000>;
3674                                         type = "passive";
3675                                 };
3676
3677                                 cpu6_bottom_crit: cpu_crit {
3678                                         temperature = <110000>;
3679                                         hysteresis = <1000>;
3680                                         type = "critical";
3681                                 };
3682                         };
3683
3684                         cooling-maps {
3685                                 map0 {
3686                                         trip = <&cpu6_bottom_alert0>;
3687                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3690                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3691                                 };
3692                                 map1 {
3693                                         trip = <&cpu6_bottom_alert1>;
3694                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3695                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3696                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3697                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3698                                 };
3699                         };
3700                 };
3701
3702                 cpu7-bottom-thermal {
3703                         polling-delay-passive = <250>;
3704                         polling-delay = <1000>;
3705
3706                         thermal-sensors = <&tsens0 14>;
3707
3708                         trips {
3709                                 cpu7_bottom_alert0: trip-point0 {
3710                                         temperature = <90000>;
3711                                         hysteresis = <2000>;
3712                                         type = "passive";
3713                                 };
3714
3715                                 cpu7_bottom_alert1: trip-point1 {
3716                                         temperature = <95000>;
3717                                         hysteresis = <2000>;
3718                                         type = "passive";
3719                                 };
3720
3721                                 cpu7_bottom_crit: cpu_crit {
3722                                         temperature = <110000>;
3723                                         hysteresis = <1000>;
3724                                         type = "critical";
3725                                 };
3726                         };
3727
3728                         cooling-maps {
3729                                 map0 {
3730                                         trip = <&cpu7_bottom_alert0>;
3731                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3732                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3733                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3734                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3735                                 };
3736                                 map1 {
3737                                         trip = <&cpu7_bottom_alert1>;
3738                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3739                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3740                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3741                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3742                                 };
3743                         };
3744                 };
3745
3746                 aoss0-thermal {
3747                         polling-delay-passive = <250>;
3748                         polling-delay = <1000>;
3749
3750                         thermal-sensors = <&tsens0 0>;
3751
3752                         trips {
3753                                 aoss0_alert0: trip-point0 {
3754                                         temperature = <90000>;
3755                                         hysteresis = <2000>;
3756                                         type = "hot";
3757                                 };
3758                         };
3759                 };
3760
3761                 cluster0-thermal {
3762                         polling-delay-passive = <250>;
3763                         polling-delay = <1000>;
3764
3765                         thermal-sensors = <&tsens0 5>;
3766
3767                         trips {
3768                                 cluster0_alert0: trip-point0 {
3769                                         temperature = <90000>;
3770                                         hysteresis = <2000>;
3771                                         type = "hot";
3772                                 };
3773                                 cluster0_crit: cluster0_crit {
3774                                         temperature = <110000>;
3775                                         hysteresis = <2000>;
3776                                         type = "critical";
3777                                 };
3778                         };
3779                 };
3780
3781                 cluster1-thermal {
3782                         polling-delay-passive = <250>;
3783                         polling-delay = <1000>;
3784
3785                         thermal-sensors = <&tsens0 6>;
3786
3787                         trips {
3788                                 cluster1_alert0: trip-point0 {
3789                                         temperature = <90000>;
3790                                         hysteresis = <2000>;
3791                                         type = "hot";
3792                                 };
3793                                 cluster1_crit: cluster1_crit {
3794                                         temperature = <110000>;
3795                                         hysteresis = <2000>;
3796                                         type = "critical";
3797                                 };
3798                         };
3799                 };
3800
3801                 gpu-thermal-top {
3802                         polling-delay-passive = <250>;
3803                         polling-delay = <1000>;
3804
3805                         thermal-sensors = <&tsens0 15>;
3806
3807                         trips {
3808                                 gpu1_alert0: trip-point0 {
3809                                         temperature = <90000>;
3810                                         hysteresis = <2000>;
3811                                         type = "hot";
3812                                 };
3813                         };
3814                 };
3815
3816                 aoss1-thermal {
3817                         polling-delay-passive = <250>;
3818                         polling-delay = <1000>;
3819
3820                         thermal-sensors = <&tsens1 0>;
3821
3822                         trips {
3823                                 aoss1_alert0: trip-point0 {
3824                                         temperature = <90000>;
3825                                         hysteresis = <2000>;
3826                                         type = "hot";
3827                                 };
3828                         };
3829                 };
3830
3831                 wlan-thermal {
3832                         polling-delay-passive = <250>;
3833                         polling-delay = <1000>;
3834
3835                         thermal-sensors = <&tsens1 1>;
3836
3837                         trips {
3838                                 wlan_alert0: trip-point0 {
3839                                         temperature = <90000>;
3840                                         hysteresis = <2000>;
3841                                         type = "hot";
3842                                 };
3843                         };
3844                 };
3845
3846                 video-thermal {
3847                         polling-delay-passive = <250>;
3848                         polling-delay = <1000>;
3849
3850                         thermal-sensors = <&tsens1 2>;
3851
3852                         trips {
3853                                 video_alert0: trip-point0 {
3854                                         temperature = <90000>;
3855                                         hysteresis = <2000>;
3856                                         type = "hot";
3857                                 };
3858                         };
3859                 };
3860
3861                 mem-thermal {
3862                         polling-delay-passive = <250>;
3863                         polling-delay = <1000>;
3864
3865                         thermal-sensors = <&tsens1 3>;
3866
3867                         trips {
3868                                 mem_alert0: trip-point0 {
3869                                         temperature = <90000>;
3870                                         hysteresis = <2000>;
3871                                         type = "hot";
3872                                 };
3873                         };
3874                 };
3875
3876                 q6-hvx-thermal {
3877                         polling-delay-passive = <250>;
3878                         polling-delay = <1000>;
3879
3880                         thermal-sensors = <&tsens1 4>;
3881
3882                         trips {
3883                                 q6_hvx_alert0: trip-point0 {
3884                                         temperature = <90000>;
3885                                         hysteresis = <2000>;
3886                                         type = "hot";
3887                                 };
3888                         };
3889                 };
3890
3891                 camera-thermal {
3892                         polling-delay-passive = <250>;
3893                         polling-delay = <1000>;
3894
3895                         thermal-sensors = <&tsens1 5>;
3896
3897                         trips {
3898                                 camera_alert0: trip-point0 {
3899                                         temperature = <90000>;
3900                                         hysteresis = <2000>;
3901                                         type = "hot";
3902                                 };
3903                         };
3904                 };
3905
3906                 compute-thermal {
3907                         polling-delay-passive = <250>;
3908                         polling-delay = <1000>;
3909
3910                         thermal-sensors = <&tsens1 6>;
3911
3912                         trips {
3913                                 compute_alert0: trip-point0 {
3914                                         temperature = <90000>;
3915                                         hysteresis = <2000>;
3916                                         type = "hot";
3917                                 };
3918                         };
3919                 };
3920
3921                 npu-thermal {
3922                         polling-delay-passive = <250>;
3923                         polling-delay = <1000>;
3924
3925                         thermal-sensors = <&tsens1 7>;
3926
3927                         trips {
3928                                 npu_alert0: trip-point0 {
3929                                         temperature = <90000>;
3930                                         hysteresis = <2000>;
3931                                         type = "hot";
3932                                 };
3933                         };
3934                 };
3935
3936                 gpu-thermal-bottom {
3937                         polling-delay-passive = <250>;
3938                         polling-delay = <1000>;
3939
3940                         thermal-sensors = <&tsens1 8>;
3941
3942                         trips {
3943                                 gpu2_alert0: trip-point0 {
3944                                         temperature = <90000>;
3945                                         hysteresis = <2000>;
3946                                         type = "hot";
3947                                 };
3948                         };
3949                 };
3950         };
3951 };