1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interconnect/qcom,sm8250.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-aoss-qmp.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,apr.h>
17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #include <dt-bindings/sound/qcom,q6afe.h>
19 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&intc>;
74 compatible = "fixed-clock";
76 clock-frequency = <38400000>;
77 clock-output-names = "xo_board";
80 sleep_clk: sleep-clk {
81 compatible = "fixed-clock";
82 clock-frequency = <32768>;
93 compatible = "qcom,kryo485";
95 enable-method = "psci";
96 capacity-dmips-mhz = <448>;
97 dynamic-power-coefficient = <205>;
98 next-level-cache = <&L2_0>;
99 qcom,freq-domain = <&cpufreq_hw 0>;
100 #cooling-cells = <2>;
102 compatible = "cache";
103 next-level-cache = <&L3_0>;
105 compatible = "cache";
112 compatible = "qcom,kryo485";
114 enable-method = "psci";
115 capacity-dmips-mhz = <448>;
116 dynamic-power-coefficient = <205>;
117 next-level-cache = <&L2_100>;
118 qcom,freq-domain = <&cpufreq_hw 0>;
119 #cooling-cells = <2>;
121 compatible = "cache";
122 next-level-cache = <&L3_0>;
128 compatible = "qcom,kryo485";
130 enable-method = "psci";
131 capacity-dmips-mhz = <448>;
132 dynamic-power-coefficient = <205>;
133 next-level-cache = <&L2_200>;
134 qcom,freq-domain = <&cpufreq_hw 0>;
135 #cooling-cells = <2>;
137 compatible = "cache";
138 next-level-cache = <&L3_0>;
144 compatible = "qcom,kryo485";
146 enable-method = "psci";
147 capacity-dmips-mhz = <448>;
148 dynamic-power-coefficient = <205>;
149 next-level-cache = <&L2_300>;
150 qcom,freq-domain = <&cpufreq_hw 0>;
151 #cooling-cells = <2>;
153 compatible = "cache";
154 next-level-cache = <&L3_0>;
160 compatible = "qcom,kryo485";
162 enable-method = "psci";
163 capacity-dmips-mhz = <1024>;
164 dynamic-power-coefficient = <379>;
165 next-level-cache = <&L2_400>;
166 qcom,freq-domain = <&cpufreq_hw 1>;
167 #cooling-cells = <2>;
169 compatible = "cache";
170 next-level-cache = <&L3_0>;
176 compatible = "qcom,kryo485";
178 enable-method = "psci";
179 capacity-dmips-mhz = <1024>;
180 dynamic-power-coefficient = <379>;
181 next-level-cache = <&L2_500>;
182 qcom,freq-domain = <&cpufreq_hw 1>;
183 #cooling-cells = <2>;
185 compatible = "cache";
186 next-level-cache = <&L3_0>;
193 compatible = "qcom,kryo485";
195 enable-method = "psci";
196 capacity-dmips-mhz = <1024>;
197 dynamic-power-coefficient = <379>;
198 next-level-cache = <&L2_600>;
199 qcom,freq-domain = <&cpufreq_hw 1>;
200 #cooling-cells = <2>;
202 compatible = "cache";
203 next-level-cache = <&L3_0>;
209 compatible = "qcom,kryo485";
211 enable-method = "psci";
212 capacity-dmips-mhz = <1024>;
213 dynamic-power-coefficient = <444>;
214 next-level-cache = <&L2_700>;
215 qcom,freq-domain = <&cpufreq_hw 2>;
216 #cooling-cells = <2>;
218 compatible = "cache";
219 next-level-cache = <&L3_0>;
262 compatible = "qcom,scm";
268 device_type = "memory";
269 /* We expect the bootloader to fill in the size */
270 reg = <0x0 0x80000000 0x0 0x0>;
274 compatible = "regulator-fixed-domain";
275 power-domains = <&rpmhpd SM8250_MMCX>;
276 required-opps = <&rpmhpd_opp_low_svs>;
277 regulator-name = "MMCX";
281 compatible = "arm,armv8-pmuv3";
282 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
286 compatible = "arm,psci-1.0";
291 #address-cells = <2>;
295 hyp_mem: memory@80000000 {
296 reg = <0x0 0x80000000 0x0 0x600000>;
300 xbl_aop_mem: memory@80700000 {
301 reg = <0x0 0x80700000 0x0 0x160000>;
305 cmd_db: memory@80860000 {
306 compatible = "qcom,cmd-db";
307 reg = <0x0 0x80860000 0x0 0x20000>;
311 smem_mem: memory@80900000 {
312 reg = <0x0 0x80900000 0x0 0x200000>;
316 removed_mem: memory@80b00000 {
317 reg = <0x0 0x80b00000 0x0 0x5300000>;
321 camera_mem: memory@86200000 {
322 reg = <0x0 0x86200000 0x0 0x500000>;
326 wlan_mem: memory@86700000 {
327 reg = <0x0 0x86700000 0x0 0x100000>;
331 ipa_fw_mem: memory@86800000 {
332 reg = <0x0 0x86800000 0x0 0x10000>;
336 ipa_gsi_mem: memory@86810000 {
337 reg = <0x0 0x86810000 0x0 0xa000>;
341 gpu_mem: memory@8681a000 {
342 reg = <0x0 0x8681a000 0x0 0x2000>;
346 npu_mem: memory@86900000 {
347 reg = <0x0 0x86900000 0x0 0x500000>;
351 video_mem: memory@86e00000 {
352 reg = <0x0 0x86e00000 0x0 0x500000>;
356 cvp_mem: memory@87300000 {
357 reg = <0x0 0x87300000 0x0 0x500000>;
361 cdsp_mem: memory@87800000 {
362 reg = <0x0 0x87800000 0x0 0x1400000>;
366 slpi_mem: memory@88c00000 {
367 reg = <0x0 0x88c00000 0x0 0x1500000>;
371 adsp_mem: memory@8a100000 {
372 reg = <0x0 0x8a100000 0x0 0x1d00000>;
376 spss_mem: memory@8be00000 {
377 reg = <0x0 0x8be00000 0x0 0x100000>;
381 cdsp_secure_heap: memory@8bf00000 {
382 reg = <0x0 0x8bf00000 0x0 0x4600000>;
388 compatible = "qcom,smem";
389 memory-region = <&smem_mem>;
390 hwlocks = <&tcsr_mutex 3>;
394 compatible = "qcom,smp2p";
395 qcom,smem = <443>, <429>;
396 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
397 IPCC_MPROC_SIGNAL_SMP2P
398 IRQ_TYPE_EDGE_RISING>;
399 mboxes = <&ipcc IPCC_CLIENT_LPASS
400 IPCC_MPROC_SIGNAL_SMP2P>;
402 qcom,local-pid = <0>;
403 qcom,remote-pid = <2>;
405 smp2p_adsp_out: master-kernel {
406 qcom,entry-name = "master-kernel";
407 #qcom,smem-state-cells = <1>;
410 smp2p_adsp_in: slave-kernel {
411 qcom,entry-name = "slave-kernel";
412 interrupt-controller;
413 #interrupt-cells = <2>;
418 compatible = "qcom,smp2p";
419 qcom,smem = <94>, <432>;
420 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
421 IPCC_MPROC_SIGNAL_SMP2P
422 IRQ_TYPE_EDGE_RISING>;
423 mboxes = <&ipcc IPCC_CLIENT_CDSP
424 IPCC_MPROC_SIGNAL_SMP2P>;
426 qcom,local-pid = <0>;
427 qcom,remote-pid = <5>;
429 smp2p_cdsp_out: master-kernel {
430 qcom,entry-name = "master-kernel";
431 #qcom,smem-state-cells = <1>;
434 smp2p_cdsp_in: slave-kernel {
435 qcom,entry-name = "slave-kernel";
436 interrupt-controller;
437 #interrupt-cells = <2>;
442 compatible = "qcom,smp2p";
443 qcom,smem = <481>, <430>;
444 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
445 IPCC_MPROC_SIGNAL_SMP2P
446 IRQ_TYPE_EDGE_RISING>;
447 mboxes = <&ipcc IPCC_CLIENT_SLPI
448 IPCC_MPROC_SIGNAL_SMP2P>;
450 qcom,local-pid = <0>;
451 qcom,remote-pid = <3>;
453 smp2p_slpi_out: master-kernel {
454 qcom,entry-name = "master-kernel";
455 #qcom,smem-state-cells = <1>;
458 smp2p_slpi_in: slave-kernel {
459 qcom,entry-name = "slave-kernel";
460 interrupt-controller;
461 #interrupt-cells = <2>;
466 #address-cells = <2>;
468 ranges = <0 0 0 0 0x10 0>;
469 dma-ranges = <0 0 0 0 0x10 0>;
470 compatible = "simple-bus";
472 gcc: clock-controller@100000 {
473 compatible = "qcom,gcc-sm8250";
474 reg = <0x0 0x00100000 0x0 0x1f0000>;
477 #power-domain-cells = <1>;
478 clock-names = "bi_tcxo",
481 clocks = <&rpmhcc RPMH_CXO_CLK>,
482 <&rpmhcc RPMH_CXO_CLK_A>,
486 ipcc: mailbox@408000 {
487 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
488 reg = <0 0x00408000 0 0x1000>;
489 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
490 interrupt-controller;
491 #interrupt-cells = <3>;
496 compatible = "qcom,prng-ee";
497 reg = <0 0x00793000 0 0x1000>;
498 clocks = <&gcc GCC_PRNG_AHB_CLK>;
499 clock-names = "core";
502 qup_opp_table: qup-opp-table {
503 compatible = "operating-points-v2";
506 opp-hz = /bits/ 64 <50000000>;
507 required-opps = <&rpmhpd_opp_min_svs>;
511 opp-hz = /bits/ 64 <75000000>;
512 required-opps = <&rpmhpd_opp_low_svs>;
516 opp-hz = /bits/ 64 <120000000>;
517 required-opps = <&rpmhpd_opp_svs>;
521 qupv3_id_2: geniqup@8c0000 {
522 compatible = "qcom,geni-se-qup";
523 reg = <0x0 0x008c0000 0x0 0x6000>;
524 clock-names = "m-ahb", "s-ahb";
525 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
526 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
527 #address-cells = <2>;
529 iommus = <&apps_smmu 0x63 0x0>;
534 compatible = "qcom,geni-i2c";
535 reg = <0 0x00880000 0 0x4000>;
537 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&qup_i2c14_default>;
540 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <1>;
547 compatible = "qcom,geni-spi";
548 reg = <0 0x00880000 0 0x4000>;
550 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&qup_spi14_default>;
553 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
556 power-domains = <&rpmhpd SM8250_CX>;
557 operating-points-v2 = <&qup_opp_table>;
562 compatible = "qcom,geni-i2c";
563 reg = <0 0x00884000 0 0x4000>;
565 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&qup_i2c15_default>;
568 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
569 #address-cells = <1>;
575 compatible = "qcom,geni-spi";
576 reg = <0 0x00884000 0 0x4000>;
578 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&qup_spi15_default>;
581 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
582 #address-cells = <1>;
584 power-domains = <&rpmhpd SM8250_CX>;
585 operating-points-v2 = <&qup_opp_table>;
590 compatible = "qcom,geni-i2c";
591 reg = <0 0x00888000 0 0x4000>;
593 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&qup_i2c16_default>;
596 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
597 #address-cells = <1>;
603 compatible = "qcom,geni-spi";
604 reg = <0 0x00888000 0 0x4000>;
606 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&qup_spi16_default>;
609 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells = <1>;
612 power-domains = <&rpmhpd SM8250_CX>;
613 operating-points-v2 = <&qup_opp_table>;
618 compatible = "qcom,geni-i2c";
619 reg = <0 0x0088c000 0 0x4000>;
621 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
622 pinctrl-names = "default";
623 pinctrl-0 = <&qup_i2c17_default>;
624 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
625 #address-cells = <1>;
631 compatible = "qcom,geni-spi";
632 reg = <0 0x0088c000 0 0x4000>;
634 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&qup_spi17_default>;
637 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
638 #address-cells = <1>;
640 power-domains = <&rpmhpd SM8250_CX>;
641 operating-points-v2 = <&qup_opp_table>;
645 uart17: serial@88c000 {
646 compatible = "qcom,geni-uart";
647 reg = <0 0x0088c000 0 0x4000>;
649 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&qup_uart17_default>;
652 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
653 power-domains = <&rpmhpd SM8250_CX>;
654 operating-points-v2 = <&qup_opp_table>;
659 compatible = "qcom,geni-i2c";
660 reg = <0 0x00890000 0 0x4000>;
662 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&qup_i2c18_default>;
665 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
666 #address-cells = <1>;
672 compatible = "qcom,geni-spi";
673 reg = <0 0x00890000 0 0x4000>;
675 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&qup_spi18_default>;
678 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
679 #address-cells = <1>;
681 power-domains = <&rpmhpd SM8250_CX>;
682 operating-points-v2 = <&qup_opp_table>;
686 uart18: serial@890000 {
687 compatible = "qcom,geni-uart";
688 reg = <0 0x00890000 0 0x4000>;
690 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&qup_uart18_default>;
693 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
694 power-domains = <&rpmhpd SM8250_CX>;
695 operating-points-v2 = <&qup_opp_table>;
700 compatible = "qcom,geni-i2c";
701 reg = <0 0x00894000 0 0x4000>;
703 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&qup_i2c19_default>;
706 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>;
713 compatible = "qcom,geni-spi";
714 reg = <0 0x00894000 0 0x4000>;
716 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&qup_spi19_default>;
719 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>;
722 power-domains = <&rpmhpd SM8250_CX>;
723 operating-points-v2 = <&qup_opp_table>;
728 qupv3_id_0: geniqup@9c0000 {
729 compatible = "qcom,geni-se-qup";
730 reg = <0x0 0x009c0000 0x0 0x6000>;
731 clock-names = "m-ahb", "s-ahb";
732 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
733 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
734 #address-cells = <2>;
736 iommus = <&apps_smmu 0x5a3 0x0>;
741 compatible = "qcom,geni-i2c";
742 reg = <0 0x00980000 0 0x4000>;
744 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&qup_i2c0_default>;
747 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
748 #address-cells = <1>;
754 compatible = "qcom,geni-spi";
755 reg = <0 0x00980000 0 0x4000>;
757 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&qup_spi0_default>;
760 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
761 #address-cells = <1>;
763 power-domains = <&rpmhpd SM8250_CX>;
764 operating-points-v2 = <&qup_opp_table>;
769 compatible = "qcom,geni-i2c";
770 reg = <0 0x00984000 0 0x4000>;
772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
773 pinctrl-names = "default";
774 pinctrl-0 = <&qup_i2c1_default>;
775 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
776 #address-cells = <1>;
782 compatible = "qcom,geni-spi";
783 reg = <0 0x00984000 0 0x4000>;
785 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
786 pinctrl-names = "default";
787 pinctrl-0 = <&qup_spi1_default>;
788 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
789 #address-cells = <1>;
791 power-domains = <&rpmhpd SM8250_CX>;
792 operating-points-v2 = <&qup_opp_table>;
797 compatible = "qcom,geni-i2c";
798 reg = <0 0x00988000 0 0x4000>;
800 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
801 pinctrl-names = "default";
802 pinctrl-0 = <&qup_i2c2_default>;
803 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
804 #address-cells = <1>;
810 compatible = "qcom,geni-spi";
811 reg = <0 0x00988000 0 0x4000>;
813 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&qup_spi2_default>;
816 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
817 #address-cells = <1>;
819 power-domains = <&rpmhpd SM8250_CX>;
820 operating-points-v2 = <&qup_opp_table>;
824 uart2: serial@988000 {
825 compatible = "qcom,geni-debug-uart";
826 reg = <0 0x00988000 0 0x4000>;
828 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&qup_uart2_default>;
831 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
832 power-domains = <&rpmhpd SM8250_CX>;
833 operating-points-v2 = <&qup_opp_table>;
838 compatible = "qcom,geni-i2c";
839 reg = <0 0x0098c000 0 0x4000>;
841 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
842 pinctrl-names = "default";
843 pinctrl-0 = <&qup_i2c3_default>;
844 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
845 #address-cells = <1>;
851 compatible = "qcom,geni-spi";
852 reg = <0 0x0098c000 0 0x4000>;
854 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
855 pinctrl-names = "default";
856 pinctrl-0 = <&qup_spi3_default>;
857 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
858 #address-cells = <1>;
860 power-domains = <&rpmhpd SM8250_CX>;
861 operating-points-v2 = <&qup_opp_table>;
866 compatible = "qcom,geni-i2c";
867 reg = <0 0x00990000 0 0x4000>;
869 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&qup_i2c4_default>;
872 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
873 #address-cells = <1>;
879 compatible = "qcom,geni-spi";
880 reg = <0 0x00990000 0 0x4000>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&qup_spi4_default>;
885 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
886 #address-cells = <1>;
888 power-domains = <&rpmhpd SM8250_CX>;
889 operating-points-v2 = <&qup_opp_table>;
894 compatible = "qcom,geni-i2c";
895 reg = <0 0x00994000 0 0x4000>;
897 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
898 pinctrl-names = "default";
899 pinctrl-0 = <&qup_i2c5_default>;
900 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
901 #address-cells = <1>;
907 compatible = "qcom,geni-spi";
908 reg = <0 0x00994000 0 0x4000>;
910 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&qup_spi5_default>;
913 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
914 #address-cells = <1>;
916 power-domains = <&rpmhpd SM8250_CX>;
917 operating-points-v2 = <&qup_opp_table>;
922 compatible = "qcom,geni-i2c";
923 reg = <0 0x00998000 0 0x4000>;
925 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
926 pinctrl-names = "default";
927 pinctrl-0 = <&qup_i2c6_default>;
928 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
929 #address-cells = <1>;
935 compatible = "qcom,geni-spi";
936 reg = <0 0x00998000 0 0x4000>;
938 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
939 pinctrl-names = "default";
940 pinctrl-0 = <&qup_spi6_default>;
941 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
942 #address-cells = <1>;
944 power-domains = <&rpmhpd SM8250_CX>;
945 operating-points-v2 = <&qup_opp_table>;
949 uart6: serial@998000 {
950 compatible = "qcom,geni-uart";
951 reg = <0 0x00998000 0 0x4000>;
953 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&qup_uart6_default>;
956 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
957 power-domains = <&rpmhpd SM8250_CX>;
958 operating-points-v2 = <&qup_opp_table>;
963 compatible = "qcom,geni-i2c";
964 reg = <0 0x0099c000 0 0x4000>;
966 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c7_default>;
969 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
970 #address-cells = <1>;
976 compatible = "qcom,geni-spi";
977 reg = <0 0x0099c000 0 0x4000>;
979 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
980 pinctrl-names = "default";
981 pinctrl-0 = <&qup_spi7_default>;
982 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
983 #address-cells = <1>;
985 power-domains = <&rpmhpd SM8250_CX>;
986 operating-points-v2 = <&qup_opp_table>;
991 qupv3_id_1: geniqup@ac0000 {
992 compatible = "qcom,geni-se-qup";
993 reg = <0x0 0x00ac0000 0x0 0x6000>;
994 clock-names = "m-ahb", "s-ahb";
995 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
996 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
997 #address-cells = <2>;
999 iommus = <&apps_smmu 0x43 0x0>;
1001 status = "disabled";
1004 compatible = "qcom,geni-i2c";
1005 reg = <0 0x00a80000 0 0x4000>;
1007 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c8_default>;
1010 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cells = <1>;
1013 status = "disabled";
1017 compatible = "qcom,geni-spi";
1018 reg = <0 0x00a80000 0 0x4000>;
1020 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1021 pinctrl-names = "default";
1022 pinctrl-0 = <&qup_spi8_default>;
1023 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1024 #address-cells = <1>;
1026 power-domains = <&rpmhpd SM8250_CX>;
1027 operating-points-v2 = <&qup_opp_table>;
1028 status = "disabled";
1032 compatible = "qcom,geni-i2c";
1033 reg = <0 0x00a84000 0 0x4000>;
1035 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1036 pinctrl-names = "default";
1037 pinctrl-0 = <&qup_i2c9_default>;
1038 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1039 #address-cells = <1>;
1041 status = "disabled";
1045 compatible = "qcom,geni-spi";
1046 reg = <0 0x00a84000 0 0x4000>;
1048 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&qup_spi9_default>;
1051 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1052 #address-cells = <1>;
1054 power-domains = <&rpmhpd SM8250_CX>;
1055 operating-points-v2 = <&qup_opp_table>;
1056 status = "disabled";
1060 compatible = "qcom,geni-i2c";
1061 reg = <0 0x00a88000 0 0x4000>;
1063 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1064 pinctrl-names = "default";
1065 pinctrl-0 = <&qup_i2c10_default>;
1066 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cells = <1>;
1069 status = "disabled";
1073 compatible = "qcom,geni-spi";
1074 reg = <0 0x00a88000 0 0x4000>;
1076 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&qup_spi10_default>;
1079 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cells = <1>;
1082 power-domains = <&rpmhpd SM8250_CX>;
1083 operating-points-v2 = <&qup_opp_table>;
1084 status = "disabled";
1088 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00a8c000 0 0x4000>;
1091 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c11_default>;
1094 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cells = <1>;
1097 status = "disabled";
1101 compatible = "qcom,geni-spi";
1102 reg = <0 0x00a8c000 0 0x4000>;
1104 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&qup_spi11_default>;
1107 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1108 #address-cells = <1>;
1110 power-domains = <&rpmhpd SM8250_CX>;
1111 operating-points-v2 = <&qup_opp_table>;
1112 status = "disabled";
1116 compatible = "qcom,geni-i2c";
1117 reg = <0 0x00a90000 0 0x4000>;
1119 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&qup_i2c12_default>;
1122 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1123 #address-cells = <1>;
1125 status = "disabled";
1129 compatible = "qcom,geni-spi";
1130 reg = <0 0x00a90000 0 0x4000>;
1132 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_spi12_default>;
1135 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1136 #address-cells = <1>;
1138 power-domains = <&rpmhpd SM8250_CX>;
1139 operating-points-v2 = <&qup_opp_table>;
1140 status = "disabled";
1143 uart12: serial@a90000 {
1144 compatible = "qcom,geni-debug-uart";
1145 reg = <0x0 0x00a90000 0x0 0x4000>;
1147 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_uart12_default>;
1150 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1151 power-domains = <&rpmhpd SM8250_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1153 status = "disabled";
1157 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00a94000 0 0x4000>;
1160 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c13_default>;
1163 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1164 #address-cells = <1>;
1166 status = "disabled";
1170 compatible = "qcom,geni-spi";
1171 reg = <0 0x00a94000 0 0x4000>;
1173 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&qup_spi13_default>;
1176 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1177 #address-cells = <1>;
1179 power-domains = <&rpmhpd SM8250_CX>;
1180 operating-points-v2 = <&qup_opp_table>;
1181 status = "disabled";
1185 config_noc: interconnect@1500000 {
1186 compatible = "qcom,sm8250-config-noc";
1187 reg = <0 0x01500000 0 0xa580>;
1188 #interconnect-cells = <1>;
1189 qcom,bcm-voters = <&apps_bcm_voter>;
1192 system_noc: interconnect@1620000 {
1193 compatible = "qcom,sm8250-system-noc";
1194 reg = <0 0x01620000 0 0x1c200>;
1195 #interconnect-cells = <1>;
1196 qcom,bcm-voters = <&apps_bcm_voter>;
1199 mc_virt: interconnect@163d000 {
1200 compatible = "qcom,sm8250-mc-virt";
1201 reg = <0 0x0163d000 0 0x1000>;
1202 #interconnect-cells = <1>;
1203 qcom,bcm-voters = <&apps_bcm_voter>;
1206 aggre1_noc: interconnect@16e0000 {
1207 compatible = "qcom,sm8250-aggre1-noc";
1208 reg = <0 0x016e0000 0 0x1f180>;
1209 #interconnect-cells = <1>;
1210 qcom,bcm-voters = <&apps_bcm_voter>;
1213 aggre2_noc: interconnect@1700000 {
1214 compatible = "qcom,sm8250-aggre2-noc";
1215 reg = <0 0x01700000 0 0x33000>;
1216 #interconnect-cells = <1>;
1217 qcom,bcm-voters = <&apps_bcm_voter>;
1220 compute_noc: interconnect@1733000 {
1221 compatible = "qcom,sm8250-compute-noc";
1222 reg = <0 0x01733000 0 0xa180>;
1223 #interconnect-cells = <1>;
1224 qcom,bcm-voters = <&apps_bcm_voter>;
1227 mmss_noc: interconnect@1740000 {
1228 compatible = "qcom,sm8250-mmss-noc";
1229 reg = <0 0x01740000 0 0x1f080>;
1230 #interconnect-cells = <1>;
1231 qcom,bcm-voters = <&apps_bcm_voter>;
1234 pcie0: pci@1c00000 {
1235 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1236 reg = <0 0x01c00000 0 0x3000>,
1237 <0 0x60000000 0 0xf1d>,
1238 <0 0x60000f20 0 0xa8>,
1239 <0 0x60001000 0 0x1000>,
1240 <0 0x60100000 0 0x100000>;
1241 reg-names = "parf", "dbi", "elbi", "atu", "config";
1242 device_type = "pci";
1243 linux,pci-domain = <0>;
1244 bus-range = <0x00 0xff>;
1247 #address-cells = <3>;
1250 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1251 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1253 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1254 interrupt-names = "msi";
1255 #interrupt-cells = <1>;
1256 interrupt-map-mask = <0 0 0 0x7>;
1257 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1258 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1259 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1260 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1262 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1263 <&gcc GCC_PCIE_0_AUX_CLK>,
1264 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1265 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1266 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1267 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1268 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1269 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1270 clock-names = "pipe",
1279 iommus = <&apps_smmu 0x1c00 0x7f>;
1280 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1281 <0x100 &apps_smmu 0x1c01 0x1>;
1283 resets = <&gcc GCC_PCIE_0_BCR>;
1284 reset-names = "pci";
1286 power-domains = <&gcc PCIE_0_GDSC>;
1288 phys = <&pcie0_lane>;
1289 phy-names = "pciephy";
1291 status = "disabled";
1294 pcie0_phy: phy@1c06000 {
1295 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1296 reg = <0 0x01c06000 0 0x1c0>;
1297 #address-cells = <2>;
1300 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1301 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1302 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1303 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1304 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1306 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1307 reset-names = "phy";
1309 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1310 assigned-clock-rates = <100000000>;
1312 status = "disabled";
1314 pcie0_lane: lanes@1c06200 {
1315 reg = <0 0x1c06200 0 0x170>, /* tx */
1316 <0 0x1c06400 0 0x200>, /* rx */
1317 <0 0x1c06800 0 0x1f0>, /* pcs */
1318 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1319 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1320 clock-names = "pipe0";
1323 clock-output-names = "pcie_0_pipe_clk";
1327 pcie1: pci@1c08000 {
1328 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1329 reg = <0 0x01c08000 0 0x3000>,
1330 <0 0x40000000 0 0xf1d>,
1331 <0 0x40000f20 0 0xa8>,
1332 <0 0x40001000 0 0x1000>,
1333 <0 0x40100000 0 0x100000>;
1334 reg-names = "parf", "dbi", "elbi", "atu", "config";
1335 device_type = "pci";
1336 linux,pci-domain = <1>;
1337 bus-range = <0x00 0xff>;
1340 #address-cells = <3>;
1343 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1344 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1346 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
1347 interrupt-names = "msi";
1348 #interrupt-cells = <1>;
1349 interrupt-map-mask = <0 0 0 0x7>;
1350 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1351 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1352 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1353 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1355 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1356 <&gcc GCC_PCIE_1_AUX_CLK>,
1357 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1358 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1359 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1360 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1361 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1362 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1363 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1364 clock-names = "pipe",
1374 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1375 assigned-clock-rates = <19200000>;
1377 iommus = <&apps_smmu 0x1c80 0x7f>;
1378 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1379 <0x100 &apps_smmu 0x1c81 0x1>;
1381 resets = <&gcc GCC_PCIE_1_BCR>;
1382 reset-names = "pci";
1384 power-domains = <&gcc PCIE_1_GDSC>;
1386 phys = <&pcie1_lane>;
1387 phy-names = "pciephy";
1389 status = "disabled";
1392 pcie1_phy: phy@1c0e000 {
1393 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1394 reg = <0 0x01c0e000 0 0x1c0>;
1395 #address-cells = <2>;
1398 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1399 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1400 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1401 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1402 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1404 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1405 reset-names = "phy";
1407 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1408 assigned-clock-rates = <100000000>;
1410 status = "disabled";
1412 pcie1_lane: lanes@1c0e200 {
1413 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1414 <0 0x1c0e400 0 0x200>, /* rx0 */
1415 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1416 <0 0x1c0e600 0 0x170>, /* tx1 */
1417 <0 0x1c0e800 0 0x200>, /* rx1 */
1418 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1419 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1420 clock-names = "pipe0";
1423 clock-output-names = "pcie_1_pipe_clk";
1427 pcie2: pci@1c10000 {
1428 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1429 reg = <0 0x01c10000 0 0x3000>,
1430 <0 0x64000000 0 0xf1d>,
1431 <0 0x64000f20 0 0xa8>,
1432 <0 0x64001000 0 0x1000>,
1433 <0 0x64100000 0 0x100000>;
1434 reg-names = "parf", "dbi", "elbi", "atu", "config";
1435 device_type = "pci";
1436 linux,pci-domain = <2>;
1437 bus-range = <0x00 0xff>;
1440 #address-cells = <3>;
1443 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
1444 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
1446 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
1447 interrupt-names = "msi";
1448 #interrupt-cells = <1>;
1449 interrupt-map-mask = <0 0 0 0x7>;
1450 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1451 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1452 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1453 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1455 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1456 <&gcc GCC_PCIE_2_AUX_CLK>,
1457 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1458 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1459 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1460 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1461 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1462 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1463 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1464 clock-names = "pipe",
1474 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1475 assigned-clock-rates = <19200000>;
1477 iommus = <&apps_smmu 0x1d00 0x7f>;
1478 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
1479 <0x100 &apps_smmu 0x1d01 0x1>;
1481 resets = <&gcc GCC_PCIE_2_BCR>;
1482 reset-names = "pci";
1484 power-domains = <&gcc PCIE_2_GDSC>;
1486 phys = <&pcie2_lane>;
1487 phy-names = "pciephy";
1489 status = "disabled";
1492 pcie2_phy: phy@1c16000 {
1493 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1494 reg = <0 0x1c16000 0 0x1c0>;
1495 #address-cells = <2>;
1498 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1499 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1500 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1501 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1502 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1504 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1505 reset-names = "phy";
1507 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1508 assigned-clock-rates = <100000000>;
1510 status = "disabled";
1512 pcie2_lane: lanes@1c0e200 {
1513 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1514 <0 0x1c16400 0 0x200>, /* rx0 */
1515 <0 0x1c16a00 0 0x1f0>, /* pcs */
1516 <0 0x1c16600 0 0x170>, /* tx1 */
1517 <0 0x1c16800 0 0x200>, /* rx1 */
1518 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1519 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1520 clock-names = "pipe0";
1523 clock-output-names = "pcie_2_pipe_clk";
1527 ufs_mem_hc: ufshc@1d84000 {
1528 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1530 reg = <0 0x01d84000 0 0x3000>;
1531 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1532 phys = <&ufs_mem_phy_lanes>;
1533 phy-names = "ufsphy";
1534 lanes-per-direction = <2>;
1536 resets = <&gcc GCC_UFS_PHY_BCR>;
1537 reset-names = "rst";
1539 power-domains = <&gcc UFS_PHY_GDSC>;
1541 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1549 "tx_lane0_sync_clk",
1550 "rx_lane0_sync_clk",
1551 "rx_lane1_sync_clk";
1553 <&gcc GCC_UFS_PHY_AXI_CLK>,
1554 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1555 <&gcc GCC_UFS_PHY_AHB_CLK>,
1556 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1557 <&rpmhcc RPMH_CXO_CLK>,
1558 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1559 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1560 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1562 <37500000 300000000>,
1565 <37500000 300000000>,
1571 status = "disabled";
1574 ufs_mem_phy: phy@1d87000 {
1575 compatible = "qcom,sm8250-qmp-ufs-phy";
1576 reg = <0 0x01d87000 0 0x1c0>;
1577 #address-cells = <2>;
1580 clock-names = "ref",
1582 clocks = <&rpmhcc RPMH_CXO_CLK>,
1583 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1585 resets = <&ufs_mem_hc 0>;
1586 reset-names = "ufsphy";
1587 status = "disabled";
1589 ufs_mem_phy_lanes: lanes@1d87400 {
1590 reg = <0 0x01d87400 0 0x108>,
1591 <0 0x01d87600 0 0x1e0>,
1592 <0 0x01d87c00 0 0x1dc>,
1593 <0 0x01d87800 0 0x108>,
1594 <0 0x01d87a00 0 0x1e0>;
1599 ipa_virt: interconnect@1e00000 {
1600 compatible = "qcom,sm8250-ipa-virt";
1601 reg = <0 0x01e00000 0 0x1000>;
1602 #interconnect-cells = <1>;
1603 qcom,bcm-voters = <&apps_bcm_voter>;
1606 tcsr_mutex: hwlock@1f40000 {
1607 compatible = "qcom,tcsr-mutex";
1608 reg = <0x0 0x01f40000 0x0 0x40000>;
1609 #hwlock-cells = <1>;
1612 wsamacro: codec@3240000 {
1613 compatible = "qcom,sm8250-lpass-wsa-macro";
1614 reg = <0 0x03240000 0 0x1000>;
1615 clocks = <&audiocc 1>,
1617 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1618 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1622 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1625 clock-frequency = <9600000>;
1626 clock-output-names = "mclk";
1627 #sound-dai-cells = <1>;
1629 pinctrl-names = "default";
1630 pinctrl-0 = <&wsa_swr_active>;
1633 swr0: soundwire-controller@3250000 {
1634 reg = <0 0x03250000 0 0x2000>;
1635 compatible = "qcom,soundwire-v1.5.1";
1636 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1637 clocks = <&wsamacro>;
1638 clock-names = "iface";
1640 qcom,din-ports = <2>;
1641 qcom,dout-ports = <6>;
1643 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1644 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1645 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1646 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1648 #sound-dai-cells = <1>;
1649 #address-cells = <2>;
1653 audiocc: clock-controller@3300000 {
1654 compatible = "qcom,sm8250-lpass-audiocc";
1655 reg = <0 0x03300000 0 0x30000>;
1657 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1658 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1659 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1660 clock-names = "core", "audio", "bus";
1663 vamacro: codec@3370000 {
1664 compatible = "qcom,sm8250-lpass-va-macro";
1665 reg = <0 0x03370000 0 0x1000>;
1666 clocks = <&aoncc 0>,
1667 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1668 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1670 clock-names = "mclk", "macro", "dcodec";
1673 clock-frequency = <9600000>;
1674 clock-output-names = "fsgen";
1675 #sound-dai-cells = <1>;
1678 aoncc: clock-controller@3380000 {
1679 compatible = "qcom,sm8250-lpass-aoncc";
1680 reg = <0 0x03380000 0 0x40000>;
1682 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1683 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1684 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1685 clock-names = "core", "audio", "bus";
1688 lpass_tlmm: pinctrl@33c0000{
1689 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1690 reg = <0 0x033c0000 0x0 0x20000>,
1691 <0 0x03550000 0x0 0x10000>;
1694 gpio-ranges = <&lpass_tlmm 0 0 14>;
1696 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1697 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1698 clock-names = "core", "audio";
1700 wsa_swr_active: wsa-swr-active-pins {
1703 function = "wsa_swr_clk";
1704 drive-strength = <2>;
1711 function = "wsa_swr_data";
1712 drive-strength = <2>;
1719 wsa_swr_sleep: wsa-swr-sleep-pins {
1722 function = "wsa_swr_clk";
1723 drive-strength = <2>;
1730 function = "wsa_swr_data";
1731 drive-strength = <2>;
1738 dmic01_active: dmic01-active-pins {
1741 function = "dmic1_clk";
1742 drive-strength = <8>;
1747 function = "dmic1_data";
1748 drive-strength = <8>;
1753 dmic01_sleep: dmic01-sleep-pins {
1756 function = "dmic1_clk";
1757 drive-strength = <2>;
1764 function = "dmic1_data";
1765 drive-strength = <2>;
1773 compatible = "qcom,adreno-650.2",
1775 #stream-id-cells = <16>;
1777 reg = <0 0x03d00000 0 0x40000>;
1778 reg-names = "kgsl_3d0_reg_memory";
1780 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1782 iommus = <&adreno_smmu 0 0x401>;
1784 operating-points-v2 = <&gpu_opp_table>;
1789 memory-region = <&gpu_mem>;
1792 /* note: downstream checks gpu binning for 670 Mhz */
1793 gpu_opp_table: opp-table {
1794 compatible = "operating-points-v2";
1797 opp-hz = /bits/ 64 <670000000>;
1798 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1802 opp-hz = /bits/ 64 <587000000>;
1803 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1807 opp-hz = /bits/ 64 <525000000>;
1808 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1812 opp-hz = /bits/ 64 <490000000>;
1813 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1817 opp-hz = /bits/ 64 <441600000>;
1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1822 opp-hz = /bits/ 64 <400000000>;
1823 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1827 opp-hz = /bits/ 64 <305000000>;
1828 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1834 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1836 reg = <0 0x03d6a000 0 0x30000>,
1837 <0 0x3de0000 0 0x10000>,
1838 <0 0xb290000 0 0x10000>,
1839 <0 0xb490000 0 0x10000>;
1840 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1842 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1844 interrupt-names = "hfi", "gmu";
1846 clocks = <&gpucc GPU_CC_AHB_CLK>,
1847 <&gpucc GPU_CC_CX_GMU_CLK>,
1848 <&gpucc GPU_CC_CXO_CLK>,
1849 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1850 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1851 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1853 power-domains = <&gpucc GPU_CX_GDSC>,
1854 <&gpucc GPU_GX_GDSC>;
1855 power-domain-names = "cx", "gx";
1857 iommus = <&adreno_smmu 5 0x400>;
1859 operating-points-v2 = <&gmu_opp_table>;
1861 gmu_opp_table: opp-table {
1862 compatible = "operating-points-v2";
1865 opp-hz = /bits/ 64 <200000000>;
1866 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1871 gpucc: clock-controller@3d90000 {
1872 compatible = "qcom,sm8250-gpucc";
1873 reg = <0 0x03d90000 0 0x9000>;
1874 clocks = <&rpmhcc RPMH_CXO_CLK>,
1875 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1876 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1877 clock-names = "bi_tcxo",
1878 "gcc_gpu_gpll0_clk_src",
1879 "gcc_gpu_gpll0_div_clk_src";
1882 #power-domain-cells = <1>;
1885 adreno_smmu: iommu@3da0000 {
1886 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1887 reg = <0 0x03da0000 0 0x10000>;
1889 #global-interrupts = <2>;
1890 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1892 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1894 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1897 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1900 clocks = <&gpucc GPU_CC_AHB_CLK>,
1901 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1902 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1903 clock-names = "ahb", "bus", "iface";
1905 power-domains = <&gpucc GPU_CX_GDSC>;
1908 slpi: remoteproc@5c00000 {
1909 compatible = "qcom,sm8250-slpi-pas";
1910 reg = <0 0x05c00000 0 0x4000>;
1912 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1913 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1914 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1915 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1916 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1917 interrupt-names = "wdog", "fatal", "ready",
1918 "handover", "stop-ack";
1920 clocks = <&rpmhcc RPMH_CXO_CLK>;
1923 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1924 <&rpmhpd SM8250_LCX>,
1925 <&rpmhpd SM8250_LMX>;
1926 power-domain-names = "load_state", "lcx", "lmx";
1928 memory-region = <&slpi_mem>;
1930 qcom,smem-states = <&smp2p_slpi_out 0>;
1931 qcom,smem-state-names = "stop";
1933 status = "disabled";
1936 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1937 IPCC_MPROC_SIGNAL_GLINK_QMP
1938 IRQ_TYPE_EDGE_RISING>;
1939 mboxes = <&ipcc IPCC_CLIENT_SLPI
1940 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1943 qcom,remote-pid = <3>;
1946 compatible = "qcom,fastrpc";
1947 qcom,glink-channels = "fastrpcglink-apps-dsp";
1949 #address-cells = <1>;
1953 compatible = "qcom,fastrpc-compute-cb";
1955 iommus = <&apps_smmu 0x0541 0x0>;
1959 compatible = "qcom,fastrpc-compute-cb";
1961 iommus = <&apps_smmu 0x0542 0x0>;
1965 compatible = "qcom,fastrpc-compute-cb";
1967 iommus = <&apps_smmu 0x0543 0x0>;
1968 /* note: shared-cb = <4> in downstream */
1974 cdsp: remoteproc@8300000 {
1975 compatible = "qcom,sm8250-cdsp-pas";
1976 reg = <0 0x08300000 0 0x10000>;
1978 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1979 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1980 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1981 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1982 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1983 interrupt-names = "wdog", "fatal", "ready",
1984 "handover", "stop-ack";
1986 clocks = <&rpmhcc RPMH_CXO_CLK>;
1989 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1990 <&rpmhpd SM8250_CX>;
1991 power-domain-names = "load_state", "cx";
1993 memory-region = <&cdsp_mem>;
1995 qcom,smem-states = <&smp2p_cdsp_out 0>;
1996 qcom,smem-state-names = "stop";
1998 status = "disabled";
2001 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2002 IPCC_MPROC_SIGNAL_GLINK_QMP
2003 IRQ_TYPE_EDGE_RISING>;
2004 mboxes = <&ipcc IPCC_CLIENT_CDSP
2005 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2008 qcom,remote-pid = <5>;
2011 compatible = "qcom,fastrpc";
2012 qcom,glink-channels = "fastrpcglink-apps-dsp";
2014 #address-cells = <1>;
2018 compatible = "qcom,fastrpc-compute-cb";
2020 iommus = <&apps_smmu 0x1001 0x0460>;
2024 compatible = "qcom,fastrpc-compute-cb";
2026 iommus = <&apps_smmu 0x1002 0x0460>;
2030 compatible = "qcom,fastrpc-compute-cb";
2032 iommus = <&apps_smmu 0x1003 0x0460>;
2036 compatible = "qcom,fastrpc-compute-cb";
2038 iommus = <&apps_smmu 0x1004 0x0460>;
2042 compatible = "qcom,fastrpc-compute-cb";
2044 iommus = <&apps_smmu 0x1005 0x0460>;
2048 compatible = "qcom,fastrpc-compute-cb";
2050 iommus = <&apps_smmu 0x1006 0x0460>;
2054 compatible = "qcom,fastrpc-compute-cb";
2056 iommus = <&apps_smmu 0x1007 0x0460>;
2060 compatible = "qcom,fastrpc-compute-cb";
2062 iommus = <&apps_smmu 0x1008 0x0460>;
2065 /* note: secure cb9 in downstream */
2073 usb_1_hsphy: phy@88e3000 {
2074 compatible = "qcom,sm8250-usb-hs-phy",
2075 "qcom,usb-snps-hs-7nm-phy";
2076 reg = <0 0x088e3000 0 0x400>;
2077 status = "disabled";
2080 clocks = <&rpmhcc RPMH_CXO_CLK>;
2081 clock-names = "ref";
2083 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2086 usb_2_hsphy: phy@88e4000 {
2087 compatible = "qcom,sm8250-usb-hs-phy",
2088 "qcom,usb-snps-hs-7nm-phy";
2089 reg = <0 0x088e4000 0 0x400>;
2090 status = "disabled";
2093 clocks = <&rpmhcc RPMH_CXO_CLK>;
2094 clock-names = "ref";
2096 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2099 usb_1_qmpphy: phy@88e9000 {
2100 compatible = "qcom,sm8250-qmp-usb3-phy";
2101 reg = <0 0x088e9000 0 0x200>,
2102 <0 0x088e8000 0 0x20>;
2103 reg-names = "reg-base", "dp_com";
2104 status = "disabled";
2106 #address-cells = <2>;
2110 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2111 <&rpmhcc RPMH_CXO_CLK>,
2112 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2113 clock-names = "aux", "ref_clk_src", "com_aux";
2115 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2116 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2117 reset-names = "phy", "common";
2119 usb_1_ssphy: lanes@88e9200 {
2120 reg = <0 0x088e9200 0 0x200>,
2121 <0 0x088e9400 0 0x200>,
2122 <0 0x088e9c00 0 0x400>,
2123 <0 0x088e9600 0 0x200>,
2124 <0 0x088e9800 0 0x200>,
2125 <0 0x088e9a00 0 0x100>;
2127 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2128 clock-names = "pipe0";
2129 clock-output-names = "usb3_phy_pipe_clk_src";
2133 usb_2_qmpphy: phy@88eb000 {
2134 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2135 reg = <0 0x088eb000 0 0x200>;
2136 status = "disabled";
2138 #address-cells = <2>;
2142 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2143 <&rpmhcc RPMH_CXO_CLK>,
2144 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2145 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2146 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2148 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2149 <&gcc GCC_USB3_PHY_SEC_BCR>;
2150 reset-names = "phy", "common";
2152 usb_2_ssphy: lane@88eb200 {
2153 reg = <0 0x088eb200 0 0x200>,
2154 <0 0x088eb400 0 0x200>,
2155 <0 0x088eb800 0 0x800>;
2157 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2158 clock-names = "pipe0";
2159 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2163 sdhc_2: sdhci@8804000 {
2164 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2165 reg = <0 0x08804000 0 0x1000>;
2167 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2168 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2169 interrupt-names = "hc_irq", "pwr_irq";
2171 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2172 <&gcc GCC_SDCC2_APPS_CLK>,
2173 <&rpmhcc RPMH_CXO_CLK>;
2174 clock-names = "iface", "core", "xo";
2175 iommus = <&apps_smmu 0x4a0 0x0>;
2176 qcom,dll-config = <0x0007642c>;
2177 qcom,ddr-config = <0x80040868>;
2178 power-domains = <&rpmhpd SM8250_CX>;
2179 operating-points-v2 = <&sdhc2_opp_table>;
2181 status = "disabled";
2183 sdhc2_opp_table: sdhc2-opp-table {
2184 compatible = "operating-points-v2";
2187 opp-hz = /bits/ 64 <19200000>;
2188 required-opps = <&rpmhpd_opp_min_svs>;
2192 opp-hz = /bits/ 64 <50000000>;
2193 required-opps = <&rpmhpd_opp_low_svs>;
2197 opp-hz = /bits/ 64 <100000000>;
2198 required-opps = <&rpmhpd_opp_svs>;
2202 opp-hz = /bits/ 64 <202000000>;
2203 required-opps = <&rpmhpd_opp_svs_l1>;
2208 dc_noc: interconnect@90c0000 {
2209 compatible = "qcom,sm8250-dc-noc";
2210 reg = <0 0x090c0000 0 0x4200>;
2211 #interconnect-cells = <1>;
2212 qcom,bcm-voters = <&apps_bcm_voter>;
2215 gem_noc: interconnect@9100000 {
2216 compatible = "qcom,sm8250-gem-noc";
2217 reg = <0 0x09100000 0 0xb4000>;
2218 #interconnect-cells = <1>;
2219 qcom,bcm-voters = <&apps_bcm_voter>;
2222 npu_noc: interconnect@9990000 {
2223 compatible = "qcom,sm8250-npu-noc";
2224 reg = <0 0x09990000 0 0x1600>;
2225 #interconnect-cells = <1>;
2226 qcom,bcm-voters = <&apps_bcm_voter>;
2229 usb_1: usb@a6f8800 {
2230 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2231 reg = <0 0x0a6f8800 0 0x400>;
2232 status = "disabled";
2233 #address-cells = <2>;
2238 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2239 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2240 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2241 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2242 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2243 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2244 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2247 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2248 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2249 assigned-clock-rates = <19200000>, <200000000>;
2251 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2252 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2253 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2254 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2255 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2256 "dm_hs_phy_irq", "ss_phy_irq";
2258 power-domains = <&gcc USB30_PRIM_GDSC>;
2260 resets = <&gcc GCC_USB30_PRIM_BCR>;
2262 usb_1_dwc3: dwc3@a600000 {
2263 compatible = "snps,dwc3";
2264 reg = <0 0x0a600000 0 0xcd00>;
2265 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2266 iommus = <&apps_smmu 0x0 0x0>;
2267 snps,dis_u2_susphy_quirk;
2268 snps,dis_enblslpm_quirk;
2269 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2270 phy-names = "usb2-phy", "usb3-phy";
2274 system-cache-controller@9200000 {
2275 compatible = "qcom,sm8250-llcc";
2276 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2277 reg-names = "llcc_base", "llcc_broadcast_base";
2280 usb_2: usb@a8f8800 {
2281 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2282 reg = <0 0x0a8f8800 0 0x400>;
2283 status = "disabled";
2284 #address-cells = <2>;
2289 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2290 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2291 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2292 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2293 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2294 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2295 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2298 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2299 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2300 assigned-clock-rates = <19200000>, <200000000>;
2302 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2303 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2304 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2305 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2306 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2307 "dm_hs_phy_irq", "ss_phy_irq";
2309 power-domains = <&gcc USB30_SEC_GDSC>;
2311 resets = <&gcc GCC_USB30_SEC_BCR>;
2313 usb_2_dwc3: dwc3@a800000 {
2314 compatible = "snps,dwc3";
2315 reg = <0 0x0a800000 0 0xcd00>;
2316 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2317 iommus = <&apps_smmu 0x20 0>;
2318 snps,dis_u2_susphy_quirk;
2319 snps,dis_enblslpm_quirk;
2320 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2321 phy-names = "usb2-phy", "usb3-phy";
2325 mdss: mdss@ae00000 {
2326 compatible = "qcom,sdm845-mdss";
2327 reg = <0 0x0ae00000 0 0x1000>;
2330 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
2331 <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
2332 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
2333 interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
2335 power-domains = <&dispcc MDSS_GDSC>;
2337 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2338 <&gcc GCC_DISP_HF_AXI_CLK>,
2339 <&gcc GCC_DISP_SF_AXI_CLK>,
2340 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2341 clock-names = "iface", "bus", "nrt_bus", "core";
2343 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2344 assigned-clock-rates = <460000000>;
2346 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2347 interrupt-controller;
2348 #interrupt-cells = <1>;
2350 iommus = <&apps_smmu 0x820 0x402>;
2352 status = "disabled";
2354 #address-cells = <2>;
2358 mdss_mdp: mdp@ae01000 {
2359 compatible = "qcom,sdm845-dpu";
2360 reg = <0 0x0ae01000 0 0x8f000>,
2361 <0 0x0aeb0000 0 0x2008>;
2362 reg-names = "mdp", "vbif";
2364 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2365 <&gcc GCC_DISP_HF_AXI_CLK>,
2366 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2367 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2368 clock-names = "iface", "bus", "core", "vsync";
2370 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2371 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2372 assigned-clock-rates = <460000000>,
2375 operating-points-v2 = <&mdp_opp_table>;
2376 power-domains = <&rpmhpd SM8250_MMCX>;
2378 interrupt-parent = <&mdss>;
2379 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2381 status = "disabled";
2384 #address-cells = <1>;
2389 dpu_intf1_out: endpoint {
2390 remote-endpoint = <&dsi0_in>;
2396 dpu_intf2_out: endpoint {
2397 remote-endpoint = <&dsi1_in>;
2402 mdp_opp_table: mdp-opp-table {
2403 compatible = "operating-points-v2";
2406 opp-hz = /bits/ 64 <200000000>;
2407 required-opps = <&rpmhpd_opp_low_svs>;
2411 opp-hz = /bits/ 64 <300000000>;
2412 required-opps = <&rpmhpd_opp_svs>;
2416 opp-hz = /bits/ 64 <345000000>;
2417 required-opps = <&rpmhpd_opp_svs_l1>;
2421 opp-hz = /bits/ 64 <460000000>;
2422 required-opps = <&rpmhpd_opp_nom>;
2428 compatible = "qcom,mdss-dsi-ctrl";
2429 reg = <0 0x0ae94000 0 0x400>;
2430 reg-names = "dsi_ctrl";
2432 interrupt-parent = <&mdss>;
2433 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2435 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2436 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2437 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2438 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2439 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2440 <&gcc GCC_DISP_HF_AXI_CLK>;
2441 clock-names = "byte",
2448 operating-points-v2 = <&dsi_opp_table>;
2449 power-domains = <&rpmhpd SM8250_MMCX>;
2454 status = "disabled";
2457 #address-cells = <1>;
2463 remote-endpoint = <&dpu_intf1_out>;
2469 dsi0_out: endpoint {
2475 dsi0_phy: dsi-phy@ae94400 {
2476 compatible = "qcom,dsi-phy-7nm";
2477 reg = <0 0x0ae94400 0 0x200>,
2478 <0 0x0ae94600 0 0x280>,
2479 <0 0x0ae94900 0 0x260>;
2480 reg-names = "dsi_phy",
2487 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2488 <&rpmhcc RPMH_CXO_CLK>;
2489 clock-names = "iface", "ref";
2491 status = "disabled";
2495 compatible = "qcom,mdss-dsi-ctrl";
2496 reg = <0 0x0ae96000 0 0x400>;
2497 reg-names = "dsi_ctrl";
2499 interrupt-parent = <&mdss>;
2500 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2502 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2503 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2504 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2505 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2506 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2507 <&gcc GCC_DISP_HF_AXI_CLK>;
2508 clock-names = "byte",
2515 operating-points-v2 = <&dsi_opp_table>;
2516 power-domains = <&rpmhpd SM8250_MMCX>;
2521 status = "disabled";
2524 #address-cells = <1>;
2530 remote-endpoint = <&dpu_intf2_out>;
2536 dsi1_out: endpoint {
2542 dsi1_phy: dsi-phy@ae96400 {
2543 compatible = "qcom,dsi-phy-7nm";
2544 reg = <0 0x0ae96400 0 0x200>,
2545 <0 0x0ae96600 0 0x280>,
2546 <0 0x0ae96900 0 0x260>;
2547 reg-names = "dsi_phy",
2554 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2555 <&rpmhcc RPMH_CXO_CLK>;
2556 clock-names = "iface", "ref";
2558 status = "disabled";
2560 dsi_opp_table: dsi-opp-table {
2561 compatible = "operating-points-v2";
2564 opp-hz = /bits/ 64 <187500000>;
2565 required-opps = <&rpmhpd_opp_low_svs>;
2569 opp-hz = /bits/ 64 <300000000>;
2570 required-opps = <&rpmhpd_opp_svs>;
2574 opp-hz = /bits/ 64 <358000000>;
2575 required-opps = <&rpmhpd_opp_svs_l1>;
2581 dispcc: clock-controller@af00000 {
2582 compatible = "qcom,sm8250-dispcc";
2583 reg = <0 0x0af00000 0 0x20000>;
2584 mmcx-supply = <&mmcx_reg>;
2585 clocks = <&rpmhcc RPMH_CXO_CLK>,
2599 clock-names = "bi_tcxo",
2600 "dsi0_phy_pll_out_byteclk",
2601 "dsi0_phy_pll_out_dsiclk",
2602 "dsi1_phy_pll_out_byteclk",
2603 "dsi1_phy_pll_out_dsiclk",
2604 "dp_link_clk_divsel_ten",
2605 "dp_vco_divided_clk_src_mux",
2606 "dptx1_phy_pll_link_clk",
2607 "dptx1_phy_pll_vco_div_clk",
2608 "dptx2_phy_pll_link_clk",
2609 "dptx2_phy_pll_vco_div_clk",
2610 "edp_phy_pll_link_clk",
2611 "edp_phy_pll_vco_div_clk",
2615 #power-domain-cells = <1>;
2618 pdc: interrupt-controller@b220000 {
2619 compatible = "qcom,sm8250-pdc", "qcom,pdc";
2620 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2621 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2622 <125 63 1>, <126 716 12>;
2623 #interrupt-cells = <2>;
2624 interrupt-parent = <&intc>;
2625 interrupt-controller;
2628 tsens0: thermal-sensor@c263000 {
2629 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2630 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2631 <0 0x0c222000 0 0x1ff>; /* SROT */
2632 #qcom,sensors = <16>;
2633 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2634 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2635 interrupt-names = "uplow", "critical";
2636 #thermal-sensor-cells = <1>;
2639 tsens1: thermal-sensor@c265000 {
2640 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2641 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2642 <0 0x0c223000 0 0x1ff>; /* SROT */
2643 #qcom,sensors = <9>;
2644 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2645 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2646 interrupt-names = "uplow", "critical";
2647 #thermal-sensor-cells = <1>;
2650 aoss_qmp: qmp@c300000 {
2651 compatible = "qcom,sm8250-aoss-qmp";
2652 reg = <0 0x0c300000 0 0x100000>;
2653 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2654 IPCC_MPROC_SIGNAL_GLINK_QMP
2655 IRQ_TYPE_EDGE_RISING>;
2656 mboxes = <&ipcc IPCC_CLIENT_AOP
2657 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2660 #power-domain-cells = <1>;
2663 spmi_bus: spmi@c440000 {
2664 compatible = "qcom,spmi-pmic-arb";
2665 reg = <0x0 0x0c440000 0x0 0x0001100>,
2666 <0x0 0x0c600000 0x0 0x2000000>,
2667 <0x0 0x0e600000 0x0 0x0100000>,
2668 <0x0 0x0e700000 0x0 0x00a0000>,
2669 <0x0 0x0c40a000 0x0 0x0026000>;
2670 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2671 interrupt-names = "periph_irq";
2672 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2675 #address-cells = <2>;
2677 interrupt-controller;
2678 #interrupt-cells = <4>;
2681 tlmm: pinctrl@f100000 {
2682 compatible = "qcom,sm8250-pinctrl";
2683 reg = <0 0x0f100000 0 0x300000>,
2684 <0 0x0f500000 0 0x300000>,
2685 <0 0x0f900000 0 0x300000>;
2686 reg-names = "west", "south", "north";
2687 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2690 interrupt-controller;
2691 #interrupt-cells = <2>;
2692 gpio-ranges = <&tlmm 0 0 180>;
2693 wakeup-parent = <&pdc>;
2695 pri_mi2s_active: pri-mi2s-active {
2698 function = "mi2s0_sck";
2699 drive-strength = <8>;
2705 function = "mi2s0_ws";
2706 drive-strength = <8>;
2712 function = "mi2s0_data0";
2713 drive-strength = <8>;
2720 function = "mi2s0_data1";
2721 drive-strength = <8>;
2726 qup_i2c0_default: qup-i2c0-default {
2728 pins = "gpio28", "gpio29";
2733 pins = "gpio28", "gpio29";
2734 drive-strength = <2>;
2739 qup_i2c1_default: qup-i2c1-default {
2741 pins = "gpio4", "gpio5";
2746 pins = "gpio4", "gpio5";
2747 drive-strength = <2>;
2752 qup_i2c2_default: qup-i2c2-default {
2754 pins = "gpio115", "gpio116";
2759 pins = "gpio115", "gpio116";
2760 drive-strength = <2>;
2765 qup_i2c3_default: qup-i2c3-default {
2767 pins = "gpio119", "gpio120";
2772 pins = "gpio119", "gpio120";
2773 drive-strength = <2>;
2778 qup_i2c4_default: qup-i2c4-default {
2780 pins = "gpio8", "gpio9";
2785 pins = "gpio8", "gpio9";
2786 drive-strength = <2>;
2791 qup_i2c5_default: qup-i2c5-default {
2793 pins = "gpio12", "gpio13";
2798 pins = "gpio12", "gpio13";
2799 drive-strength = <2>;
2804 qup_i2c6_default: qup-i2c6-default {
2806 pins = "gpio16", "gpio17";
2811 pins = "gpio16", "gpio17";
2812 drive-strength = <2>;
2817 qup_i2c7_default: qup-i2c7-default {
2819 pins = "gpio20", "gpio21";
2824 pins = "gpio20", "gpio21";
2825 drive-strength = <2>;
2830 qup_i2c8_default: qup-i2c8-default {
2832 pins = "gpio24", "gpio25";
2837 pins = "gpio24", "gpio25";
2838 drive-strength = <2>;
2843 qup_i2c9_default: qup-i2c9-default {
2845 pins = "gpio125", "gpio126";
2850 pins = "gpio125", "gpio126";
2851 drive-strength = <2>;
2856 qup_i2c10_default: qup-i2c10-default {
2858 pins = "gpio129", "gpio130";
2863 pins = "gpio129", "gpio130";
2864 drive-strength = <2>;
2869 qup_i2c11_default: qup-i2c11-default {
2871 pins = "gpio60", "gpio61";
2876 pins = "gpio60", "gpio61";
2877 drive-strength = <2>;
2882 qup_i2c12_default: qup-i2c12-default {
2884 pins = "gpio32", "gpio33";
2889 pins = "gpio32", "gpio33";
2890 drive-strength = <2>;
2895 qup_i2c13_default: qup-i2c13-default {
2897 pins = "gpio36", "gpio37";
2902 pins = "gpio36", "gpio37";
2903 drive-strength = <2>;
2908 qup_i2c14_default: qup-i2c14-default {
2910 pins = "gpio40", "gpio41";
2915 pins = "gpio40", "gpio41";
2916 drive-strength = <2>;
2921 qup_i2c15_default: qup-i2c15-default {
2923 pins = "gpio44", "gpio45";
2928 pins = "gpio44", "gpio45";
2929 drive-strength = <2>;
2934 qup_i2c16_default: qup-i2c16-default {
2936 pins = "gpio48", "gpio49";
2941 pins = "gpio48", "gpio49";
2942 drive-strength = <2>;
2947 qup_i2c17_default: qup-i2c17-default {
2949 pins = "gpio52", "gpio53";
2954 pins = "gpio52", "gpio53";
2955 drive-strength = <2>;
2960 qup_i2c18_default: qup-i2c18-default {
2962 pins = "gpio56", "gpio57";
2967 pins = "gpio56", "gpio57";
2968 drive-strength = <2>;
2973 qup_i2c19_default: qup-i2c19-default {
2975 pins = "gpio0", "gpio1";
2980 pins = "gpio0", "gpio1";
2981 drive-strength = <2>;
2986 qup_spi0_default: qup-spi0-default {
2988 pins = "gpio28", "gpio29",
2994 pins = "gpio28", "gpio29",
2996 drive-strength = <6>;
3001 qup_spi1_default: qup-spi1-default {
3003 pins = "gpio4", "gpio5",
3009 pins = "gpio4", "gpio5",
3011 drive-strength = <6>;
3016 qup_spi2_default: qup-spi2-default {
3018 pins = "gpio115", "gpio116",
3019 "gpio117", "gpio118";
3024 pins = "gpio115", "gpio116",
3025 "gpio117", "gpio118";
3026 drive-strength = <6>;
3031 qup_spi3_default: qup-spi3-default {
3033 pins = "gpio119", "gpio120",
3034 "gpio121", "gpio122";
3039 pins = "gpio119", "gpio120",
3040 "gpio121", "gpio122";
3041 drive-strength = <6>;
3046 qup_spi4_default: qup-spi4-default {
3048 pins = "gpio8", "gpio9",
3054 pins = "gpio8", "gpio9",
3056 drive-strength = <6>;
3061 qup_spi5_default: qup-spi5-default {
3063 pins = "gpio12", "gpio13",
3069 pins = "gpio12", "gpio13",
3071 drive-strength = <6>;
3076 qup_spi6_default: qup-spi6-default {
3078 pins = "gpio16", "gpio17",
3084 pins = "gpio16", "gpio17",
3086 drive-strength = <6>;
3091 qup_spi7_default: qup-spi7-default {
3093 pins = "gpio20", "gpio21",
3099 pins = "gpio20", "gpio21",
3101 drive-strength = <6>;
3106 qup_spi8_default: qup-spi8-default {
3108 pins = "gpio24", "gpio25",
3114 pins = "gpio24", "gpio25",
3116 drive-strength = <6>;
3121 qup_spi9_default: qup-spi9-default {
3123 pins = "gpio125", "gpio126",
3124 "gpio127", "gpio128";
3129 pins = "gpio125", "gpio126",
3130 "gpio127", "gpio128";
3131 drive-strength = <6>;
3136 qup_spi10_default: qup-spi10-default {
3138 pins = "gpio129", "gpio130",
3139 "gpio131", "gpio132";
3144 pins = "gpio129", "gpio130",
3145 "gpio131", "gpio132";
3146 drive-strength = <6>;
3151 qup_spi11_default: qup-spi11-default {
3153 pins = "gpio60", "gpio61",
3159 pins = "gpio60", "gpio61",
3161 drive-strength = <6>;
3166 qup_spi12_default: qup-spi12-default {
3168 pins = "gpio32", "gpio33",
3174 pins = "gpio32", "gpio33",
3176 drive-strength = <6>;
3181 qup_spi13_default: qup-spi13-default {
3183 pins = "gpio36", "gpio37",
3189 pins = "gpio36", "gpio37",
3191 drive-strength = <6>;
3196 qup_spi14_default: qup-spi14-default {
3198 pins = "gpio40", "gpio41",
3204 pins = "gpio40", "gpio41",
3206 drive-strength = <6>;
3211 qup_spi15_default: qup-spi15-default {
3213 pins = "gpio44", "gpio45",
3219 pins = "gpio44", "gpio45",
3221 drive-strength = <6>;
3226 qup_spi16_default: qup-spi16-default {
3228 pins = "gpio48", "gpio49",
3234 pins = "gpio48", "gpio49",
3236 drive-strength = <6>;
3241 qup_spi17_default: qup-spi17-default {
3243 pins = "gpio52", "gpio53",
3249 pins = "gpio52", "gpio53",
3251 drive-strength = <6>;
3256 qup_spi18_default: qup-spi18-default {
3258 pins = "gpio56", "gpio57",
3264 pins = "gpio56", "gpio57",
3266 drive-strength = <6>;
3271 qup_spi19_default: qup-spi19-default {
3273 pins = "gpio0", "gpio1",
3279 pins = "gpio0", "gpio1",
3281 drive-strength = <6>;
3286 qup_uart2_default: qup-uart2-default {
3288 pins = "gpio117", "gpio118";
3293 qup_uart6_default: qup-uart6-default {
3295 pins = "gpio16", "gpio17",
3301 qup_uart12_default: qup-uart12-default {
3303 pins = "gpio34", "gpio35";
3308 qup_uart17_default: qup-uart17-default {
3310 pins = "gpio52", "gpio53",
3316 qup_uart18_default: qup-uart18-default {
3318 pins = "gpio58", "gpio59";
3323 tert_mi2s_active: tert-mi2s-active {
3326 function = "mi2s2_sck";
3327 drive-strength = <8>;
3333 function = "mi2s2_data0";
3334 drive-strength = <8>;
3341 function = "mi2s2_ws";
3342 drive-strength = <8>;
3348 apps_smmu: iommu@15000000 {
3349 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3350 reg = <0 0x15000000 0 0x100000>;
3352 #global-interrupts = <2>;
3353 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3354 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3355 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3356 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3357 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3358 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3359 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3360 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3361 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3362 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3363 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3364 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3365 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3366 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3367 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3368 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3369 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3370 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3371 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3372 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3373 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3374 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3375 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3376 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3377 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3378 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3379 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3380 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3381 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3382 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3383 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3384 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3385 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3386 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3387 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3388 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3389 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3390 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3391 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3392 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3393 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3394 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3395 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3396 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3397 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3398 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3399 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3400 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3401 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3402 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3403 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3404 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3405 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3406 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3407 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3408 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3409 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3410 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3411 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3412 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3413 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3414 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3415 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3416 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3417 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3418 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3419 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3420 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3421 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3422 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3423 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3424 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3425 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3426 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3427 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3428 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3429 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3430 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3431 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3432 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3433 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3434 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3435 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3436 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3437 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3438 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3439 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3440 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3441 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3442 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3443 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3444 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3445 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3446 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3447 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3448 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3449 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3450 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3453 adsp: remoteproc@17300000 {
3454 compatible = "qcom,sm8250-adsp-pas";
3455 reg = <0 0x17300000 0 0x100>;
3457 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3458 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3459 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3460 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3461 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3462 interrupt-names = "wdog", "fatal", "ready",
3463 "handover", "stop-ack";
3465 clocks = <&rpmhcc RPMH_CXO_CLK>;
3468 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3469 <&rpmhpd SM8250_LCX>,
3470 <&rpmhpd SM8250_LMX>;
3471 power-domain-names = "load_state", "lcx", "lmx";
3473 memory-region = <&adsp_mem>;
3475 qcom,smem-states = <&smp2p_adsp_out 0>;
3476 qcom,smem-state-names = "stop";
3478 status = "disabled";
3481 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3482 IPCC_MPROC_SIGNAL_GLINK_QMP
3483 IRQ_TYPE_EDGE_RISING>;
3484 mboxes = <&ipcc IPCC_CLIENT_LPASS
3485 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3488 qcom,remote-pid = <2>;
3491 compatible = "qcom,apr-v2";
3492 qcom,glink-channels = "apr_audio_svc";
3493 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3494 #address-cells = <1>;
3498 reg = <APR_SVC_ADSP_CORE>;
3499 compatible = "qcom,q6core";
3500 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3503 q6afe: apr-service@4 {
3504 compatible = "qcom,q6afe";
3505 reg = <APR_SVC_AFE>;
3506 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3508 compatible = "qcom,q6afe-dais";
3509 #address-cells = <1>;
3511 #sound-dai-cells = <1>;
3515 compatible = "qcom,q6afe-clocks";
3520 q6asm: apr-service@7 {
3521 compatible = "qcom,q6asm";
3522 reg = <APR_SVC_ASM>;
3523 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3525 compatible = "qcom,q6asm-dais";
3526 #address-cells = <1>;
3528 #sound-dai-cells = <1>;
3529 iommus = <&apps_smmu 0x1801 0x0>;
3533 q6adm: apr-service@8 {
3534 compatible = "qcom,q6adm";
3535 reg = <APR_SVC_ADM>;
3536 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3537 q6routing: routing {
3538 compatible = "qcom,q6adm-routing";
3539 #sound-dai-cells = <0>;
3545 compatible = "qcom,fastrpc";
3546 qcom,glink-channels = "fastrpcglink-apps-dsp";
3548 #address-cells = <1>;
3552 compatible = "qcom,fastrpc-compute-cb";
3554 iommus = <&apps_smmu 0x1803 0x0>;
3558 compatible = "qcom,fastrpc-compute-cb";
3560 iommus = <&apps_smmu 0x1804 0x0>;
3564 compatible = "qcom,fastrpc-compute-cb";
3566 iommus = <&apps_smmu 0x1805 0x0>;
3572 intc: interrupt-controller@17a00000 {
3573 compatible = "arm,gic-v3";
3574 #interrupt-cells = <3>;
3575 interrupt-controller;
3576 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3577 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3578 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3582 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3583 reg = <0 0x17c10000 0 0x1000>;
3584 clocks = <&sleep_clk>;
3585 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3589 #address-cells = <2>;
3592 compatible = "arm,armv7-timer-mem";
3593 reg = <0x0 0x17c20000 0x0 0x1000>;
3594 clock-frequency = <19200000>;
3598 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3600 reg = <0x0 0x17c21000 0x0 0x1000>,
3601 <0x0 0x17c22000 0x0 0x1000>;
3606 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3607 reg = <0x0 0x17c23000 0x0 0x1000>;
3608 status = "disabled";
3613 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3614 reg = <0x0 0x17c25000 0x0 0x1000>;
3615 status = "disabled";
3620 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3621 reg = <0x0 0x17c27000 0x0 0x1000>;
3622 status = "disabled";
3627 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3628 reg = <0x0 0x17c29000 0x0 0x1000>;
3629 status = "disabled";
3634 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3635 reg = <0x0 0x17c2b000 0x0 0x1000>;
3636 status = "disabled";
3641 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3642 reg = <0x0 0x17c2d000 0x0 0x1000>;
3643 status = "disabled";
3647 apps_rsc: rsc@18200000 {
3649 compatible = "qcom,rpmh-rsc";
3650 reg = <0x0 0x18200000 0x0 0x10000>,
3651 <0x0 0x18210000 0x0 0x10000>,
3652 <0x0 0x18220000 0x0 0x10000>;
3653 reg-names = "drv-0", "drv-1", "drv-2";
3654 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3655 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3656 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3657 qcom,tcs-offset = <0xd00>;
3659 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3660 <WAKE_TCS 3>, <CONTROL_TCS 1>;
3662 rpmhcc: clock-controller {
3663 compatible = "qcom,sm8250-rpmh-clk";
3666 clocks = <&xo_board>;
3669 rpmhpd: power-controller {
3670 compatible = "qcom,sm8250-rpmhpd";
3671 #power-domain-cells = <1>;
3672 operating-points-v2 = <&rpmhpd_opp_table>;
3674 rpmhpd_opp_table: opp-table {
3675 compatible = "operating-points-v2";
3677 rpmhpd_opp_ret: opp1 {
3678 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3681 rpmhpd_opp_min_svs: opp2 {
3682 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3685 rpmhpd_opp_low_svs: opp3 {
3686 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3689 rpmhpd_opp_svs: opp4 {
3690 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3693 rpmhpd_opp_svs_l1: opp5 {
3694 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3697 rpmhpd_opp_nom: opp6 {
3698 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3701 rpmhpd_opp_nom_l1: opp7 {
3702 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3705 rpmhpd_opp_nom_l2: opp8 {
3706 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3709 rpmhpd_opp_turbo: opp9 {
3710 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3713 rpmhpd_opp_turbo_l1: opp10 {
3714 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3719 apps_bcm_voter: bcm_voter {
3720 compatible = "qcom,bcm-voter";
3724 epss_l3: interconnect@18591000 {
3725 compatible = "qcom,sm8250-epss-l3";
3726 reg = <0 0x18590000 0 0x1000>;
3728 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3729 clock-names = "xo", "alternate";
3731 #interconnect-cells = <1>;
3734 cpufreq_hw: cpufreq@18591000 {
3735 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3736 reg = <0 0x18591000 0 0x1000>,
3737 <0 0x18592000 0 0x1000>,
3738 <0 0x18593000 0 0x1000>;
3739 reg-names = "freq-domain0", "freq-domain1",
3742 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3743 clock-names = "xo", "alternate";
3745 #freq-domain-cells = <1>;
3750 compatible = "arm,armv8-timer";
3751 interrupts = <GIC_PPI 13
3752 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3754 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3756 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3758 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3763 polling-delay-passive = <250>;
3764 polling-delay = <1000>;
3766 thermal-sensors = <&tsens0 1>;
3769 cpu0_alert0: trip-point0 {
3770 temperature = <90000>;
3771 hysteresis = <2000>;
3775 cpu0_alert1: trip-point1 {
3776 temperature = <95000>;
3777 hysteresis = <2000>;
3781 cpu0_crit: cpu_crit {
3782 temperature = <110000>;
3783 hysteresis = <1000>;
3790 trip = <&cpu0_alert0>;
3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3792 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3793 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3794 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3797 trip = <&cpu0_alert1>;
3798 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3799 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3800 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3801 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3807 polling-delay-passive = <250>;
3808 polling-delay = <1000>;
3810 thermal-sensors = <&tsens0 2>;
3813 cpu1_alert0: trip-point0 {
3814 temperature = <90000>;
3815 hysteresis = <2000>;
3819 cpu1_alert1: trip-point1 {
3820 temperature = <95000>;
3821 hysteresis = <2000>;
3825 cpu1_crit: cpu_crit {
3826 temperature = <110000>;
3827 hysteresis = <1000>;
3834 trip = <&cpu1_alert0>;
3835 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3836 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3837 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3838 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3841 trip = <&cpu1_alert1>;
3842 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3843 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3844 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3845 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3851 polling-delay-passive = <250>;
3852 polling-delay = <1000>;
3854 thermal-sensors = <&tsens0 3>;
3857 cpu2_alert0: trip-point0 {
3858 temperature = <90000>;
3859 hysteresis = <2000>;
3863 cpu2_alert1: trip-point1 {
3864 temperature = <95000>;
3865 hysteresis = <2000>;
3869 cpu2_crit: cpu_crit {
3870 temperature = <110000>;
3871 hysteresis = <1000>;
3878 trip = <&cpu2_alert0>;
3879 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3880 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3881 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3882 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3885 trip = <&cpu2_alert1>;
3886 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3887 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3888 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3889 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3895 polling-delay-passive = <250>;
3896 polling-delay = <1000>;
3898 thermal-sensors = <&tsens0 4>;
3901 cpu3_alert0: trip-point0 {
3902 temperature = <90000>;
3903 hysteresis = <2000>;
3907 cpu3_alert1: trip-point1 {
3908 temperature = <95000>;
3909 hysteresis = <2000>;
3913 cpu3_crit: cpu_crit {
3914 temperature = <110000>;
3915 hysteresis = <1000>;
3922 trip = <&cpu3_alert0>;
3923 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3924 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3925 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3926 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3929 trip = <&cpu3_alert1>;
3930 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3931 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3932 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3933 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3939 polling-delay-passive = <250>;
3940 polling-delay = <1000>;
3942 thermal-sensors = <&tsens0 7>;
3945 cpu4_top_alert0: trip-point0 {
3946 temperature = <90000>;
3947 hysteresis = <2000>;
3951 cpu4_top_alert1: trip-point1 {
3952 temperature = <95000>;
3953 hysteresis = <2000>;
3957 cpu4_top_crit: cpu_crit {
3958 temperature = <110000>;
3959 hysteresis = <1000>;
3966 trip = <&cpu4_top_alert0>;
3967 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3968 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3969 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3970 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3973 trip = <&cpu4_top_alert1>;
3974 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3975 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3976 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3977 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3983 polling-delay-passive = <250>;
3984 polling-delay = <1000>;
3986 thermal-sensors = <&tsens0 8>;
3989 cpu5_top_alert0: trip-point0 {
3990 temperature = <90000>;
3991 hysteresis = <2000>;
3995 cpu5_top_alert1: trip-point1 {
3996 temperature = <95000>;
3997 hysteresis = <2000>;
4001 cpu5_top_crit: cpu_crit {
4002 temperature = <110000>;
4003 hysteresis = <1000>;
4010 trip = <&cpu5_top_alert0>;
4011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4017 trip = <&cpu5_top_alert1>;
4018 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4020 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4027 polling-delay-passive = <250>;
4028 polling-delay = <1000>;
4030 thermal-sensors = <&tsens0 9>;
4033 cpu6_top_alert0: trip-point0 {
4034 temperature = <90000>;
4035 hysteresis = <2000>;
4039 cpu6_top_alert1: trip-point1 {
4040 temperature = <95000>;
4041 hysteresis = <2000>;
4045 cpu6_top_crit: cpu_crit {
4046 temperature = <110000>;
4047 hysteresis = <1000>;
4054 trip = <&cpu6_top_alert0>;
4055 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4057 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4058 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4061 trip = <&cpu6_top_alert1>;
4062 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4063 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4064 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4071 polling-delay-passive = <250>;
4072 polling-delay = <1000>;
4074 thermal-sensors = <&tsens0 10>;
4077 cpu7_top_alert0: trip-point0 {
4078 temperature = <90000>;
4079 hysteresis = <2000>;
4083 cpu7_top_alert1: trip-point1 {
4084 temperature = <95000>;
4085 hysteresis = <2000>;
4089 cpu7_top_crit: cpu_crit {
4090 temperature = <110000>;
4091 hysteresis = <1000>;
4098 trip = <&cpu7_top_alert0>;
4099 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4100 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4101 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4102 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4105 trip = <&cpu7_top_alert1>;
4106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4114 cpu4-bottom-thermal {
4115 polling-delay-passive = <250>;
4116 polling-delay = <1000>;
4118 thermal-sensors = <&tsens0 11>;
4121 cpu4_bottom_alert0: trip-point0 {
4122 temperature = <90000>;
4123 hysteresis = <2000>;
4127 cpu4_bottom_alert1: trip-point1 {
4128 temperature = <95000>;
4129 hysteresis = <2000>;
4133 cpu4_bottom_crit: cpu_crit {
4134 temperature = <110000>;
4135 hysteresis = <1000>;
4142 trip = <&cpu4_bottom_alert0>;
4143 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4144 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4145 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4146 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4149 trip = <&cpu4_bottom_alert1>;
4150 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4151 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4152 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4158 cpu5-bottom-thermal {
4159 polling-delay-passive = <250>;
4160 polling-delay = <1000>;
4162 thermal-sensors = <&tsens0 12>;
4165 cpu5_bottom_alert0: trip-point0 {
4166 temperature = <90000>;
4167 hysteresis = <2000>;
4171 cpu5_bottom_alert1: trip-point1 {
4172 temperature = <95000>;
4173 hysteresis = <2000>;
4177 cpu5_bottom_crit: cpu_crit {
4178 temperature = <110000>;
4179 hysteresis = <1000>;
4186 trip = <&cpu5_bottom_alert0>;
4187 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4188 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4189 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4190 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4193 trip = <&cpu5_bottom_alert1>;
4194 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4195 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4196 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4197 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4202 cpu6-bottom-thermal {
4203 polling-delay-passive = <250>;
4204 polling-delay = <1000>;
4206 thermal-sensors = <&tsens0 13>;
4209 cpu6_bottom_alert0: trip-point0 {
4210 temperature = <90000>;
4211 hysteresis = <2000>;
4215 cpu6_bottom_alert1: trip-point1 {
4216 temperature = <95000>;
4217 hysteresis = <2000>;
4221 cpu6_bottom_crit: cpu_crit {
4222 temperature = <110000>;
4223 hysteresis = <1000>;
4230 trip = <&cpu6_bottom_alert0>;
4231 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4232 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4233 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4234 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4237 trip = <&cpu6_bottom_alert1>;
4238 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4240 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4241 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4246 cpu7-bottom-thermal {
4247 polling-delay-passive = <250>;
4248 polling-delay = <1000>;
4250 thermal-sensors = <&tsens0 14>;
4253 cpu7_bottom_alert0: trip-point0 {
4254 temperature = <90000>;
4255 hysteresis = <2000>;
4259 cpu7_bottom_alert1: trip-point1 {
4260 temperature = <95000>;
4261 hysteresis = <2000>;
4265 cpu7_bottom_crit: cpu_crit {
4266 temperature = <110000>;
4267 hysteresis = <1000>;
4274 trip = <&cpu7_bottom_alert0>;
4275 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4276 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4277 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4278 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4281 trip = <&cpu7_bottom_alert1>;
4282 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4283 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4284 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4285 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4291 polling-delay-passive = <250>;
4292 polling-delay = <1000>;
4294 thermal-sensors = <&tsens0 0>;
4297 aoss0_alert0: trip-point0 {
4298 temperature = <90000>;
4299 hysteresis = <2000>;
4306 polling-delay-passive = <250>;
4307 polling-delay = <1000>;
4309 thermal-sensors = <&tsens0 5>;
4312 cluster0_alert0: trip-point0 {
4313 temperature = <90000>;
4314 hysteresis = <2000>;
4317 cluster0_crit: cluster0_crit {
4318 temperature = <110000>;
4319 hysteresis = <2000>;
4326 polling-delay-passive = <250>;
4327 polling-delay = <1000>;
4329 thermal-sensors = <&tsens0 6>;
4332 cluster1_alert0: trip-point0 {
4333 temperature = <90000>;
4334 hysteresis = <2000>;
4337 cluster1_crit: cluster1_crit {
4338 temperature = <110000>;
4339 hysteresis = <2000>;
4346 polling-delay-passive = <250>;
4347 polling-delay = <1000>;
4349 thermal-sensors = <&tsens0 15>;
4352 gpu1_alert0: trip-point0 {
4353 temperature = <90000>;
4354 hysteresis = <2000>;
4361 polling-delay-passive = <250>;
4362 polling-delay = <1000>;
4364 thermal-sensors = <&tsens1 0>;
4367 aoss1_alert0: trip-point0 {
4368 temperature = <90000>;
4369 hysteresis = <2000>;
4376 polling-delay-passive = <250>;
4377 polling-delay = <1000>;
4379 thermal-sensors = <&tsens1 1>;
4382 wlan_alert0: trip-point0 {
4383 temperature = <90000>;
4384 hysteresis = <2000>;
4391 polling-delay-passive = <250>;
4392 polling-delay = <1000>;
4394 thermal-sensors = <&tsens1 2>;
4397 video_alert0: trip-point0 {
4398 temperature = <90000>;
4399 hysteresis = <2000>;
4406 polling-delay-passive = <250>;
4407 polling-delay = <1000>;
4409 thermal-sensors = <&tsens1 3>;
4412 mem_alert0: trip-point0 {
4413 temperature = <90000>;
4414 hysteresis = <2000>;
4421 polling-delay-passive = <250>;
4422 polling-delay = <1000>;
4424 thermal-sensors = <&tsens1 4>;
4427 q6_hvx_alert0: trip-point0 {
4428 temperature = <90000>;
4429 hysteresis = <2000>;
4436 polling-delay-passive = <250>;
4437 polling-delay = <1000>;
4439 thermal-sensors = <&tsens1 5>;
4442 camera_alert0: trip-point0 {
4443 temperature = <90000>;
4444 hysteresis = <2000>;
4451 polling-delay-passive = <250>;
4452 polling-delay = <1000>;
4454 thermal-sensors = <&tsens1 6>;
4457 compute_alert0: trip-point0 {
4458 temperature = <90000>;
4459 hysteresis = <2000>;
4466 polling-delay-passive = <250>;
4467 polling-delay = <1000>;
4469 thermal-sensors = <&tsens1 7>;
4472 npu_alert0: trip-point0 {
4473 temperature = <90000>;
4474 hysteresis = <2000>;
4480 gpu-thermal-bottom {
4481 polling-delay-passive = <250>;
4482 polling-delay = <1000>;
4484 thermal-sensors = <&tsens1 8>;
4487 gpu2_alert0: trip-point0 {
4488 temperature = <90000>;
4489 hysteresis = <2000>;