arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-aoss-qmp.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 i2c9 = &i2c9;
  34                 i2c10 = &i2c10;
  35                 i2c11 = &i2c11;
  36                 i2c12 = &i2c12;
  37                 i2c13 = &i2c13;
  38                 i2c14 = &i2c14;
  39                 i2c15 = &i2c15;
  40                 i2c16 = &i2c16;
  41                 i2c17 = &i2c17;
  42                 i2c18 = &i2c18;
  43                 i2c19 = &i2c19;
  44                 spi0 = &spi0;
  45                 spi1 = &spi1;
  46                 spi2 = &spi2;
  47                 spi3 = &spi3;
  48                 spi4 = &spi4;
  49                 spi5 = &spi5;
  50                 spi6 = &spi6;
  51                 spi7 = &spi7;
  52                 spi8 = &spi8;
  53                 spi9 = &spi9;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56                 spi12 = &spi12;
  57                 spi13 = &spi13;
  58                 spi14 = &spi14;
  59                 spi15 = &spi15;
  60                 spi16 = &spi16;
  61                 spi17 = &spi17;
  62                 spi18 = &spi18;
  63                 spi19 = &spi19;
  64         };
  65
  66         chosen { };
  67
  68         clocks {
  69                 xo_board: xo-board {
  70                         compatible = "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <38400000>;
  73                         clock-output-names = "xo_board";
  74                 };
  75
  76                 sleep_clk: sleep-clk {
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <32768>;
  79                         #clock-cells = <0>;
  80                 };
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 CPU0: cpu@0 {
  88                         device_type = "cpu";
  89                         compatible = "qcom,kryo485";
  90                         reg = <0x0 0x0>;
  91                         enable-method = "psci";
  92                         next-level-cache = <&L2_0>;
  93                         qcom,freq-domain = <&cpufreq_hw 0>;
  94                         #cooling-cells = <2>;
  95                         L2_0: l2-cache {
  96                                 compatible = "cache";
  97                                 next-level-cache = <&L3_0>;
  98                                 L3_0: l3-cache {
  99                                         compatible = "cache";
 100                                 };
 101                         };
 102                 };
 103
 104                 CPU1: cpu@100 {
 105                         device_type = "cpu";
 106                         compatible = "qcom,kryo485";
 107                         reg = <0x0 0x100>;
 108                         enable-method = "psci";
 109                         next-level-cache = <&L2_100>;
 110                         qcom,freq-domain = <&cpufreq_hw 0>;
 111                         #cooling-cells = <2>;
 112                         L2_100: l2-cache {
 113                                 compatible = "cache";
 114                                 next-level-cache = <&L3_0>;
 115                         };
 116                 };
 117
 118                 CPU2: cpu@200 {
 119                         device_type = "cpu";
 120                         compatible = "qcom,kryo485";
 121                         reg = <0x0 0x200>;
 122                         enable-method = "psci";
 123                         next-level-cache = <&L2_200>;
 124                         qcom,freq-domain = <&cpufreq_hw 0>;
 125                         #cooling-cells = <2>;
 126                         L2_200: l2-cache {
 127                                 compatible = "cache";
 128                                 next-level-cache = <&L3_0>;
 129                         };
 130                 };
 131
 132                 CPU3: cpu@300 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo485";
 135                         reg = <0x0 0x300>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&L2_300>;
 138                         qcom,freq-domain = <&cpufreq_hw 0>;
 139                         #cooling-cells = <2>;
 140                         L2_300: l2-cache {
 141                                 compatible = "cache";
 142                                 next-level-cache = <&L3_0>;
 143                         };
 144                 };
 145
 146                 CPU4: cpu@400 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo485";
 149                         reg = <0x0 0x400>;
 150                         enable-method = "psci";
 151                         next-level-cache = <&L2_400>;
 152                         qcom,freq-domain = <&cpufreq_hw 1>;
 153                         #cooling-cells = <2>;
 154                         L2_400: l2-cache {
 155                                 compatible = "cache";
 156                                 next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159
 160                 CPU5: cpu@500 {
 161                         device_type = "cpu";
 162                         compatible = "qcom,kryo485";
 163                         reg = <0x0 0x500>;
 164                         enable-method = "psci";
 165                         next-level-cache = <&L2_500>;
 166                         qcom,freq-domain = <&cpufreq_hw 1>;
 167                         #cooling-cells = <2>;
 168                         L2_500: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172
 173                 };
 174
 175                 CPU6: cpu@600 {
 176                         device_type = "cpu";
 177                         compatible = "qcom,kryo485";
 178                         reg = <0x0 0x600>;
 179                         enable-method = "psci";
 180                         next-level-cache = <&L2_600>;
 181                         qcom,freq-domain = <&cpufreq_hw 1>;
 182                         #cooling-cells = <2>;
 183                         L2_600: l2-cache {
 184                                 compatible = "cache";
 185                                 next-level-cache = <&L3_0>;
 186                         };
 187                 };
 188
 189                 CPU7: cpu@700 {
 190                         device_type = "cpu";
 191                         compatible = "qcom,kryo485";
 192                         reg = <0x0 0x700>;
 193                         enable-method = "psci";
 194                         next-level-cache = <&L2_700>;
 195                         qcom,freq-domain = <&cpufreq_hw 2>;
 196                         #cooling-cells = <2>;
 197                         L2_700: l2-cache {
 198                                 compatible = "cache";
 199                                 next-level-cache = <&L3_0>;
 200                         };
 201                 };
 202         };
 203
 204         firmware {
 205                 scm: scm {
 206                         compatible = "qcom,scm";
 207                         #reset-cells = <1>;
 208                 };
 209         };
 210
 211         memory@80000000 {
 212                 device_type = "memory";
 213                 /* We expect the bootloader to fill in the size */
 214                 reg = <0x0 0x80000000 0x0 0x0>;
 215         };
 216
 217         pmu {
 218                 compatible = "arm,armv8-pmuv3";
 219                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 220         };
 221
 222         psci {
 223                 compatible = "arm,psci-1.0";
 224                 method = "smc";
 225         };
 226
 227         reserved-memory {
 228                 #address-cells = <2>;
 229                 #size-cells = <2>;
 230                 ranges;
 231
 232                 hyp_mem: memory@80000000 {
 233                         reg = <0x0 0x80000000 0x0 0x600000>;
 234                         no-map;
 235                 };
 236
 237                 xbl_aop_mem: memory@80700000 {
 238                         reg = <0x0 0x80700000 0x0 0x160000>;
 239                         no-map;
 240                 };
 241
 242                 cmd_db: memory@80860000 {
 243                         compatible = "qcom,cmd-db";
 244                         reg = <0x0 0x80860000 0x0 0x20000>;
 245                         no-map;
 246                 };
 247
 248                 smem_mem: memory@80900000 {
 249                         reg = <0x0 0x80900000 0x0 0x200000>;
 250                         no-map;
 251                 };
 252
 253                 removed_mem: memory@80b00000 {
 254                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 255                         no-map;
 256                 };
 257
 258                 camera_mem: memory@86200000 {
 259                         reg = <0x0 0x86200000 0x0 0x500000>;
 260                         no-map;
 261                 };
 262
 263                 wlan_mem: memory@86700000 {
 264                         reg = <0x0 0x86700000 0x0 0x100000>;
 265                         no-map;
 266                 };
 267
 268                 ipa_fw_mem: memory@86800000 {
 269                         reg = <0x0 0x86800000 0x0 0x10000>;
 270                         no-map;
 271                 };
 272
 273                 ipa_gsi_mem: memory@86810000 {
 274                         reg = <0x0 0x86810000 0x0 0xa000>;
 275                         no-map;
 276                 };
 277
 278                 gpu_mem: memory@8681a000 {
 279                         reg = <0x0 0x8681a000 0x0 0x2000>;
 280                         no-map;
 281                 };
 282
 283                 npu_mem: memory@86900000 {
 284                         reg = <0x0 0x86900000 0x0 0x500000>;
 285                         no-map;
 286                 };
 287
 288                 video_mem: memory@86e00000 {
 289                         reg = <0x0 0x86e00000 0x0 0x500000>;
 290                         no-map;
 291                 };
 292
 293                 cvp_mem: memory@87300000 {
 294                         reg = <0x0 0x87300000 0x0 0x500000>;
 295                         no-map;
 296                 };
 297
 298                 cdsp_mem: memory@87800000 {
 299                         reg = <0x0 0x87800000 0x0 0x1400000>;
 300                         no-map;
 301                 };
 302
 303                 slpi_mem: memory@88c00000 {
 304                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 305                         no-map;
 306                 };
 307
 308                 adsp_mem: memory@8a100000 {
 309                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 310                         no-map;
 311                 };
 312
 313                 spss_mem: memory@8be00000 {
 314                         reg = <0x0 0x8be00000 0x0 0x100000>;
 315                         no-map;
 316                 };
 317
 318                 cdsp_secure_heap: memory@8bf00000 {
 319                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 320                         no-map;
 321                 };
 322         };
 323
 324         smem: qcom,smem {
 325                 compatible = "qcom,smem";
 326                 memory-region = <&smem_mem>;
 327                 hwlocks = <&tcsr_mutex 3>;
 328         };
 329
 330         smp2p-adsp {
 331                 compatible = "qcom,smp2p";
 332                 qcom,smem = <443>, <429>;
 333                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 334                                              IPCC_MPROC_SIGNAL_SMP2P
 335                                              IRQ_TYPE_EDGE_RISING>;
 336                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 337                                 IPCC_MPROC_SIGNAL_SMP2P>;
 338
 339                 qcom,local-pid = <0>;
 340                 qcom,remote-pid = <2>;
 341
 342                 smp2p_adsp_out: master-kernel {
 343                         qcom,entry-name = "master-kernel";
 344                         #qcom,smem-state-cells = <1>;
 345                 };
 346
 347                 smp2p_adsp_in: slave-kernel {
 348                         qcom,entry-name = "slave-kernel";
 349                         interrupt-controller;
 350                         #interrupt-cells = <2>;
 351                 };
 352         };
 353
 354         smp2p-cdsp {
 355                 compatible = "qcom,smp2p";
 356                 qcom,smem = <94>, <432>;
 357                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 358                                              IPCC_MPROC_SIGNAL_SMP2P
 359                                              IRQ_TYPE_EDGE_RISING>;
 360                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 361                                 IPCC_MPROC_SIGNAL_SMP2P>;
 362
 363                 qcom,local-pid = <0>;
 364                 qcom,remote-pid = <5>;
 365
 366                 smp2p_cdsp_out: master-kernel {
 367                         qcom,entry-name = "master-kernel";
 368                         #qcom,smem-state-cells = <1>;
 369                 };
 370
 371                 smp2p_cdsp_in: slave-kernel {
 372                         qcom,entry-name = "slave-kernel";
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                 };
 376         };
 377
 378         smp2p-slpi {
 379                 compatible = "qcom,smp2p";
 380                 qcom,smem = <481>, <430>;
 381                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 382                                              IPCC_MPROC_SIGNAL_SMP2P
 383                                              IRQ_TYPE_EDGE_RISING>;
 384                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 385                                 IPCC_MPROC_SIGNAL_SMP2P>;
 386
 387                 qcom,local-pid = <0>;
 388                 qcom,remote-pid = <3>;
 389
 390                 smp2p_slpi_out: master-kernel {
 391                         qcom,entry-name = "master-kernel";
 392                         #qcom,smem-state-cells = <1>;
 393                 };
 394
 395                 smp2p_slpi_in: slave-kernel {
 396                         qcom,entry-name = "slave-kernel";
 397                         interrupt-controller;
 398                         #interrupt-cells = <2>;
 399                 };
 400         };
 401
 402         soc: soc@0 {
 403                 #address-cells = <2>;
 404                 #size-cells = <2>;
 405                 ranges = <0 0 0 0 0x10 0>;
 406                 dma-ranges = <0 0 0 0 0x10 0>;
 407                 compatible = "simple-bus";
 408
 409                 gcc: clock-controller@100000 {
 410                         compatible = "qcom,gcc-sm8250";
 411                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 412                         #clock-cells = <1>;
 413                         #reset-cells = <1>;
 414                         #power-domain-cells = <1>;
 415                         clock-names = "bi_tcxo",
 416                                       "bi_tcxo_ao",
 417                                       "sleep_clk";
 418                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 419                                  <&rpmhcc RPMH_CXO_CLK_A>,
 420                                  <&sleep_clk>;
 421                 };
 422
 423                 ipcc: mailbox@408000 {
 424                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 425                         reg = <0 0x00408000 0 0x1000>;
 426                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 427                         interrupt-controller;
 428                         #interrupt-cells = <3>;
 429                         #mbox-cells = <2>;
 430                 };
 431
 432                 rng: rng@793000 {
 433                         compatible = "qcom,prng-ee";
 434                         reg = <0 0x00793000 0 0x1000>;
 435                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 436                         clock-names = "core";
 437                 };
 438
 439                 qup_opp_table: qup-opp-table {
 440                         compatible = "operating-points-v2";
 441
 442                         opp-50000000 {
 443                                 opp-hz = /bits/ 64 <50000000>;
 444                                 required-opps = <&rpmhpd_opp_min_svs>;
 445                         };
 446
 447                         opp-75000000 {
 448                                 opp-hz = /bits/ 64 <75000000>;
 449                                 required-opps = <&rpmhpd_opp_low_svs>;
 450                         };
 451
 452                         opp-120000000 {
 453                                 opp-hz = /bits/ 64 <120000000>;
 454                                 required-opps = <&rpmhpd_opp_svs>;
 455                         };
 456                 };
 457
 458                 qupv3_id_2: geniqup@8c0000 {
 459                         compatible = "qcom,geni-se-qup";
 460                         reg = <0x0 0x008c0000 0x0 0x6000>;
 461                         clock-names = "m-ahb", "s-ahb";
 462                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 463                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 464                         #address-cells = <2>;
 465                         #size-cells = <2>;
 466                         iommus = <&apps_smmu 0x63 0x0>;
 467                         ranges;
 468                         status = "disabled";
 469
 470                         i2c14: i2c@880000 {
 471                                 compatible = "qcom,geni-i2c";
 472                                 reg = <0 0x00880000 0 0x4000>;
 473                                 clock-names = "se";
 474                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 475                                 pinctrl-names = "default";
 476                                 pinctrl-0 = <&qup_i2c14_default>;
 477                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480                                 status = "disabled";
 481                         };
 482
 483                         spi14: spi@880000 {
 484                                 compatible = "qcom,geni-spi";
 485                                 reg = <0 0x00880000 0 0x4000>;
 486                                 clock-names = "se";
 487                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 488                                 pinctrl-names = "default";
 489                                 pinctrl-0 = <&qup_spi14_default>;
 490                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 491                                 #address-cells = <1>;
 492                                 #size-cells = <0>;
 493                                 power-domains = <&rpmhpd SM8250_CX>;
 494                                 operating-points-v2 = <&qup_opp_table>;
 495                                 status = "disabled";
 496                         };
 497
 498                         i2c15: i2c@884000 {
 499                                 compatible = "qcom,geni-i2c";
 500                                 reg = <0 0x00884000 0 0x4000>;
 501                                 clock-names = "se";
 502                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 503                                 pinctrl-names = "default";
 504                                 pinctrl-0 = <&qup_i2c15_default>;
 505                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 506                                 #address-cells = <1>;
 507                                 #size-cells = <0>;
 508                                 status = "disabled";
 509                         };
 510
 511                         spi15: spi@884000 {
 512                                 compatible = "qcom,geni-spi";
 513                                 reg = <0 0x00884000 0 0x4000>;
 514                                 clock-names = "se";
 515                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 516                                 pinctrl-names = "default";
 517                                 pinctrl-0 = <&qup_spi15_default>;
 518                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 519                                 #address-cells = <1>;
 520                                 #size-cells = <0>;
 521                                 power-domains = <&rpmhpd SM8250_CX>;
 522                                 operating-points-v2 = <&qup_opp_table>;
 523                                 status = "disabled";
 524                         };
 525
 526                         i2c16: i2c@888000 {
 527                                 compatible = "qcom,geni-i2c";
 528                                 reg = <0 0x00888000 0 0x4000>;
 529                                 clock-names = "se";
 530                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 531                                 pinctrl-names = "default";
 532                                 pinctrl-0 = <&qup_i2c16_default>;
 533                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 534                                 #address-cells = <1>;
 535                                 #size-cells = <0>;
 536                                 status = "disabled";
 537                         };
 538
 539                         spi16: spi@888000 {
 540                                 compatible = "qcom,geni-spi";
 541                                 reg = <0 0x00888000 0 0x4000>;
 542                                 clock-names = "se";
 543                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 544                                 pinctrl-names = "default";
 545                                 pinctrl-0 = <&qup_spi16_default>;
 546                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 547                                 #address-cells = <1>;
 548                                 #size-cells = <0>;
 549                                 power-domains = <&rpmhpd SM8250_CX>;
 550                                 operating-points-v2 = <&qup_opp_table>;
 551                                 status = "disabled";
 552                         };
 553
 554                         i2c17: i2c@88c000 {
 555                                 compatible = "qcom,geni-i2c";
 556                                 reg = <0 0x0088c000 0 0x4000>;
 557                                 clock-names = "se";
 558                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 559                                 pinctrl-names = "default";
 560                                 pinctrl-0 = <&qup_i2c17_default>;
 561                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 562                                 #address-cells = <1>;
 563                                 #size-cells = <0>;
 564                                 status = "disabled";
 565                         };
 566
 567                         spi17: spi@88c000 {
 568                                 compatible = "qcom,geni-spi";
 569                                 reg = <0 0x0088c000 0 0x4000>;
 570                                 clock-names = "se";
 571                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 572                                 pinctrl-names = "default";
 573                                 pinctrl-0 = <&qup_spi17_default>;
 574                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 575                                 #address-cells = <1>;
 576                                 #size-cells = <0>;
 577                                 power-domains = <&rpmhpd SM8250_CX>;
 578                                 operating-points-v2 = <&qup_opp_table>;
 579                                 status = "disabled";
 580                         };
 581
 582                         uart17: serial@88c000 {
 583                                 compatible = "qcom,geni-uart";
 584                                 reg = <0 0x0088c000 0 0x4000>;
 585                                 clock-names = "se";
 586                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 587                                 pinctrl-names = "default";
 588                                 pinctrl-0 = <&qup_uart17_default>;
 589                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 590                                 power-domains = <&rpmhpd SM8250_CX>;
 591                                 operating-points-v2 = <&qup_opp_table>;
 592                                 status = "disabled";
 593                         };
 594
 595                         i2c18: i2c@890000 {
 596                                 compatible = "qcom,geni-i2c";
 597                                 reg = <0 0x00890000 0 0x4000>;
 598                                 clock-names = "se";
 599                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 600                                 pinctrl-names = "default";
 601                                 pinctrl-0 = <&qup_i2c18_default>;
 602                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 603                                 #address-cells = <1>;
 604                                 #size-cells = <0>;
 605                                 status = "disabled";
 606                         };
 607
 608                         spi18: spi@890000 {
 609                                 compatible = "qcom,geni-spi";
 610                                 reg = <0 0x00890000 0 0x4000>;
 611                                 clock-names = "se";
 612                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 613                                 pinctrl-names = "default";
 614                                 pinctrl-0 = <&qup_spi18_default>;
 615                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 616                                 #address-cells = <1>;
 617                                 #size-cells = <0>;
 618                                 power-domains = <&rpmhpd SM8250_CX>;
 619                                 operating-points-v2 = <&qup_opp_table>;
 620                                 status = "disabled";
 621                         };
 622
 623                         uart18: serial@890000 {
 624                                 compatible = "qcom,geni-uart";
 625                                 reg = <0 0x00890000 0 0x4000>;
 626                                 clock-names = "se";
 627                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 628                                 pinctrl-names = "default";
 629                                 pinctrl-0 = <&qup_uart18_default>;
 630                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 631                                 power-domains = <&rpmhpd SM8250_CX>;
 632                                 operating-points-v2 = <&qup_opp_table>;
 633                                 status = "disabled";
 634                         };
 635
 636                         i2c19: i2c@894000 {
 637                                 compatible = "qcom,geni-i2c";
 638                                 reg = <0 0x00894000 0 0x4000>;
 639                                 clock-names = "se";
 640                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 641                                 pinctrl-names = "default";
 642                                 pinctrl-0 = <&qup_i2c19_default>;
 643                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 644                                 #address-cells = <1>;
 645                                 #size-cells = <0>;
 646                                 status = "disabled";
 647                         };
 648
 649                         spi19: spi@894000 {
 650                                 compatible = "qcom,geni-spi";
 651                                 reg = <0 0x00894000 0 0x4000>;
 652                                 clock-names = "se";
 653                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 654                                 pinctrl-names = "default";
 655                                 pinctrl-0 = <&qup_spi19_default>;
 656                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 657                                 #address-cells = <1>;
 658                                 #size-cells = <0>;
 659                                 power-domains = <&rpmhpd SM8250_CX>;
 660                                 operating-points-v2 = <&qup_opp_table>;
 661                                 status = "disabled";
 662                         };
 663                 };
 664
 665                 qupv3_id_0: geniqup@9c0000 {
 666                         compatible = "qcom,geni-se-qup";
 667                         reg = <0x0 0x009c0000 0x0 0x6000>;
 668                         clock-names = "m-ahb", "s-ahb";
 669                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 670                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 671                         #address-cells = <2>;
 672                         #size-cells = <2>;
 673                         iommus = <&apps_smmu 0x5a3 0x0>;
 674                         ranges;
 675                         status = "disabled";
 676
 677                         i2c0: i2c@980000 {
 678                                 compatible = "qcom,geni-i2c";
 679                                 reg = <0 0x00980000 0 0x4000>;
 680                                 clock-names = "se";
 681                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 682                                 pinctrl-names = "default";
 683                                 pinctrl-0 = <&qup_i2c0_default>;
 684                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 685                                 #address-cells = <1>;
 686                                 #size-cells = <0>;
 687                                 status = "disabled";
 688                         };
 689
 690                         spi0: spi@980000 {
 691                                 compatible = "qcom,geni-spi";
 692                                 reg = <0 0x00980000 0 0x4000>;
 693                                 clock-names = "se";
 694                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 695                                 pinctrl-names = "default";
 696                                 pinctrl-0 = <&qup_spi0_default>;
 697                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 698                                 #address-cells = <1>;
 699                                 #size-cells = <0>;
 700                                 power-domains = <&rpmhpd SM8250_CX>;
 701                                 operating-points-v2 = <&qup_opp_table>;
 702                                 status = "disabled";
 703                         };
 704
 705                         i2c1: i2c@984000 {
 706                                 compatible = "qcom,geni-i2c";
 707                                 reg = <0 0x00984000 0 0x4000>;
 708                                 clock-names = "se";
 709                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 710                                 pinctrl-names = "default";
 711                                 pinctrl-0 = <&qup_i2c1_default>;
 712                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 713                                 #address-cells = <1>;
 714                                 #size-cells = <0>;
 715                                 status = "disabled";
 716                         };
 717
 718                         spi1: spi@984000 {
 719                                 compatible = "qcom,geni-spi";
 720                                 reg = <0 0x00984000 0 0x4000>;
 721                                 clock-names = "se";
 722                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 723                                 pinctrl-names = "default";
 724                                 pinctrl-0 = <&qup_spi1_default>;
 725                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 726                                 #address-cells = <1>;
 727                                 #size-cells = <0>;
 728                                 power-domains = <&rpmhpd SM8250_CX>;
 729                                 operating-points-v2 = <&qup_opp_table>;
 730                                 status = "disabled";
 731                         };
 732
 733                         i2c2: i2c@988000 {
 734                                 compatible = "qcom,geni-i2c";
 735                                 reg = <0 0x00988000 0 0x4000>;
 736                                 clock-names = "se";
 737                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 738                                 pinctrl-names = "default";
 739                                 pinctrl-0 = <&qup_i2c2_default>;
 740                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 741                                 #address-cells = <1>;
 742                                 #size-cells = <0>;
 743                                 status = "disabled";
 744                         };
 745
 746                         spi2: spi@988000 {
 747                                 compatible = "qcom,geni-spi";
 748                                 reg = <0 0x00988000 0 0x4000>;
 749                                 clock-names = "se";
 750                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 751                                 pinctrl-names = "default";
 752                                 pinctrl-0 = <&qup_spi2_default>;
 753                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 power-domains = <&rpmhpd SM8250_CX>;
 757                                 operating-points-v2 = <&qup_opp_table>;
 758                                 status = "disabled";
 759                         };
 760
 761                         uart2: serial@988000 {
 762                                 compatible = "qcom,geni-debug-uart";
 763                                 reg = <0 0x00988000 0 0x4000>;
 764                                 clock-names = "se";
 765                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 766                                 pinctrl-names = "default";
 767                                 pinctrl-0 = <&qup_uart2_default>;
 768                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 769                                 power-domains = <&rpmhpd SM8250_CX>;
 770                                 operating-points-v2 = <&qup_opp_table>;
 771                                 status = "disabled";
 772                         };
 773
 774                         i2c3: i2c@98c000 {
 775                                 compatible = "qcom,geni-i2c";
 776                                 reg = <0 0x0098c000 0 0x4000>;
 777                                 clock-names = "se";
 778                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 779                                 pinctrl-names = "default";
 780                                 pinctrl-0 = <&qup_i2c3_default>;
 781                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 782                                 #address-cells = <1>;
 783                                 #size-cells = <0>;
 784                                 status = "disabled";
 785                         };
 786
 787                         spi3: spi@98c000 {
 788                                 compatible = "qcom,geni-spi";
 789                                 reg = <0 0x0098c000 0 0x4000>;
 790                                 clock-names = "se";
 791                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 792                                 pinctrl-names = "default";
 793                                 pinctrl-0 = <&qup_spi3_default>;
 794                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 795                                 #address-cells = <1>;
 796                                 #size-cells = <0>;
 797                                 power-domains = <&rpmhpd SM8250_CX>;
 798                                 operating-points-v2 = <&qup_opp_table>;
 799                                 status = "disabled";
 800                         };
 801
 802                         i2c4: i2c@990000 {
 803                                 compatible = "qcom,geni-i2c";
 804                                 reg = <0 0x00990000 0 0x4000>;
 805                                 clock-names = "se";
 806                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 807                                 pinctrl-names = "default";
 808                                 pinctrl-0 = <&qup_i2c4_default>;
 809                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 810                                 #address-cells = <1>;
 811                                 #size-cells = <0>;
 812                                 status = "disabled";
 813                         };
 814
 815                         spi4: spi@990000 {
 816                                 compatible = "qcom,geni-spi";
 817                                 reg = <0 0x00990000 0 0x4000>;
 818                                 clock-names = "se";
 819                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 820                                 pinctrl-names = "default";
 821                                 pinctrl-0 = <&qup_spi4_default>;
 822                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 823                                 #address-cells = <1>;
 824                                 #size-cells = <0>;
 825                                 power-domains = <&rpmhpd SM8250_CX>;
 826                                 operating-points-v2 = <&qup_opp_table>;
 827                                 status = "disabled";
 828                         };
 829
 830                         i2c5: i2c@994000 {
 831                                 compatible = "qcom,geni-i2c";
 832                                 reg = <0 0x00994000 0 0x4000>;
 833                                 clock-names = "se";
 834                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 835                                 pinctrl-names = "default";
 836                                 pinctrl-0 = <&qup_i2c5_default>;
 837                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 status = "disabled";
 841                         };
 842
 843                         spi5: spi@994000 {
 844                                 compatible = "qcom,geni-spi";
 845                                 reg = <0 0x00994000 0 0x4000>;
 846                                 clock-names = "se";
 847                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 848                                 pinctrl-names = "default";
 849                                 pinctrl-0 = <&qup_spi5_default>;
 850                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 851                                 #address-cells = <1>;
 852                                 #size-cells = <0>;
 853                                 power-domains = <&rpmhpd SM8250_CX>;
 854                                 operating-points-v2 = <&qup_opp_table>;
 855                                 status = "disabled";
 856                         };
 857
 858                         i2c6: i2c@998000 {
 859                                 compatible = "qcom,geni-i2c";
 860                                 reg = <0 0x00998000 0 0x4000>;
 861                                 clock-names = "se";
 862                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 863                                 pinctrl-names = "default";
 864                                 pinctrl-0 = <&qup_i2c6_default>;
 865                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 866                                 #address-cells = <1>;
 867                                 #size-cells = <0>;
 868                                 status = "disabled";
 869                         };
 870
 871                         spi6: spi@998000 {
 872                                 compatible = "qcom,geni-spi";
 873                                 reg = <0 0x00998000 0 0x4000>;
 874                                 clock-names = "se";
 875                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 876                                 pinctrl-names = "default";
 877                                 pinctrl-0 = <&qup_spi6_default>;
 878                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 power-domains = <&rpmhpd SM8250_CX>;
 882                                 operating-points-v2 = <&qup_opp_table>;
 883                                 status = "disabled";
 884                         };
 885
 886                         uart6: serial@998000 {
 887                                 compatible = "qcom,geni-uart";
 888                                 reg = <0 0x00998000 0 0x4000>;
 889                                 clock-names = "se";
 890                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 891                                 pinctrl-names = "default";
 892                                 pinctrl-0 = <&qup_uart6_default>;
 893                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 894                                 power-domains = <&rpmhpd SM8250_CX>;
 895                                 operating-points-v2 = <&qup_opp_table>;
 896                                 status = "disabled";
 897                         };
 898
 899                         i2c7: i2c@99c000 {
 900                                 compatible = "qcom,geni-i2c";
 901                                 reg = <0 0x0099c000 0 0x4000>;
 902                                 clock-names = "se";
 903                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 904                                 pinctrl-names = "default";
 905                                 pinctrl-0 = <&qup_i2c7_default>;
 906                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909                                 status = "disabled";
 910                         };
 911
 912                         spi7: spi@99c000 {
 913                                 compatible = "qcom,geni-spi";
 914                                 reg = <0 0x0099c000 0 0x4000>;
 915                                 clock-names = "se";
 916                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 917                                 pinctrl-names = "default";
 918                                 pinctrl-0 = <&qup_spi7_default>;
 919                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 power-domains = <&rpmhpd SM8250_CX>;
 923                                 operating-points-v2 = <&qup_opp_table>;
 924                                 status = "disabled";
 925                         };
 926                 };
 927
 928                 qupv3_id_1: geniqup@ac0000 {
 929                         compatible = "qcom,geni-se-qup";
 930                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 931                         clock-names = "m-ahb", "s-ahb";
 932                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 933                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 934                         #address-cells = <2>;
 935                         #size-cells = <2>;
 936                         iommus = <&apps_smmu 0x43 0x0>;
 937                         ranges;
 938                         status = "disabled";
 939
 940                         i2c8: i2c@a80000 {
 941                                 compatible = "qcom,geni-i2c";
 942                                 reg = <0 0x00a80000 0 0x4000>;
 943                                 clock-names = "se";
 944                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 945                                 pinctrl-names = "default";
 946                                 pinctrl-0 = <&qup_i2c8_default>;
 947                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 948                                 #address-cells = <1>;
 949                                 #size-cells = <0>;
 950                                 status = "disabled";
 951                         };
 952
 953                         spi8: spi@a80000 {
 954                                 compatible = "qcom,geni-spi";
 955                                 reg = <0 0x00a80000 0 0x4000>;
 956                                 clock-names = "se";
 957                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 958                                 pinctrl-names = "default";
 959                                 pinctrl-0 = <&qup_spi8_default>;
 960                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 961                                 #address-cells = <1>;
 962                                 #size-cells = <0>;
 963                                 power-domains = <&rpmhpd SM8250_CX>;
 964                                 operating-points-v2 = <&qup_opp_table>;
 965                                 status = "disabled";
 966                         };
 967
 968                         i2c9: i2c@a84000 {
 969                                 compatible = "qcom,geni-i2c";
 970                                 reg = <0 0x00a84000 0 0x4000>;
 971                                 clock-names = "se";
 972                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 973                                 pinctrl-names = "default";
 974                                 pinctrl-0 = <&qup_i2c9_default>;
 975                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978                                 status = "disabled";
 979                         };
 980
 981                         spi9: spi@a84000 {
 982                                 compatible = "qcom,geni-spi";
 983                                 reg = <0 0x00a84000 0 0x4000>;
 984                                 clock-names = "se";
 985                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 986                                 pinctrl-names = "default";
 987                                 pinctrl-0 = <&qup_spi9_default>;
 988                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 989                                 #address-cells = <1>;
 990                                 #size-cells = <0>;
 991                                 power-domains = <&rpmhpd SM8250_CX>;
 992                                 operating-points-v2 = <&qup_opp_table>;
 993                                 status = "disabled";
 994                         };
 995
 996                         i2c10: i2c@a88000 {
 997                                 compatible = "qcom,geni-i2c";
 998                                 reg = <0 0x00a88000 0 0x4000>;
 999                                 clock-names = "se";
1000                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1001                                 pinctrl-names = "default";
1002                                 pinctrl-0 = <&qup_i2c10_default>;
1003                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1004                                 #address-cells = <1>;
1005                                 #size-cells = <0>;
1006                                 status = "disabled";
1007                         };
1008
1009                         spi10: spi@a88000 {
1010                                 compatible = "qcom,geni-spi";
1011                                 reg = <0 0x00a88000 0 0x4000>;
1012                                 clock-names = "se";
1013                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1014                                 pinctrl-names = "default";
1015                                 pinctrl-0 = <&qup_spi10_default>;
1016                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1017                                 #address-cells = <1>;
1018                                 #size-cells = <0>;
1019                                 power-domains = <&rpmhpd SM8250_CX>;
1020                                 operating-points-v2 = <&qup_opp_table>;
1021                                 status = "disabled";
1022                         };
1023
1024                         i2c11: i2c@a8c000 {
1025                                 compatible = "qcom,geni-i2c";
1026                                 reg = <0 0x00a8c000 0 0x4000>;
1027                                 clock-names = "se";
1028                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1029                                 pinctrl-names = "default";
1030                                 pinctrl-0 = <&qup_i2c11_default>;
1031                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1032                                 #address-cells = <1>;
1033                                 #size-cells = <0>;
1034                                 status = "disabled";
1035                         };
1036
1037                         spi11: spi@a8c000 {
1038                                 compatible = "qcom,geni-spi";
1039                                 reg = <0 0x00a8c000 0 0x4000>;
1040                                 clock-names = "se";
1041                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1042                                 pinctrl-names = "default";
1043                                 pinctrl-0 = <&qup_spi11_default>;
1044                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1045                                 #address-cells = <1>;
1046                                 #size-cells = <0>;
1047                                 power-domains = <&rpmhpd SM8250_CX>;
1048                                 operating-points-v2 = <&qup_opp_table>;
1049                                 status = "disabled";
1050                         };
1051
1052                         i2c12: i2c@a90000 {
1053                                 compatible = "qcom,geni-i2c";
1054                                 reg = <0 0x00a90000 0 0x4000>;
1055                                 clock-names = "se";
1056                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1057                                 pinctrl-names = "default";
1058                                 pinctrl-0 = <&qup_i2c12_default>;
1059                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1060                                 #address-cells = <1>;
1061                                 #size-cells = <0>;
1062                                 status = "disabled";
1063                         };
1064
1065                         spi12: spi@a90000 {
1066                                 compatible = "qcom,geni-spi";
1067                                 reg = <0 0x00a90000 0 0x4000>;
1068                                 clock-names = "se";
1069                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1070                                 pinctrl-names = "default";
1071                                 pinctrl-0 = <&qup_spi12_default>;
1072                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1073                                 #address-cells = <1>;
1074                                 #size-cells = <0>;
1075                                 power-domains = <&rpmhpd SM8250_CX>;
1076                                 operating-points-v2 = <&qup_opp_table>;
1077                                 status = "disabled";
1078                         };
1079
1080                         uart12: serial@a90000 {
1081                                 compatible = "qcom,geni-debug-uart";
1082                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1083                                 clock-names = "se";
1084                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1085                                 pinctrl-names = "default";
1086                                 pinctrl-0 = <&qup_uart12_default>;
1087                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1088                                 power-domains = <&rpmhpd SM8250_CX>;
1089                                 operating-points-v2 = <&qup_opp_table>;
1090                                 status = "disabled";
1091                         };
1092
1093                         i2c13: i2c@a94000 {
1094                                 compatible = "qcom,geni-i2c";
1095                                 reg = <0 0x00a94000 0 0x4000>;
1096                                 clock-names = "se";
1097                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1098                                 pinctrl-names = "default";
1099                                 pinctrl-0 = <&qup_i2c13_default>;
1100                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1101                                 #address-cells = <1>;
1102                                 #size-cells = <0>;
1103                                 status = "disabled";
1104                         };
1105
1106                         spi13: spi@a94000 {
1107                                 compatible = "qcom,geni-spi";
1108                                 reg = <0 0x00a94000 0 0x4000>;
1109                                 clock-names = "se";
1110                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1111                                 pinctrl-names = "default";
1112                                 pinctrl-0 = <&qup_spi13_default>;
1113                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1114                                 #address-cells = <1>;
1115                                 #size-cells = <0>;
1116                                 power-domains = <&rpmhpd SM8250_CX>;
1117                                 operating-points-v2 = <&qup_opp_table>;
1118                                 status = "disabled";
1119                         };
1120                 };
1121
1122                 config_noc: interconnect@1500000 {
1123                         compatible = "qcom,sm8250-config-noc";
1124                         reg = <0 0x01500000 0 0xa580>;
1125                         #interconnect-cells = <1>;
1126                         qcom,bcm-voters = <&apps_bcm_voter>;
1127                 };
1128
1129                 system_noc: interconnect@1620000 {
1130                         compatible = "qcom,sm8250-system-noc";
1131                         reg = <0 0x01620000 0 0x1c200>;
1132                         #interconnect-cells = <1>;
1133                         qcom,bcm-voters = <&apps_bcm_voter>;
1134                 };
1135
1136                 mc_virt: interconnect@163d000 {
1137                         compatible = "qcom,sm8250-mc-virt";
1138                         reg = <0 0x0163d000 0 0x1000>;
1139                         #interconnect-cells = <1>;
1140                         qcom,bcm-voters = <&apps_bcm_voter>;
1141                 };
1142
1143                 aggre1_noc: interconnect@16e0000 {
1144                         compatible = "qcom,sm8250-aggre1-noc";
1145                         reg = <0 0x016e0000 0 0x1f180>;
1146                         #interconnect-cells = <1>;
1147                         qcom,bcm-voters = <&apps_bcm_voter>;
1148                 };
1149
1150                 aggre2_noc: interconnect@1700000 {
1151                         compatible = "qcom,sm8250-aggre2-noc";
1152                         reg = <0 0x01700000 0 0x33000>;
1153                         #interconnect-cells = <1>;
1154                         qcom,bcm-voters = <&apps_bcm_voter>;
1155                 };
1156
1157                 compute_noc: interconnect@1733000 {
1158                         compatible = "qcom,sm8250-compute-noc";
1159                         reg = <0 0x01733000 0 0xa180>;
1160                         #interconnect-cells = <1>;
1161                         qcom,bcm-voters = <&apps_bcm_voter>;
1162                 };
1163
1164                 mmss_noc: interconnect@1740000 {
1165                         compatible = "qcom,sm8250-mmss-noc";
1166                         reg = <0 0x01740000 0 0x1f080>;
1167                         #interconnect-cells = <1>;
1168                         qcom,bcm-voters = <&apps_bcm_voter>;
1169                 };
1170
1171                 ufs_mem_hc: ufshc@1d84000 {
1172                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1173                                      "jedec,ufs-2.0";
1174                         reg = <0 0x01d84000 0 0x3000>;
1175                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1176                         phys = <&ufs_mem_phy_lanes>;
1177                         phy-names = "ufsphy";
1178                         lanes-per-direction = <2>;
1179                         #reset-cells = <1>;
1180                         resets = <&gcc GCC_UFS_PHY_BCR>;
1181                         reset-names = "rst";
1182
1183                         power-domains = <&gcc UFS_PHY_GDSC>;
1184
1185                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1186
1187                         clock-names =
1188                                 "core_clk",
1189                                 "bus_aggr_clk",
1190                                 "iface_clk",
1191                                 "core_clk_unipro",
1192                                 "ref_clk",
1193                                 "tx_lane0_sync_clk",
1194                                 "rx_lane0_sync_clk",
1195                                 "rx_lane1_sync_clk";
1196                         clocks =
1197                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1198                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1199                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1200                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1201                                 <&rpmhcc RPMH_CXO_CLK>,
1202                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1203                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1204                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1205                         freq-table-hz =
1206                                 <37500000 300000000>,
1207                                 <0 0>,
1208                                 <0 0>,
1209                                 <37500000 300000000>,
1210                                 <0 0>,
1211                                 <0 0>,
1212                                 <0 0>,
1213                                 <0 0>;
1214
1215                         status = "disabled";
1216                 };
1217
1218                 ufs_mem_phy: phy@1d87000 {
1219                         compatible = "qcom,sm8250-qmp-ufs-phy";
1220                         reg = <0 0x01d87000 0 0x1c0>;
1221                         #address-cells = <2>;
1222                         #size-cells = <2>;
1223                         ranges;
1224                         clock-names = "ref",
1225                                       "ref_aux";
1226                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1227                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1228
1229                         resets = <&ufs_mem_hc 0>;
1230                         reset-names = "ufsphy";
1231                         status = "disabled";
1232
1233                         ufs_mem_phy_lanes: lanes@1d87400 {
1234                                 reg = <0 0x01d87400 0 0x108>,
1235                                       <0 0x01d87600 0 0x1e0>,
1236                                       <0 0x01d87c00 0 0x1dc>,
1237                                       <0 0x01d87800 0 0x108>,
1238                                       <0 0x01d87a00 0 0x1e0>;
1239                                 #phy-cells = <0>;
1240                         };
1241                 };
1242
1243                 ipa_virt: interconnect@1e00000 {
1244                         compatible = "qcom,sm8250-ipa-virt";
1245                         reg = <0 0x01e00000 0 0x1000>;
1246                         #interconnect-cells = <1>;
1247                         qcom,bcm-voters = <&apps_bcm_voter>;
1248                 };
1249
1250                 tcsr_mutex: hwlock@1f40000 {
1251                         compatible = "qcom,tcsr-mutex";
1252                         reg = <0x0 0x01f40000 0x0 0x40000>;
1253                         #hwlock-cells = <1>;
1254                 };
1255
1256                 gpu: gpu@3d00000 {
1257                         /*
1258                          * note: the amd,imageon compatible makes it possible
1259                          * to use the drm/msm driver without the display node,
1260                          * make sure to remove it when display node is added
1261                          */
1262                         compatible = "qcom,adreno-650.2",
1263                                      "qcom,adreno",
1264                                      "amd,imageon";
1265                         #stream-id-cells = <16>;
1266
1267                         reg = <0 0x03d00000 0 0x40000>;
1268                         reg-names = "kgsl_3d0_reg_memory";
1269
1270                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1271
1272                         iommus = <&adreno_smmu 0 0x401>;
1273
1274                         operating-points-v2 = <&gpu_opp_table>;
1275
1276                         qcom,gmu = <&gmu>;
1277
1278                         zap-shader {
1279                                 memory-region = <&gpu_mem>;
1280                         };
1281
1282                         /* note: downstream checks gpu binning for 670 Mhz */
1283                         gpu_opp_table: opp-table {
1284                                 compatible = "operating-points-v2";
1285
1286                                 opp-670000000 {
1287                                         opp-hz = /bits/ 64 <670000000>;
1288                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1289                                 };
1290
1291                                 opp-587000000 {
1292                                         opp-hz = /bits/ 64 <587000000>;
1293                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1294                                 };
1295
1296                                 opp-525000000 {
1297                                         opp-hz = /bits/ 64 <525000000>;
1298                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1299                                 };
1300
1301                                 opp-490000000 {
1302                                         opp-hz = /bits/ 64 <490000000>;
1303                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1304                                 };
1305
1306                                 opp-441600000 {
1307                                         opp-hz = /bits/ 64 <441600000>;
1308                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1309                                 };
1310
1311                                 opp-400000000 {
1312                                         opp-hz = /bits/ 64 <400000000>;
1313                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1314                                 };
1315
1316                                 opp-305000000 {
1317                                         opp-hz = /bits/ 64 <305000000>;
1318                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1319                                 };
1320                         };
1321                 };
1322
1323                 gmu: gmu@3d6a000 {
1324                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1325
1326                         reg = <0 0x03d6a000 0 0x30000>,
1327                               <0 0x3de0000 0 0x10000>,
1328                               <0 0xb290000 0 0x10000>,
1329                               <0 0xb490000 0 0x10000>;
1330                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1331
1332                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1333                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1334                         interrupt-names = "hfi", "gmu";
1335
1336                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1337                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1338                                  <&gpucc GPU_CC_CXO_CLK>,
1339                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1340                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1341                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1342
1343                         power-domains = <&gpucc GPU_CX_GDSC>,
1344                                         <&gpucc GPU_GX_GDSC>;
1345                         power-domain-names = "cx", "gx";
1346
1347                         iommus = <&adreno_smmu 5 0x400>;
1348
1349                         operating-points-v2 = <&gmu_opp_table>;
1350
1351                         gmu_opp_table: opp-table {
1352                                 compatible = "operating-points-v2";
1353
1354                                 opp-200000000 {
1355                                         opp-hz = /bits/ 64 <200000000>;
1356                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1357                                 };
1358                         };
1359                 };
1360
1361                 gpucc: clock-controller@3d90000 {
1362                         compatible = "qcom,sm8250-gpucc";
1363                         reg = <0 0x03d90000 0 0x9000>;
1364                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1365                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1366                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1367                         clock-names = "bi_tcxo",
1368                                       "gcc_gpu_gpll0_clk_src",
1369                                       "gcc_gpu_gpll0_div_clk_src";
1370                         #clock-cells = <1>;
1371                         #reset-cells = <1>;
1372                         #power-domain-cells = <1>;
1373                 };
1374
1375                 adreno_smmu: iommu@3da0000 {
1376                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1377                         reg = <0 0x03da0000 0 0x10000>;
1378                         #iommu-cells = <2>;
1379                         #global-interrupts = <2>;
1380                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1381                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1382                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1383                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1384                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1385                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1386                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1387                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1388                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1389                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1390                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1391                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1392                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1393                         clock-names = "ahb", "bus", "iface";
1394
1395                         power-domains = <&gpucc GPU_CX_GDSC>;
1396                 };
1397
1398                 slpi: remoteproc@5c00000 {
1399                         compatible = "qcom,sm8250-slpi-pas";
1400                         reg = <0 0x05c00000 0 0x4000>;
1401
1402                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1403                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1404                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1405                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1406                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1407                         interrupt-names = "wdog", "fatal", "ready",
1408                                           "handover", "stop-ack";
1409
1410                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1411                         clock-names = "xo";
1412
1413                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1414                                         <&rpmhpd SM8250_LCX>,
1415                                         <&rpmhpd SM8250_LMX>;
1416                         power-domain-names = "load_state", "lcx", "lmx";
1417
1418                         memory-region = <&slpi_mem>;
1419
1420                         qcom,smem-states = <&smp2p_slpi_out 0>;
1421                         qcom,smem-state-names = "stop";
1422
1423                         status = "disabled";
1424
1425                         glink-edge {
1426                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1427                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1428                                                              IRQ_TYPE_EDGE_RISING>;
1429                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1430                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1431
1432                                 label = "slpi";
1433                                 qcom,remote-pid = <3>;
1434
1435                                 fastrpc {
1436                                         compatible = "qcom,fastrpc";
1437                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1438                                         label = "sdsp";
1439                                         #address-cells = <1>;
1440                                         #size-cells = <0>;
1441
1442                                         compute-cb@1 {
1443                                                 compatible = "qcom,fastrpc-compute-cb";
1444                                                 reg = <1>;
1445                                                 iommus = <&apps_smmu 0x0541 0x0>;
1446                                         };
1447
1448                                         compute-cb@2 {
1449                                                 compatible = "qcom,fastrpc-compute-cb";
1450                                                 reg = <2>;
1451                                                 iommus = <&apps_smmu 0x0542 0x0>;
1452                                         };
1453
1454                                         compute-cb@3 {
1455                                                 compatible = "qcom,fastrpc-compute-cb";
1456                                                 reg = <3>;
1457                                                 iommus = <&apps_smmu 0x0543 0x0>;
1458                                                 /* note: shared-cb = <4> in downstream */
1459                                         };
1460                                 };
1461                         };
1462                 };
1463
1464                 cdsp: remoteproc@8300000 {
1465                         compatible = "qcom,sm8250-cdsp-pas";
1466                         reg = <0 0x08300000 0 0x10000>;
1467
1468                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1469                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1470                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1471                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1472                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1473                         interrupt-names = "wdog", "fatal", "ready",
1474                                           "handover", "stop-ack";
1475
1476                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1477                         clock-names = "xo";
1478
1479                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1480                                         <&rpmhpd SM8250_CX>;
1481                         power-domain-names = "load_state", "cx";
1482
1483                         memory-region = <&cdsp_mem>;
1484
1485                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1486                         qcom,smem-state-names = "stop";
1487
1488                         status = "disabled";
1489
1490                         glink-edge {
1491                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1492                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1493                                                              IRQ_TYPE_EDGE_RISING>;
1494                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1495                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1496
1497                                 label = "cdsp";
1498                                 qcom,remote-pid = <5>;
1499
1500                                 fastrpc {
1501                                         compatible = "qcom,fastrpc";
1502                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1503                                         label = "cdsp";
1504                                         #address-cells = <1>;
1505                                         #size-cells = <0>;
1506
1507                                         compute-cb@1 {
1508                                                 compatible = "qcom,fastrpc-compute-cb";
1509                                                 reg = <1>;
1510                                                 iommus = <&apps_smmu 0x1001 0x0460>;
1511                                         };
1512
1513                                         compute-cb@2 {
1514                                                 compatible = "qcom,fastrpc-compute-cb";
1515                                                 reg = <2>;
1516                                                 iommus = <&apps_smmu 0x1002 0x0460>;
1517                                         };
1518
1519                                         compute-cb@3 {
1520                                                 compatible = "qcom,fastrpc-compute-cb";
1521                                                 reg = <3>;
1522                                                 iommus = <&apps_smmu 0x1003 0x0460>;
1523                                         };
1524
1525                                         compute-cb@4 {
1526                                                 compatible = "qcom,fastrpc-compute-cb";
1527                                                 reg = <4>;
1528                                                 iommus = <&apps_smmu 0x1004 0x0460>;
1529                                         };
1530
1531                                         compute-cb@5 {
1532                                                 compatible = "qcom,fastrpc-compute-cb";
1533                                                 reg = <5>;
1534                                                 iommus = <&apps_smmu 0x1005 0x0460>;
1535                                         };
1536
1537                                         compute-cb@6 {
1538                                                 compatible = "qcom,fastrpc-compute-cb";
1539                                                 reg = <6>;
1540                                                 iommus = <&apps_smmu 0x1006 0x0460>;
1541                                         };
1542
1543                                         compute-cb@7 {
1544                                                 compatible = "qcom,fastrpc-compute-cb";
1545                                                 reg = <7>;
1546                                                 iommus = <&apps_smmu 0x1007 0x0460>;
1547                                         };
1548
1549                                         compute-cb@8 {
1550                                                 compatible = "qcom,fastrpc-compute-cb";
1551                                                 reg = <8>;
1552                                                 iommus = <&apps_smmu 0x1008 0x0460>;
1553                                         };
1554
1555                                         /* note: secure cb9 in downstream */
1556                                 };
1557                         };
1558                 };
1559
1560                 usb_1_hsphy: phy@88e3000 {
1561                         compatible = "qcom,sm8250-usb-hs-phy",
1562                                      "qcom,usb-snps-hs-7nm-phy";
1563                         reg = <0 0x088e3000 0 0x400>;
1564                         status = "disabled";
1565                         #phy-cells = <0>;
1566
1567                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1568                         clock-names = "ref";
1569
1570                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1571                 };
1572
1573                 usb_2_hsphy: phy@88e4000 {
1574                         compatible = "qcom,sm8250-usb-hs-phy",
1575                                      "qcom,usb-snps-hs-7nm-phy";
1576                         reg = <0 0x088e4000 0 0x400>;
1577                         status = "disabled";
1578                         #phy-cells = <0>;
1579
1580                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1581                         clock-names = "ref";
1582
1583                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1584                 };
1585
1586                 usb_1_qmpphy: phy@88e9000 {
1587                         compatible = "qcom,sm8250-qmp-usb3-phy";
1588                         reg = <0 0x088e9000 0 0x200>,
1589                               <0 0x088e8000 0 0x20>;
1590                         reg-names = "reg-base", "dp_com";
1591                         status = "disabled";
1592                         #clock-cells = <1>;
1593                         #address-cells = <2>;
1594                         #size-cells = <2>;
1595                         ranges;
1596
1597                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1598                                  <&rpmhcc RPMH_CXO_CLK>,
1599                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1600                         clock-names = "aux", "ref_clk_src", "com_aux";
1601
1602                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1603                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
1604                         reset-names = "phy", "common";
1605
1606                         usb_1_ssphy: lanes@88e9200 {
1607                                 reg = <0 0x088e9200 0 0x200>,
1608                                       <0 0x088e9400 0 0x200>,
1609                                       <0 0x088e9c00 0 0x400>,
1610                                       <0 0x088e9600 0 0x200>,
1611                                       <0 0x088e9800 0 0x200>,
1612                                       <0 0x088e9a00 0 0x100>;
1613                                 #phy-cells = <0>;
1614                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1615                                 clock-names = "pipe0";
1616                                 clock-output-names = "usb3_phy_pipe_clk_src";
1617                         };
1618                 };
1619
1620                 usb_2_qmpphy: phy@88eb000 {
1621                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
1622                         reg = <0 0x088eb000 0 0x200>;
1623                         status = "disabled";
1624                         #clock-cells = <1>;
1625                         #address-cells = <2>;
1626                         #size-cells = <2>;
1627                         ranges;
1628
1629                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1630                                  <&rpmhcc RPMH_CXO_CLK>,
1631                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
1632                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1633                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1634
1635                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1636                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
1637                         reset-names = "phy", "common";
1638
1639                         usb_2_ssphy: lane@88eb200 {
1640                                 reg = <0 0x088eb200 0 0x200>,
1641                                       <0 0x088eb400 0 0x200>,
1642                                       <0 0x088eb800 0 0x800>;
1643                                 #phy-cells = <0>;
1644                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1645                                 clock-names = "pipe0";
1646                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1647                         };
1648                 };
1649
1650                 sdhc_2: sdhci@8804000 {
1651                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
1652                         reg = <0 0x08804000 0 0x1000>;
1653
1654                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1655                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1656                         interrupt-names = "hc_irq", "pwr_irq";
1657
1658                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1659                                  <&gcc GCC_SDCC2_APPS_CLK>,
1660                                  <&xo_board>;
1661                         clock-names = "iface", "core", "xo";
1662                         iommus = <&apps_smmu 0x4a0 0x0>;
1663                         qcom,dll-config = <0x0007642c>;
1664                         qcom,ddr-config = <0x80040868>;
1665                         power-domains = <&rpmhpd SM8250_CX>;
1666                         operating-points-v2 = <&sdhc2_opp_table>;
1667
1668                         status = "disabled";
1669
1670                         sdhc2_opp_table: sdhc2-opp-table {
1671                                 compatible = "operating-points-v2";
1672
1673                                 opp-19200000 {
1674                                         opp-hz = /bits/ 64 <19200000>;
1675                                         required-opps = <&rpmhpd_opp_min_svs>;
1676                                 };
1677
1678                                 opp-50000000 {
1679                                         opp-hz = /bits/ 64 <50000000>;
1680                                         required-opps = <&rpmhpd_opp_low_svs>;
1681                                 };
1682
1683                                 opp-100000000 {
1684                                         opp-hz = /bits/ 64 <100000000>;
1685                                         required-opps = <&rpmhpd_opp_svs>;
1686                                 };
1687
1688                                 opp-202000000 {
1689                                         opp-hz = /bits/ 64 <202000000>;
1690                                         required-opps = <&rpmhpd_opp_svs_l1>;
1691                                 };
1692                         };
1693                 };
1694
1695                 dc_noc: interconnect@90c0000 {
1696                         compatible = "qcom,sm8250-dc-noc";
1697                         reg = <0 0x090c0000 0 0x4200>;
1698                         #interconnect-cells = <1>;
1699                         qcom,bcm-voters = <&apps_bcm_voter>;
1700                 };
1701
1702                 gem_noc: interconnect@9100000 {
1703                         compatible = "qcom,sm8250-gem-noc";
1704                         reg = <0 0x09100000 0 0xb4000>;
1705                         #interconnect-cells = <1>;
1706                         qcom,bcm-voters = <&apps_bcm_voter>;
1707                 };
1708
1709                 npu_noc: interconnect@9990000 {
1710                         compatible = "qcom,sm8250-npu-noc";
1711                         reg = <0 0x09990000 0 0x1600>;
1712                         #interconnect-cells = <1>;
1713                         qcom,bcm-voters = <&apps_bcm_voter>;
1714                 };
1715
1716                 usb_1: usb@a6f8800 {
1717                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1718                         reg = <0 0x0a6f8800 0 0x400>;
1719                         status = "disabled";
1720                         #address-cells = <2>;
1721                         #size-cells = <2>;
1722                         ranges;
1723                         dma-ranges;
1724
1725                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1726                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1727                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1728                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1729                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1730                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1731                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1732                                       "sleep", "xo";
1733
1734                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1735                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1736                         assigned-clock-rates = <19200000>, <200000000>;
1737
1738                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1739                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1740                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1741                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1742                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1743                                           "dm_hs_phy_irq", "ss_phy_irq";
1744
1745                         power-domains = <&gcc USB30_PRIM_GDSC>;
1746
1747                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1748
1749                         usb_1_dwc3: dwc3@a600000 {
1750                                 compatible = "snps,dwc3";
1751                                 reg = <0 0x0a600000 0 0xcd00>;
1752                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1753                                 iommus = <&apps_smmu 0x0 0x0>;
1754                                 snps,dis_u2_susphy_quirk;
1755                                 snps,dis_enblslpm_quirk;
1756                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1757                                 phy-names = "usb2-phy", "usb3-phy";
1758                         };
1759                 };
1760
1761                 usb_2: usb@a8f8800 {
1762                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
1763                         reg = <0 0x0a8f8800 0 0x400>;
1764                         status = "disabled";
1765                         #address-cells = <2>;
1766                         #size-cells = <2>;
1767                         ranges;
1768                         dma-ranges;
1769
1770                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1771                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1772                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1773                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1774                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1775                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
1776                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1777                                       "sleep", "xo";
1778
1779                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1780                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1781                         assigned-clock-rates = <19200000>, <200000000>;
1782
1783                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1784                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1785                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1786                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
1787                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1788                                           "dm_hs_phy_irq", "ss_phy_irq";
1789
1790                         power-domains = <&gcc USB30_SEC_GDSC>;
1791
1792                         resets = <&gcc GCC_USB30_SEC_BCR>;
1793
1794                         usb_2_dwc3: dwc3@a800000 {
1795                                 compatible = "snps,dwc3";
1796                                 reg = <0 0x0a800000 0 0xcd00>;
1797                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1798                                 iommus = <&apps_smmu 0x20 0>;
1799                                 snps,dis_u2_susphy_quirk;
1800                                 snps,dis_enblslpm_quirk;
1801                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1802                                 phy-names = "usb2-phy", "usb3-phy";
1803                         };
1804                 };
1805
1806                 pdc: interrupt-controller@b220000 {
1807                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
1808                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1809                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1810                                           <125 63 1>, <126 716 12>;
1811                         #interrupt-cells = <2>;
1812                         interrupt-parent = <&intc>;
1813                         interrupt-controller;
1814                 };
1815
1816                 tsens0: thermal-sensor@c263000 {
1817                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1818                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1819                               <0 0x0c222000 0 0x1ff>; /* SROT */
1820                         #qcom,sensors = <16>;
1821                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1822                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1823                         interrupt-names = "uplow", "critical";
1824                         #thermal-sensor-cells = <1>;
1825                 };
1826
1827                 tsens1: thermal-sensor@c265000 {
1828                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1829                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1830                               <0 0x0c223000 0 0x1ff>; /* SROT */
1831                         #qcom,sensors = <9>;
1832                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1833                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1834                         interrupt-names = "uplow", "critical";
1835                         #thermal-sensor-cells = <1>;
1836                 };
1837
1838                 aoss_qmp: qmp@c300000 {
1839                         compatible = "qcom,sm8250-aoss-qmp";
1840                         reg = <0 0x0c300000 0 0x100000>;
1841                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1842                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
1843                                                      IRQ_TYPE_EDGE_RISING>;
1844                         mboxes = <&ipcc IPCC_CLIENT_AOP
1845                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
1846
1847                         #clock-cells = <0>;
1848                         #power-domain-cells = <1>;
1849                 };
1850
1851                 spmi_bus: spmi@c440000 {
1852                         compatible = "qcom,spmi-pmic-arb";
1853                         reg = <0x0 0x0c440000 0x0 0x0001100>,
1854                               <0x0 0x0c600000 0x0 0x2000000>,
1855                               <0x0 0x0e600000 0x0 0x0100000>,
1856                               <0x0 0x0e700000 0x0 0x00a0000>,
1857                               <0x0 0x0c40a000 0x0 0x0026000>;
1858                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1859                         interrupt-names = "periph_irq";
1860                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1861                         qcom,ee = <0>;
1862                         qcom,channel = <0>;
1863                         #address-cells = <2>;
1864                         #size-cells = <0>;
1865                         interrupt-controller;
1866                         #interrupt-cells = <4>;
1867                 };
1868
1869                 tlmm: pinctrl@f100000 {
1870                         compatible = "qcom,sm8250-pinctrl";
1871                         reg = <0 0x0f100000 0 0x300000>,
1872                               <0 0x0f500000 0 0x300000>,
1873                               <0 0x0f900000 0 0x300000>;
1874                         reg-names = "west", "south", "north";
1875                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1876                         gpio-controller;
1877                         #gpio-cells = <2>;
1878                         interrupt-controller;
1879                         #interrupt-cells = <2>;
1880                         gpio-ranges = <&tlmm 0 0 180>;
1881                         wakeup-parent = <&pdc>;
1882
1883                         qup_i2c0_default: qup-i2c0-default {
1884                                 mux {
1885                                         pins = "gpio28", "gpio29";
1886                                         function = "qup0";
1887                                 };
1888
1889                                 config {
1890                                         pins = "gpio28", "gpio29";
1891                                         drive-strength = <2>;
1892                                         bias-disable;
1893                                 };
1894                         };
1895
1896                         qup_i2c1_default: qup-i2c1-default {
1897                                 pinmux {
1898                                         pins = "gpio4", "gpio5";
1899                                         function = "qup1";
1900                                 };
1901
1902                                 config {
1903                                         pins = "gpio4", "gpio5";
1904                                         drive-strength = <2>;
1905                                         bias-disable;
1906                                 };
1907                         };
1908
1909                         qup_i2c2_default: qup-i2c2-default {
1910                                 mux {
1911                                         pins = "gpio115", "gpio116";
1912                                         function = "qup2";
1913                                 };
1914
1915                                 config {
1916                                         pins = "gpio115", "gpio116";
1917                                         drive-strength = <2>;
1918                                         bias-disable;
1919                                 };
1920                         };
1921
1922                         qup_i2c3_default: qup-i2c3-default {
1923                                 mux {
1924                                         pins = "gpio119", "gpio120";
1925                                         function = "qup3";
1926                                 };
1927
1928                                 config {
1929                                         pins = "gpio119", "gpio120";
1930                                         drive-strength = <2>;
1931                                         bias-disable;
1932                                 };
1933                         };
1934
1935                         qup_i2c4_default: qup-i2c4-default {
1936                                 mux {
1937                                         pins = "gpio8", "gpio9";
1938                                         function = "qup4";
1939                                 };
1940
1941                                 config {
1942                                         pins = "gpio8", "gpio9";
1943                                         drive-strength = <2>;
1944                                         bias-disable;
1945                                 };
1946                         };
1947
1948                         qup_i2c5_default: qup-i2c5-default {
1949                                 mux {
1950                                         pins = "gpio12", "gpio13";
1951                                         function = "qup5";
1952                                 };
1953
1954                                 config {
1955                                         pins = "gpio12", "gpio13";
1956                                         drive-strength = <2>;
1957                                         bias-disable;
1958                                 };
1959                         };
1960
1961                         qup_i2c6_default: qup-i2c6-default {
1962                                 mux {
1963                                         pins = "gpio16", "gpio17";
1964                                         function = "qup6";
1965                                 };
1966
1967                                 config {
1968                                         pins = "gpio16", "gpio17";
1969                                         drive-strength = <2>;
1970                                         bias-disable;
1971                                 };
1972                         };
1973
1974                         qup_i2c7_default: qup-i2c7-default {
1975                                 mux {
1976                                         pins = "gpio20", "gpio21";
1977                                         function = "qup7";
1978                                 };
1979
1980                                 config {
1981                                         pins = "gpio20", "gpio21";
1982                                         drive-strength = <2>;
1983                                         bias-disable;
1984                                 };
1985                         };
1986
1987                         qup_i2c8_default: qup-i2c8-default {
1988                                 mux {
1989                                         pins = "gpio24", "gpio25";
1990                                         function = "qup8";
1991                                 };
1992
1993                                 config {
1994                                         pins = "gpio24", "gpio25";
1995                                         drive-strength = <2>;
1996                                         bias-disable;
1997                                 };
1998                         };
1999
2000                         qup_i2c9_default: qup-i2c9-default {
2001                                 mux {
2002                                         pins = "gpio125", "gpio126";
2003                                         function = "qup9";
2004                                 };
2005
2006                                 config {
2007                                         pins = "gpio125", "gpio126";
2008                                         drive-strength = <2>;
2009                                         bias-disable;
2010                                 };
2011                         };
2012
2013                         qup_i2c10_default: qup-i2c10-default {
2014                                 mux {
2015                                         pins = "gpio129", "gpio130";
2016                                         function = "qup10";
2017                                 };
2018
2019                                 config {
2020                                         pins = "gpio129", "gpio130";
2021                                         drive-strength = <2>;
2022                                         bias-disable;
2023                                 };
2024                         };
2025
2026                         qup_i2c11_default: qup-i2c11-default {
2027                                 mux {
2028                                         pins = "gpio60", "gpio61";
2029                                         function = "qup11";
2030                                 };
2031
2032                                 config {
2033                                         pins = "gpio60", "gpio61";
2034                                         drive-strength = <2>;
2035                                         bias-disable;
2036                                 };
2037                         };
2038
2039                         qup_i2c12_default: qup-i2c12-default {
2040                                 mux {
2041                                         pins = "gpio32", "gpio33";
2042                                         function = "qup12";
2043                                 };
2044
2045                                 config {
2046                                         pins = "gpio32", "gpio33";
2047                                         drive-strength = <2>;
2048                                         bias-disable;
2049                                 };
2050                         };
2051
2052                         qup_i2c13_default: qup-i2c13-default {
2053                                 mux {
2054                                         pins = "gpio36", "gpio37";
2055                                         function = "qup13";
2056                                 };
2057
2058                                 config {
2059                                         pins = "gpio36", "gpio37";
2060                                         drive-strength = <2>;
2061                                         bias-disable;
2062                                 };
2063                         };
2064
2065                         qup_i2c14_default: qup-i2c14-default {
2066                                 mux {
2067                                         pins = "gpio40", "gpio41";
2068                                         function = "qup14";
2069                                 };
2070
2071                                 config {
2072                                         pins = "gpio40", "gpio41";
2073                                         drive-strength = <2>;
2074                                         bias-disable;
2075                                 };
2076                         };
2077
2078                         qup_i2c15_default: qup-i2c15-default {
2079                                 mux {
2080                                         pins = "gpio44", "gpio45";
2081                                         function = "qup15";
2082                                 };
2083
2084                                 config {
2085                                         pins = "gpio44", "gpio45";
2086                                         drive-strength = <2>;
2087                                         bias-disable;
2088                                 };
2089                         };
2090
2091                         qup_i2c16_default: qup-i2c16-default {
2092                                 mux {
2093                                         pins = "gpio48", "gpio49";
2094                                         function = "qup16";
2095                                 };
2096
2097                                 config {
2098                                         pins = "gpio48", "gpio49";
2099                                         drive-strength = <2>;
2100                                         bias-disable;
2101                                 };
2102                         };
2103
2104                         qup_i2c17_default: qup-i2c17-default {
2105                                 mux {
2106                                         pins = "gpio52", "gpio53";
2107                                         function = "qup17";
2108                                 };
2109
2110                                 config {
2111                                         pins = "gpio52", "gpio53";
2112                                         drive-strength = <2>;
2113                                         bias-disable;
2114                                 };
2115                         };
2116
2117                         qup_i2c18_default: qup-i2c18-default {
2118                                 mux {
2119                                         pins = "gpio56", "gpio57";
2120                                         function = "qup18";
2121                                 };
2122
2123                                 config {
2124                                         pins = "gpio56", "gpio57";
2125                                         drive-strength = <2>;
2126                                         bias-disable;
2127                                 };
2128                         };
2129
2130                         qup_i2c19_default: qup-i2c19-default {
2131                                 mux {
2132                                         pins = "gpio0", "gpio1";
2133                                         function = "qup19";
2134                                 };
2135
2136                                 config {
2137                                         pins = "gpio0", "gpio1";
2138                                         drive-strength = <2>;
2139                                         bias-disable;
2140                                 };
2141                         };
2142
2143                         qup_spi0_default: qup-spi0-default {
2144                                 mux {
2145                                         pins = "gpio28", "gpio29",
2146                                                "gpio30", "gpio31";
2147                                         function = "qup0";
2148                                 };
2149
2150                                 config {
2151                                         pins = "gpio28", "gpio29",
2152                                                "gpio30", "gpio31";
2153                                         drive-strength = <6>;
2154                                         bias-disable;
2155                                 };
2156                         };
2157
2158                         qup_spi1_default: qup-spi1-default {
2159                                 mux {
2160                                         pins = "gpio4", "gpio5",
2161                                                "gpio6", "gpio7";
2162                                         function = "qup1";
2163                                 };
2164
2165                                 config {
2166                                         pins = "gpio4", "gpio5",
2167                                                "gpio6", "gpio7";
2168                                         drive-strength = <6>;
2169                                         bias-disable;
2170                                 };
2171                         };
2172
2173                         qup_spi2_default: qup-spi2-default {
2174                                 mux {
2175                                         pins = "gpio115", "gpio116",
2176                                                "gpio117", "gpio118";
2177                                         function = "qup2";
2178                                 };
2179
2180                                 config {
2181                                         pins = "gpio115", "gpio116",
2182                                                "gpio117", "gpio118";
2183                                         drive-strength = <6>;
2184                                         bias-disable;
2185                                 };
2186                         };
2187
2188                         qup_spi3_default: qup-spi3-default {
2189                                 mux {
2190                                         pins = "gpio119", "gpio120",
2191                                                "gpio121", "gpio122";
2192                                         function = "qup3";
2193                                 };
2194
2195                                 config {
2196                                         pins = "gpio119", "gpio120",
2197                                                "gpio121", "gpio122";
2198                                         drive-strength = <6>;
2199                                         bias-disable;
2200                                 };
2201                         };
2202
2203                         qup_spi4_default: qup-spi4-default {
2204                                 mux {
2205                                         pins = "gpio8", "gpio9",
2206                                                "gpio10", "gpio11";
2207                                         function = "qup4";
2208                                 };
2209
2210                                 config {
2211                                         pins = "gpio8", "gpio9",
2212                                                "gpio10", "gpio11";
2213                                         drive-strength = <6>;
2214                                         bias-disable;
2215                                 };
2216                         };
2217
2218                         qup_spi5_default: qup-spi5-default {
2219                                 mux {
2220                                         pins = "gpio12", "gpio13",
2221                                                "gpio14", "gpio15";
2222                                         function = "qup5";
2223                                 };
2224
2225                                 config {
2226                                         pins = "gpio12", "gpio13",
2227                                                "gpio14", "gpio15";
2228                                         drive-strength = <6>;
2229                                         bias-disable;
2230                                 };
2231                         };
2232
2233                         qup_spi6_default: qup-spi6-default {
2234                                 mux {
2235                                         pins = "gpio16", "gpio17",
2236                                                "gpio18", "gpio19";
2237                                         function = "qup6";
2238                                 };
2239
2240                                 config {
2241                                         pins = "gpio16", "gpio17",
2242                                                "gpio18", "gpio19";
2243                                         drive-strength = <6>;
2244                                         bias-disable;
2245                                 };
2246                         };
2247
2248                         qup_spi7_default: qup-spi7-default {
2249                                 mux {
2250                                         pins = "gpio20", "gpio21",
2251                                                "gpio22", "gpio23";
2252                                         function = "qup7";
2253                                 };
2254
2255                                 config {
2256                                         pins = "gpio20", "gpio21",
2257                                                "gpio22", "gpio23";
2258                                         drive-strength = <6>;
2259                                         bias-disable;
2260                                 };
2261                         };
2262
2263                         qup_spi8_default: qup-spi8-default {
2264                                 mux {
2265                                         pins = "gpio24", "gpio25",
2266                                                "gpio26", "gpio27";
2267                                         function = "qup8";
2268                                 };
2269
2270                                 config {
2271                                         pins = "gpio24", "gpio25",
2272                                                "gpio26", "gpio27";
2273                                         drive-strength = <6>;
2274                                         bias-disable;
2275                                 };
2276                         };
2277
2278                         qup_spi9_default: qup-spi9-default {
2279                                 mux {
2280                                         pins = "gpio125", "gpio126",
2281                                                "gpio127", "gpio128";
2282                                         function = "qup9";
2283                                 };
2284
2285                                 config {
2286                                         pins = "gpio125", "gpio126",
2287                                                "gpio127", "gpio128";
2288                                         drive-strength = <6>;
2289                                         bias-disable;
2290                                 };
2291                         };
2292
2293                         qup_spi10_default: qup-spi10-default {
2294                                 mux {
2295                                         pins = "gpio129", "gpio130",
2296                                                "gpio131", "gpio132";
2297                                         function = "qup10";
2298                                 };
2299
2300                                 config {
2301                                         pins = "gpio129", "gpio130",
2302                                                "gpio131", "gpio132";
2303                                         drive-strength = <6>;
2304                                         bias-disable;
2305                                 };
2306                         };
2307
2308                         qup_spi11_default: qup-spi11-default {
2309                                 mux {
2310                                         pins = "gpio60", "gpio61",
2311                                                "gpio62", "gpio63";
2312                                         function = "qup11";
2313                                 };
2314
2315                                 config {
2316                                         pins = "gpio60", "gpio61",
2317                                                "gpio62", "gpio63";
2318                                         drive-strength = <6>;
2319                                         bias-disable;
2320                                 };
2321                         };
2322
2323                         qup_spi12_default: qup-spi12-default {
2324                                 mux {
2325                                         pins = "gpio32", "gpio33",
2326                                                "gpio34", "gpio35";
2327                                         function = "qup12";
2328                                 };
2329
2330                                 config {
2331                                         pins = "gpio32", "gpio33",
2332                                                "gpio34", "gpio35";
2333                                         drive-strength = <6>;
2334                                         bias-disable;
2335                                 };
2336                         };
2337
2338                         qup_spi13_default: qup-spi13-default {
2339                                 mux {
2340                                         pins = "gpio36", "gpio37",
2341                                                "gpio38", "gpio39";
2342                                         function = "qup13";
2343                                 };
2344
2345                                 config {
2346                                         pins = "gpio36", "gpio37",
2347                                                "gpio38", "gpio39";
2348                                         drive-strength = <6>;
2349                                         bias-disable;
2350                                 };
2351                         };
2352
2353                         qup_spi14_default: qup-spi14-default {
2354                                 mux {
2355                                         pins = "gpio40", "gpio41",
2356                                                "gpio42", "gpio43";
2357                                         function = "qup14";
2358                                 };
2359
2360                                 config {
2361                                         pins = "gpio40", "gpio41",
2362                                                "gpio42", "gpio43";
2363                                         drive-strength = <6>;
2364                                         bias-disable;
2365                                 };
2366                         };
2367
2368                         qup_spi15_default: qup-spi15-default {
2369                                 mux {
2370                                         pins = "gpio44", "gpio45",
2371                                                "gpio46", "gpio47";
2372                                         function = "qup15";
2373                                 };
2374
2375                                 config {
2376                                         pins = "gpio44", "gpio45",
2377                                                "gpio46", "gpio47";
2378                                         drive-strength = <6>;
2379                                         bias-disable;
2380                                 };
2381                         };
2382
2383                         qup_spi16_default: qup-spi16-default {
2384                                 mux {
2385                                         pins = "gpio48", "gpio49",
2386                                                "gpio50", "gpio51";
2387                                         function = "qup16";
2388                                 };
2389
2390                                 config {
2391                                         pins = "gpio48", "gpio49",
2392                                                "gpio50", "gpio51";
2393                                         drive-strength = <6>;
2394                                         bias-disable;
2395                                 };
2396                         };
2397
2398                         qup_spi17_default: qup-spi17-default {
2399                                 mux {
2400                                         pins = "gpio52", "gpio53",
2401                                                "gpio54", "gpio55";
2402                                         function = "qup17";
2403                                 };
2404
2405                                 config {
2406                                         pins = "gpio52", "gpio53",
2407                                                "gpio54", "gpio55";
2408                                         drive-strength = <6>;
2409                                         bias-disable;
2410                                 };
2411                         };
2412
2413                         qup_spi18_default: qup-spi18-default {
2414                                 mux {
2415                                         pins = "gpio56", "gpio57",
2416                                                "gpio58", "gpio59";
2417                                         function = "qup18";
2418                                 };
2419
2420                                 config {
2421                                         pins = "gpio56", "gpio57",
2422                                                "gpio58", "gpio59";
2423                                         drive-strength = <6>;
2424                                         bias-disable;
2425                                 };
2426                         };
2427
2428                         qup_spi19_default: qup-spi19-default {
2429                                 mux {
2430                                         pins = "gpio0", "gpio1",
2431                                                "gpio2", "gpio3";
2432                                         function = "qup19";
2433                                 };
2434
2435                                 config {
2436                                         pins = "gpio0", "gpio1",
2437                                                "gpio2", "gpio3";
2438                                         drive-strength = <6>;
2439                                         bias-disable;
2440                                 };
2441                         };
2442
2443                         qup_uart2_default: qup-uart2-default {
2444                                 mux {
2445                                         pins = "gpio117", "gpio118";
2446                                         function = "qup2";
2447                                 };
2448                         };
2449
2450                         qup_uart6_default: qup-uart6-default {
2451                                 mux {
2452                                         pins = "gpio16", "gpio17",
2453                                                 "gpio18", "gpio19";
2454                                         function = "qup6";
2455                                 };
2456                         };
2457
2458                         qup_uart12_default: qup-uart12-default {
2459                                 mux {
2460                                         pins = "gpio34", "gpio35";
2461                                         function = "qup12";
2462                                 };
2463                         };
2464
2465                         qup_uart17_default: qup-uart17-default {
2466                                 mux {
2467                                         pins = "gpio52", "gpio53",
2468                                                 "gpio54", "gpio55";
2469                                         function = "qup17";
2470                                 };
2471                         };
2472
2473                         qup_uart18_default: qup-uart18-default {
2474                                 mux {
2475                                         pins = "gpio58", "gpio59";
2476                                         function = "qup18";
2477                                 };
2478                         };
2479                 };
2480
2481                 apps_smmu: iommu@15000000 {
2482                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2483                         reg = <0 0x15000000 0 0x100000>;
2484                         #iommu-cells = <2>;
2485                         #global-interrupts = <2>;
2486                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2487                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2488                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2489                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2490                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2491                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2492                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2493                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2494                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2495                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2496                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2497                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2498                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2499                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2500                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2501                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2502                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2503                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2504                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2505                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2506                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2507                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2508                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2509                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2510                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2511                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2512                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2513                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2514                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2515                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2516                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2517                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2518                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2519                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2520                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2521                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2522                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2523                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2524                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2525                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2526                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2527                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2528                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2529                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2530                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2531                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2532                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2533                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2534                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2535                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2536                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2537                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2538                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2539                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2540                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2541                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2542                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2543                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2544                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2545                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2546                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2547                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2548                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2549                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2550                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2551                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2552                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2553                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2554                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2555                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2556                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2557                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2558                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2559                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2560                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2561                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2562                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2563                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2564                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2565                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2566                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2567                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2568                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2569                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2570                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2571                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2572                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2573                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2574                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2575                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2576                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2577                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2578                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2579                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2580                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2581                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2582                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
2583                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
2584                 };
2585
2586                 adsp: remoteproc@17300000 {
2587                         compatible = "qcom,sm8250-adsp-pas";
2588                         reg = <0 0x17300000 0 0x100>;
2589
2590                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2591                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2592                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2593                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2594                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2595                         interrupt-names = "wdog", "fatal", "ready",
2596                                           "handover", "stop-ack";
2597
2598                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2599                         clock-names = "xo";
2600
2601                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2602                                         <&rpmhpd SM8250_LCX>,
2603                                         <&rpmhpd SM8250_LMX>;
2604                         power-domain-names = "load_state", "lcx", "lmx";
2605
2606                         memory-region = <&adsp_mem>;
2607
2608                         qcom,smem-states = <&smp2p_adsp_out 0>;
2609                         qcom,smem-state-names = "stop";
2610
2611                         status = "disabled";
2612
2613                         glink-edge {
2614                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2615                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2616                                                              IRQ_TYPE_EDGE_RISING>;
2617                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2618                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2619
2620                                 label = "lpass";
2621                                 qcom,remote-pid = <2>;
2622
2623                                 fastrpc {
2624                                         compatible = "qcom,fastrpc";
2625                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2626                                         label = "adsp";
2627                                         #address-cells = <1>;
2628                                         #size-cells = <0>;
2629
2630                                         compute-cb@3 {
2631                                                 compatible = "qcom,fastrpc-compute-cb";
2632                                                 reg = <3>;
2633                                                 iommus = <&apps_smmu 0x1803 0x0>;
2634                                         };
2635
2636                                         compute-cb@4 {
2637                                                 compatible = "qcom,fastrpc-compute-cb";
2638                                                 reg = <4>;
2639                                                 iommus = <&apps_smmu 0x1804 0x0>;
2640                                         };
2641
2642                                         compute-cb@5 {
2643                                                 compatible = "qcom,fastrpc-compute-cb";
2644                                                 reg = <5>;
2645                                                 iommus = <&apps_smmu 0x1805 0x0>;
2646                                         };
2647                                 };
2648                         };
2649                 };
2650
2651                 intc: interrupt-controller@17a00000 {
2652                         compatible = "arm,gic-v3";
2653                         #interrupt-cells = <3>;
2654                         interrupt-controller;
2655                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2656                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2657                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2658                 };
2659
2660                 watchdog@17c10000 {
2661                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
2662                         reg = <0 0x17c10000 0 0x1000>;
2663                         clocks = <&sleep_clk>;
2664                 };
2665
2666                 timer@17c20000 {
2667                         #address-cells = <2>;
2668                         #size-cells = <2>;
2669                         ranges;
2670                         compatible = "arm,armv7-timer-mem";
2671                         reg = <0x0 0x17c20000 0x0 0x1000>;
2672                         clock-frequency = <19200000>;
2673
2674                         frame@17c21000 {
2675                                 frame-number = <0>;
2676                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2677                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2678                                 reg = <0x0 0x17c21000 0x0 0x1000>,
2679                                       <0x0 0x17c22000 0x0 0x1000>;
2680                         };
2681
2682                         frame@17c23000 {
2683                                 frame-number = <1>;
2684                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2685                                 reg = <0x0 0x17c23000 0x0 0x1000>;
2686                                 status = "disabled";
2687                         };
2688
2689                         frame@17c25000 {
2690                                 frame-number = <2>;
2691                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2692                                 reg = <0x0 0x17c25000 0x0 0x1000>;
2693                                 status = "disabled";
2694                         };
2695
2696                         frame@17c27000 {
2697                                 frame-number = <3>;
2698                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2699                                 reg = <0x0 0x17c27000 0x0 0x1000>;
2700                                 status = "disabled";
2701                         };
2702
2703                         frame@17c29000 {
2704                                 frame-number = <4>;
2705                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2706                                 reg = <0x0 0x17c29000 0x0 0x1000>;
2707                                 status = "disabled";
2708                         };
2709
2710                         frame@17c2b000 {
2711                                 frame-number = <5>;
2712                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2713                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
2714                                 status = "disabled";
2715                         };
2716
2717                         frame@17c2d000 {
2718                                 frame-number = <6>;
2719                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2720                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
2721                                 status = "disabled";
2722                         };
2723                 };
2724
2725                 apps_rsc: rsc@18200000 {
2726                         label = "apps_rsc";
2727                         compatible = "qcom,rpmh-rsc";
2728                         reg = <0x0 0x18200000 0x0 0x10000>,
2729                                 <0x0 0x18210000 0x0 0x10000>,
2730                                 <0x0 0x18220000 0x0 0x10000>;
2731                         reg-names = "drv-0", "drv-1", "drv-2";
2732                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2733                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2734                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2735                         qcom,tcs-offset = <0xd00>;
2736                         qcom,drv-id = <2>;
2737                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2738                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
2739
2740                         rpmhcc: clock-controller {
2741                                 compatible = "qcom,sm8250-rpmh-clk";
2742                                 #clock-cells = <1>;
2743                                 clock-names = "xo";
2744                                 clocks = <&xo_board>;
2745                         };
2746
2747                         rpmhpd: power-controller {
2748                                 compatible = "qcom,sm8250-rpmhpd";
2749                                 #power-domain-cells = <1>;
2750                                 operating-points-v2 = <&rpmhpd_opp_table>;
2751
2752                                 rpmhpd_opp_table: opp-table {
2753                                         compatible = "operating-points-v2";
2754
2755                                         rpmhpd_opp_ret: opp1 {
2756                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2757                                         };
2758
2759                                         rpmhpd_opp_min_svs: opp2 {
2760                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2761                                         };
2762
2763                                         rpmhpd_opp_low_svs: opp3 {
2764                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2765                                         };
2766
2767                                         rpmhpd_opp_svs: opp4 {
2768                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2769                                         };
2770
2771                                         rpmhpd_opp_svs_l1: opp5 {
2772                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2773                                         };
2774
2775                                         rpmhpd_opp_nom: opp6 {
2776                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2777                                         };
2778
2779                                         rpmhpd_opp_nom_l1: opp7 {
2780                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2781                                         };
2782
2783                                         rpmhpd_opp_nom_l2: opp8 {
2784                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2785                                         };
2786
2787                                         rpmhpd_opp_turbo: opp9 {
2788                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2789                                         };
2790
2791                                         rpmhpd_opp_turbo_l1: opp10 {
2792                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2793                                         };
2794                                 };
2795                         };
2796
2797                         apps_bcm_voter: bcm_voter {
2798                                 compatible = "qcom,bcm-voter";
2799                         };
2800                 };
2801
2802                 epss_l3: interconnect@18591000 {
2803                         compatible = "qcom,sm8250-epss-l3";
2804                         reg = <0 0x18590000 0 0x1000>;
2805
2806                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2807                         clock-names = "xo", "alternate";
2808
2809                         #interconnect-cells = <1>;
2810                 };
2811
2812                 cpufreq_hw: cpufreq@18591000 {
2813                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
2814                         reg = <0 0x18591000 0 0x1000>,
2815                               <0 0x18592000 0 0x1000>,
2816                               <0 0x18593000 0 0x1000>;
2817                         reg-names = "freq-domain0", "freq-domain1",
2818                                     "freq-domain2";
2819
2820                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2821                         clock-names = "xo", "alternate";
2822
2823                         #freq-domain-cells = <1>;
2824                 };
2825         };
2826
2827         timer {
2828                 compatible = "arm,armv8-timer";
2829                 interrupts = <GIC_PPI 13
2830                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2831                              <GIC_PPI 14
2832                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2833                              <GIC_PPI 11
2834                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2835                              <GIC_PPI 12
2836                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2837         };
2838
2839         thermal-zones {
2840                 cpu0-thermal {
2841                         polling-delay-passive = <250>;
2842                         polling-delay = <1000>;
2843
2844                         thermal-sensors = <&tsens0 1>;
2845
2846                         trips {
2847                                 cpu0_alert0: trip-point0 {
2848                                         temperature = <90000>;
2849                                         hysteresis = <2000>;
2850                                         type = "passive";
2851                                 };
2852
2853                                 cpu0_alert1: trip-point1 {
2854                                         temperature = <95000>;
2855                                         hysteresis = <2000>;
2856                                         type = "passive";
2857                                 };
2858
2859                                 cpu0_crit: cpu_crit {
2860                                         temperature = <110000>;
2861                                         hysteresis = <1000>;
2862                                         type = "critical";
2863                                 };
2864                         };
2865
2866                         cooling-maps {
2867                                 map0 {
2868                                         trip = <&cpu0_alert0>;
2869                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2870                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2871                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2872                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2873                                 };
2874                                 map1 {
2875                                         trip = <&cpu0_alert1>;
2876                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2877                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2878                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2879                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2880                                 };
2881                         };
2882                 };
2883
2884                 cpu1-thermal {
2885                         polling-delay-passive = <250>;
2886                         polling-delay = <1000>;
2887
2888                         thermal-sensors = <&tsens0 2>;
2889
2890                         trips {
2891                                 cpu1_alert0: trip-point0 {
2892                                         temperature = <90000>;
2893                                         hysteresis = <2000>;
2894                                         type = "passive";
2895                                 };
2896
2897                                 cpu1_alert1: trip-point1 {
2898                                         temperature = <95000>;
2899                                         hysteresis = <2000>;
2900                                         type = "passive";
2901                                 };
2902
2903                                 cpu1_crit: cpu_crit {
2904                                         temperature = <110000>;
2905                                         hysteresis = <1000>;
2906                                         type = "critical";
2907                                 };
2908                         };
2909
2910                         cooling-maps {
2911                                 map0 {
2912                                         trip = <&cpu1_alert0>;
2913                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2914                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2915                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2916                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2917                                 };
2918                                 map1 {
2919                                         trip = <&cpu1_alert1>;
2920                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2921                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2922                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2923                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2924                                 };
2925                         };
2926                 };
2927
2928                 cpu2-thermal {
2929                         polling-delay-passive = <250>;
2930                         polling-delay = <1000>;
2931
2932                         thermal-sensors = <&tsens0 3>;
2933
2934                         trips {
2935                                 cpu2_alert0: trip-point0 {
2936                                         temperature = <90000>;
2937                                         hysteresis = <2000>;
2938                                         type = "passive";
2939                                 };
2940
2941                                 cpu2_alert1: trip-point1 {
2942                                         temperature = <95000>;
2943                                         hysteresis = <2000>;
2944                                         type = "passive";
2945                                 };
2946
2947                                 cpu2_crit: cpu_crit {
2948                                         temperature = <110000>;
2949                                         hysteresis = <1000>;
2950                                         type = "critical";
2951                                 };
2952                         };
2953
2954                         cooling-maps {
2955                                 map0 {
2956                                         trip = <&cpu2_alert0>;
2957                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2958                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2959                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2960                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2961                                 };
2962                                 map1 {
2963                                         trip = <&cpu2_alert1>;
2964                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2965                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2966                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2967                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2968                                 };
2969                         };
2970                 };
2971
2972                 cpu3-thermal {
2973                         polling-delay-passive = <250>;
2974                         polling-delay = <1000>;
2975
2976                         thermal-sensors = <&tsens0 4>;
2977
2978                         trips {
2979                                 cpu3_alert0: trip-point0 {
2980                                         temperature = <90000>;
2981                                         hysteresis = <2000>;
2982                                         type = "passive";
2983                                 };
2984
2985                                 cpu3_alert1: trip-point1 {
2986                                         temperature = <95000>;
2987                                         hysteresis = <2000>;
2988                                         type = "passive";
2989                                 };
2990
2991                                 cpu3_crit: cpu_crit {
2992                                         temperature = <110000>;
2993                                         hysteresis = <1000>;
2994                                         type = "critical";
2995                                 };
2996                         };
2997
2998                         cooling-maps {
2999                                 map0 {
3000                                         trip = <&cpu3_alert0>;
3001                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3002                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3003                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3004                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3005                                 };
3006                                 map1 {
3007                                         trip = <&cpu3_alert1>;
3008                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3009                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3010                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3011                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3012                                 };
3013                         };
3014                 };
3015
3016                 cpu4-top-thermal {
3017                         polling-delay-passive = <250>;
3018                         polling-delay = <1000>;
3019
3020                         thermal-sensors = <&tsens0 7>;
3021
3022                         trips {
3023                                 cpu4_top_alert0: trip-point0 {
3024                                         temperature = <90000>;
3025                                         hysteresis = <2000>;
3026                                         type = "passive";
3027                                 };
3028
3029                                 cpu4_top_alert1: trip-point1 {
3030                                         temperature = <95000>;
3031                                         hysteresis = <2000>;
3032                                         type = "passive";
3033                                 };
3034
3035                                 cpu4_top_crit: cpu_crit {
3036                                         temperature = <110000>;
3037                                         hysteresis = <1000>;
3038                                         type = "critical";
3039                                 };
3040                         };
3041
3042                         cooling-maps {
3043                                 map0 {
3044                                         trip = <&cpu4_top_alert0>;
3045                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3046                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3047                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3048                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3049                                 };
3050                                 map1 {
3051                                         trip = <&cpu4_top_alert1>;
3052                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3053                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3054                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3055                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3056                                 };
3057                         };
3058                 };
3059
3060                 cpu5-top-thermal {
3061                         polling-delay-passive = <250>;
3062                         polling-delay = <1000>;
3063
3064                         thermal-sensors = <&tsens0 8>;
3065
3066                         trips {
3067                                 cpu5_top_alert0: trip-point0 {
3068                                         temperature = <90000>;
3069                                         hysteresis = <2000>;
3070                                         type = "passive";
3071                                 };
3072
3073                                 cpu5_top_alert1: trip-point1 {
3074                                         temperature = <95000>;
3075                                         hysteresis = <2000>;
3076                                         type = "passive";
3077                                 };
3078
3079                                 cpu5_top_crit: cpu_crit {
3080                                         temperature = <110000>;
3081                                         hysteresis = <1000>;
3082                                         type = "critical";
3083                                 };
3084                         };
3085
3086                         cooling-maps {
3087                                 map0 {
3088                                         trip = <&cpu5_top_alert0>;
3089                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3090                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3091                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3092                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3093                                 };
3094                                 map1 {
3095                                         trip = <&cpu5_top_alert1>;
3096                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3097                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3098                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3099                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3100                                 };
3101                         };
3102                 };
3103
3104                 cpu6-top-thermal {
3105                         polling-delay-passive = <250>;
3106                         polling-delay = <1000>;
3107
3108                         thermal-sensors = <&tsens0 9>;
3109
3110                         trips {
3111                                 cpu6_top_alert0: trip-point0 {
3112                                         temperature = <90000>;
3113                                         hysteresis = <2000>;
3114                                         type = "passive";
3115                                 };
3116
3117                                 cpu6_top_alert1: trip-point1 {
3118                                         temperature = <95000>;
3119                                         hysteresis = <2000>;
3120                                         type = "passive";
3121                                 };
3122
3123                                 cpu6_top_crit: cpu_crit {
3124                                         temperature = <110000>;
3125                                         hysteresis = <1000>;
3126                                         type = "critical";
3127                                 };
3128                         };
3129
3130                         cooling-maps {
3131                                 map0 {
3132                                         trip = <&cpu6_top_alert0>;
3133                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3134                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3135                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3136                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3137                                 };
3138                                 map1 {
3139                                         trip = <&cpu6_top_alert1>;
3140                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3141                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3142                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3143                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3144                                 };
3145                         };
3146                 };
3147
3148                 cpu7-top-thermal {
3149                         polling-delay-passive = <250>;
3150                         polling-delay = <1000>;
3151
3152                         thermal-sensors = <&tsens0 10>;
3153
3154                         trips {
3155                                 cpu7_top_alert0: trip-point0 {
3156                                         temperature = <90000>;
3157                                         hysteresis = <2000>;
3158                                         type = "passive";
3159                                 };
3160
3161                                 cpu7_top_alert1: trip-point1 {
3162                                         temperature = <95000>;
3163                                         hysteresis = <2000>;
3164                                         type = "passive";
3165                                 };
3166
3167                                 cpu7_top_crit: cpu_crit {
3168                                         temperature = <110000>;
3169                                         hysteresis = <1000>;
3170                                         type = "critical";
3171                                 };
3172                         };
3173
3174                         cooling-maps {
3175                                 map0 {
3176                                         trip = <&cpu7_top_alert0>;
3177                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3178                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3179                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3180                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3181                                 };
3182                                 map1 {
3183                                         trip = <&cpu7_top_alert1>;
3184                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3185                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3186                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3187                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3188                                 };
3189                         };
3190                 };
3191
3192                 cpu4-bottom-thermal {
3193                         polling-delay-passive = <250>;
3194                         polling-delay = <1000>;
3195
3196                         thermal-sensors = <&tsens0 11>;
3197
3198                         trips {
3199                                 cpu4_bottom_alert0: trip-point0 {
3200                                         temperature = <90000>;
3201                                         hysteresis = <2000>;
3202                                         type = "passive";
3203                                 };
3204
3205                                 cpu4_bottom_alert1: trip-point1 {
3206                                         temperature = <95000>;
3207                                         hysteresis = <2000>;
3208                                         type = "passive";
3209                                 };
3210
3211                                 cpu4_bottom_crit: cpu_crit {
3212                                         temperature = <110000>;
3213                                         hysteresis = <1000>;
3214                                         type = "critical";
3215                                 };
3216                         };
3217
3218                         cooling-maps {
3219                                 map0 {
3220                                         trip = <&cpu4_bottom_alert0>;
3221                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3222                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3223                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3224                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3225                                 };
3226                                 map1 {
3227                                         trip = <&cpu4_bottom_alert1>;
3228                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3229                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3230                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3231                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3232                                 };
3233                         };
3234                 };
3235
3236                 cpu5-bottom-thermal {
3237                         polling-delay-passive = <250>;
3238                         polling-delay = <1000>;
3239
3240                         thermal-sensors = <&tsens0 12>;
3241
3242                         trips {
3243                                 cpu5_bottom_alert0: trip-point0 {
3244                                         temperature = <90000>;
3245                                         hysteresis = <2000>;
3246                                         type = "passive";
3247                                 };
3248
3249                                 cpu5_bottom_alert1: trip-point1 {
3250                                         temperature = <95000>;
3251                                         hysteresis = <2000>;
3252                                         type = "passive";
3253                                 };
3254
3255                                 cpu5_bottom_crit: cpu_crit {
3256                                         temperature = <110000>;
3257                                         hysteresis = <1000>;
3258                                         type = "critical";
3259                                 };
3260                         };
3261
3262                         cooling-maps {
3263                                 map0 {
3264                                         trip = <&cpu5_bottom_alert0>;
3265                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3266                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3267                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3268                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3269                                 };
3270                                 map1 {
3271                                         trip = <&cpu5_bottom_alert1>;
3272                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3273                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3274                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3275                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3276                                 };
3277                         };
3278                 };
3279
3280                 cpu6-bottom-thermal {
3281                         polling-delay-passive = <250>;
3282                         polling-delay = <1000>;
3283
3284                         thermal-sensors = <&tsens0 13>;
3285
3286                         trips {
3287                                 cpu6_bottom_alert0: trip-point0 {
3288                                         temperature = <90000>;
3289                                         hysteresis = <2000>;
3290                                         type = "passive";
3291                                 };
3292
3293                                 cpu6_bottom_alert1: trip-point1 {
3294                                         temperature = <95000>;
3295                                         hysteresis = <2000>;
3296                                         type = "passive";
3297                                 };
3298
3299                                 cpu6_bottom_crit: cpu_crit {
3300                                         temperature = <110000>;
3301                                         hysteresis = <1000>;
3302                                         type = "critical";
3303                                 };
3304                         };
3305
3306                         cooling-maps {
3307                                 map0 {
3308                                         trip = <&cpu6_bottom_alert0>;
3309                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3310                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3311                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3312                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3313                                 };
3314                                 map1 {
3315                                         trip = <&cpu6_bottom_alert1>;
3316                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3317                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3318                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3319                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3320                                 };
3321                         };
3322                 };
3323
3324                 cpu7-bottom-thermal {
3325                         polling-delay-passive = <250>;
3326                         polling-delay = <1000>;
3327
3328                         thermal-sensors = <&tsens0 14>;
3329
3330                         trips {
3331                                 cpu7_bottom_alert0: trip-point0 {
3332                                         temperature = <90000>;
3333                                         hysteresis = <2000>;
3334                                         type = "passive";
3335                                 };
3336
3337                                 cpu7_bottom_alert1: trip-point1 {
3338                                         temperature = <95000>;
3339                                         hysteresis = <2000>;
3340                                         type = "passive";
3341                                 };
3342
3343                                 cpu7_bottom_crit: cpu_crit {
3344                                         temperature = <110000>;
3345                                         hysteresis = <1000>;
3346                                         type = "critical";
3347                                 };
3348                         };
3349
3350                         cooling-maps {
3351                                 map0 {
3352                                         trip = <&cpu7_bottom_alert0>;
3353                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3354                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3355                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3356                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3357                                 };
3358                                 map1 {
3359                                         trip = <&cpu7_bottom_alert1>;
3360                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3361                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3362                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3363                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3364                                 };
3365                         };
3366                 };
3367
3368                 aoss0-thermal {
3369                         polling-delay-passive = <250>;
3370                         polling-delay = <1000>;
3371
3372                         thermal-sensors = <&tsens0 0>;
3373
3374                         trips {
3375                                 aoss0_alert0: trip-point0 {
3376                                         temperature = <90000>;
3377                                         hysteresis = <2000>;
3378                                         type = "hot";
3379                                 };
3380                         };
3381                 };
3382
3383                 cluster0-thermal {
3384                         polling-delay-passive = <250>;
3385                         polling-delay = <1000>;
3386
3387                         thermal-sensors = <&tsens0 5>;
3388
3389                         trips {
3390                                 cluster0_alert0: trip-point0 {
3391                                         temperature = <90000>;
3392                                         hysteresis = <2000>;
3393                                         type = "hot";
3394                                 };
3395                                 cluster0_crit: cluster0_crit {
3396                                         temperature = <110000>;
3397                                         hysteresis = <2000>;
3398                                         type = "critical";
3399                                 };
3400                         };
3401                 };
3402
3403                 cluster1-thermal {
3404                         polling-delay-passive = <250>;
3405                         polling-delay = <1000>;
3406
3407                         thermal-sensors = <&tsens0 6>;
3408
3409                         trips {
3410                                 cluster1_alert0: trip-point0 {
3411                                         temperature = <90000>;
3412                                         hysteresis = <2000>;
3413                                         type = "hot";
3414                                 };
3415                                 cluster1_crit: cluster1_crit {
3416                                         temperature = <110000>;
3417                                         hysteresis = <2000>;
3418                                         type = "critical";
3419                                 };
3420                         };
3421                 };
3422
3423                 gpu-thermal-top {
3424                         polling-delay-passive = <250>;
3425                         polling-delay = <1000>;
3426
3427                         thermal-sensors = <&tsens0 15>;
3428
3429                         trips {
3430                                 gpu1_alert0: trip-point0 {
3431                                         temperature = <90000>;
3432                                         hysteresis = <2000>;
3433                                         type = "hot";
3434                                 };
3435                         };
3436                 };
3437
3438                 aoss1-thermal {
3439                         polling-delay-passive = <250>;
3440                         polling-delay = <1000>;
3441
3442                         thermal-sensors = <&tsens1 0>;
3443
3444                         trips {
3445                                 aoss1_alert0: trip-point0 {
3446                                         temperature = <90000>;
3447                                         hysteresis = <2000>;
3448                                         type = "hot";
3449                                 };
3450                         };
3451                 };
3452
3453                 wlan-thermal {
3454                         polling-delay-passive = <250>;
3455                         polling-delay = <1000>;
3456
3457                         thermal-sensors = <&tsens1 1>;
3458
3459                         trips {
3460                                 wlan_alert0: trip-point0 {
3461                                         temperature = <90000>;
3462                                         hysteresis = <2000>;
3463                                         type = "hot";
3464                                 };
3465                         };
3466                 };
3467
3468                 video-thermal {
3469                         polling-delay-passive = <250>;
3470                         polling-delay = <1000>;
3471
3472                         thermal-sensors = <&tsens1 2>;
3473
3474                         trips {
3475                                 video_alert0: trip-point0 {
3476                                         temperature = <90000>;
3477                                         hysteresis = <2000>;
3478                                         type = "hot";
3479                                 };
3480                         };
3481                 };
3482
3483                 mem-thermal {
3484                         polling-delay-passive = <250>;
3485                         polling-delay = <1000>;
3486
3487                         thermal-sensors = <&tsens1 3>;
3488
3489                         trips {
3490                                 mem_alert0: trip-point0 {
3491                                         temperature = <90000>;
3492                                         hysteresis = <2000>;
3493                                         type = "hot";
3494                                 };
3495                         };
3496                 };
3497
3498                 q6-hvx-thermal {
3499                         polling-delay-passive = <250>;
3500                         polling-delay = <1000>;
3501
3502                         thermal-sensors = <&tsens1 4>;
3503
3504                         trips {
3505                                 q6_hvx_alert0: trip-point0 {
3506                                         temperature = <90000>;
3507                                         hysteresis = <2000>;
3508                                         type = "hot";
3509                                 };
3510                         };
3511                 };
3512
3513                 camera-thermal {
3514                         polling-delay-passive = <250>;
3515                         polling-delay = <1000>;
3516
3517                         thermal-sensors = <&tsens1 5>;
3518
3519                         trips {
3520                                 camera_alert0: trip-point0 {
3521                                         temperature = <90000>;
3522                                         hysteresis = <2000>;
3523                                         type = "hot";
3524                                 };
3525                         };
3526                 };
3527
3528                 compute-thermal {
3529                         polling-delay-passive = <250>;
3530                         polling-delay = <1000>;
3531
3532                         thermal-sensors = <&tsens1 6>;
3533
3534                         trips {
3535                                 compute_alert0: trip-point0 {
3536                                         temperature = <90000>;
3537                                         hysteresis = <2000>;
3538                                         type = "hot";
3539                                 };
3540                         };
3541                 };
3542
3543                 npu-thermal {
3544                         polling-delay-passive = <250>;
3545                         polling-delay = <1000>;
3546
3547                         thermal-sensors = <&tsens1 7>;
3548
3549                         trips {
3550                                 npu_alert0: trip-point0 {
3551                                         temperature = <90000>;
3552                                         hysteresis = <2000>;
3553                                         type = "hot";
3554                                 };
3555                         };
3556                 };
3557
3558                 gpu-thermal-bottom {
3559                         polling-delay-passive = <250>;
3560                         polling-delay = <1000>;
3561
3562                         thermal-sensors = <&tsens1 8>;
3563
3564                         trips {
3565                                 gpu2_alert0: trip-point0 {
3566                                         temperature = <90000>;
3567                                         hysteresis = <2000>;
3568                                         type = "hot";
3569                                 };
3570                         };
3571                 };
3572         };
3573 };