1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,apr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/sound/qcom,q6afe.h>
21 #include <dt-bindings/thermal/thermal.h>
22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 interrupt-parent = <&intc>;
77 compatible = "fixed-clock";
79 clock-frequency = <38400000>;
80 clock-output-names = "xo_board";
83 sleep_clk: sleep-clk {
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
96 compatible = "qcom,kryo485";
98 enable-method = "psci";
99 capacity-dmips-mhz = <448>;
100 dynamic-power-coefficient = <205>;
101 next-level-cache = <&L2_0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
105 compatible = "cache";
106 next-level-cache = <&L3_0>;
108 compatible = "cache";
115 compatible = "qcom,kryo485";
117 enable-method = "psci";
118 capacity-dmips-mhz = <448>;
119 dynamic-power-coefficient = <205>;
120 next-level-cache = <&L2_100>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 #cooling-cells = <2>;
124 compatible = "cache";
125 next-level-cache = <&L3_0>;
131 compatible = "qcom,kryo485";
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <205>;
136 next-level-cache = <&L2_200>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 #cooling-cells = <2>;
140 compatible = "cache";
141 next-level-cache = <&L3_0>;
147 compatible = "qcom,kryo485";
149 enable-method = "psci";
150 capacity-dmips-mhz = <448>;
151 dynamic-power-coefficient = <205>;
152 next-level-cache = <&L2_300>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 #cooling-cells = <2>;
156 compatible = "cache";
157 next-level-cache = <&L3_0>;
163 compatible = "qcom,kryo485";
165 enable-method = "psci";
166 capacity-dmips-mhz = <1024>;
167 dynamic-power-coefficient = <379>;
168 next-level-cache = <&L2_400>;
169 qcom,freq-domain = <&cpufreq_hw 1>;
170 #cooling-cells = <2>;
172 compatible = "cache";
173 next-level-cache = <&L3_0>;
179 compatible = "qcom,kryo485";
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <379>;
184 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 #cooling-cells = <2>;
188 compatible = "cache";
189 next-level-cache = <&L3_0>;
196 compatible = "qcom,kryo485";
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <379>;
201 next-level-cache = <&L2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 #cooling-cells = <2>;
205 compatible = "cache";
206 next-level-cache = <&L3_0>;
212 compatible = "qcom,kryo485";
214 enable-method = "psci";
215 capacity-dmips-mhz = <1024>;
216 dynamic-power-coefficient = <444>;
217 next-level-cache = <&L2_700>;
218 qcom,freq-domain = <&cpufreq_hw 2>;
219 #cooling-cells = <2>;
221 compatible = "cache";
222 next-level-cache = <&L3_0>;
265 compatible = "qcom,scm";
271 device_type = "memory";
272 /* We expect the bootloader to fill in the size */
273 reg = <0x0 0x80000000 0x0 0x0>;
277 compatible = "regulator-fixed-domain";
278 power-domains = <&rpmhpd SM8250_MMCX>;
279 required-opps = <&rpmhpd_opp_low_svs>;
280 regulator-name = "MMCX";
284 compatible = "arm,armv8-pmuv3";
285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
289 compatible = "arm,psci-1.0";
294 #address-cells = <2>;
298 hyp_mem: memory@80000000 {
299 reg = <0x0 0x80000000 0x0 0x600000>;
303 xbl_aop_mem: memory@80700000 {
304 reg = <0x0 0x80700000 0x0 0x160000>;
308 cmd_db: memory@80860000 {
309 compatible = "qcom,cmd-db";
310 reg = <0x0 0x80860000 0x0 0x20000>;
314 smem_mem: memory@80900000 {
315 reg = <0x0 0x80900000 0x0 0x200000>;
319 removed_mem: memory@80b00000 {
320 reg = <0x0 0x80b00000 0x0 0x5300000>;
324 camera_mem: memory@86200000 {
325 reg = <0x0 0x86200000 0x0 0x500000>;
329 wlan_mem: memory@86700000 {
330 reg = <0x0 0x86700000 0x0 0x100000>;
334 ipa_fw_mem: memory@86800000 {
335 reg = <0x0 0x86800000 0x0 0x10000>;
339 ipa_gsi_mem: memory@86810000 {
340 reg = <0x0 0x86810000 0x0 0xa000>;
344 gpu_mem: memory@8681a000 {
345 reg = <0x0 0x8681a000 0x0 0x2000>;
349 npu_mem: memory@86900000 {
350 reg = <0x0 0x86900000 0x0 0x500000>;
354 video_mem: memory@86e00000 {
355 reg = <0x0 0x86e00000 0x0 0x500000>;
359 cvp_mem: memory@87300000 {
360 reg = <0x0 0x87300000 0x0 0x500000>;
364 cdsp_mem: memory@87800000 {
365 reg = <0x0 0x87800000 0x0 0x1400000>;
369 slpi_mem: memory@88c00000 {
370 reg = <0x0 0x88c00000 0x0 0x1500000>;
374 adsp_mem: memory@8a100000 {
375 reg = <0x0 0x8a100000 0x0 0x1d00000>;
379 spss_mem: memory@8be00000 {
380 reg = <0x0 0x8be00000 0x0 0x100000>;
384 cdsp_secure_heap: memory@8bf00000 {
385 reg = <0x0 0x8bf00000 0x0 0x4600000>;
391 compatible = "qcom,smem";
392 memory-region = <&smem_mem>;
393 hwlocks = <&tcsr_mutex 3>;
397 compatible = "qcom,smp2p";
398 qcom,smem = <443>, <429>;
399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
400 IPCC_MPROC_SIGNAL_SMP2P
401 IRQ_TYPE_EDGE_RISING>;
402 mboxes = <&ipcc IPCC_CLIENT_LPASS
403 IPCC_MPROC_SIGNAL_SMP2P>;
405 qcom,local-pid = <0>;
406 qcom,remote-pid = <2>;
408 smp2p_adsp_out: master-kernel {
409 qcom,entry-name = "master-kernel";
410 #qcom,smem-state-cells = <1>;
413 smp2p_adsp_in: slave-kernel {
414 qcom,entry-name = "slave-kernel";
415 interrupt-controller;
416 #interrupt-cells = <2>;
421 compatible = "qcom,smp2p";
422 qcom,smem = <94>, <432>;
423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
424 IPCC_MPROC_SIGNAL_SMP2P
425 IRQ_TYPE_EDGE_RISING>;
426 mboxes = <&ipcc IPCC_CLIENT_CDSP
427 IPCC_MPROC_SIGNAL_SMP2P>;
429 qcom,local-pid = <0>;
430 qcom,remote-pid = <5>;
432 smp2p_cdsp_out: master-kernel {
433 qcom,entry-name = "master-kernel";
434 #qcom,smem-state-cells = <1>;
437 smp2p_cdsp_in: slave-kernel {
438 qcom,entry-name = "slave-kernel";
439 interrupt-controller;
440 #interrupt-cells = <2>;
445 compatible = "qcom,smp2p";
446 qcom,smem = <481>, <430>;
447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
448 IPCC_MPROC_SIGNAL_SMP2P
449 IRQ_TYPE_EDGE_RISING>;
450 mboxes = <&ipcc IPCC_CLIENT_SLPI
451 IPCC_MPROC_SIGNAL_SMP2P>;
453 qcom,local-pid = <0>;
454 qcom,remote-pid = <3>;
456 smp2p_slpi_out: master-kernel {
457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells = <1>;
461 smp2p_slpi_in: slave-kernel {
462 qcom,entry-name = "slave-kernel";
463 interrupt-controller;
464 #interrupt-cells = <2>;
469 #address-cells = <2>;
471 ranges = <0 0 0 0 0x10 0>;
472 dma-ranges = <0 0 0 0 0x10 0>;
473 compatible = "simple-bus";
475 gcc: clock-controller@100000 {
476 compatible = "qcom,gcc-sm8250";
477 reg = <0x0 0x00100000 0x0 0x1f0000>;
480 #power-domain-cells = <1>;
481 clock-names = "bi_tcxo",
484 clocks = <&rpmhcc RPMH_CXO_CLK>,
485 <&rpmhcc RPMH_CXO_CLK_A>,
489 ipcc: mailbox@408000 {
490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
491 reg = <0 0x00408000 0 0x1000>;
492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-controller;
494 #interrupt-cells = <3>;
499 compatible = "qcom,prng-ee";
500 reg = <0 0x00793000 0 0x1000>;
501 clocks = <&gcc GCC_PRNG_AHB_CLK>;
502 clock-names = "core";
505 qup_opp_table: qup-opp-table {
506 compatible = "operating-points-v2";
509 opp-hz = /bits/ 64 <50000000>;
510 required-opps = <&rpmhpd_opp_min_svs>;
514 opp-hz = /bits/ 64 <75000000>;
515 required-opps = <&rpmhpd_opp_low_svs>;
519 opp-hz = /bits/ 64 <120000000>;
520 required-opps = <&rpmhpd_opp_svs>;
524 gpi_dma2: dma-controller@800000 {
525 compatible = "qcom,sm8250-gpi-dma";
526 reg = <0 0x00800000 0 0x70000>;
527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
538 dma-channel-mask = <0x3f>;
539 iommus = <&apps_smmu 0x76 0x0>;
544 qupv3_id_2: geniqup@8c0000 {
545 compatible = "qcom,geni-se-qup";
546 reg = <0x0 0x008c0000 0x0 0x6000>;
547 clock-names = "m-ahb", "s-ahb";
548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
550 #address-cells = <2>;
552 iommus = <&apps_smmu 0x63 0x0>;
557 compatible = "qcom,geni-i2c";
558 reg = <0 0x00880000 0 0x4000>;
560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&qup_i2c14_default>;
563 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
570 compatible = "qcom,geni-spi";
571 reg = <0 0x00880000 0 0x4000>;
573 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
574 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
575 #address-cells = <1>;
577 power-domains = <&rpmhpd SM8250_CX>;
578 operating-points-v2 = <&qup_opp_table>;
583 compatible = "qcom,geni-i2c";
584 reg = <0 0x00884000 0 0x4000>;
586 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&qup_i2c15_default>;
589 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
590 #address-cells = <1>;
596 compatible = "qcom,geni-spi";
597 reg = <0 0x00884000 0 0x4000>;
599 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
600 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
601 #address-cells = <1>;
603 power-domains = <&rpmhpd SM8250_CX>;
604 operating-points-v2 = <&qup_opp_table>;
609 compatible = "qcom,geni-i2c";
610 reg = <0 0x00888000 0 0x4000>;
612 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&qup_i2c16_default>;
615 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>;
622 compatible = "qcom,geni-spi";
623 reg = <0 0x00888000 0 0x4000>;
625 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
626 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
627 #address-cells = <1>;
629 power-domains = <&rpmhpd SM8250_CX>;
630 operating-points-v2 = <&qup_opp_table>;
635 compatible = "qcom,geni-i2c";
636 reg = <0 0x0088c000 0 0x4000>;
638 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&qup_i2c17_default>;
641 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
642 #address-cells = <1>;
648 compatible = "qcom,geni-spi";
649 reg = <0 0x0088c000 0 0x4000>;
651 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
652 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
655 power-domains = <&rpmhpd SM8250_CX>;
656 operating-points-v2 = <&qup_opp_table>;
660 uart17: serial@88c000 {
661 compatible = "qcom,geni-uart";
662 reg = <0 0x0088c000 0 0x4000>;
664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&qup_uart17_default>;
667 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
668 power-domains = <&rpmhpd SM8250_CX>;
669 operating-points-v2 = <&qup_opp_table>;
674 compatible = "qcom,geni-i2c";
675 reg = <0 0x00890000 0 0x4000>;
677 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&qup_i2c18_default>;
680 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
687 compatible = "qcom,geni-spi";
688 reg = <0 0x00890000 0 0x4000>;
690 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
691 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>;
694 power-domains = <&rpmhpd SM8250_CX>;
695 operating-points-v2 = <&qup_opp_table>;
699 uart18: serial@890000 {
700 compatible = "qcom,geni-uart";
701 reg = <0 0x00890000 0 0x4000>;
703 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&qup_uart18_default>;
706 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
707 power-domains = <&rpmhpd SM8250_CX>;
708 operating-points-v2 = <&qup_opp_table>;
713 compatible = "qcom,geni-i2c";
714 reg = <0 0x00894000 0 0x4000>;
716 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&qup_i2c19_default>;
719 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>;
726 compatible = "qcom,geni-spi";
727 reg = <0 0x00894000 0 0x4000>;
729 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
730 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
733 power-domains = <&rpmhpd SM8250_CX>;
734 operating-points-v2 = <&qup_opp_table>;
739 gpi_dma0: dma-controller@900000 {
740 compatible = "qcom,sm8250-gpi-dma";
741 reg = <0 0x00900000 0 0x70000>;
742 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
756 dma-channel-mask = <0x7ff>;
757 iommus = <&apps_smmu 0x5b6 0x0>;
762 qupv3_id_0: geniqup@9c0000 {
763 compatible = "qcom,geni-se-qup";
764 reg = <0x0 0x009c0000 0x0 0x6000>;
765 clock-names = "m-ahb", "s-ahb";
766 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
767 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
768 #address-cells = <2>;
770 iommus = <&apps_smmu 0x5a3 0x0>;
775 compatible = "qcom,geni-i2c";
776 reg = <0 0x00980000 0 0x4000>;
778 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&qup_i2c0_default>;
781 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
782 #address-cells = <1>;
788 compatible = "qcom,geni-spi";
789 reg = <0 0x00980000 0 0x4000>;
791 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
792 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
793 #address-cells = <1>;
795 power-domains = <&rpmhpd SM8250_CX>;
796 operating-points-v2 = <&qup_opp_table>;
801 compatible = "qcom,geni-i2c";
802 reg = <0 0x00984000 0 0x4000>;
804 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&qup_i2c1_default>;
807 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
808 #address-cells = <1>;
814 compatible = "qcom,geni-spi";
815 reg = <0 0x00984000 0 0x4000>;
817 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
818 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
819 #address-cells = <1>;
821 power-domains = <&rpmhpd SM8250_CX>;
822 operating-points-v2 = <&qup_opp_table>;
827 compatible = "qcom,geni-i2c";
828 reg = <0 0x00988000 0 0x4000>;
830 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_i2c2_default>;
833 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
834 #address-cells = <1>;
840 compatible = "qcom,geni-spi";
841 reg = <0 0x00988000 0 0x4000>;
843 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
844 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
845 #address-cells = <1>;
847 power-domains = <&rpmhpd SM8250_CX>;
848 operating-points-v2 = <&qup_opp_table>;
852 uart2: serial@988000 {
853 compatible = "qcom,geni-debug-uart";
854 reg = <0 0x00988000 0 0x4000>;
856 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&qup_uart2_default>;
859 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
860 power-domains = <&rpmhpd SM8250_CX>;
861 operating-points-v2 = <&qup_opp_table>;
866 compatible = "qcom,geni-i2c";
867 reg = <0 0x0098c000 0 0x4000>;
869 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&qup_i2c3_default>;
872 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
873 #address-cells = <1>;
879 compatible = "qcom,geni-spi";
880 reg = <0 0x0098c000 0 0x4000>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
883 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>;
886 power-domains = <&rpmhpd SM8250_CX>;
887 operating-points-v2 = <&qup_opp_table>;
892 compatible = "qcom,geni-i2c";
893 reg = <0 0x00990000 0 0x4000>;
895 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
896 pinctrl-names = "default";
897 pinctrl-0 = <&qup_i2c4_default>;
898 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
899 #address-cells = <1>;
905 compatible = "qcom,geni-spi";
906 reg = <0 0x00990000 0 0x4000>;
908 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
909 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
910 #address-cells = <1>;
912 power-domains = <&rpmhpd SM8250_CX>;
913 operating-points-v2 = <&qup_opp_table>;
918 compatible = "qcom,geni-i2c";
919 reg = <0 0x00994000 0 0x4000>;
921 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
922 pinctrl-names = "default";
923 pinctrl-0 = <&qup_i2c5_default>;
924 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
925 #address-cells = <1>;
931 compatible = "qcom,geni-spi";
932 reg = <0 0x00994000 0 0x4000>;
934 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
935 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
936 #address-cells = <1>;
938 power-domains = <&rpmhpd SM8250_CX>;
939 operating-points-v2 = <&qup_opp_table>;
944 compatible = "qcom,geni-i2c";
945 reg = <0 0x00998000 0 0x4000>;
947 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_i2c6_default>;
950 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells = <1>;
957 compatible = "qcom,geni-spi";
958 reg = <0 0x00998000 0 0x4000>;
960 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
961 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
962 #address-cells = <1>;
964 power-domains = <&rpmhpd SM8250_CX>;
965 operating-points-v2 = <&qup_opp_table>;
969 uart6: serial@998000 {
970 compatible = "qcom,geni-uart";
971 reg = <0 0x00998000 0 0x4000>;
973 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&qup_uart6_default>;
976 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
977 power-domains = <&rpmhpd SM8250_CX>;
978 operating-points-v2 = <&qup_opp_table>;
983 compatible = "qcom,geni-i2c";
984 reg = <0 0x0099c000 0 0x4000>;
986 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
987 pinctrl-names = "default";
988 pinctrl-0 = <&qup_i2c7_default>;
989 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
990 #address-cells = <1>;
996 compatible = "qcom,geni-spi";
997 reg = <0 0x0099c000 0 0x4000>;
999 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1000 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cells = <1>;
1003 power-domains = <&rpmhpd SM8250_CX>;
1004 operating-points-v2 = <&qup_opp_table>;
1005 status = "disabled";
1009 gpi_dma1: dma-controller@a00000 {
1010 compatible = "qcom,sm8250-gpi-dma";
1011 reg = <0 0x00a00000 0 0x70000>;
1012 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1022 dma-channels = <10>;
1023 dma-channel-mask = <0x3f>;
1024 iommus = <&apps_smmu 0x56 0x0>;
1026 status = "disabled";
1029 qupv3_id_1: geniqup@ac0000 {
1030 compatible = "qcom,geni-se-qup";
1031 reg = <0x0 0x00ac0000 0x0 0x6000>;
1032 clock-names = "m-ahb", "s-ahb";
1033 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1034 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1035 #address-cells = <2>;
1037 iommus = <&apps_smmu 0x43 0x0>;
1039 status = "disabled";
1042 compatible = "qcom,geni-i2c";
1043 reg = <0 0x00a80000 0 0x4000>;
1045 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_i2c8_default>;
1048 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1049 #address-cells = <1>;
1051 status = "disabled";
1055 compatible = "qcom,geni-spi";
1056 reg = <0 0x00a80000 0 0x4000>;
1058 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1059 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1060 #address-cells = <1>;
1062 power-domains = <&rpmhpd SM8250_CX>;
1063 operating-points-v2 = <&qup_opp_table>;
1064 status = "disabled";
1068 compatible = "qcom,geni-i2c";
1069 reg = <0 0x00a84000 0 0x4000>;
1071 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c9_default>;
1074 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1075 #address-cells = <1>;
1077 status = "disabled";
1081 compatible = "qcom,geni-spi";
1082 reg = <0 0x00a84000 0 0x4000>;
1084 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1085 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1086 #address-cells = <1>;
1088 power-domains = <&rpmhpd SM8250_CX>;
1089 operating-points-v2 = <&qup_opp_table>;
1090 status = "disabled";
1094 compatible = "qcom,geni-i2c";
1095 reg = <0 0x00a88000 0 0x4000>;
1097 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_i2c10_default>;
1100 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1101 #address-cells = <1>;
1103 status = "disabled";
1107 compatible = "qcom,geni-spi";
1108 reg = <0 0x00a88000 0 0x4000>;
1110 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1111 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1112 #address-cells = <1>;
1114 power-domains = <&rpmhpd SM8250_CX>;
1115 operating-points-v2 = <&qup_opp_table>;
1116 status = "disabled";
1120 compatible = "qcom,geni-i2c";
1121 reg = <0 0x00a8c000 0 0x4000>;
1123 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&qup_i2c11_default>;
1126 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1127 #address-cells = <1>;
1129 status = "disabled";
1133 compatible = "qcom,geni-spi";
1134 reg = <0 0x00a8c000 0 0x4000>;
1136 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1137 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1138 #address-cells = <1>;
1140 power-domains = <&rpmhpd SM8250_CX>;
1141 operating-points-v2 = <&qup_opp_table>;
1142 status = "disabled";
1146 compatible = "qcom,geni-i2c";
1147 reg = <0 0x00a90000 0 0x4000>;
1149 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&qup_i2c12_default>;
1152 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1153 #address-cells = <1>;
1155 status = "disabled";
1159 compatible = "qcom,geni-spi";
1160 reg = <0 0x00a90000 0 0x4000>;
1162 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1163 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1164 #address-cells = <1>;
1166 power-domains = <&rpmhpd SM8250_CX>;
1167 operating-points-v2 = <&qup_opp_table>;
1168 status = "disabled";
1171 uart12: serial@a90000 {
1172 compatible = "qcom,geni-debug-uart";
1173 reg = <0x0 0x00a90000 0x0 0x4000>;
1175 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&qup_uart12_default>;
1178 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1179 power-domains = <&rpmhpd SM8250_CX>;
1180 operating-points-v2 = <&qup_opp_table>;
1181 status = "disabled";
1185 compatible = "qcom,geni-i2c";
1186 reg = <0 0x00a94000 0 0x4000>;
1188 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1189 pinctrl-names = "default";
1190 pinctrl-0 = <&qup_i2c13_default>;
1191 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1192 #address-cells = <1>;
1194 status = "disabled";
1198 compatible = "qcom,geni-spi";
1199 reg = <0 0x00a94000 0 0x4000>;
1201 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1202 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1203 #address-cells = <1>;
1205 power-domains = <&rpmhpd SM8250_CX>;
1206 operating-points-v2 = <&qup_opp_table>;
1207 status = "disabled";
1211 config_noc: interconnect@1500000 {
1212 compatible = "qcom,sm8250-config-noc";
1213 reg = <0 0x01500000 0 0xa580>;
1214 #interconnect-cells = <1>;
1215 qcom,bcm-voters = <&apps_bcm_voter>;
1218 system_noc: interconnect@1620000 {
1219 compatible = "qcom,sm8250-system-noc";
1220 reg = <0 0x01620000 0 0x1c200>;
1221 #interconnect-cells = <1>;
1222 qcom,bcm-voters = <&apps_bcm_voter>;
1225 mc_virt: interconnect@163d000 {
1226 compatible = "qcom,sm8250-mc-virt";
1227 reg = <0 0x0163d000 0 0x1000>;
1228 #interconnect-cells = <1>;
1229 qcom,bcm-voters = <&apps_bcm_voter>;
1232 aggre1_noc: interconnect@16e0000 {
1233 compatible = "qcom,sm8250-aggre1-noc";
1234 reg = <0 0x016e0000 0 0x1f180>;
1235 #interconnect-cells = <1>;
1236 qcom,bcm-voters = <&apps_bcm_voter>;
1239 aggre2_noc: interconnect@1700000 {
1240 compatible = "qcom,sm8250-aggre2-noc";
1241 reg = <0 0x01700000 0 0x33000>;
1242 #interconnect-cells = <1>;
1243 qcom,bcm-voters = <&apps_bcm_voter>;
1246 compute_noc: interconnect@1733000 {
1247 compatible = "qcom,sm8250-compute-noc";
1248 reg = <0 0x01733000 0 0xa180>;
1249 #interconnect-cells = <1>;
1250 qcom,bcm-voters = <&apps_bcm_voter>;
1253 mmss_noc: interconnect@1740000 {
1254 compatible = "qcom,sm8250-mmss-noc";
1255 reg = <0 0x01740000 0 0x1f080>;
1256 #interconnect-cells = <1>;
1257 qcom,bcm-voters = <&apps_bcm_voter>;
1260 pcie0: pci@1c00000 {
1261 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1262 reg = <0 0x01c00000 0 0x3000>,
1263 <0 0x60000000 0 0xf1d>,
1264 <0 0x60000f20 0 0xa8>,
1265 <0 0x60001000 0 0x1000>,
1266 <0 0x60100000 0 0x100000>;
1267 reg-names = "parf", "dbi", "elbi", "atu", "config";
1268 device_type = "pci";
1269 linux,pci-domain = <0>;
1270 bus-range = <0x00 0xff>;
1273 #address-cells = <3>;
1276 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1277 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1279 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1280 interrupt-names = "msi";
1281 #interrupt-cells = <1>;
1282 interrupt-map-mask = <0 0 0 0x7>;
1283 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1284 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1285 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1286 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1288 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1289 <&gcc GCC_PCIE_0_AUX_CLK>,
1290 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1291 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1292 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1293 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1294 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1295 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1296 clock-names = "pipe",
1305 iommus = <&apps_smmu 0x1c00 0x7f>;
1306 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1307 <0x100 &apps_smmu 0x1c01 0x1>;
1309 resets = <&gcc GCC_PCIE_0_BCR>;
1310 reset-names = "pci";
1312 power-domains = <&gcc PCIE_0_GDSC>;
1314 phys = <&pcie0_lane>;
1315 phy-names = "pciephy";
1317 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
1318 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&pcie0_default_state>;
1323 status = "disabled";
1326 pcie0_phy: phy@1c06000 {
1327 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1328 reg = <0 0x01c06000 0 0x1c0>;
1329 #address-cells = <2>;
1332 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1333 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1334 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1335 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1336 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1338 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1339 reset-names = "phy";
1341 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1342 assigned-clock-rates = <100000000>;
1344 status = "disabled";
1346 pcie0_lane: lanes@1c06200 {
1347 reg = <0 0x1c06200 0 0x170>, /* tx */
1348 <0 0x1c06400 0 0x200>, /* rx */
1349 <0 0x1c06800 0 0x1f0>, /* pcs */
1350 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1351 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1352 clock-names = "pipe0";
1355 clock-output-names = "pcie_0_pipe_clk";
1359 pcie1: pci@1c08000 {
1360 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1361 reg = <0 0x01c08000 0 0x3000>,
1362 <0 0x40000000 0 0xf1d>,
1363 <0 0x40000f20 0 0xa8>,
1364 <0 0x40001000 0 0x1000>,
1365 <0 0x40100000 0 0x100000>;
1366 reg-names = "parf", "dbi", "elbi", "atu", "config";
1367 device_type = "pci";
1368 linux,pci-domain = <1>;
1369 bus-range = <0x00 0xff>;
1372 #address-cells = <3>;
1375 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1376 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1378 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
1379 interrupt-names = "msi";
1380 #interrupt-cells = <1>;
1381 interrupt-map-mask = <0 0 0 0x7>;
1382 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1383 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1384 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1385 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1387 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1388 <&gcc GCC_PCIE_1_AUX_CLK>,
1389 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1390 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1391 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1392 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1393 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1394 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1395 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1396 clock-names = "pipe",
1406 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1407 assigned-clock-rates = <19200000>;
1409 iommus = <&apps_smmu 0x1c80 0x7f>;
1410 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1411 <0x100 &apps_smmu 0x1c81 0x1>;
1413 resets = <&gcc GCC_PCIE_1_BCR>;
1414 reset-names = "pci";
1416 power-domains = <&gcc PCIE_1_GDSC>;
1418 phys = <&pcie1_lane>;
1419 phy-names = "pciephy";
1421 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
1422 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&pcie1_default_state>;
1427 status = "disabled";
1430 pcie1_phy: phy@1c0e000 {
1431 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1432 reg = <0 0x01c0e000 0 0x1c0>;
1433 #address-cells = <2>;
1436 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1437 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1438 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1439 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1440 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1442 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1443 reset-names = "phy";
1445 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1446 assigned-clock-rates = <100000000>;
1448 status = "disabled";
1450 pcie1_lane: lanes@1c0e200 {
1451 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1452 <0 0x1c0e400 0 0x200>, /* rx0 */
1453 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1454 <0 0x1c0e600 0 0x170>, /* tx1 */
1455 <0 0x1c0e800 0 0x200>, /* rx1 */
1456 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1457 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1458 clock-names = "pipe0";
1461 clock-output-names = "pcie_1_pipe_clk";
1465 pcie2: pci@1c10000 {
1466 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1467 reg = <0 0x01c10000 0 0x3000>,
1468 <0 0x64000000 0 0xf1d>,
1469 <0 0x64000f20 0 0xa8>,
1470 <0 0x64001000 0 0x1000>,
1471 <0 0x64100000 0 0x100000>;
1472 reg-names = "parf", "dbi", "elbi", "atu", "config";
1473 device_type = "pci";
1474 linux,pci-domain = <2>;
1475 bus-range = <0x00 0xff>;
1478 #address-cells = <3>;
1481 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
1482 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
1484 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
1485 interrupt-names = "msi";
1486 #interrupt-cells = <1>;
1487 interrupt-map-mask = <0 0 0 0x7>;
1488 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1489 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1490 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1491 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1493 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1494 <&gcc GCC_PCIE_2_AUX_CLK>,
1495 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1496 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1497 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1498 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1499 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1500 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1501 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1502 clock-names = "pipe",
1512 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1513 assigned-clock-rates = <19200000>;
1515 iommus = <&apps_smmu 0x1d00 0x7f>;
1516 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
1517 <0x100 &apps_smmu 0x1d01 0x1>;
1519 resets = <&gcc GCC_PCIE_2_BCR>;
1520 reset-names = "pci";
1522 power-domains = <&gcc PCIE_2_GDSC>;
1524 phys = <&pcie2_lane>;
1525 phy-names = "pciephy";
1527 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
1528 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&pcie2_default_state>;
1533 status = "disabled";
1536 pcie2_phy: phy@1c16000 {
1537 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1538 reg = <0 0x1c16000 0 0x1c0>;
1539 #address-cells = <2>;
1542 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1543 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1544 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1545 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1546 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1548 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1549 reset-names = "phy";
1551 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1552 assigned-clock-rates = <100000000>;
1554 status = "disabled";
1556 pcie2_lane: lanes@1c16200 {
1557 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1558 <0 0x1c16400 0 0x200>, /* rx0 */
1559 <0 0x1c16a00 0 0x1f0>, /* pcs */
1560 <0 0x1c16600 0 0x170>, /* tx1 */
1561 <0 0x1c16800 0 0x200>, /* rx1 */
1562 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1563 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1564 clock-names = "pipe0";
1567 clock-output-names = "pcie_2_pipe_clk";
1571 ufs_mem_hc: ufshc@1d84000 {
1572 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1574 reg = <0 0x01d84000 0 0x3000>;
1575 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1576 phys = <&ufs_mem_phy_lanes>;
1577 phy-names = "ufsphy";
1578 lanes-per-direction = <2>;
1580 resets = <&gcc GCC_UFS_PHY_BCR>;
1581 reset-names = "rst";
1583 power-domains = <&gcc UFS_PHY_GDSC>;
1585 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1593 "tx_lane0_sync_clk",
1594 "rx_lane0_sync_clk",
1595 "rx_lane1_sync_clk";
1597 <&gcc GCC_UFS_PHY_AXI_CLK>,
1598 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1599 <&gcc GCC_UFS_PHY_AHB_CLK>,
1600 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1601 <&rpmhcc RPMH_CXO_CLK>,
1602 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1603 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1604 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1606 <37500000 300000000>,
1609 <37500000 300000000>,
1615 status = "disabled";
1618 ufs_mem_phy: phy@1d87000 {
1619 compatible = "qcom,sm8250-qmp-ufs-phy";
1620 reg = <0 0x01d87000 0 0x1c0>;
1621 #address-cells = <2>;
1624 clock-names = "ref",
1626 clocks = <&rpmhcc RPMH_CXO_CLK>,
1627 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1629 resets = <&ufs_mem_hc 0>;
1630 reset-names = "ufsphy";
1631 status = "disabled";
1633 ufs_mem_phy_lanes: lanes@1d87400 {
1634 reg = <0 0x01d87400 0 0x108>,
1635 <0 0x01d87600 0 0x1e0>,
1636 <0 0x01d87c00 0 0x1dc>,
1637 <0 0x01d87800 0 0x108>,
1638 <0 0x01d87a00 0 0x1e0>;
1643 ipa_virt: interconnect@1e00000 {
1644 compatible = "qcom,sm8250-ipa-virt";
1645 reg = <0 0x01e00000 0 0x1000>;
1646 #interconnect-cells = <1>;
1647 qcom,bcm-voters = <&apps_bcm_voter>;
1650 tcsr_mutex: hwlock@1f40000 {
1651 compatible = "qcom,tcsr-mutex";
1652 reg = <0x0 0x01f40000 0x0 0x40000>;
1653 #hwlock-cells = <1>;
1656 wsamacro: codec@3240000 {
1657 compatible = "qcom,sm8250-lpass-wsa-macro";
1658 reg = <0 0x03240000 0 0x1000>;
1659 clocks = <&audiocc 1>,
1661 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1662 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1666 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1669 clock-frequency = <9600000>;
1670 clock-output-names = "mclk";
1671 #sound-dai-cells = <1>;
1673 pinctrl-names = "default";
1674 pinctrl-0 = <&wsa_swr_active>;
1677 swr0: soundwire-controller@3250000 {
1678 reg = <0 0x03250000 0 0x2000>;
1679 compatible = "qcom,soundwire-v1.5.1";
1680 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1681 clocks = <&wsamacro>;
1682 clock-names = "iface";
1684 qcom,din-ports = <2>;
1685 qcom,dout-ports = <6>;
1687 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1688 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1689 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1690 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1692 #sound-dai-cells = <1>;
1693 #address-cells = <2>;
1697 audiocc: clock-controller@3300000 {
1698 compatible = "qcom,sm8250-lpass-audiocc";
1699 reg = <0 0x03300000 0 0x30000>;
1701 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1702 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1703 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1704 clock-names = "core", "audio", "bus";
1707 vamacro: codec@3370000 {
1708 compatible = "qcom,sm8250-lpass-va-macro";
1709 reg = <0 0x03370000 0 0x1000>;
1710 clocks = <&aoncc 0>,
1711 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1712 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1714 clock-names = "mclk", "macro", "dcodec";
1717 clock-frequency = <9600000>;
1718 clock-output-names = "fsgen";
1719 #sound-dai-cells = <1>;
1722 aoncc: clock-controller@3380000 {
1723 compatible = "qcom,sm8250-lpass-aoncc";
1724 reg = <0 0x03380000 0 0x40000>;
1726 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1727 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1728 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1729 clock-names = "core", "audio", "bus";
1732 lpass_tlmm: pinctrl@33c0000{
1733 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1734 reg = <0 0x033c0000 0x0 0x20000>,
1735 <0 0x03550000 0x0 0x10000>;
1738 gpio-ranges = <&lpass_tlmm 0 0 14>;
1740 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1741 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1742 clock-names = "core", "audio";
1744 wsa_swr_active: wsa-swr-active-pins {
1747 function = "wsa_swr_clk";
1748 drive-strength = <2>;
1755 function = "wsa_swr_data";
1756 drive-strength = <2>;
1763 wsa_swr_sleep: wsa-swr-sleep-pins {
1766 function = "wsa_swr_clk";
1767 drive-strength = <2>;
1774 function = "wsa_swr_data";
1775 drive-strength = <2>;
1782 dmic01_active: dmic01-active-pins {
1785 function = "dmic1_clk";
1786 drive-strength = <8>;
1791 function = "dmic1_data";
1792 drive-strength = <8>;
1797 dmic01_sleep: dmic01-sleep-pins {
1800 function = "dmic1_clk";
1801 drive-strength = <2>;
1808 function = "dmic1_data";
1809 drive-strength = <2>;
1817 compatible = "qcom,adreno-650.2",
1819 #stream-id-cells = <16>;
1821 reg = <0 0x03d00000 0 0x40000>;
1822 reg-names = "kgsl_3d0_reg_memory";
1824 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1826 iommus = <&adreno_smmu 0 0x401>;
1828 operating-points-v2 = <&gpu_opp_table>;
1832 status = "disabled";
1835 memory-region = <&gpu_mem>;
1838 /* note: downstream checks gpu binning for 670 Mhz */
1839 gpu_opp_table: opp-table {
1840 compatible = "operating-points-v2";
1843 opp-hz = /bits/ 64 <670000000>;
1844 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1848 opp-hz = /bits/ 64 <587000000>;
1849 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1853 opp-hz = /bits/ 64 <525000000>;
1854 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1858 opp-hz = /bits/ 64 <490000000>;
1859 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1863 opp-hz = /bits/ 64 <441600000>;
1864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1868 opp-hz = /bits/ 64 <400000000>;
1869 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1873 opp-hz = /bits/ 64 <305000000>;
1874 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1880 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1882 reg = <0 0x03d6a000 0 0x30000>,
1883 <0 0x3de0000 0 0x10000>,
1884 <0 0xb290000 0 0x10000>,
1885 <0 0xb490000 0 0x10000>;
1886 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1888 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1889 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1890 interrupt-names = "hfi", "gmu";
1892 clocks = <&gpucc GPU_CC_AHB_CLK>,
1893 <&gpucc GPU_CC_CX_GMU_CLK>,
1894 <&gpucc GPU_CC_CXO_CLK>,
1895 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1896 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1897 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1899 power-domains = <&gpucc GPU_CX_GDSC>,
1900 <&gpucc GPU_GX_GDSC>;
1901 power-domain-names = "cx", "gx";
1903 iommus = <&adreno_smmu 5 0x400>;
1905 operating-points-v2 = <&gmu_opp_table>;
1907 status = "disabled";
1909 gmu_opp_table: opp-table {
1910 compatible = "operating-points-v2";
1913 opp-hz = /bits/ 64 <200000000>;
1914 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1919 gpucc: clock-controller@3d90000 {
1920 compatible = "qcom,sm8250-gpucc";
1921 reg = <0 0x03d90000 0 0x9000>;
1922 clocks = <&rpmhcc RPMH_CXO_CLK>,
1923 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1924 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1925 clock-names = "bi_tcxo",
1926 "gcc_gpu_gpll0_clk_src",
1927 "gcc_gpu_gpll0_div_clk_src";
1930 #power-domain-cells = <1>;
1933 adreno_smmu: iommu@3da0000 {
1934 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1935 reg = <0 0x03da0000 0 0x10000>;
1937 #global-interrupts = <2>;
1938 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1948 clocks = <&gpucc GPU_CC_AHB_CLK>,
1949 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1950 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1951 clock-names = "ahb", "bus", "iface";
1953 power-domains = <&gpucc GPU_CX_GDSC>;
1956 slpi: remoteproc@5c00000 {
1957 compatible = "qcom,sm8250-slpi-pas";
1958 reg = <0 0x05c00000 0 0x4000>;
1960 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1961 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1962 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1963 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1964 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1965 interrupt-names = "wdog", "fatal", "ready",
1966 "handover", "stop-ack";
1968 clocks = <&rpmhcc RPMH_CXO_CLK>;
1971 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1972 <&rpmhpd SM8250_LCX>,
1973 <&rpmhpd SM8250_LMX>;
1974 power-domain-names = "load_state", "lcx", "lmx";
1976 memory-region = <&slpi_mem>;
1978 qcom,smem-states = <&smp2p_slpi_out 0>;
1979 qcom,smem-state-names = "stop";
1981 status = "disabled";
1984 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1985 IPCC_MPROC_SIGNAL_GLINK_QMP
1986 IRQ_TYPE_EDGE_RISING>;
1987 mboxes = <&ipcc IPCC_CLIENT_SLPI
1988 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1991 qcom,remote-pid = <3>;
1994 compatible = "qcom,fastrpc";
1995 qcom,glink-channels = "fastrpcglink-apps-dsp";
1997 #address-cells = <1>;
2001 compatible = "qcom,fastrpc-compute-cb";
2003 iommus = <&apps_smmu 0x0541 0x0>;
2007 compatible = "qcom,fastrpc-compute-cb";
2009 iommus = <&apps_smmu 0x0542 0x0>;
2013 compatible = "qcom,fastrpc-compute-cb";
2015 iommus = <&apps_smmu 0x0543 0x0>;
2016 /* note: shared-cb = <4> in downstream */
2022 cdsp: remoteproc@8300000 {
2023 compatible = "qcom,sm8250-cdsp-pas";
2024 reg = <0 0x08300000 0 0x10000>;
2026 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2027 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2028 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2029 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2030 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2031 interrupt-names = "wdog", "fatal", "ready",
2032 "handover", "stop-ack";
2034 clocks = <&rpmhcc RPMH_CXO_CLK>;
2037 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2038 <&rpmhpd SM8250_CX>;
2039 power-domain-names = "load_state", "cx";
2041 memory-region = <&cdsp_mem>;
2043 qcom,smem-states = <&smp2p_cdsp_out 0>;
2044 qcom,smem-state-names = "stop";
2046 status = "disabled";
2049 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2050 IPCC_MPROC_SIGNAL_GLINK_QMP
2051 IRQ_TYPE_EDGE_RISING>;
2052 mboxes = <&ipcc IPCC_CLIENT_CDSP
2053 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2056 qcom,remote-pid = <5>;
2059 compatible = "qcom,fastrpc";
2060 qcom,glink-channels = "fastrpcglink-apps-dsp";
2062 #address-cells = <1>;
2066 compatible = "qcom,fastrpc-compute-cb";
2068 iommus = <&apps_smmu 0x1001 0x0460>;
2072 compatible = "qcom,fastrpc-compute-cb";
2074 iommus = <&apps_smmu 0x1002 0x0460>;
2078 compatible = "qcom,fastrpc-compute-cb";
2080 iommus = <&apps_smmu 0x1003 0x0460>;
2084 compatible = "qcom,fastrpc-compute-cb";
2086 iommus = <&apps_smmu 0x1004 0x0460>;
2090 compatible = "qcom,fastrpc-compute-cb";
2092 iommus = <&apps_smmu 0x1005 0x0460>;
2096 compatible = "qcom,fastrpc-compute-cb";
2098 iommus = <&apps_smmu 0x1006 0x0460>;
2102 compatible = "qcom,fastrpc-compute-cb";
2104 iommus = <&apps_smmu 0x1007 0x0460>;
2108 compatible = "qcom,fastrpc-compute-cb";
2110 iommus = <&apps_smmu 0x1008 0x0460>;
2113 /* note: secure cb9 in downstream */
2121 usb_1_hsphy: phy@88e3000 {
2122 compatible = "qcom,sm8250-usb-hs-phy",
2123 "qcom,usb-snps-hs-7nm-phy";
2124 reg = <0 0x088e3000 0 0x400>;
2125 status = "disabled";
2128 clocks = <&rpmhcc RPMH_CXO_CLK>;
2129 clock-names = "ref";
2131 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2134 usb_2_hsphy: phy@88e4000 {
2135 compatible = "qcom,sm8250-usb-hs-phy",
2136 "qcom,usb-snps-hs-7nm-phy";
2137 reg = <0 0x088e4000 0 0x400>;
2138 status = "disabled";
2141 clocks = <&rpmhcc RPMH_CXO_CLK>;
2142 clock-names = "ref";
2144 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2147 usb_1_qmpphy: phy@88e9000 {
2148 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2149 reg = <0 0x088e9000 0 0x200>,
2150 <0 0x088e8000 0 0x40>,
2151 <0 0x088ea000 0 0x200>;
2152 status = "disabled";
2153 #address-cells = <2>;
2157 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2158 <&rpmhcc RPMH_CXO_CLK>,
2159 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2160 clock-names = "aux", "ref_clk_src", "com_aux";
2162 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2163 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2164 reset-names = "phy", "common";
2166 usb_1_ssphy: usb3-phy@88e9200 {
2167 reg = <0 0x088e9200 0 0x200>,
2168 <0 0x088e9400 0 0x200>,
2169 <0 0x088e9c00 0 0x400>,
2170 <0 0x088e9600 0 0x200>,
2171 <0 0x088e9800 0 0x200>,
2172 <0 0x088e9a00 0 0x100>;
2175 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2176 clock-names = "pipe0";
2177 clock-output-names = "usb3_phy_pipe_clk_src";
2180 dp_phy: dp-phy@88ea200 {
2181 reg = <0 0x088ea200 0 0x200>,
2182 <0 0x088ea400 0 0x200>,
2183 <0 0x088eac00 0 0x400>,
2184 <0 0x088ea600 0 0x200>,
2185 <0 0x088ea800 0 0x200>,
2186 <0 0x088eaa00 0 0x100>;
2189 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2190 clock-names = "pipe0";
2191 clock-output-names = "usb3_phy_pipe_clk_src";
2195 usb_2_qmpphy: phy@88eb000 {
2196 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2197 reg = <0 0x088eb000 0 0x200>;
2198 status = "disabled";
2199 #address-cells = <2>;
2203 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2204 <&rpmhcc RPMH_CXO_CLK>,
2205 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2206 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2207 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2209 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2210 <&gcc GCC_USB3_PHY_SEC_BCR>;
2211 reset-names = "phy", "common";
2213 usb_2_ssphy: lane@88eb200 {
2214 reg = <0 0x088eb200 0 0x200>,
2215 <0 0x088eb400 0 0x200>,
2216 <0 0x088eb800 0 0x800>;
2219 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2220 clock-names = "pipe0";
2221 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2225 sdhc_2: sdhci@8804000 {
2226 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2227 reg = <0 0x08804000 0 0x1000>;
2229 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2231 interrupt-names = "hc_irq", "pwr_irq";
2233 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234 <&gcc GCC_SDCC2_APPS_CLK>,
2235 <&rpmhcc RPMH_CXO_CLK>;
2236 clock-names = "iface", "core", "xo";
2237 iommus = <&apps_smmu 0x4a0 0x0>;
2238 qcom,dll-config = <0x0007642c>;
2239 qcom,ddr-config = <0x80040868>;
2240 power-domains = <&rpmhpd SM8250_CX>;
2241 operating-points-v2 = <&sdhc2_opp_table>;
2243 status = "disabled";
2245 sdhc2_opp_table: sdhc2-opp-table {
2246 compatible = "operating-points-v2";
2249 opp-hz = /bits/ 64 <19200000>;
2250 required-opps = <&rpmhpd_opp_min_svs>;
2254 opp-hz = /bits/ 64 <50000000>;
2255 required-opps = <&rpmhpd_opp_low_svs>;
2259 opp-hz = /bits/ 64 <100000000>;
2260 required-opps = <&rpmhpd_opp_svs>;
2264 opp-hz = /bits/ 64 <202000000>;
2265 required-opps = <&rpmhpd_opp_svs_l1>;
2270 dc_noc: interconnect@90c0000 {
2271 compatible = "qcom,sm8250-dc-noc";
2272 reg = <0 0x090c0000 0 0x4200>;
2273 #interconnect-cells = <1>;
2274 qcom,bcm-voters = <&apps_bcm_voter>;
2277 gem_noc: interconnect@9100000 {
2278 compatible = "qcom,sm8250-gem-noc";
2279 reg = <0 0x09100000 0 0xb4000>;
2280 #interconnect-cells = <1>;
2281 qcom,bcm-voters = <&apps_bcm_voter>;
2284 npu_noc: interconnect@9990000 {
2285 compatible = "qcom,sm8250-npu-noc";
2286 reg = <0 0x09990000 0 0x1600>;
2287 #interconnect-cells = <1>;
2288 qcom,bcm-voters = <&apps_bcm_voter>;
2291 usb_1: usb@a6f8800 {
2292 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2293 reg = <0 0x0a6f8800 0 0x400>;
2294 status = "disabled";
2295 #address-cells = <2>;
2300 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2301 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2302 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2303 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2304 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2305 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2306 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2309 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2310 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2311 assigned-clock-rates = <19200000>, <200000000>;
2313 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2314 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2315 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2316 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2317 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2318 "dm_hs_phy_irq", "ss_phy_irq";
2320 power-domains = <&gcc USB30_PRIM_GDSC>;
2322 resets = <&gcc GCC_USB30_PRIM_BCR>;
2324 usb_1_dwc3: dwc3@a600000 {
2325 compatible = "snps,dwc3";
2326 reg = <0 0x0a600000 0 0xcd00>;
2327 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2328 iommus = <&apps_smmu 0x0 0x0>;
2329 snps,dis_u2_susphy_quirk;
2330 snps,dis_enblslpm_quirk;
2331 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2332 phy-names = "usb2-phy", "usb3-phy";
2336 system-cache-controller@9200000 {
2337 compatible = "qcom,sm8250-llcc";
2338 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2339 reg-names = "llcc_base", "llcc_broadcast_base";
2342 usb_2: usb@a8f8800 {
2343 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2344 reg = <0 0x0a8f8800 0 0x400>;
2345 status = "disabled";
2346 #address-cells = <2>;
2351 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2352 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2353 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2354 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2355 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2356 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2357 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2360 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2361 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2362 assigned-clock-rates = <19200000>, <200000000>;
2364 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2365 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2366 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2367 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2368 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2369 "dm_hs_phy_irq", "ss_phy_irq";
2371 power-domains = <&gcc USB30_SEC_GDSC>;
2373 resets = <&gcc GCC_USB30_SEC_BCR>;
2375 usb_2_dwc3: dwc3@a800000 {
2376 compatible = "snps,dwc3";
2377 reg = <0 0x0a800000 0 0xcd00>;
2378 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2379 iommus = <&apps_smmu 0x20 0>;
2380 snps,dis_u2_susphy_quirk;
2381 snps,dis_enblslpm_quirk;
2382 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2383 phy-names = "usb2-phy", "usb3-phy";
2387 venus: video-codec@aa00000 {
2388 compatible = "qcom,sm8250-venus";
2389 reg = <0 0x0aa00000 0 0x100000>;
2390 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2391 power-domains = <&videocc MVS0C_GDSC>,
2392 <&videocc MVS0_GDSC>,
2393 <&rpmhpd SM8250_MX>;
2394 power-domain-names = "venus", "vcodec0", "mx";
2395 operating-points-v2 = <&venus_opp_table>;
2397 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
2398 <&videocc VIDEO_CC_MVS0C_CLK>,
2399 <&videocc VIDEO_CC_MVS0_CLK>;
2400 clock-names = "iface", "core", "vcodec0_core";
2402 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
2403 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
2404 interconnect-names = "cpu-cfg", "video-mem";
2406 iommus = <&apps_smmu 0x2100 0x0400>;
2407 memory-region = <&video_mem>;
2409 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
2410 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
2411 reset-names = "bus", "core";
2413 status = "disabled";
2416 compatible = "venus-decoder";
2420 compatible = "venus-encoder";
2423 venus_opp_table: venus-opp-table {
2424 compatible = "operating-points-v2";
2427 opp-hz = /bits/ 64 <720000000>;
2428 required-opps = <&rpmhpd_opp_low_svs>;
2432 opp-hz = /bits/ 64 <1014000000>;
2433 required-opps = <&rpmhpd_opp_svs>;
2437 opp-hz = /bits/ 64 <1098000000>;
2438 required-opps = <&rpmhpd_opp_svs_l1>;
2442 opp-hz = /bits/ 64 <1332000000>;
2443 required-opps = <&rpmhpd_opp_nom>;
2448 videocc: clock-controller@abf0000 {
2449 compatible = "qcom,sm8250-videocc";
2450 reg = <0 0x0abf0000 0 0x10000>;
2451 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
2452 <&rpmhcc RPMH_CXO_CLK>,
2453 <&rpmhcc RPMH_CXO_CLK_A>;
2454 mmcx-supply = <&mmcx_reg>;
2455 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
2458 #power-domain-cells = <1>;
2461 mdss: mdss@ae00000 {
2462 compatible = "qcom,sm8250-mdss";
2463 reg = <0 0x0ae00000 0 0x1000>;
2466 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
2467 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
2468 interconnect-names = "mdp0-mem", "mdp1-mem";
2470 power-domains = <&dispcc MDSS_GDSC>;
2472 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2473 <&gcc GCC_DISP_HF_AXI_CLK>,
2474 <&gcc GCC_DISP_SF_AXI_CLK>,
2475 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2476 clock-names = "iface", "bus", "nrt_bus", "core";
2478 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2479 assigned-clock-rates = <460000000>;
2481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2482 interrupt-controller;
2483 #interrupt-cells = <1>;
2485 iommus = <&apps_smmu 0x820 0x402>;
2487 status = "disabled";
2489 #address-cells = <2>;
2493 mdss_mdp: mdp@ae01000 {
2494 compatible = "qcom,sm8250-dpu";
2495 reg = <0 0x0ae01000 0 0x8f000>,
2496 <0 0x0aeb0000 0 0x2008>;
2497 reg-names = "mdp", "vbif";
2499 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2500 <&gcc GCC_DISP_HF_AXI_CLK>,
2501 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2502 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2503 clock-names = "iface", "bus", "core", "vsync";
2505 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2506 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2507 assigned-clock-rates = <460000000>,
2510 operating-points-v2 = <&mdp_opp_table>;
2511 power-domains = <&rpmhpd SM8250_MMCX>;
2513 interrupt-parent = <&mdss>;
2514 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2517 #address-cells = <1>;
2522 dpu_intf1_out: endpoint {
2523 remote-endpoint = <&dsi0_in>;
2529 dpu_intf2_out: endpoint {
2530 remote-endpoint = <&dsi1_in>;
2535 mdp_opp_table: mdp-opp-table {
2536 compatible = "operating-points-v2";
2539 opp-hz = /bits/ 64 <200000000>;
2540 required-opps = <&rpmhpd_opp_low_svs>;
2544 opp-hz = /bits/ 64 <300000000>;
2545 required-opps = <&rpmhpd_opp_svs>;
2549 opp-hz = /bits/ 64 <345000000>;
2550 required-opps = <&rpmhpd_opp_svs_l1>;
2554 opp-hz = /bits/ 64 <460000000>;
2555 required-opps = <&rpmhpd_opp_nom>;
2561 compatible = "qcom,mdss-dsi-ctrl";
2562 reg = <0 0x0ae94000 0 0x400>;
2563 reg-names = "dsi_ctrl";
2565 interrupt-parent = <&mdss>;
2566 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2568 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2569 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2570 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2571 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2572 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2573 <&gcc GCC_DISP_HF_AXI_CLK>;
2574 clock-names = "byte",
2581 operating-points-v2 = <&dsi_opp_table>;
2582 power-domains = <&rpmhpd SM8250_MMCX>;
2587 status = "disabled";
2589 #address-cells = <1>;
2593 #address-cells = <1>;
2599 remote-endpoint = <&dpu_intf1_out>;
2605 dsi0_out: endpoint {
2611 dsi0_phy: dsi-phy@ae94400 {
2612 compatible = "qcom,dsi-phy-7nm";
2613 reg = <0 0x0ae94400 0 0x200>,
2614 <0 0x0ae94600 0 0x280>,
2615 <0 0x0ae94900 0 0x260>;
2616 reg-names = "dsi_phy",
2623 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2624 <&rpmhcc RPMH_CXO_CLK>;
2625 clock-names = "iface", "ref";
2627 status = "disabled";
2631 compatible = "qcom,mdss-dsi-ctrl";
2632 reg = <0 0x0ae96000 0 0x400>;
2633 reg-names = "dsi_ctrl";
2635 interrupt-parent = <&mdss>;
2636 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2638 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2639 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2640 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2641 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2642 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2643 <&gcc GCC_DISP_HF_AXI_CLK>;
2644 clock-names = "byte",
2651 operating-points-v2 = <&dsi_opp_table>;
2652 power-domains = <&rpmhpd SM8250_MMCX>;
2657 status = "disabled";
2659 #address-cells = <1>;
2663 #address-cells = <1>;
2669 remote-endpoint = <&dpu_intf2_out>;
2675 dsi1_out: endpoint {
2681 dsi1_phy: dsi-phy@ae96400 {
2682 compatible = "qcom,dsi-phy-7nm";
2683 reg = <0 0x0ae96400 0 0x200>,
2684 <0 0x0ae96600 0 0x280>,
2685 <0 0x0ae96900 0 0x260>;
2686 reg-names = "dsi_phy",
2693 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2694 <&rpmhcc RPMH_CXO_CLK>;
2695 clock-names = "iface", "ref";
2697 status = "disabled";
2699 dsi_opp_table: dsi-opp-table {
2700 compatible = "operating-points-v2";
2703 opp-hz = /bits/ 64 <187500000>;
2704 required-opps = <&rpmhpd_opp_low_svs>;
2708 opp-hz = /bits/ 64 <300000000>;
2709 required-opps = <&rpmhpd_opp_svs>;
2713 opp-hz = /bits/ 64 <358000000>;
2714 required-opps = <&rpmhpd_opp_svs_l1>;
2720 dispcc: clock-controller@af00000 {
2721 compatible = "qcom,sm8250-dispcc";
2722 reg = <0 0x0af00000 0 0x10000>;
2723 mmcx-supply = <&mmcx_reg>;
2724 clocks = <&rpmhcc RPMH_CXO_CLK>,
2731 clock-names = "bi_tcxo",
2732 "dsi0_phy_pll_out_byteclk",
2733 "dsi0_phy_pll_out_dsiclk",
2734 "dsi1_phy_pll_out_byteclk",
2735 "dsi1_phy_pll_out_dsiclk",
2736 "dp_phy_pll_link_clk",
2737 "dp_phy_pll_vco_div_clk";
2740 #power-domain-cells = <1>;
2743 pdc: interrupt-controller@b220000 {
2744 compatible = "qcom,sm8250-pdc", "qcom,pdc";
2745 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2746 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2747 <125 63 1>, <126 716 12>;
2748 #interrupt-cells = <2>;
2749 interrupt-parent = <&intc>;
2750 interrupt-controller;
2753 tsens0: thermal-sensor@c263000 {
2754 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2755 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2756 <0 0x0c222000 0 0x1ff>; /* SROT */
2757 #qcom,sensors = <16>;
2758 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2759 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2760 interrupt-names = "uplow", "critical";
2761 #thermal-sensor-cells = <1>;
2764 tsens1: thermal-sensor@c265000 {
2765 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2766 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2767 <0 0x0c223000 0 0x1ff>; /* SROT */
2768 #qcom,sensors = <9>;
2769 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2770 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2771 interrupt-names = "uplow", "critical";
2772 #thermal-sensor-cells = <1>;
2775 aoss_qmp: power-controller@c300000 {
2776 compatible = "qcom,sm8250-aoss-qmp";
2777 reg = <0 0x0c300000 0 0x100000>;
2778 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2779 IPCC_MPROC_SIGNAL_GLINK_QMP
2780 IRQ_TYPE_EDGE_RISING>;
2781 mboxes = <&ipcc IPCC_CLIENT_AOP
2782 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2785 #power-domain-cells = <1>;
2788 spmi_bus: spmi@c440000 {
2789 compatible = "qcom,spmi-pmic-arb";
2790 reg = <0x0 0x0c440000 0x0 0x0001100>,
2791 <0x0 0x0c600000 0x0 0x2000000>,
2792 <0x0 0x0e600000 0x0 0x0100000>,
2793 <0x0 0x0e700000 0x0 0x00a0000>,
2794 <0x0 0x0c40a000 0x0 0x0026000>;
2795 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2796 interrupt-names = "periph_irq";
2797 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2800 #address-cells = <2>;
2802 interrupt-controller;
2803 #interrupt-cells = <4>;
2806 tlmm: pinctrl@f100000 {
2807 compatible = "qcom,sm8250-pinctrl";
2808 reg = <0 0x0f100000 0 0x300000>,
2809 <0 0x0f500000 0 0x300000>,
2810 <0 0x0f900000 0 0x300000>;
2811 reg-names = "west", "south", "north";
2812 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2815 interrupt-controller;
2816 #interrupt-cells = <2>;
2817 gpio-ranges = <&tlmm 0 0 181>;
2818 wakeup-parent = <&pdc>;
2820 pri_mi2s_active: pri-mi2s-active {
2823 function = "mi2s0_sck";
2824 drive-strength = <8>;
2830 function = "mi2s0_ws";
2831 drive-strength = <8>;
2837 function = "mi2s0_data0";
2838 drive-strength = <8>;
2845 function = "mi2s0_data1";
2846 drive-strength = <8>;
2851 qup_i2c0_default: qup-i2c0-default {
2853 pins = "gpio28", "gpio29";
2858 pins = "gpio28", "gpio29";
2859 drive-strength = <2>;
2864 qup_i2c1_default: qup-i2c1-default {
2866 pins = "gpio4", "gpio5";
2871 pins = "gpio4", "gpio5";
2872 drive-strength = <2>;
2877 qup_i2c2_default: qup-i2c2-default {
2879 pins = "gpio115", "gpio116";
2884 pins = "gpio115", "gpio116";
2885 drive-strength = <2>;
2890 qup_i2c3_default: qup-i2c3-default {
2892 pins = "gpio119", "gpio120";
2897 pins = "gpio119", "gpio120";
2898 drive-strength = <2>;
2903 qup_i2c4_default: qup-i2c4-default {
2905 pins = "gpio8", "gpio9";
2910 pins = "gpio8", "gpio9";
2911 drive-strength = <2>;
2916 qup_i2c5_default: qup-i2c5-default {
2918 pins = "gpio12", "gpio13";
2923 pins = "gpio12", "gpio13";
2924 drive-strength = <2>;
2929 qup_i2c6_default: qup-i2c6-default {
2931 pins = "gpio16", "gpio17";
2936 pins = "gpio16", "gpio17";
2937 drive-strength = <2>;
2942 qup_i2c7_default: qup-i2c7-default {
2944 pins = "gpio20", "gpio21";
2949 pins = "gpio20", "gpio21";
2950 drive-strength = <2>;
2955 qup_i2c8_default: qup-i2c8-default {
2957 pins = "gpio24", "gpio25";
2962 pins = "gpio24", "gpio25";
2963 drive-strength = <2>;
2968 qup_i2c9_default: qup-i2c9-default {
2970 pins = "gpio125", "gpio126";
2975 pins = "gpio125", "gpio126";
2976 drive-strength = <2>;
2981 qup_i2c10_default: qup-i2c10-default {
2983 pins = "gpio129", "gpio130";
2988 pins = "gpio129", "gpio130";
2989 drive-strength = <2>;
2994 qup_i2c11_default: qup-i2c11-default {
2996 pins = "gpio60", "gpio61";
3001 pins = "gpio60", "gpio61";
3002 drive-strength = <2>;
3007 qup_i2c12_default: qup-i2c12-default {
3009 pins = "gpio32", "gpio33";
3014 pins = "gpio32", "gpio33";
3015 drive-strength = <2>;
3020 qup_i2c13_default: qup-i2c13-default {
3022 pins = "gpio36", "gpio37";
3027 pins = "gpio36", "gpio37";
3028 drive-strength = <2>;
3033 qup_i2c14_default: qup-i2c14-default {
3035 pins = "gpio40", "gpio41";
3040 pins = "gpio40", "gpio41";
3041 drive-strength = <2>;
3046 qup_i2c15_default: qup-i2c15-default {
3048 pins = "gpio44", "gpio45";
3053 pins = "gpio44", "gpio45";
3054 drive-strength = <2>;
3059 qup_i2c16_default: qup-i2c16-default {
3061 pins = "gpio48", "gpio49";
3066 pins = "gpio48", "gpio49";
3067 drive-strength = <2>;
3072 qup_i2c17_default: qup-i2c17-default {
3074 pins = "gpio52", "gpio53";
3079 pins = "gpio52", "gpio53";
3080 drive-strength = <2>;
3085 qup_i2c18_default: qup-i2c18-default {
3087 pins = "gpio56", "gpio57";
3092 pins = "gpio56", "gpio57";
3093 drive-strength = <2>;
3098 qup_i2c19_default: qup-i2c19-default {
3100 pins = "gpio0", "gpio1";
3105 pins = "gpio0", "gpio1";
3106 drive-strength = <2>;
3111 qup_spi0_cs: qup-spi0-cs {
3116 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
3121 qup_spi0_data_clk: qup-spi0-data-clk {
3122 pins = "gpio28", "gpio29",
3127 qup_spi1_cs: qup-spi1-cs {
3132 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
3137 qup_spi1_data_clk: qup-spi1-data-clk {
3138 pins = "gpio4", "gpio5",
3143 qup_spi2_cs: qup-spi2-cs {
3148 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
3153 qup_spi2_data_clk: qup-spi2-data-clk {
3154 pins = "gpio115", "gpio116",
3159 qup_spi3_cs: qup-spi3-cs {
3164 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
3169 qup_spi3_data_clk: qup-spi3-data-clk {
3170 pins = "gpio119", "gpio120",
3175 qup_spi4_cs: qup-spi4-cs {
3180 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
3185 qup_spi4_data_clk: qup-spi4-data-clk {
3186 pins = "gpio8", "gpio9",
3191 qup_spi5_cs: qup-spi5-cs {
3196 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
3201 qup_spi5_data_clk: qup-spi5-data-clk {
3202 pins = "gpio12", "gpio13",
3207 qup_spi6_cs: qup-spi6-cs {
3212 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
3217 qup_spi6_data_clk: qup-spi6-data-clk {
3218 pins = "gpio16", "gpio17",
3223 qup_spi7_cs: qup-spi7-cs {
3228 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
3233 qup_spi7_data_clk: qup-spi7-data-clk {
3234 pins = "gpio20", "gpio21",
3239 qup_spi8_cs: qup-spi8-cs {
3244 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
3249 qup_spi8_data_clk: qup-spi8-data-clk {
3250 pins = "gpio24", "gpio25",
3255 qup_spi9_cs: qup-spi9-cs {
3260 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
3265 qup_spi9_data_clk: qup-spi9-data-clk {
3266 pins = "gpio125", "gpio126",
3271 qup_spi10_cs: qup-spi10-cs {
3276 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
3281 qup_spi10_data_clk: qup-spi10-data-clk {
3282 pins = "gpio129", "gpio130",
3287 qup_spi11_cs: qup-spi11-cs {
3292 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
3297 qup_spi11_data_clk: qup-spi11-data-clk {
3298 pins = "gpio60", "gpio61",
3303 qup_spi12_cs: qup-spi12-cs {
3308 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
3313 qup_spi12_data_clk: qup-spi12-data-clk {
3314 pins = "gpio32", "gpio33",
3319 qup_spi13_cs: qup-spi13-cs {
3324 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
3329 qup_spi13_data_clk: qup-spi13-data-clk {
3330 pins = "gpio36", "gpio37",
3335 qup_spi14_cs: qup-spi14-cs {
3340 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
3345 qup_spi14_data_clk: qup-spi14-data-clk {
3346 pins = "gpio40", "gpio41",
3351 qup_spi15_cs: qup-spi15-cs {
3356 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
3361 qup_spi15_data_clk: qup-spi15-data-clk {
3362 pins = "gpio44", "gpio45",
3367 qup_spi16_cs: qup-spi16-cs {
3372 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
3377 qup_spi16_data_clk: qup-spi16-data-clk {
3378 pins = "gpio48", "gpio49",
3383 qup_spi17_cs: qup-spi17-cs {
3388 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
3393 qup_spi17_data_clk: qup-spi17-data-clk {
3394 pins = "gpio52", "gpio53",
3399 qup_spi18_cs: qup-spi18-cs {
3404 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
3409 qup_spi18_data_clk: qup-spi18-data-clk {
3410 pins = "gpio56", "gpio57",
3415 qup_spi19_cs: qup-spi19-cs {
3420 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
3425 qup_spi19_data_clk: qup-spi19-data-clk {
3426 pins = "gpio0", "gpio1",
3431 qup_uart2_default: qup-uart2-default {
3433 pins = "gpio117", "gpio118";
3438 qup_uart6_default: qup-uart6-default {
3440 pins = "gpio16", "gpio17",
3446 qup_uart12_default: qup-uart12-default {
3448 pins = "gpio34", "gpio35";
3453 qup_uart17_default: qup-uart17-default {
3455 pins = "gpio52", "gpio53",
3461 qup_uart18_default: qup-uart18-default {
3463 pins = "gpio58", "gpio59";
3468 tert_mi2s_active: tert-mi2s-active {
3471 function = "mi2s2_sck";
3472 drive-strength = <8>;
3478 function = "mi2s2_data0";
3479 drive-strength = <8>;
3486 function = "mi2s2_ws";
3487 drive-strength = <8>;
3492 sdc2_sleep_state: sdc2-sleep {
3495 drive-strength = <2>;
3501 drive-strength = <2>;
3507 drive-strength = <2>;
3512 pcie0_default_state: pcie0-default {
3516 drive-strength = <2>;
3522 function = "pci_e0";
3523 drive-strength = <2>;
3530 drive-strength = <2>;
3535 pcie1_default_state: pcie1-default {
3539 drive-strength = <2>;
3545 function = "pci_e1";
3546 drive-strength = <2>;
3553 drive-strength = <2>;
3558 pcie2_default_state: pcie2-default {
3562 drive-strength = <2>;
3568 function = "pci_e2";
3569 drive-strength = <2>;
3576 drive-strength = <2>;
3582 apps_smmu: iommu@15000000 {
3583 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3584 reg = <0 0x15000000 0 0x100000>;
3586 #global-interrupts = <2>;
3587 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3628 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3629 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3630 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3631 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3632 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3633 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3634 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3635 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3636 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3637 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3638 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3639 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3640 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3641 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3642 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3643 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3644 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3645 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3646 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3647 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3648 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3649 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3650 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3651 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3652 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3653 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3654 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3655 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3656 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3657 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3658 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3659 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3660 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3661 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3662 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3663 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3664 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3665 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3666 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3667 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3668 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3669 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3670 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3671 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3672 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3673 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3674 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3675 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3676 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3677 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3678 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3679 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3680 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3681 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3682 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3683 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3684 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3687 adsp: remoteproc@17300000 {
3688 compatible = "qcom,sm8250-adsp-pas";
3689 reg = <0 0x17300000 0 0x100>;
3691 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3692 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3693 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3694 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3695 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3696 interrupt-names = "wdog", "fatal", "ready",
3697 "handover", "stop-ack";
3699 clocks = <&rpmhcc RPMH_CXO_CLK>;
3702 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3703 <&rpmhpd SM8250_LCX>,
3704 <&rpmhpd SM8250_LMX>;
3705 power-domain-names = "load_state", "lcx", "lmx";
3707 memory-region = <&adsp_mem>;
3709 qcom,smem-states = <&smp2p_adsp_out 0>;
3710 qcom,smem-state-names = "stop";
3712 status = "disabled";
3715 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3716 IPCC_MPROC_SIGNAL_GLINK_QMP
3717 IRQ_TYPE_EDGE_RISING>;
3718 mboxes = <&ipcc IPCC_CLIENT_LPASS
3719 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3722 qcom,remote-pid = <2>;
3725 compatible = "qcom,apr-v2";
3726 qcom,glink-channels = "apr_audio_svc";
3727 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3728 #address-cells = <1>;
3732 reg = <APR_SVC_ADSP_CORE>;
3733 compatible = "qcom,q6core";
3734 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3737 q6afe: apr-service@4 {
3738 compatible = "qcom,q6afe";
3739 reg = <APR_SVC_AFE>;
3740 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3742 compatible = "qcom,q6afe-dais";
3743 #address-cells = <1>;
3745 #sound-dai-cells = <1>;
3749 compatible = "qcom,q6afe-clocks";
3754 q6asm: apr-service@7 {
3755 compatible = "qcom,q6asm";
3756 reg = <APR_SVC_ASM>;
3757 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3759 compatible = "qcom,q6asm-dais";
3760 #address-cells = <1>;
3762 #sound-dai-cells = <1>;
3763 iommus = <&apps_smmu 0x1801 0x0>;
3767 q6adm: apr-service@8 {
3768 compatible = "qcom,q6adm";
3769 reg = <APR_SVC_ADM>;
3770 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3771 q6routing: routing {
3772 compatible = "qcom,q6adm-routing";
3773 #sound-dai-cells = <0>;
3779 compatible = "qcom,fastrpc";
3780 qcom,glink-channels = "fastrpcglink-apps-dsp";
3782 #address-cells = <1>;
3786 compatible = "qcom,fastrpc-compute-cb";
3788 iommus = <&apps_smmu 0x1803 0x0>;
3792 compatible = "qcom,fastrpc-compute-cb";
3794 iommus = <&apps_smmu 0x1804 0x0>;
3798 compatible = "qcom,fastrpc-compute-cb";
3800 iommus = <&apps_smmu 0x1805 0x0>;
3806 intc: interrupt-controller@17a00000 {
3807 compatible = "arm,gic-v3";
3808 #interrupt-cells = <3>;
3809 interrupt-controller;
3810 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3811 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3812 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3816 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3817 reg = <0 0x17c10000 0 0x1000>;
3818 clocks = <&sleep_clk>;
3819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3823 #address-cells = <2>;
3826 compatible = "arm,armv7-timer-mem";
3827 reg = <0x0 0x17c20000 0x0 0x1000>;
3828 clock-frequency = <19200000>;
3832 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3833 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3834 reg = <0x0 0x17c21000 0x0 0x1000>,
3835 <0x0 0x17c22000 0x0 0x1000>;
3840 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3841 reg = <0x0 0x17c23000 0x0 0x1000>;
3842 status = "disabled";
3847 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3848 reg = <0x0 0x17c25000 0x0 0x1000>;
3849 status = "disabled";
3854 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3855 reg = <0x0 0x17c27000 0x0 0x1000>;
3856 status = "disabled";
3861 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3862 reg = <0x0 0x17c29000 0x0 0x1000>;
3863 status = "disabled";
3868 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3869 reg = <0x0 0x17c2b000 0x0 0x1000>;
3870 status = "disabled";
3875 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3876 reg = <0x0 0x17c2d000 0x0 0x1000>;
3877 status = "disabled";
3881 apps_rsc: rsc@18200000 {
3883 compatible = "qcom,rpmh-rsc";
3884 reg = <0x0 0x18200000 0x0 0x10000>,
3885 <0x0 0x18210000 0x0 0x10000>,
3886 <0x0 0x18220000 0x0 0x10000>;
3887 reg-names = "drv-0", "drv-1", "drv-2";
3888 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3889 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3890 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3891 qcom,tcs-offset = <0xd00>;
3893 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3894 <WAKE_TCS 3>, <CONTROL_TCS 1>;
3896 rpmhcc: clock-controller {
3897 compatible = "qcom,sm8250-rpmh-clk";
3900 clocks = <&xo_board>;
3903 rpmhpd: power-controller {
3904 compatible = "qcom,sm8250-rpmhpd";
3905 #power-domain-cells = <1>;
3906 operating-points-v2 = <&rpmhpd_opp_table>;
3908 rpmhpd_opp_table: opp-table {
3909 compatible = "operating-points-v2";
3911 rpmhpd_opp_ret: opp1 {
3912 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3915 rpmhpd_opp_min_svs: opp2 {
3916 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3919 rpmhpd_opp_low_svs: opp3 {
3920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3923 rpmhpd_opp_svs: opp4 {
3924 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3927 rpmhpd_opp_svs_l1: opp5 {
3928 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3931 rpmhpd_opp_nom: opp6 {
3932 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3935 rpmhpd_opp_nom_l1: opp7 {
3936 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3939 rpmhpd_opp_nom_l2: opp8 {
3940 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3943 rpmhpd_opp_turbo: opp9 {
3944 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3947 rpmhpd_opp_turbo_l1: opp10 {
3948 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3953 apps_bcm_voter: bcm_voter {
3954 compatible = "qcom,bcm-voter";
3958 epss_l3: interconnect@18591000 {
3959 compatible = "qcom,sm8250-epss-l3";
3960 reg = <0 0x18590000 0 0x1000>;
3962 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3963 clock-names = "xo", "alternate";
3965 #interconnect-cells = <1>;
3968 cpufreq_hw: cpufreq@18591000 {
3969 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3970 reg = <0 0x18591000 0 0x1000>,
3971 <0 0x18592000 0 0x1000>,
3972 <0 0x18593000 0 0x1000>;
3973 reg-names = "freq-domain0", "freq-domain1",
3976 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3977 clock-names = "xo", "alternate";
3979 #freq-domain-cells = <1>;
3984 compatible = "arm,armv8-timer";
3985 interrupts = <GIC_PPI 13
3986 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3988 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3990 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3992 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3997 polling-delay-passive = <250>;
3998 polling-delay = <1000>;
4000 thermal-sensors = <&tsens0 1>;
4003 cpu0_alert0: trip-point0 {
4004 temperature = <90000>;
4005 hysteresis = <2000>;
4009 cpu0_alert1: trip-point1 {
4010 temperature = <95000>;
4011 hysteresis = <2000>;
4015 cpu0_crit: cpu_crit {
4016 temperature = <110000>;
4017 hysteresis = <1000>;
4024 trip = <&cpu0_alert0>;
4025 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4026 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4027 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4028 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4031 trip = <&cpu0_alert1>;
4032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4033 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4034 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4041 polling-delay-passive = <250>;
4042 polling-delay = <1000>;
4044 thermal-sensors = <&tsens0 2>;
4047 cpu1_alert0: trip-point0 {
4048 temperature = <90000>;
4049 hysteresis = <2000>;
4053 cpu1_alert1: trip-point1 {
4054 temperature = <95000>;
4055 hysteresis = <2000>;
4059 cpu1_crit: cpu_crit {
4060 temperature = <110000>;
4061 hysteresis = <1000>;
4068 trip = <&cpu1_alert0>;
4069 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4072 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4075 trip = <&cpu1_alert1>;
4076 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4085 polling-delay-passive = <250>;
4086 polling-delay = <1000>;
4088 thermal-sensors = <&tsens0 3>;
4091 cpu2_alert0: trip-point0 {
4092 temperature = <90000>;
4093 hysteresis = <2000>;
4097 cpu2_alert1: trip-point1 {
4098 temperature = <95000>;
4099 hysteresis = <2000>;
4103 cpu2_crit: cpu_crit {
4104 temperature = <110000>;
4105 hysteresis = <1000>;
4112 trip = <&cpu2_alert0>;
4113 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4114 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4119 trip = <&cpu2_alert1>;
4120 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4121 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4122 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4123 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 polling-delay-passive = <250>;
4130 polling-delay = <1000>;
4132 thermal-sensors = <&tsens0 4>;
4135 cpu3_alert0: trip-point0 {
4136 temperature = <90000>;
4137 hysteresis = <2000>;
4141 cpu3_alert1: trip-point1 {
4142 temperature = <95000>;
4143 hysteresis = <2000>;
4147 cpu3_crit: cpu_crit {
4148 temperature = <110000>;
4149 hysteresis = <1000>;
4156 trip = <&cpu3_alert0>;
4157 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4158 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4159 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4160 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4163 trip = <&cpu3_alert1>;
4164 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4173 polling-delay-passive = <250>;
4174 polling-delay = <1000>;
4176 thermal-sensors = <&tsens0 7>;
4179 cpu4_top_alert0: trip-point0 {
4180 temperature = <90000>;
4181 hysteresis = <2000>;
4185 cpu4_top_alert1: trip-point1 {
4186 temperature = <95000>;
4187 hysteresis = <2000>;
4191 cpu4_top_crit: cpu_crit {
4192 temperature = <110000>;
4193 hysteresis = <1000>;
4200 trip = <&cpu4_top_alert0>;
4201 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4202 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4203 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4204 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4207 trip = <&cpu4_top_alert1>;
4208 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4209 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4210 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4217 polling-delay-passive = <250>;
4218 polling-delay = <1000>;
4220 thermal-sensors = <&tsens0 8>;
4223 cpu5_top_alert0: trip-point0 {
4224 temperature = <90000>;
4225 hysteresis = <2000>;
4229 cpu5_top_alert1: trip-point1 {
4230 temperature = <95000>;
4231 hysteresis = <2000>;
4235 cpu5_top_crit: cpu_crit {
4236 temperature = <110000>;
4237 hysteresis = <1000>;
4244 trip = <&cpu5_top_alert0>;
4245 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4246 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4247 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4248 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4251 trip = <&cpu5_top_alert1>;
4252 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4253 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4254 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4255 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4261 polling-delay-passive = <250>;
4262 polling-delay = <1000>;
4264 thermal-sensors = <&tsens0 9>;
4267 cpu6_top_alert0: trip-point0 {
4268 temperature = <90000>;
4269 hysteresis = <2000>;
4273 cpu6_top_alert1: trip-point1 {
4274 temperature = <95000>;
4275 hysteresis = <2000>;
4279 cpu6_top_crit: cpu_crit {
4280 temperature = <110000>;
4281 hysteresis = <1000>;
4288 trip = <&cpu6_top_alert0>;
4289 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4290 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4291 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4292 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4295 trip = <&cpu6_top_alert1>;
4296 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4297 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4298 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4299 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4305 polling-delay-passive = <250>;
4306 polling-delay = <1000>;
4308 thermal-sensors = <&tsens0 10>;
4311 cpu7_top_alert0: trip-point0 {
4312 temperature = <90000>;
4313 hysteresis = <2000>;
4317 cpu7_top_alert1: trip-point1 {
4318 temperature = <95000>;
4319 hysteresis = <2000>;
4323 cpu7_top_crit: cpu_crit {
4324 temperature = <110000>;
4325 hysteresis = <1000>;
4332 trip = <&cpu7_top_alert0>;
4333 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4334 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4335 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4339 trip = <&cpu7_top_alert1>;
4340 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4341 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4342 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4343 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4348 cpu4-bottom-thermal {
4349 polling-delay-passive = <250>;
4350 polling-delay = <1000>;
4352 thermal-sensors = <&tsens0 11>;
4355 cpu4_bottom_alert0: trip-point0 {
4356 temperature = <90000>;
4357 hysteresis = <2000>;
4361 cpu4_bottom_alert1: trip-point1 {
4362 temperature = <95000>;
4363 hysteresis = <2000>;
4367 cpu4_bottom_crit: cpu_crit {
4368 temperature = <110000>;
4369 hysteresis = <1000>;
4376 trip = <&cpu4_bottom_alert0>;
4377 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4378 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4379 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4380 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4383 trip = <&cpu4_bottom_alert1>;
4384 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4385 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4386 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4387 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4392 cpu5-bottom-thermal {
4393 polling-delay-passive = <250>;
4394 polling-delay = <1000>;
4396 thermal-sensors = <&tsens0 12>;
4399 cpu5_bottom_alert0: trip-point0 {
4400 temperature = <90000>;
4401 hysteresis = <2000>;
4405 cpu5_bottom_alert1: trip-point1 {
4406 temperature = <95000>;
4407 hysteresis = <2000>;
4411 cpu5_bottom_crit: cpu_crit {
4412 temperature = <110000>;
4413 hysteresis = <1000>;
4420 trip = <&cpu5_bottom_alert0>;
4421 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4422 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4423 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4424 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4427 trip = <&cpu5_bottom_alert1>;
4428 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4429 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4430 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4431 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 cpu6-bottom-thermal {
4437 polling-delay-passive = <250>;
4438 polling-delay = <1000>;
4440 thermal-sensors = <&tsens0 13>;
4443 cpu6_bottom_alert0: trip-point0 {
4444 temperature = <90000>;
4445 hysteresis = <2000>;
4449 cpu6_bottom_alert1: trip-point1 {
4450 temperature = <95000>;
4451 hysteresis = <2000>;
4455 cpu6_bottom_crit: cpu_crit {
4456 temperature = <110000>;
4457 hysteresis = <1000>;
4464 trip = <&cpu6_bottom_alert0>;
4465 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4466 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4467 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4468 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4471 trip = <&cpu6_bottom_alert1>;
4472 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4473 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4474 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4480 cpu7-bottom-thermal {
4481 polling-delay-passive = <250>;
4482 polling-delay = <1000>;
4484 thermal-sensors = <&tsens0 14>;
4487 cpu7_bottom_alert0: trip-point0 {
4488 temperature = <90000>;
4489 hysteresis = <2000>;
4493 cpu7_bottom_alert1: trip-point1 {
4494 temperature = <95000>;
4495 hysteresis = <2000>;
4499 cpu7_bottom_crit: cpu_crit {
4500 temperature = <110000>;
4501 hysteresis = <1000>;
4508 trip = <&cpu7_bottom_alert0>;
4509 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4510 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4511 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4512 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4515 trip = <&cpu7_bottom_alert1>;
4516 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4517 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4518 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4519 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4525 polling-delay-passive = <250>;
4526 polling-delay = <1000>;
4528 thermal-sensors = <&tsens0 0>;
4531 aoss0_alert0: trip-point0 {
4532 temperature = <90000>;
4533 hysteresis = <2000>;
4540 polling-delay-passive = <250>;
4541 polling-delay = <1000>;
4543 thermal-sensors = <&tsens0 5>;
4546 cluster0_alert0: trip-point0 {
4547 temperature = <90000>;
4548 hysteresis = <2000>;
4551 cluster0_crit: cluster0_crit {
4552 temperature = <110000>;
4553 hysteresis = <2000>;
4560 polling-delay-passive = <250>;
4561 polling-delay = <1000>;
4563 thermal-sensors = <&tsens0 6>;
4566 cluster1_alert0: trip-point0 {
4567 temperature = <90000>;
4568 hysteresis = <2000>;
4571 cluster1_crit: cluster1_crit {
4572 temperature = <110000>;
4573 hysteresis = <2000>;
4580 polling-delay-passive = <250>;
4581 polling-delay = <1000>;
4583 thermal-sensors = <&tsens0 15>;
4586 gpu1_alert0: trip-point0 {
4587 temperature = <90000>;
4588 hysteresis = <2000>;
4595 polling-delay-passive = <250>;
4596 polling-delay = <1000>;
4598 thermal-sensors = <&tsens1 0>;
4601 aoss1_alert0: trip-point0 {
4602 temperature = <90000>;
4603 hysteresis = <2000>;
4610 polling-delay-passive = <250>;
4611 polling-delay = <1000>;
4613 thermal-sensors = <&tsens1 1>;
4616 wlan_alert0: trip-point0 {
4617 temperature = <90000>;
4618 hysteresis = <2000>;
4625 polling-delay-passive = <250>;
4626 polling-delay = <1000>;
4628 thermal-sensors = <&tsens1 2>;
4631 video_alert0: trip-point0 {
4632 temperature = <90000>;
4633 hysteresis = <2000>;
4640 polling-delay-passive = <250>;
4641 polling-delay = <1000>;
4643 thermal-sensors = <&tsens1 3>;
4646 mem_alert0: trip-point0 {
4647 temperature = <90000>;
4648 hysteresis = <2000>;
4655 polling-delay-passive = <250>;
4656 polling-delay = <1000>;
4658 thermal-sensors = <&tsens1 4>;
4661 q6_hvx_alert0: trip-point0 {
4662 temperature = <90000>;
4663 hysteresis = <2000>;
4670 polling-delay-passive = <250>;
4671 polling-delay = <1000>;
4673 thermal-sensors = <&tsens1 5>;
4676 camera_alert0: trip-point0 {
4677 temperature = <90000>;
4678 hysteresis = <2000>;
4685 polling-delay-passive = <250>;
4686 polling-delay = <1000>;
4688 thermal-sensors = <&tsens1 6>;
4691 compute_alert0: trip-point0 {
4692 temperature = <90000>;
4693 hysteresis = <2000>;
4700 polling-delay-passive = <250>;
4701 polling-delay = <1000>;
4703 thermal-sensors = <&tsens1 7>;
4706 npu_alert0: trip-point0 {
4707 temperature = <90000>;
4708 hysteresis = <2000>;
4714 gpu-thermal-bottom {
4715 polling-delay-passive = <250>;
4716 polling-delay = <1000>;
4718 thermal-sensors = <&tsens1 8>;
4721 gpu2_alert0: trip-point0 {
4722 temperature = <90000>;
4723 hysteresis = <2000>;