arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/mailbox/qcom-ipcc.h>
  10 #include <dt-bindings/power/qcom-aoss-qmp.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 i2c6 = &i2c6;
  28                 i2c7 = &i2c7;
  29                 i2c8 = &i2c8;
  30                 i2c9 = &i2c9;
  31                 i2c10 = &i2c10;
  32                 i2c11 = &i2c11;
  33                 i2c12 = &i2c12;
  34                 i2c13 = &i2c13;
  35                 i2c14 = &i2c14;
  36                 i2c15 = &i2c15;
  37                 i2c16 = &i2c16;
  38                 i2c17 = &i2c17;
  39                 i2c18 = &i2c18;
  40                 i2c19 = &i2c19;
  41                 spi0 = &spi0;
  42                 spi1 = &spi1;
  43                 spi2 = &spi2;
  44                 spi3 = &spi3;
  45                 spi4 = &spi4;
  46                 spi5 = &spi5;
  47                 spi6 = &spi6;
  48                 spi7 = &spi7;
  49                 spi8 = &spi8;
  50                 spi9 = &spi9;
  51                 spi10 = &spi10;
  52                 spi11 = &spi11;
  53                 spi12 = &spi12;
  54                 spi13 = &spi13;
  55                 spi14 = &spi14;
  56                 spi15 = &spi15;
  57                 spi16 = &spi16;
  58                 spi17 = &spi17;
  59                 spi18 = &spi18;
  60                 spi19 = &spi19;
  61         };
  62
  63         chosen { };
  64
  65         clocks {
  66                 xo_board: xo-board {
  67                         compatible = "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <38400000>;
  70                         clock-output-names = "xo_board";
  71                 };
  72
  73                 sleep_clk: sleep-clk {
  74                         compatible = "fixed-clock";
  75                         clock-frequency = <32000>;
  76                         #clock-cells = <0>;
  77                 };
  78         };
  79
  80         cpus {
  81                 #address-cells = <2>;
  82                 #size-cells = <0>;
  83
  84                 CPU0: cpu@0 {
  85                         device_type = "cpu";
  86                         compatible = "qcom,kryo485";
  87                         reg = <0x0 0x0>;
  88                         enable-method = "psci";
  89                         next-level-cache = <&L2_0>;
  90                         L2_0: l2-cache {
  91                               compatible = "cache";
  92                               next-level-cache = <&L3_0>;
  93                                 L3_0: l3-cache {
  94                                       compatible = "cache";
  95                                 };
  96                         };
  97                 };
  98
  99                 CPU1: cpu@100 {
 100                         device_type = "cpu";
 101                         compatible = "qcom,kryo485";
 102                         reg = <0x0 0x100>;
 103                         enable-method = "psci";
 104                         next-level-cache = <&L2_100>;
 105                         L2_100: l2-cache {
 106                               compatible = "cache";
 107                               next-level-cache = <&L3_0>;
 108                         };
 109                 };
 110
 111                 CPU2: cpu@200 {
 112                         device_type = "cpu";
 113                         compatible = "qcom,kryo485";
 114                         reg = <0x0 0x200>;
 115                         enable-method = "psci";
 116                         next-level-cache = <&L2_200>;
 117                         L2_200: l2-cache {
 118                               compatible = "cache";
 119                               next-level-cache = <&L3_0>;
 120                         };
 121                 };
 122
 123                 CPU3: cpu@300 {
 124                         device_type = "cpu";
 125                         compatible = "qcom,kryo485";
 126                         reg = <0x0 0x300>;
 127                         enable-method = "psci";
 128                         next-level-cache = <&L2_300>;
 129                         L2_300: l2-cache {
 130                               compatible = "cache";
 131                               next-level-cache = <&L3_0>;
 132                         };
 133                 };
 134
 135                 CPU4: cpu@400 {
 136                         device_type = "cpu";
 137                         compatible = "qcom,kryo485";
 138                         reg = <0x0 0x400>;
 139                         enable-method = "psci";
 140                         next-level-cache = <&L2_400>;
 141                         L2_400: l2-cache {
 142                               compatible = "cache";
 143                               next-level-cache = <&L3_0>;
 144                         };
 145                 };
 146
 147                 CPU5: cpu@500 {
 148                         device_type = "cpu";
 149                         compatible = "qcom,kryo485";
 150                         reg = <0x0 0x500>;
 151                         enable-method = "psci";
 152                         next-level-cache = <&L2_500>;
 153                         L2_500: l2-cache {
 154                               compatible = "cache";
 155                               next-level-cache = <&L3_0>;
 156                         };
 157
 158                 };
 159
 160                 CPU6: cpu@600 {
 161                         device_type = "cpu";
 162                         compatible = "qcom,kryo485";
 163                         reg = <0x0 0x600>;
 164                         enable-method = "psci";
 165                         next-level-cache = <&L2_600>;
 166                         L2_600: l2-cache {
 167                               compatible = "cache";
 168                               next-level-cache = <&L3_0>;
 169                         };
 170                 };
 171
 172                 CPU7: cpu@700 {
 173                         device_type = "cpu";
 174                         compatible = "qcom,kryo485";
 175                         reg = <0x0 0x700>;
 176                         enable-method = "psci";
 177                         next-level-cache = <&L2_700>;
 178                         L2_700: l2-cache {
 179                               compatible = "cache";
 180                               next-level-cache = <&L3_0>;
 181                         };
 182                 };
 183         };
 184
 185         firmware {
 186                 scm: scm {
 187                         compatible = "qcom,scm";
 188                         #reset-cells = <1>;
 189                 };
 190         };
 191
 192         memory@80000000 {
 193                 device_type = "memory";
 194                 /* We expect the bootloader to fill in the size */
 195                 reg = <0x0 0x80000000 0x0 0x0>;
 196         };
 197
 198         pmu {
 199                 compatible = "arm,armv8-pmuv3";
 200                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 201         };
 202
 203         psci {
 204                 compatible = "arm,psci-1.0";
 205                 method = "smc";
 206         };
 207
 208         reserved-memory {
 209                 #address-cells = <2>;
 210                 #size-cells = <2>;
 211                 ranges;
 212
 213                 hyp_mem: memory@80000000 {
 214                         reg = <0x0 0x80000000 0x0 0x600000>;
 215                         no-map;
 216                 };
 217
 218                 xbl_aop_mem: memory@80700000 {
 219                         reg = <0x0 0x80700000 0x0 0x160000>;
 220                         no-map;
 221                 };
 222
 223                 cmd_db: memory@80860000 {
 224                         compatible = "qcom,cmd-db";
 225                         reg = <0x0 0x80860000 0x0 0x20000>;
 226                         no-map;
 227                 };
 228
 229                 smem_mem: memory@80900000 {
 230                         reg = <0x0 0x80900000 0x0 0x200000>;
 231                         no-map;
 232                 };
 233
 234                 removed_mem: memory@80b00000 {
 235                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 236                         no-map;
 237                 };
 238
 239                 camera_mem: memory@86200000 {
 240                         reg = <0x0 0x86200000 0x0 0x500000>;
 241                         no-map;
 242                 };
 243
 244                 wlan_mem: memory@86700000 {
 245                         reg = <0x0 0x86700000 0x0 0x100000>;
 246                         no-map;
 247                 };
 248
 249                 ipa_fw_mem: memory@86800000 {
 250                         reg = <0x0 0x86800000 0x0 0x10000>;
 251                         no-map;
 252                 };
 253
 254                 ipa_gsi_mem: memory@86810000 {
 255                         reg = <0x0 0x86810000 0x0 0xa000>;
 256                         no-map;
 257                 };
 258
 259                 gpu_mem: memory@8681a000 {
 260                         reg = <0x0 0x8681a000 0x0 0x2000>;
 261                         no-map;
 262                 };
 263
 264                 npu_mem: memory@86900000 {
 265                         reg = <0x0 0x86900000 0x0 0x500000>;
 266                         no-map;
 267                 };
 268
 269                 video_mem: memory@86e00000 {
 270                         reg = <0x0 0x86e00000 0x0 0x500000>;
 271                         no-map;
 272                 };
 273
 274                 cvp_mem: memory@87300000 {
 275                         reg = <0x0 0x87300000 0x0 0x500000>;
 276                         no-map;
 277                 };
 278
 279                 cdsp_mem: memory@87800000 {
 280                         reg = <0x0 0x87800000 0x0 0x1400000>;
 281                         no-map;
 282                 };
 283
 284                 slpi_mem: memory@88c00000 {
 285                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 286                         no-map;
 287                 };
 288
 289                 adsp_mem: memory@8a100000 {
 290                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 291                         no-map;
 292                 };
 293
 294                 spss_mem: memory@8be00000 {
 295                         reg = <0x0 0x8be00000 0x0 0x100000>;
 296                         no-map;
 297                 };
 298
 299                 cdsp_secure_heap: memory@8bf00000 {
 300                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 301                         no-map;
 302                 };
 303         };
 304
 305         smem: qcom,smem {
 306                 compatible = "qcom,smem";
 307                 memory-region = <&smem_mem>;
 308                 hwlocks = <&tcsr_mutex 3>;
 309         };
 310
 311         smp2p-adsp {
 312                 compatible = "qcom,smp2p";
 313                 qcom,smem = <443>, <429>;
 314                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 315                                              IPCC_MPROC_SIGNAL_SMP2P
 316                                              IRQ_TYPE_EDGE_RISING>;
 317                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 318                                 IPCC_MPROC_SIGNAL_SMP2P>;
 319
 320                 qcom,local-pid = <0>;
 321                 qcom,remote-pid = <2>;
 322
 323                 smp2p_adsp_out: master-kernel {
 324                         qcom,entry-name = "master-kernel";
 325                         #qcom,smem-state-cells = <1>;
 326                 };
 327
 328                 smp2p_adsp_in: slave-kernel {
 329                         qcom,entry-name = "slave-kernel";
 330                         interrupt-controller;
 331                         #interrupt-cells = <2>;
 332                 };
 333         };
 334
 335         smp2p-cdsp {
 336                 compatible = "qcom,smp2p";
 337                 qcom,smem = <94>, <432>;
 338                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 339                                              IPCC_MPROC_SIGNAL_SMP2P
 340                                              IRQ_TYPE_EDGE_RISING>;
 341                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 342                                 IPCC_MPROC_SIGNAL_SMP2P>;
 343
 344                 qcom,local-pid = <0>;
 345                 qcom,remote-pid = <5>;
 346
 347                 smp2p_cdsp_out: master-kernel {
 348                         qcom,entry-name = "master-kernel";
 349                         #qcom,smem-state-cells = <1>;
 350                 };
 351
 352                 smp2p_cdsp_in: slave-kernel {
 353                         qcom,entry-name = "slave-kernel";
 354                         interrupt-controller;
 355                         #interrupt-cells = <2>;
 356                 };
 357         };
 358
 359         smp2p-slpi {
 360                 compatible = "qcom,smp2p";
 361                 qcom,smem = <481>, <430>;
 362                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 363                                              IPCC_MPROC_SIGNAL_SMP2P
 364                                              IRQ_TYPE_EDGE_RISING>;
 365                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 366                                 IPCC_MPROC_SIGNAL_SMP2P>;
 367
 368                 qcom,local-pid = <0>;
 369                 qcom,remote-pid = <3>;
 370
 371                 smp2p_slpi_out: master-kernel {
 372                         qcom,entry-name = "master-kernel";
 373                         #qcom,smem-state-cells = <1>;
 374                 };
 375
 376                 smp2p_slpi_in: slave-kernel {
 377                         qcom,entry-name = "slave-kernel";
 378                         interrupt-controller;
 379                         #interrupt-cells = <2>;
 380                 };
 381         };
 382
 383         soc: soc@0 {
 384                 #address-cells = <2>;
 385                 #size-cells = <2>;
 386                 ranges = <0 0 0 0 0x10 0>;
 387                 dma-ranges = <0 0 0 0 0x10 0>;
 388                 compatible = "simple-bus";
 389
 390                 gcc: clock-controller@100000 {
 391                         compatible = "qcom,gcc-sm8250";
 392                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 393                         #clock-cells = <1>;
 394                         #reset-cells = <1>;
 395                         #power-domain-cells = <1>;
 396                         clock-names = "bi_tcxo", "sleep_clk";
 397                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
 398                 };
 399
 400                 ipcc: mailbox@408000 {
 401                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 402                         reg = <0 0x00408000 0 0x1000>;
 403                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <3>;
 406                         #mbox-cells = <2>;
 407                 };
 408
 409                 qupv3_id_2: geniqup@8c0000 {
 410                         compatible = "qcom,geni-se-qup";
 411                         reg = <0x0 0x008c0000 0x0 0x6000>;
 412                         clock-names = "m-ahb", "s-ahb";
 413                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 414                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 415                         #address-cells = <2>;
 416                         #size-cells = <2>;
 417                         ranges;
 418                         status = "disabled";
 419
 420                         i2c14: i2c@880000 {
 421                                 compatible = "qcom,geni-i2c";
 422                                 reg = <0 0x00880000 0 0x4000>;
 423                                 clock-names = "se";
 424                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 425                                 pinctrl-names = "default";
 426                                 pinctrl-0 = <&qup_i2c14_default>;
 427                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 428                                 #address-cells = <1>;
 429                                 #size-cells = <0>;
 430                                 status = "disabled";
 431                         };
 432
 433                         spi14: spi@880000 {
 434                                 compatible = "qcom,geni-spi";
 435                                 reg = <0 0x00880000 0 0x4000>;
 436                                 clock-names = "se";
 437                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 438                                 pinctrl-names = "default";
 439                                 pinctrl-0 = <&qup_spi14_default>;
 440                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 441                                 #address-cells = <1>;
 442                                 #size-cells = <0>;
 443                                 status = "disabled";
 444                         };
 445
 446                         i2c15: i2c@884000 {
 447                                 compatible = "qcom,geni-i2c";
 448                                 reg = <0 0x00884000 0 0x4000>;
 449                                 clock-names = "se";
 450                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 451                                 pinctrl-names = "default";
 452                                 pinctrl-0 = <&qup_i2c15_default>;
 453                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 454                                 #address-cells = <1>;
 455                                 #size-cells = <0>;
 456                                 status = "disabled";
 457                         };
 458
 459                         spi15: spi@884000 {
 460                                 compatible = "qcom,geni-spi";
 461                                 reg = <0 0x00884000 0 0x4000>;
 462                                 clock-names = "se";
 463                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 464                                 pinctrl-names = "default";
 465                                 pinctrl-0 = <&qup_spi15_default>;
 466                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 467                                 #address-cells = <1>;
 468                                 #size-cells = <0>;
 469                                 status = "disabled";
 470                         };
 471
 472                         i2c16: i2c@888000 {
 473                                 compatible = "qcom,geni-i2c";
 474                                 reg = <0 0x00888000 0 0x4000>;
 475                                 clock-names = "se";
 476                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 477                                 pinctrl-names = "default";
 478                                 pinctrl-0 = <&qup_i2c16_default>;
 479                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 480                                 #address-cells = <1>;
 481                                 #size-cells = <0>;
 482                                 status = "disabled";
 483                         };
 484
 485                         spi16: spi@888000 {
 486                                 compatible = "qcom,geni-spi";
 487                                 reg = <0 0x00888000 0 0x4000>;
 488                                 clock-names = "se";
 489                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 490                                 pinctrl-names = "default";
 491                                 pinctrl-0 = <&qup_spi16_default>;
 492                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 493                                 #address-cells = <1>;
 494                                 #size-cells = <0>;
 495                                 status = "disabled";
 496                         };
 497
 498                         i2c17: i2c@88c000 {
 499                                 compatible = "qcom,geni-i2c";
 500                                 reg = <0 0x0088c000 0 0x4000>;
 501                                 clock-names = "se";
 502                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 503                                 pinctrl-names = "default";
 504                                 pinctrl-0 = <&qup_i2c17_default>;
 505                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 506                                 #address-cells = <1>;
 507                                 #size-cells = <0>;
 508                                 status = "disabled";
 509                         };
 510
 511                         spi17: spi@88c000 {
 512                                 compatible = "qcom,geni-spi";
 513                                 reg = <0 0x0088c000 0 0x4000>;
 514                                 clock-names = "se";
 515                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 516                                 pinctrl-names = "default";
 517                                 pinctrl-0 = <&qup_spi17_default>;
 518                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 519                                 #address-cells = <1>;
 520                                 #size-cells = <0>;
 521                                 status = "disabled";
 522                         };
 523
 524                         i2c18: i2c@890000 {
 525                                 compatible = "qcom,geni-i2c";
 526                                 reg = <0 0x00890000 0 0x4000>;
 527                                 clock-names = "se";
 528                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 529                                 pinctrl-names = "default";
 530                                 pinctrl-0 = <&qup_i2c18_default>;
 531                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 532                                 #address-cells = <1>;
 533                                 #size-cells = <0>;
 534                                 status = "disabled";
 535                         };
 536
 537                         spi18: spi@890000 {
 538                                 compatible = "qcom,geni-spi";
 539                                 reg = <0 0x00890000 0 0x4000>;
 540                                 clock-names = "se";
 541                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 542                                 pinctrl-names = "default";
 543                                 pinctrl-0 = <&qup_spi18_default>;
 544                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 545                                 #address-cells = <1>;
 546                                 #size-cells = <0>;
 547                                 status = "disabled";
 548                         };
 549
 550                         i2c19: i2c@894000 {
 551                                 compatible = "qcom,geni-i2c";
 552                                 reg = <0 0x00894000 0 0x4000>;
 553                                 clock-names = "se";
 554                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 555                                 pinctrl-names = "default";
 556                                 pinctrl-0 = <&qup_i2c19_default>;
 557                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 status = "disabled";
 561                         };
 562
 563                         spi19: spi@894000 {
 564                                 compatible = "qcom,geni-spi";
 565                                 reg = <0 0x00894000 0 0x4000>;
 566                                 clock-names = "se";
 567                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 568                                 pinctrl-names = "default";
 569                                 pinctrl-0 = <&qup_spi19_default>;
 570                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 571                                 #address-cells = <1>;
 572                                 #size-cells = <0>;
 573                                 status = "disabled";
 574                         };
 575                 };
 576
 577                 qupv3_id_0: geniqup@9c0000 {
 578                         compatible = "qcom,geni-se-qup";
 579                         reg = <0x0 0x009c0000 0x0 0x6000>;
 580                         clock-names = "m-ahb", "s-ahb";
 581                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 582                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 583                         #address-cells = <2>;
 584                         #size-cells = <2>;
 585                         ranges;
 586                         status = "disabled";
 587
 588                         i2c0: i2c@980000 {
 589                                 compatible = "qcom,geni-i2c";
 590                                 reg = <0 0x00980000 0 0x4000>;
 591                                 clock-names = "se";
 592                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 593                                 pinctrl-names = "default";
 594                                 pinctrl-0 = <&qup_i2c0_default>;
 595                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 596                                 #address-cells = <1>;
 597                                 #size-cells = <0>;
 598                                 status = "disabled";
 599                         };
 600
 601                         spi0: spi@980000 {
 602                                 compatible = "qcom,geni-spi";
 603                                 reg = <0 0x00980000 0 0x4000>;
 604                                 clock-names = "se";
 605                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 606                                 pinctrl-names = "default";
 607                                 pinctrl-0 = <&qup_spi0_default>;
 608                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 609                                 #address-cells = <1>;
 610                                 #size-cells = <0>;
 611                                 status = "disabled";
 612                         };
 613
 614                         i2c1: i2c@984000 {
 615                                 compatible = "qcom,geni-i2c";
 616                                 reg = <0 0x00984000 0 0x4000>;
 617                                 clock-names = "se";
 618                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 619                                 pinctrl-names = "default";
 620                                 pinctrl-0 = <&qup_i2c1_default>;
 621                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 622                                 #address-cells = <1>;
 623                                 #size-cells = <0>;
 624                                 status = "disabled";
 625                         };
 626
 627                         spi1: spi@984000 {
 628                                 compatible = "qcom,geni-spi";
 629                                 reg = <0 0x00984000 0 0x4000>;
 630                                 clock-names = "se";
 631                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 632                                 pinctrl-names = "default";
 633                                 pinctrl-0 = <&qup_spi1_default>;
 634                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 635                                 #address-cells = <1>;
 636                                 #size-cells = <0>;
 637                                 status = "disabled";
 638                         };
 639
 640                         i2c2: i2c@988000 {
 641                                 compatible = "qcom,geni-i2c";
 642                                 reg = <0 0x00988000 0 0x4000>;
 643                                 clock-names = "se";
 644                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 645                                 pinctrl-names = "default";
 646                                 pinctrl-0 = <&qup_i2c2_default>;
 647                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 648                                 #address-cells = <1>;
 649                                 #size-cells = <0>;
 650                                 status = "disabled";
 651                         };
 652
 653                         spi2: spi@988000 {
 654                                 compatible = "qcom,geni-spi";
 655                                 reg = <0 0x00988000 0 0x4000>;
 656                                 clock-names = "se";
 657                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 658                                 pinctrl-names = "default";
 659                                 pinctrl-0 = <&qup_spi2_default>;
 660                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 661                                 #address-cells = <1>;
 662                                 #size-cells = <0>;
 663                                 status = "disabled";
 664                         };
 665
 666                         i2c3: i2c@98c000 {
 667                                 compatible = "qcom,geni-i2c";
 668                                 reg = <0 0x0098c000 0 0x4000>;
 669                                 clock-names = "se";
 670                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 671                                 pinctrl-names = "default";
 672                                 pinctrl-0 = <&qup_i2c3_default>;
 673                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 674                                 #address-cells = <1>;
 675                                 #size-cells = <0>;
 676                                 status = "disabled";
 677                         };
 678
 679                         spi3: spi@98c000 {
 680                                 compatible = "qcom,geni-spi";
 681                                 reg = <0 0x0098c000 0 0x4000>;
 682                                 clock-names = "se";
 683                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 684                                 pinctrl-names = "default";
 685                                 pinctrl-0 = <&qup_spi3_default>;
 686                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 687                                 #address-cells = <1>;
 688                                 #size-cells = <0>;
 689                                 status = "disabled";
 690                         };
 691
 692                         i2c4: i2c@990000 {
 693                                 compatible = "qcom,geni-i2c";
 694                                 reg = <0 0x00990000 0 0x4000>;
 695                                 clock-names = "se";
 696                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 697                                 pinctrl-names = "default";
 698                                 pinctrl-0 = <&qup_i2c4_default>;
 699                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 700                                 #address-cells = <1>;
 701                                 #size-cells = <0>;
 702                                 status = "disabled";
 703                         };
 704
 705                         spi4: spi@990000 {
 706                                 compatible = "qcom,geni-spi";
 707                                 reg = <0 0x00990000 0 0x4000>;
 708                                 clock-names = "se";
 709                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 710                                 pinctrl-names = "default";
 711                                 pinctrl-0 = <&qup_spi4_default>;
 712                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 713                                 #address-cells = <1>;
 714                                 #size-cells = <0>;
 715                                 status = "disabled";
 716                         };
 717
 718                         i2c5: i2c@994000 {
 719                                 compatible = "qcom,geni-i2c";
 720                                 reg = <0 0x00994000 0 0x4000>;
 721                                 clock-names = "se";
 722                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 723                                 pinctrl-names = "default";
 724                                 pinctrl-0 = <&qup_i2c5_default>;
 725                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 726                                 #address-cells = <1>;
 727                                 #size-cells = <0>;
 728                                 status = "disabled";
 729                         };
 730
 731                         spi5: spi@994000 {
 732                                 compatible = "qcom,geni-spi";
 733                                 reg = <0 0x00994000 0 0x4000>;
 734                                 clock-names = "se";
 735                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 736                                 pinctrl-names = "default";
 737                                 pinctrl-0 = <&qup_spi5_default>;
 738                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 739                                 #address-cells = <1>;
 740                                 #size-cells = <0>;
 741                                 status = "disabled";
 742                         };
 743
 744                         i2c6: i2c@998000 {
 745                                 compatible = "qcom,geni-i2c";
 746                                 reg = <0 0x00998000 0 0x4000>;
 747                                 clock-names = "se";
 748                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 749                                 pinctrl-names = "default";
 750                                 pinctrl-0 = <&qup_i2c6_default>;
 751                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 752                                 #address-cells = <1>;
 753                                 #size-cells = <0>;
 754                                 status = "disabled";
 755                         };
 756
 757                         spi6: spi@998000 {
 758                                 compatible = "qcom,geni-spi";
 759                                 reg = <0 0x00998000 0 0x4000>;
 760                                 clock-names = "se";
 761                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 762                                 pinctrl-names = "default";
 763                                 pinctrl-0 = <&qup_spi6_default>;
 764                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 765                                 #address-cells = <1>;
 766                                 #size-cells = <0>;
 767                                 status = "disabled";
 768                         };
 769
 770                         i2c7: i2c@99c000 {
 771                                 compatible = "qcom,geni-i2c";
 772                                 reg = <0 0x0099c000 0 0x4000>;
 773                                 clock-names = "se";
 774                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 775                                 pinctrl-names = "default";
 776                                 pinctrl-0 = <&qup_i2c7_default>;
 777                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 778                                 #address-cells = <1>;
 779                                 #size-cells = <0>;
 780                                 status = "disabled";
 781                         };
 782
 783                         spi7: spi@99c000 {
 784                                 compatible = "qcom,geni-spi";
 785                                 reg = <0 0x0099c000 0 0x4000>;
 786                                 clock-names = "se";
 787                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 788                                 pinctrl-names = "default";
 789                                 pinctrl-0 = <&qup_spi7_default>;
 790                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                                 status = "disabled";
 794                         };
 795                 };
 796
 797                 qupv3_id_1: geniqup@ac0000 {
 798                         compatible = "qcom,geni-se-qup";
 799                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 800                         clock-names = "m-ahb", "s-ahb";
 801                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 802                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 803                         #address-cells = <2>;
 804                         #size-cells = <2>;
 805                         ranges;
 806                         status = "disabled";
 807
 808                         i2c8: i2c@a80000 {
 809                                 compatible = "qcom,geni-i2c";
 810                                 reg = <0 0x00a80000 0 0x4000>;
 811                                 clock-names = "se";
 812                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 813                                 pinctrl-names = "default";
 814                                 pinctrl-0 = <&qup_i2c8_default>;
 815                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 816                                 #address-cells = <1>;
 817                                 #size-cells = <0>;
 818                                 status = "disabled";
 819                         };
 820
 821                         spi8: spi@a80000 {
 822                                 compatible = "qcom,geni-spi";
 823                                 reg = <0 0x00a80000 0 0x4000>;
 824                                 clock-names = "se";
 825                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 826                                 pinctrl-names = "default";
 827                                 pinctrl-0 = <&qup_spi8_default>;
 828                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 829                                 #address-cells = <1>;
 830                                 #size-cells = <0>;
 831                                 status = "disabled";
 832                         };
 833
 834                         i2c9: i2c@a84000 {
 835                                 compatible = "qcom,geni-i2c";
 836                                 reg = <0 0x00a84000 0 0x4000>;
 837                                 clock-names = "se";
 838                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 839                                 pinctrl-names = "default";
 840                                 pinctrl-0 = <&qup_i2c9_default>;
 841                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 842                                 #address-cells = <1>;
 843                                 #size-cells = <0>;
 844                                 status = "disabled";
 845                         };
 846
 847                         spi9: spi@a84000 {
 848                                 compatible = "qcom,geni-spi";
 849                                 reg = <0 0x00a84000 0 0x4000>;
 850                                 clock-names = "se";
 851                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 852                                 pinctrl-names = "default";
 853                                 pinctrl-0 = <&qup_spi9_default>;
 854                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 855                                 #address-cells = <1>;
 856                                 #size-cells = <0>;
 857                                 status = "disabled";
 858                         };
 859
 860                         i2c10: i2c@a88000 {
 861                                 compatible = "qcom,geni-i2c";
 862                                 reg = <0 0x00a88000 0 0x4000>;
 863                                 clock-names = "se";
 864                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 865                                 pinctrl-names = "default";
 866                                 pinctrl-0 = <&qup_i2c10_default>;
 867                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 868                                 #address-cells = <1>;
 869                                 #size-cells = <0>;
 870                                 status = "disabled";
 871                         };
 872
 873                         spi10: spi@a88000 {
 874                                 compatible = "qcom,geni-spi";
 875                                 reg = <0 0x00a88000 0 0x4000>;
 876                                 clock-names = "se";
 877                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 878                                 pinctrl-names = "default";
 879                                 pinctrl-0 = <&qup_spi10_default>;
 880                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 881                                 #address-cells = <1>;
 882                                 #size-cells = <0>;
 883                                 status = "disabled";
 884                         };
 885
 886                         i2c11: i2c@a8c000 {
 887                                 compatible = "qcom,geni-i2c";
 888                                 reg = <0 0x00a8c000 0 0x4000>;
 889                                 clock-names = "se";
 890                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 891                                 pinctrl-names = "default";
 892                                 pinctrl-0 = <&qup_i2c11_default>;
 893                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 894                                 #address-cells = <1>;
 895                                 #size-cells = <0>;
 896                                 status = "disabled";
 897                         };
 898
 899                         spi11: spi@a8c000 {
 900                                 compatible = "qcom,geni-spi";
 901                                 reg = <0 0x00a8c000 0 0x4000>;
 902                                 clock-names = "se";
 903                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 904                                 pinctrl-names = "default";
 905                                 pinctrl-0 = <&qup_spi11_default>;
 906                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909                                 status = "disabled";
 910                         };
 911
 912                         i2c12: i2c@a90000 {
 913                                 compatible = "qcom,geni-i2c";
 914                                 reg = <0 0x00a90000 0 0x4000>;
 915                                 clock-names = "se";
 916                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 917                                 pinctrl-names = "default";
 918                                 pinctrl-0 = <&qup_i2c12_default>;
 919                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 status = "disabled";
 923                         };
 924
 925                         spi12: spi@a90000 {
 926                                 compatible = "qcom,geni-spi";
 927                                 reg = <0 0x00a90000 0 0x4000>;
 928                                 clock-names = "se";
 929                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 930                                 pinctrl-names = "default";
 931                                 pinctrl-0 = <&qup_spi12_default>;
 932                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 933                                 #address-cells = <1>;
 934                                 #size-cells = <0>;
 935                                 status = "disabled";
 936                         };
 937
 938                         uart2: serial@a90000 {
 939                                 compatible = "qcom,geni-debug-uart";
 940                                 reg = <0x0 0x00a90000 0x0 0x4000>;
 941                                 clock-names = "se";
 942                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 943                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 944                                 status = "disabled";
 945                         };
 946
 947                         i2c13: i2c@a94000 {
 948                                 compatible = "qcom,geni-i2c";
 949                                 reg = <0 0x00a94000 0 0x4000>;
 950                                 clock-names = "se";
 951                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 952                                 pinctrl-names = "default";
 953                                 pinctrl-0 = <&qup_i2c13_default>;
 954                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 955                                 #address-cells = <1>;
 956                                 #size-cells = <0>;
 957                                 status = "disabled";
 958                         };
 959
 960                         spi13: spi@a94000 {
 961                                 compatible = "qcom,geni-spi";
 962                                 reg = <0 0x00a94000 0 0x4000>;
 963                                 clock-names = "se";
 964                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 965                                 pinctrl-names = "default";
 966                                 pinctrl-0 = <&qup_spi13_default>;
 967                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 968                                 #address-cells = <1>;
 969                                 #size-cells = <0>;
 970                                 status = "disabled";
 971                         };
 972                 };
 973
 974                 ufs_mem_hc: ufshc@1d84000 {
 975                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
 976                                      "jedec,ufs-2.0";
 977                         reg = <0 0x01d84000 0 0x3000>;
 978                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 979                         phys = <&ufs_mem_phy_lanes>;
 980                         phy-names = "ufsphy";
 981                         lanes-per-direction = <2>;
 982                         #reset-cells = <1>;
 983                         resets = <&gcc GCC_UFS_PHY_BCR>;
 984                         reset-names = "rst";
 985
 986                         power-domains = <&gcc UFS_PHY_GDSC>;
 987
 988                         clock-names =
 989                                 "core_clk",
 990                                 "bus_aggr_clk",
 991                                 "iface_clk",
 992                                 "core_clk_unipro",
 993                                 "ref_clk",
 994                                 "tx_lane0_sync_clk",
 995                                 "rx_lane0_sync_clk",
 996                                 "rx_lane1_sync_clk";
 997                         clocks =
 998                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
 999                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1000                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1001                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1002                                 <&rpmhcc RPMH_CXO_CLK>,
1003                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1004                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1005                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1006                         freq-table-hz =
1007                                 <37500000 300000000>,
1008                                 <0 0>,
1009                                 <0 0>,
1010                                 <37500000 300000000>,
1011                                 <0 0>,
1012                                 <0 0>,
1013                                 <0 0>,
1014                                 <0 0>;
1015
1016                         status = "disabled";
1017                 };
1018
1019                 ufs_mem_phy: phy@1d87000 {
1020                         compatible = "qcom,sm8250-qmp-ufs-phy";
1021                         reg = <0 0x01d87000 0 0x1c0>;
1022                         #address-cells = <2>;
1023                         #size-cells = <2>;
1024                         ranges;
1025                         clock-names = "ref",
1026                                       "ref_aux";
1027                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1028                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1029
1030                         resets = <&ufs_mem_hc 0>;
1031                         reset-names = "ufsphy";
1032                         status = "disabled";
1033
1034                         ufs_mem_phy_lanes: lanes@1d87400 {
1035                                 reg = <0 0x01d87400 0 0x108>,
1036                                       <0 0x01d87600 0 0x1e0>,
1037                                       <0 0x01d87c00 0 0x1dc>,
1038                                       <0 0x01d87800 0 0x108>,
1039                                       <0 0x01d87a00 0 0x1e0>;
1040                                 #phy-cells = <0>;
1041                         };
1042                 };
1043
1044                 tcsr_mutex: hwlock@1f40000 {
1045                         compatible = "qcom,tcsr-mutex";
1046                         reg = <0x0 0x01f40000 0x0 0x40000>;
1047                         #hwlock-cells = <1>;
1048                 };
1049
1050                 gpu: gpu@3d00000 {
1051                         /*
1052                          * note: the amd,imageon compatible makes it possible
1053                          * to use the drm/msm driver without the display node,
1054                          * make sure to remove it when display node is added
1055                          */
1056                         compatible = "qcom,adreno-650.2",
1057                                      "qcom,adreno",
1058                                      "amd,imageon";
1059                         #stream-id-cells = <16>;
1060
1061                         reg = <0 0x03d00000 0 0x40000>;
1062                         reg-names = "kgsl_3d0_reg_memory";
1063
1064                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1065
1066                         iommus = <&adreno_smmu 0 0x401>;
1067
1068                         operating-points-v2 = <&gpu_opp_table>;
1069
1070                         qcom,gmu = <&gmu>;
1071
1072                         zap-shader {
1073                                 memory-region = <&gpu_mem>;
1074                         };
1075
1076                         /* note: downstream checks gpu binning for 670 Mhz */
1077                         gpu_opp_table: opp-table {
1078                                 compatible = "operating-points-v2";
1079
1080                                 opp-670000000 {
1081                                         opp-hz = /bits/ 64 <670000000>;
1082                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1083                                 };
1084
1085                                 opp-587000000 {
1086                                         opp-hz = /bits/ 64 <587000000>;
1087                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1088                                 };
1089
1090                                 opp-525000000 {
1091                                         opp-hz = /bits/ 64 <525000000>;
1092                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1093                                 };
1094
1095                                 opp-490000000 {
1096                                         opp-hz = /bits/ 64 <490000000>;
1097                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1098                                 };
1099
1100                                 opp-441600000 {
1101                                         opp-hz = /bits/ 64 <441600000>;
1102                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1103                                 };
1104
1105                                 opp-400000000 {
1106                                         opp-hz = /bits/ 64 <400000000>;
1107                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1108                                 };
1109
1110                                 opp-305000000 {
1111                                         opp-hz = /bits/ 64 <305000000>;
1112                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1113                                 };
1114                         };
1115                 };
1116
1117                 gmu: gmu@3d6a000 {
1118                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1119
1120                         reg = <0 0x03d6a000 0 0x30000>,
1121                               <0 0x3de0000 0 0x10000>,
1122                               <0 0xb290000 0 0x10000>,
1123                               <0 0xb490000 0 0x10000>;
1124                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1125
1126                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1127                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1128                         interrupt-names = "hfi", "gmu";
1129
1130                         clocks = <&gpucc 0>,
1131                                  <&gpucc 3>,
1132                                  <&gpucc 6>,
1133                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1134                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1135                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1136
1137                         power-domains = <&gpucc 0>,
1138                                         <&gpucc 1>;
1139                         power-domain-names = "cx", "gx";
1140
1141                         iommus = <&adreno_smmu 5 0x400>;
1142
1143                         operating-points-v2 = <&gmu_opp_table>;
1144
1145                         gmu_opp_table: opp-table {
1146                                 compatible = "operating-points-v2";
1147
1148                                 opp-200000000 {
1149                                         opp-hz = /bits/ 64 <200000000>;
1150                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1151                                 };
1152                         };
1153                 };
1154
1155                 gpucc: clock-controller@3d90000 {
1156                         compatible = "qcom,sm8250-gpucc";
1157                         reg = <0 0x03d90000 0 0x9000>;
1158                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1159                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1160                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1161                         clock-names = "bi_tcxo",
1162                                       "gcc_gpu_gpll0_clk_src",
1163                                       "gcc_gpu_gpll0_div_clk_src";
1164                         #clock-cells = <1>;
1165                         #reset-cells = <1>;
1166                         #power-domain-cells = <1>;
1167                 };
1168
1169                 adreno_smmu: iommu@3da0000 {
1170                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1171                         reg = <0 0x03da0000 0 0x10000>;
1172                         #iommu-cells = <2>;
1173                         #global-interrupts = <2>;
1174                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1175                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1176                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1177                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1178                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1179                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1180                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1181                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1182                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1183                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1184                         clocks = <&gpucc 0>,
1185                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1186                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1187                         clock-names = "ahb", "bus", "iface";
1188
1189                         power-domains = <&gpucc 0>;
1190                 };
1191
1192                 slpi: remoteproc@5c00000 {
1193                         compatible = "qcom,sm8250-slpi-pas";
1194                         reg = <0 0x05c00000 0 0x4000>;
1195
1196                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1197                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1198                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1199                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1200                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1201                         interrupt-names = "wdog", "fatal", "ready",
1202                                           "handover", "stop-ack";
1203
1204                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1205                         clock-names = "xo";
1206
1207                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1208                                         <&rpmhpd SM8250_LCX>,
1209                                         <&rpmhpd SM8250_LMX>;
1210                         power-domain-names = "load_state", "lcx", "lmx";
1211
1212                         memory-region = <&slpi_mem>;
1213
1214                         qcom,smem-states = <&smp2p_slpi_out 0>;
1215                         qcom,smem-state-names = "stop";
1216
1217                         status = "disabled";
1218
1219                         glink-edge {
1220                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1221                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1222                                                              IRQ_TYPE_EDGE_RISING>;
1223                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1224                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1225
1226                                 label = "lpass";
1227                                 qcom,remote-pid = <3>;
1228                         };
1229                 };
1230
1231                 cdsp: remoteproc@8300000 {
1232                         compatible = "qcom,sm8250-cdsp-pas";
1233                         reg = <0 0x08300000 0 0x10000>;
1234
1235                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1236                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1237                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1238                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1239                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1240                         interrupt-names = "wdog", "fatal", "ready",
1241                                           "handover", "stop-ack";
1242
1243                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1244                         clock-names = "xo";
1245
1246                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1247                                         <&rpmhpd SM8250_CX>;
1248                         power-domain-names = "load_state", "cx";
1249
1250                         memory-region = <&cdsp_mem>;
1251
1252                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1253                         qcom,smem-state-names = "stop";
1254
1255                         status = "disabled";
1256
1257                         glink-edge {
1258                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1259                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1260                                                              IRQ_TYPE_EDGE_RISING>;
1261                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1262                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1263
1264                                 label = "lpass";
1265                                 qcom,remote-pid = <5>;
1266                         };
1267                 };
1268
1269                 pdc: interrupt-controller@b220000 {
1270                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
1271                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1272                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1273                                           <125 63 1>, <126 716 12>;
1274                         #interrupt-cells = <2>;
1275                         interrupt-parent = <&intc>;
1276                         interrupt-controller;
1277                 };
1278
1279                 aoss_qmp: qmp@c300000 {
1280                         compatible = "qcom,sm8250-aoss-qmp";
1281                         reg = <0 0x0c300000 0 0x100000>;
1282                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1283                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
1284                                                      IRQ_TYPE_EDGE_RISING>;
1285                         mboxes = <&ipcc IPCC_CLIENT_AOP
1286                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
1287
1288                         #clock-cells = <0>;
1289                         #power-domain-cells = <1>;
1290                 };
1291
1292                 spmi_bus: spmi@c440000 {
1293                         compatible = "qcom,spmi-pmic-arb";
1294                         reg = <0x0 0x0c440000 0x0 0x0001100>,
1295                               <0x0 0x0c600000 0x0 0x2000000>,
1296                               <0x0 0x0e600000 0x0 0x0100000>,
1297                               <0x0 0x0e700000 0x0 0x00a0000>,
1298                               <0x0 0x0c40a000 0x0 0x0026000>;
1299                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1300                         interrupt-names = "periph_irq";
1301                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1302                         qcom,ee = <0>;
1303                         qcom,channel = <0>;
1304                         #address-cells = <2>;
1305                         #size-cells = <0>;
1306                         interrupt-controller;
1307                         #interrupt-cells = <4>;
1308                 };
1309
1310                 tlmm: pinctrl@f100000 {
1311                         compatible = "qcom,sm8250-pinctrl";
1312                         reg = <0 0x0f100000 0 0x300000>,
1313                               <0 0x0f500000 0 0x300000>,
1314                               <0 0x0f900000 0 0x300000>;
1315                         reg-names = "west", "south", "north";
1316                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1317                         gpio-controller;
1318                         #gpio-cells = <2>;
1319                         interrupt-controller;
1320                         #interrupt-cells = <2>;
1321                         gpio-ranges = <&tlmm 0 0 180>;
1322                         wakeup-parent = <&pdc>;
1323
1324                         qup_i2c0_default: qup-i2c0-default {
1325                                 mux {
1326                                         pins = "gpio28", "gpio29";
1327                                         function = "qup0";
1328                                 };
1329
1330                                 config {
1331                                         pins = "gpio28", "gpio29";
1332                                         drive-strength = <2>;
1333                                         bias-disable;
1334                                 };
1335                         };
1336
1337                         qup_i2c1_default: qup-i2c1-default {
1338                                 pinmux {
1339                                         pins = "gpio4", "gpio5";
1340                                         function = "qup1";
1341                                 };
1342
1343                                 config {
1344                                         pins = "gpio4", "gpio5";
1345                                         drive-strength = <2>;
1346                                         bias-disable;
1347                                 };
1348                         };
1349
1350                         qup_i2c2_default: qup-i2c2-default {
1351                                 mux {
1352                                         pins = "gpio115", "gpio116";
1353                                         function = "qup2";
1354                                 };
1355
1356                                 config {
1357                                         pins = "gpio115", "gpio116";
1358                                         drive-strength = <2>;
1359                                         bias-disable;
1360                                 };
1361                         };
1362
1363                         qup_i2c3_default: qup-i2c3-default {
1364                                 mux {
1365                                         pins = "gpio119", "gpio120";
1366                                         function = "qup3";
1367                                 };
1368
1369                                 config {
1370                                         pins = "gpio119", "gpio120";
1371                                         drive-strength = <2>;
1372                                         bias-disable;
1373                                 };
1374                         };
1375
1376                         qup_i2c4_default: qup-i2c4-default {
1377                                 mux {
1378                                         pins = "gpio8", "gpio9";
1379                                         function = "qup4";
1380                                 };
1381
1382                                 config {
1383                                         pins = "gpio8", "gpio9";
1384                                         drive-strength = <2>;
1385                                         bias-disable;
1386                                 };
1387                         };
1388
1389                         qup_i2c5_default: qup-i2c5-default {
1390                                 mux {
1391                                         pins = "gpio12", "gpio13";
1392                                         function = "qup5";
1393                                 };
1394
1395                                 config {
1396                                         pins = "gpio12", "gpio13";
1397                                         drive-strength = <2>;
1398                                         bias-disable;
1399                                 };
1400                         };
1401
1402                         qup_i2c6_default: qup-i2c6-default {
1403                                 mux {
1404                                         pins = "gpio16", "gpio17";
1405                                         function = "qup6";
1406                                 };
1407
1408                                 config {
1409                                         pins = "gpio16", "gpio17";
1410                                         drive-strength = <2>;
1411                                         bias-disable;
1412                                 };
1413                         };
1414
1415                         qup_i2c7_default: qup-i2c7-default {
1416                                 mux {
1417                                         pins = "gpio20", "gpio21";
1418                                         function = "qup7";
1419                                 };
1420
1421                                 config {
1422                                         pins = "gpio20", "gpio21";
1423                                         drive-strength = <2>;
1424                                         bias-disable;
1425                                 };
1426                         };
1427
1428                         qup_i2c8_default: qup-i2c8-default {
1429                                 mux {
1430                                         pins = "gpio24", "gpio25";
1431                                         function = "qup8";
1432                                 };
1433
1434                                 config {
1435                                         pins = "gpio24", "gpio25";
1436                                         drive-strength = <2>;
1437                                         bias-disable;
1438                                 };
1439                         };
1440
1441                         qup_i2c9_default: qup-i2c9-default {
1442                                 mux {
1443                                         pins = "gpio125", "gpio126";
1444                                         function = "qup9";
1445                                 };
1446
1447                                 config {
1448                                         pins = "gpio125", "gpio126";
1449                                         drive-strength = <2>;
1450                                         bias-disable;
1451                                 };
1452                         };
1453
1454                         qup_i2c10_default: qup-i2c10-default {
1455                                 mux {
1456                                         pins = "gpio129", "gpio130";
1457                                         function = "qup10";
1458                                 };
1459
1460                                 config {
1461                                         pins = "gpio129", "gpio130";
1462                                         drive-strength = <2>;
1463                                         bias-disable;
1464                                 };
1465                         };
1466
1467                         qup_i2c11_default: qup-i2c11-default {
1468                                 mux {
1469                                         pins = "gpio60", "gpio61";
1470                                         function = "qup11";
1471                                 };
1472
1473                                 config {
1474                                         pins = "gpio60", "gpio61";
1475                                         drive-strength = <2>;
1476                                         bias-disable;
1477                                 };
1478                         };
1479
1480                         qup_i2c12_default: qup-i2c12-default {
1481                                 mux {
1482                                         pins = "gpio32", "gpio33";
1483                                         function = "qup12";
1484                                 };
1485
1486                                 config {
1487                                         pins = "gpio32", "gpio33";
1488                                         drive-strength = <2>;
1489                                         bias-disable;
1490                                 };
1491                         };
1492
1493                         qup_i2c13_default: qup-i2c13-default {
1494                                 mux {
1495                                         pins = "gpio36", "gpio37";
1496                                         function = "qup13";
1497                                 };
1498
1499                                 config {
1500                                         pins = "gpio36", "gpio37";
1501                                         drive-strength = <2>;
1502                                         bias-disable;
1503                                 };
1504                         };
1505
1506                         qup_i2c14_default: qup-i2c14-default {
1507                                 mux {
1508                                         pins = "gpio40", "gpio41";
1509                                         function = "qup14";
1510                                 };
1511
1512                                 config {
1513                                         pins = "gpio40", "gpio41";
1514                                         drive-strength = <2>;
1515                                         bias-disable;
1516                                 };
1517                         };
1518
1519                         qup_i2c15_default: qup-i2c15-default {
1520                                 mux {
1521                                         pins = "gpio44", "gpio45";
1522                                         function = "qup15";
1523                                 };
1524
1525                                 config {
1526                                         pins = "gpio44", "gpio45";
1527                                         drive-strength = <2>;
1528                                         bias-disable;
1529                                 };
1530                         };
1531
1532                         qup_i2c16_default: qup-i2c16-default {
1533                                 mux {
1534                                         pins = "gpio48", "gpio49";
1535                                         function = "qup16";
1536                                 };
1537
1538                                 config {
1539                                         pins = "gpio48", "gpio49";
1540                                         drive-strength = <2>;
1541                                         bias-disable;
1542                                 };
1543                         };
1544
1545                         qup_i2c17_default: qup-i2c17-default {
1546                                 mux {
1547                                         pins = "gpio52", "gpio53";
1548                                         function = "qup17";
1549                                 };
1550
1551                                 config {
1552                                         pins = "gpio52", "gpio53";
1553                                         drive-strength = <2>;
1554                                         bias-disable;
1555                                 };
1556                         };
1557
1558                         qup_i2c18_default: qup-i2c18-default {
1559                                 mux {
1560                                         pins = "gpio56", "gpio57";
1561                                         function = "qup18";
1562                                 };
1563
1564                                 config {
1565                                         pins = "gpio56", "gpio57";
1566                                         drive-strength = <2>;
1567                                         bias-disable;
1568                                 };
1569                         };
1570
1571                         qup_i2c19_default: qup-i2c19-default {
1572                                 mux {
1573                                         pins = "gpio0", "gpio1";
1574                                         function = "qup19";
1575                                 };
1576
1577                                 config {
1578                                         pins = "gpio0", "gpio1";
1579                                         drive-strength = <2>;
1580                                         bias-disable;
1581                                 };
1582                         };
1583
1584                         qup_spi0_default: qup-spi0-default {
1585                                 mux {
1586                                         pins = "gpio28", "gpio29",
1587                                                "gpio30", "gpio31";
1588                                         function = "qup0";
1589                                 };
1590
1591                                 config {
1592                                         pins = "gpio28", "gpio29",
1593                                                "gpio30", "gpio31";
1594                                         drive-strength = <6>;
1595                                         bias-disable;
1596                                 };
1597                         };
1598
1599                         qup_spi1_default: qup-spi1-default {
1600                                 mux {
1601                                         pins = "gpio4", "gpio5",
1602                                                "gpio6", "gpio7";
1603                                         function = "qup1";
1604                                 };
1605
1606                                 config {
1607                                         pins = "gpio4", "gpio5",
1608                                                "gpio6", "gpio7";
1609                                         drive-strength = <6>;
1610                                         bias-disable;
1611                                 };
1612                         };
1613
1614                         qup_spi2_default: qup-spi2-default {
1615                                 mux {
1616                                         pins = "gpio115", "gpio116",
1617                                                "gpio117", "gpio118";
1618                                         function = "qup2";
1619                                 };
1620
1621                                 config {
1622                                         pins = "gpio115", "gpio116",
1623                                                "gpio117", "gpio118";
1624                                         drive-strength = <6>;
1625                                         bias-disable;
1626                                 };
1627                         };
1628
1629                         qup_spi3_default: qup-spi3-default {
1630                                 mux {
1631                                         pins = "gpio119", "gpio120",
1632                                                "gpio121", "gpio122";
1633                                         function = "qup3";
1634                                 };
1635
1636                                 config {
1637                                         pins = "gpio119", "gpio120",
1638                                                "gpio121", "gpio122";
1639                                         drive-strength = <6>;
1640                                         bias-disable;
1641                                 };
1642                         };
1643
1644                         qup_spi4_default: qup-spi4-default {
1645                                 mux {
1646                                         pins = "gpio8", "gpio9",
1647                                                "gpio10", "gpio11";
1648                                         function = "qup4";
1649                                 };
1650
1651                                 config {
1652                                         pins = "gpio8", "gpio9",
1653                                                "gpio10", "gpio11";
1654                                         drive-strength = <6>;
1655                                         bias-disable;
1656                                 };
1657                         };
1658
1659                         qup_spi5_default: qup-spi5-default {
1660                                 mux {
1661                                         pins = "gpio12", "gpio13",
1662                                                "gpio14", "gpio15";
1663                                         function = "qup5";
1664                                 };
1665
1666                                 config {
1667                                         pins = "gpio12", "gpio13",
1668                                                "gpio14", "gpio15";
1669                                         drive-strength = <6>;
1670                                         bias-disable;
1671                                 };
1672                         };
1673
1674                         qup_spi6_default: qup-spi6-default {
1675                                 mux {
1676                                         pins = "gpio16", "gpio17",
1677                                                "gpio18", "gpio19";
1678                                         function = "qup6";
1679                                 };
1680
1681                                 config {
1682                                         pins = "gpio16", "gpio17",
1683                                                "gpio18", "gpio19";
1684                                         drive-strength = <6>;
1685                                         bias-disable;
1686                                 };
1687                         };
1688
1689                         qup_spi7_default: qup-spi7-default {
1690                                 mux {
1691                                         pins = "gpio20", "gpio21",
1692                                                "gpio22", "gpio23";
1693                                         function = "qup7";
1694                                 };
1695
1696                                 config {
1697                                         pins = "gpio20", "gpio21",
1698                                                "gpio22", "gpio23";
1699                                         drive-strength = <6>;
1700                                         bias-disable;
1701                                 };
1702                         };
1703
1704                         qup_spi8_default: qup-spi8-default {
1705                                 mux {
1706                                         pins = "gpio24", "gpio25",
1707                                                "gpio26", "gpio27";
1708                                         function = "qup8";
1709                                 };
1710
1711                                 config {
1712                                         pins = "gpio24", "gpio25",
1713                                                "gpio26", "gpio27";
1714                                         drive-strength = <6>;
1715                                         bias-disable;
1716                                 };
1717                         };
1718
1719                         qup_spi9_default: qup-spi9-default {
1720                                 mux {
1721                                         pins = "gpio125", "gpio126",
1722                                                "gpio127", "gpio128";
1723                                         function = "qup9";
1724                                 };
1725
1726                                 config {
1727                                         pins = "gpio125", "gpio126",
1728                                                "gpio127", "gpio128";
1729                                         drive-strength = <6>;
1730                                         bias-disable;
1731                                 };
1732                         };
1733
1734                         qup_spi10_default: qup-spi10-default {
1735                                 mux {
1736                                         pins = "gpio129", "gpio130",
1737                                                "gpio131", "gpio132";
1738                                         function = "qup10";
1739                                 };
1740
1741                                 config {
1742                                         pins = "gpio129", "gpio130",
1743                                                "gpio131", "gpio132";
1744                                         drive-strength = <6>;
1745                                         bias-disable;
1746                                 };
1747                         };
1748
1749                         qup_spi11_default: qup-spi11-default {
1750                                 mux {
1751                                         pins = "gpio60", "gpio61",
1752                                                "gpio62", "gpio63";
1753                                         function = "qup11";
1754                                 };
1755
1756                                 config {
1757                                         pins = "gpio60", "gpio61",
1758                                                "gpio62", "gpio63";
1759                                         drive-strength = <6>;
1760                                         bias-disable;
1761                                 };
1762                         };
1763
1764                         qup_spi12_default: qup-spi12-default {
1765                                 mux {
1766                                         pins = "gpio32", "gpio33",
1767                                                "gpio34", "gpio35";
1768                                         function = "qup12";
1769                                 };
1770
1771                                 config {
1772                                         pins = "gpio32", "gpio33",
1773                                                "gpio34", "gpio35";
1774                                         drive-strength = <6>;
1775                                         bias-disable;
1776                                 };
1777                         };
1778
1779                         qup_spi13_default: qup-spi13-default {
1780                                 mux {
1781                                         pins = "gpio36", "gpio37",
1782                                                "gpio38", "gpio39";
1783                                         function = "qup13";
1784                                 };
1785
1786                                 config {
1787                                         pins = "gpio36", "gpio37",
1788                                                "gpio38", "gpio39";
1789                                         drive-strength = <6>;
1790                                         bias-disable;
1791                                 };
1792                         };
1793
1794                         qup_spi14_default: qup-spi14-default {
1795                                 mux {
1796                                         pins = "gpio40", "gpio41",
1797                                                "gpio42", "gpio43";
1798                                         function = "qup14";
1799                                 };
1800
1801                                 config {
1802                                         pins = "gpio40", "gpio41",
1803                                                "gpio42", "gpio43";
1804                                         drive-strength = <6>;
1805                                         bias-disable;
1806                                 };
1807                         };
1808
1809                         qup_spi15_default: qup-spi15-default {
1810                                 mux {
1811                                         pins = "gpio44", "gpio45",
1812                                                "gpio46", "gpio47";
1813                                         function = "qup15";
1814                                 };
1815
1816                                 config {
1817                                         pins = "gpio44", "gpio45",
1818                                                "gpio46", "gpio47";
1819                                         drive-strength = <6>;
1820                                         bias-disable;
1821                                 };
1822                         };
1823
1824                         qup_spi16_default: qup-spi16-default {
1825                                 mux {
1826                                         pins = "gpio48", "gpio49",
1827                                                "gpio50", "gpio51";
1828                                         function = "qup16";
1829                                 };
1830
1831                                 config {
1832                                         pins = "gpio48", "gpio49",
1833                                                "gpio50", "gpio51";
1834                                         drive-strength = <6>;
1835                                         bias-disable;
1836                                 };
1837                         };
1838
1839                         qup_spi17_default: qup-spi17-default {
1840                                 mux {
1841                                         pins = "gpio52", "gpio53",
1842                                                "gpio54", "gpio55";
1843                                         function = "qup17";
1844                                 };
1845
1846                                 config {
1847                                         pins = "gpio52", "gpio53",
1848                                                "gpio54", "gpio55";
1849                                         drive-strength = <6>;
1850                                         bias-disable;
1851                                 };
1852                         };
1853
1854                         qup_spi18_default: qup-spi18-default {
1855                                 mux {
1856                                         pins = "gpio56", "gpio57",
1857                                                "gpio58", "gpio59";
1858                                         function = "qup18";
1859                                 };
1860
1861                                 config {
1862                                         pins = "gpio56", "gpio57",
1863                                                "gpio58", "gpio59";
1864                                         drive-strength = <6>;
1865                                         bias-disable;
1866                                 };
1867                         };
1868
1869                         qup_spi19_default: qup-spi19-default {
1870                                 mux {
1871                                         pins = "gpio0", "gpio1",
1872                                                "gpio2", "gpio3";
1873                                         function = "qup19";
1874                                 };
1875
1876                                 config {
1877                                         pins = "gpio0", "gpio1",
1878                                                "gpio2", "gpio3";
1879                                         drive-strength = <6>;
1880                                         bias-disable;
1881                                 };
1882                         };
1883                 };
1884
1885                 adsp: remoteproc@17300000 {
1886                         compatible = "qcom,sm8250-adsp-pas";
1887                         reg = <0 0x17300000 0 0x100>;
1888
1889                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1890                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1891                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1892                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1893                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1894                         interrupt-names = "wdog", "fatal", "ready",
1895                                           "handover", "stop-ack";
1896
1897                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1898                         clock-names = "xo";
1899
1900                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1901                                         <&rpmhpd SM8250_LCX>,
1902                                         <&rpmhpd SM8250_LMX>;
1903                         power-domain-names = "load_state", "lcx", "lmx";
1904
1905                         memory-region = <&adsp_mem>;
1906
1907                         qcom,smem-states = <&smp2p_adsp_out 0>;
1908                         qcom,smem-state-names = "stop";
1909
1910                         status = "disabled";
1911
1912                         glink-edge {
1913                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1914                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1915                                                              IRQ_TYPE_EDGE_RISING>;
1916                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
1917                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1918
1919                                 label = "lpass";
1920                                 qcom,remote-pid = <2>;
1921                         };
1922                 };
1923
1924                 intc: interrupt-controller@17a00000 {
1925                         compatible = "arm,gic-v3";
1926                         #interrupt-cells = <3>;
1927                         interrupt-controller;
1928                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1929                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1930                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1931                 };
1932
1933                 watchdog@17c10000 {
1934                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
1935                         reg = <0 0x17c10000 0 0x1000>;
1936                         clocks = <&sleep_clk>;
1937                 };
1938
1939                 timer@17c20000 {
1940                         #address-cells = <2>;
1941                         #size-cells = <2>;
1942                         ranges;
1943                         compatible = "arm,armv7-timer-mem";
1944                         reg = <0x0 0x17c20000 0x0 0x1000>;
1945                         clock-frequency = <19200000>;
1946
1947                         frame@17c21000 {
1948                                 frame-number = <0>;
1949                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1950                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1951                                 reg = <0x0 0x17c21000 0x0 0x1000>,
1952                                       <0x0 0x17c22000 0x0 0x1000>;
1953                         };
1954
1955                         frame@17c23000 {
1956                                 frame-number = <1>;
1957                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1958                                 reg = <0x0 0x17c23000 0x0 0x1000>;
1959                                 status = "disabled";
1960                         };
1961
1962                         frame@17c25000 {
1963                                 frame-number = <2>;
1964                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1965                                 reg = <0x0 0x17c25000 0x0 0x1000>;
1966                                 status = "disabled";
1967                         };
1968
1969                         frame@17c27000 {
1970                                 frame-number = <3>;
1971                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1972                                 reg = <0x0 0x17c27000 0x0 0x1000>;
1973                                 status = "disabled";
1974                         };
1975
1976                         frame@17c29000 {
1977                                 frame-number = <4>;
1978                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1979                                 reg = <0x0 0x17c29000 0x0 0x1000>;
1980                                 status = "disabled";
1981                         };
1982
1983                         frame@17c2b000 {
1984                                 frame-number = <5>;
1985                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1986                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
1987                                 status = "disabled";
1988                         };
1989
1990                         frame@17c2d000 {
1991                                 frame-number = <6>;
1992                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1993                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
1994                                 status = "disabled";
1995                         };
1996                 };
1997
1998                 apps_rsc: rsc@18200000 {
1999                         label = "apps_rsc";
2000                         compatible = "qcom,rpmh-rsc";
2001                         reg = <0x0 0x18200000 0x0 0x10000>,
2002                                 <0x0 0x18210000 0x0 0x10000>,
2003                                 <0x0 0x18220000 0x0 0x10000>;
2004                         reg-names = "drv-0", "drv-1", "drv-2";
2005                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2006                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2007                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2008                         qcom,tcs-offset = <0xd00>;
2009                         qcom,drv-id = <2>;
2010                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2011                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
2012
2013                         rpmhcc: clock-controller {
2014                                 compatible = "qcom,sm8250-rpmh-clk";
2015                                 #clock-cells = <1>;
2016                                 clock-names = "xo";
2017                                 clocks = <&xo_board>;
2018                         };
2019
2020                         rpmhpd: power-controller {
2021                                 compatible = "qcom,sm8250-rpmhpd";
2022                                 #power-domain-cells = <1>;
2023                                 operating-points-v2 = <&rpmhpd_opp_table>;
2024
2025                                 rpmhpd_opp_table: opp-table {
2026                                         compatible = "operating-points-v2";
2027
2028                                         rpmhpd_opp_ret: opp1 {
2029                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2030                                         };
2031
2032                                         rpmhpd_opp_min_svs: opp2 {
2033                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2034                                         };
2035
2036                                         rpmhpd_opp_low_svs: opp3 {
2037                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2038                                         };
2039
2040                                         rpmhpd_opp_svs: opp4 {
2041                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2042                                         };
2043
2044                                         rpmhpd_opp_svs_l1: opp5 {
2045                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2046                                         };
2047
2048                                         rpmhpd_opp_nom: opp6 {
2049                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2050                                         };
2051
2052                                         rpmhpd_opp_nom_l1: opp7 {
2053                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2054                                         };
2055
2056                                         rpmhpd_opp_nom_l2: opp8 {
2057                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2058                                         };
2059
2060                                         rpmhpd_opp_turbo: opp9 {
2061                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2062                                         };
2063
2064                                         rpmhpd_opp_turbo_l1: opp10 {
2065                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2066                                         };
2067                                 };
2068                         };
2069                 };
2070         };
2071
2072         timer {
2073                 compatible = "arm,armv8-timer";
2074                 interrupts = <GIC_PPI 13
2075                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2076                              <GIC_PPI 14
2077                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2078                              <GIC_PPI 11
2079                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2080                              <GIC_PPI 12
2081                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2082         };
2083 };