arch/arm64/boot/dts/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/power/qcom-aoss-qmp.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         clocks {
  26                 xo_board: xo-board {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <38400000>;
  30                         clock-output-names = "xo_board";
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <32764>;
  37                         clock-output-names = "sleep_clk";
  38                 };
  39         };
  40
  41         cpus {
  42                 #address-cells = <2>;
  43                 #size-cells = <0>;
  44
  45                 CPU0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "qcom,kryo485";
  48                         reg = <0x0 0x0>;
  49                         enable-method = "psci";
  50                         capacity-dmips-mhz = <488>;
  51                         dynamic-power-coefficient = <232>;
  52                         next-level-cache = <&L2_0>;
  53                         qcom,freq-domain = <&cpufreq_hw 0>;
  54                         power-domains = <&CPU_PD0>;
  55                         power-domain-names = "psci";
  56                         #cooling-cells = <2>;
  57                         L2_0: l2-cache {
  58                                 compatible = "cache";
  59                                 next-level-cache = <&L3_0>;
  60                                 L3_0: l3-cache {
  61                                       compatible = "cache";
  62                                 };
  63                         };
  64                 };
  65
  66                 CPU1: cpu@100 {
  67                         device_type = "cpu";
  68                         compatible = "qcom,kryo485";
  69                         reg = <0x0 0x100>;
  70                         enable-method = "psci";
  71                         capacity-dmips-mhz = <488>;
  72                         dynamic-power-coefficient = <232>;
  73                         next-level-cache = <&L2_100>;
  74                         qcom,freq-domain = <&cpufreq_hw 0>;
  75                         power-domains = <&CPU_PD1>;
  76                         power-domain-names = "psci";
  77                         #cooling-cells = <2>;
  78                         L2_100: l2-cache {
  79                                 compatible = "cache";
  80                                 next-level-cache = <&L3_0>;
  81                         };
  82
  83                 };
  84
  85                 CPU2: cpu@200 {
  86                         device_type = "cpu";
  87                         compatible = "qcom,kryo485";
  88                         reg = <0x0 0x200>;
  89                         enable-method = "psci";
  90                         capacity-dmips-mhz = <488>;
  91                         dynamic-power-coefficient = <232>;
  92                         next-level-cache = <&L2_200>;
  93                         qcom,freq-domain = <&cpufreq_hw 0>;
  94                         power-domains = <&CPU_PD2>;
  95                         power-domain-names = "psci";
  96                         #cooling-cells = <2>;
  97                         L2_200: l2-cache {
  98                                 compatible = "cache";
  99                                 next-level-cache = <&L3_0>;
 100                         };
 101                 };
 102
 103                 CPU3: cpu@300 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo485";
 106                         reg = <0x0 0x300>;
 107                         enable-method = "psci";
 108                         capacity-dmips-mhz = <488>;
 109                         dynamic-power-coefficient = <232>;
 110                         next-level-cache = <&L2_300>;
 111                         qcom,freq-domain = <&cpufreq_hw 0>;
 112                         power-domains = <&CPU_PD3>;
 113                         power-domain-names = "psci";
 114                         #cooling-cells = <2>;
 115                         L2_300: l2-cache {
 116                                 compatible = "cache";
 117                                 next-level-cache = <&L3_0>;
 118                         };
 119                 };
 120
 121                 CPU4: cpu@400 {
 122                         device_type = "cpu";
 123                         compatible = "qcom,kryo485";
 124                         reg = <0x0 0x400>;
 125                         enable-method = "psci";
 126                         capacity-dmips-mhz = <1024>;
 127                         dynamic-power-coefficient = <369>;
 128                         next-level-cache = <&L2_400>;
 129                         qcom,freq-domain = <&cpufreq_hw 1>;
 130                         power-domains = <&CPU_PD4>;
 131                         power-domain-names = "psci";
 132                         #cooling-cells = <2>;
 133                         L2_400: l2-cache {
 134                                 compatible = "cache";
 135                                 next-level-cache = <&L3_0>;
 136                         };
 137                 };
 138
 139                 CPU5: cpu@500 {
 140                         device_type = "cpu";
 141                         compatible = "qcom,kryo485";
 142                         reg = <0x0 0x500>;
 143                         enable-method = "psci";
 144                         capacity-dmips-mhz = <1024>;
 145                         dynamic-power-coefficient = <369>;
 146                         next-level-cache = <&L2_500>;
 147                         qcom,freq-domain = <&cpufreq_hw 1>;
 148                         power-domains = <&CPU_PD5>;
 149                         power-domain-names = "psci";
 150                         #cooling-cells = <2>;
 151                         L2_500: l2-cache {
 152                                 compatible = "cache";
 153                                 next-level-cache = <&L3_0>;
 154                         };
 155                 };
 156
 157                 CPU6: cpu@600 {
 158                         device_type = "cpu";
 159                         compatible = "qcom,kryo485";
 160                         reg = <0x0 0x600>;
 161                         enable-method = "psci";
 162                         capacity-dmips-mhz = <1024>;
 163                         dynamic-power-coefficient = <369>;
 164                         next-level-cache = <&L2_600>;
 165                         qcom,freq-domain = <&cpufreq_hw 1>;
 166                         power-domains = <&CPU_PD6>;
 167                         power-domain-names = "psci";
 168                         #cooling-cells = <2>;
 169                         L2_600: l2-cache {
 170                                 compatible = "cache";
 171                                 next-level-cache = <&L3_0>;
 172                         };
 173                 };
 174
 175                 CPU7: cpu@700 {
 176                         device_type = "cpu";
 177                         compatible = "qcom,kryo485";
 178                         reg = <0x0 0x700>;
 179                         enable-method = "psci";
 180                         capacity-dmips-mhz = <1024>;
 181                         dynamic-power-coefficient = <421>;
 182                         next-level-cache = <&L2_700>;
 183                         qcom,freq-domain = <&cpufreq_hw 2>;
 184                         power-domains = <&CPU_PD7>;
 185                         power-domain-names = "psci";
 186                         #cooling-cells = <2>;
 187                         L2_700: l2-cache {
 188                                 compatible = "cache";
 189                                 next-level-cache = <&L3_0>;
 190                         };
 191                 };
 192
 193                 cpu-map {
 194                         cluster0 {
 195                                 core0 {
 196                                         cpu = <&CPU0>;
 197                                 };
 198
 199                                 core1 {
 200                                         cpu = <&CPU1>;
 201                                 };
 202
 203                                 core2 {
 204                                         cpu = <&CPU2>;
 205                                 };
 206
 207                                 core3 {
 208                                         cpu = <&CPU3>;
 209                                 };
 210
 211                                 core4 {
 212                                         cpu = <&CPU4>;
 213                                 };
 214
 215                                 core5 {
 216                                         cpu = <&CPU5>;
 217                                 };
 218
 219                                 core6 {
 220                                         cpu = <&CPU6>;
 221                                 };
 222
 223                                 core7 {
 224                                         cpu = <&CPU7>;
 225                                 };
 226                         };
 227                 };
 228
 229                 idle-states {
 230                         entry-method = "psci";
 231
 232                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 233                                 compatible = "arm,idle-state";
 234                                 idle-state-name = "little-rail-power-collapse";
 235                                 arm,psci-suspend-param = <0x40000004>;
 236                                 entry-latency-us = <355>;
 237                                 exit-latency-us = <909>;
 238                                 min-residency-us = <3934>;
 239                                 local-timer-stop;
 240                         };
 241
 242                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 243                                 compatible = "arm,idle-state";
 244                                 idle-state-name = "big-rail-power-collapse";
 245                                 arm,psci-suspend-param = <0x40000004>;
 246                                 entry-latency-us = <241>;
 247                                 exit-latency-us = <1461>;
 248                                 min-residency-us = <4488>;
 249                                 local-timer-stop;
 250                         };
 251                 };
 252
 253                 domain-idle-states {
 254                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 255                                 compatible = "domain-idle-state";
 256                                 idle-state-name = "cluster-power-collapse";
 257                                 arm,psci-suspend-param = <0x4100c244>;
 258                                 entry-latency-us = <3263>;
 259                                 exit-latency-us = <6562>;
 260                                 min-residency-us = <9987>;
 261                                 local-timer-stop;
 262                         };
 263                 };
 264         };
 265
 266         firmware {
 267                 scm: scm {
 268                         compatible = "qcom,scm-sm8150", "qcom,scm";
 269                         #reset-cells = <1>;
 270                 };
 271         };
 272
 273         tcsr_mutex: hwlock {
 274                 compatible = "qcom,tcsr-mutex";
 275                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 276                 #hwlock-cells = <1>;
 277         };
 278
 279         memory@80000000 {
 280                 device_type = "memory";
 281                 /* We expect the bootloader to fill in the size */
 282                 reg = <0x0 0x80000000 0x0 0x0>;
 283         };
 284
 285         pmu {
 286                 compatible = "arm,armv8-pmuv3";
 287                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 288         };
 289
 290         psci {
 291                 compatible = "arm,psci-1.0";
 292                 method = "smc";
 293
 294                 CPU_PD0: cpu0 {
 295                         #power-domain-cells = <0>;
 296                         power-domains = <&CLUSTER_PD>;
 297                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 298                 };
 299
 300                 CPU_PD1: cpu1 {
 301                         #power-domain-cells = <0>;
 302                         power-domains = <&CLUSTER_PD>;
 303                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 304                 };
 305
 306                 CPU_PD2: cpu2 {
 307                         #power-domain-cells = <0>;
 308                         power-domains = <&CLUSTER_PD>;
 309                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 310                 };
 311
 312                 CPU_PD3: cpu3 {
 313                         #power-domain-cells = <0>;
 314                         power-domains = <&CLUSTER_PD>;
 315                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 316                 };
 317
 318                 CPU_PD4: cpu4 {
 319                         #power-domain-cells = <0>;
 320                         power-domains = <&CLUSTER_PD>;
 321                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 322                 };
 323
 324                 CPU_PD5: cpu5 {
 325                         #power-domain-cells = <0>;
 326                         power-domains = <&CLUSTER_PD>;
 327                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 328                 };
 329
 330                 CPU_PD6: cpu6 {
 331                         #power-domain-cells = <0>;
 332                         power-domains = <&CLUSTER_PD>;
 333                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 334                 };
 335
 336                 CPU_PD7: cpu7 {
 337                         #power-domain-cells = <0>;
 338                         power-domains = <&CLUSTER_PD>;
 339                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 340                 };
 341
 342                 CLUSTER_PD: cpu-cluster0 {
 343                         #power-domain-cells = <0>;
 344                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 345                 };
 346         };
 347
 348         reserved-memory {
 349                 #address-cells = <2>;
 350                 #size-cells = <2>;
 351                 ranges;
 352
 353                 hyp_mem: memory@85700000 {
 354                         reg = <0x0 0x85700000 0x0 0x600000>;
 355                         no-map;
 356                 };
 357
 358                 xbl_mem: memory@85d00000 {
 359                         reg = <0x0 0x85d00000 0x0 0x140000>;
 360                         no-map;
 361                 };
 362
 363                 aop_mem: memory@85f00000 {
 364                         reg = <0x0 0x85f00000 0x0 0x20000>;
 365                         no-map;
 366                 };
 367
 368                 aop_cmd_db: memory@85f20000 {
 369                         compatible = "qcom,cmd-db";
 370                         reg = <0x0 0x85f20000 0x0 0x20000>;
 371                         no-map;
 372                 };
 373
 374                 smem_mem: memory@86000000 {
 375                         reg = <0x0 0x86000000 0x0 0x200000>;
 376                         no-map;
 377                 };
 378
 379                 tz_mem: memory@86200000 {
 380                         reg = <0x0 0x86200000 0x0 0x3900000>;
 381                         no-map;
 382                 };
 383
 384                 rmtfs_mem: memory@89b00000 {
 385                         compatible = "qcom,rmtfs-mem";
 386                         reg = <0x0 0x89b00000 0x0 0x200000>;
 387                         no-map;
 388
 389                         qcom,client-id = <1>;
 390                         qcom,vmid = <15>;
 391                 };
 392
 393                 camera_mem: memory@8b700000 {
 394                         reg = <0x0 0x8b700000 0x0 0x500000>;
 395                         no-map;
 396                 };
 397
 398                 wlan_mem: memory@8bc00000 {
 399                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 400                         no-map;
 401                 };
 402
 403                 npu_mem: memory@8bd80000 {
 404                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 405                         no-map;
 406                 };
 407
 408                 adsp_mem: memory@8be00000 {
 409                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 410                         no-map;
 411                 };
 412
 413                 mpss_mem: memory@8d800000 {
 414                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 415                         no-map;
 416                 };
 417
 418                 venus_mem: memory@96e00000 {
 419                         reg = <0x0 0x96e00000 0x0 0x500000>;
 420                         no-map;
 421                 };
 422
 423                 slpi_mem: memory@97300000 {
 424                         reg = <0x0 0x97300000 0x0 0x1400000>;
 425                         no-map;
 426                 };
 427
 428                 ipa_fw_mem: memory@98700000 {
 429                         reg = <0x0 0x98700000 0x0 0x10000>;
 430                         no-map;
 431                 };
 432
 433                 ipa_gsi_mem: memory@98710000 {
 434                         reg = <0x0 0x98710000 0x0 0x5000>;
 435                         no-map;
 436                 };
 437
 438                 gpu_mem: memory@98715000 {
 439                         reg = <0x0 0x98715000 0x0 0x2000>;
 440                         no-map;
 441                 };
 442
 443                 spss_mem: memory@98800000 {
 444                         reg = <0x0 0x98800000 0x0 0x100000>;
 445                         no-map;
 446                 };
 447
 448                 cdsp_mem: memory@98900000 {
 449                         reg = <0x0 0x98900000 0x0 0x1400000>;
 450                         no-map;
 451                 };
 452
 453                 qseecom_mem: memory@9e400000 {
 454                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 455                         no-map;
 456                 };
 457         };
 458
 459         smem {
 460                 compatible = "qcom,smem";
 461                 memory-region = <&smem_mem>;
 462                 hwlocks = <&tcsr_mutex 3>;
 463         };
 464
 465         smp2p-cdsp {
 466                 compatible = "qcom,smp2p";
 467                 qcom,smem = <94>, <432>;
 468
 469                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 470
 471                 mboxes = <&apss_shared 6>;
 472
 473                 qcom,local-pid = <0>;
 474                 qcom,remote-pid = <5>;
 475
 476                 cdsp_smp2p_out: master-kernel {
 477                         qcom,entry-name = "master-kernel";
 478                         #qcom,smem-state-cells = <1>;
 479                 };
 480
 481                 cdsp_smp2p_in: slave-kernel {
 482                         qcom,entry-name = "slave-kernel";
 483
 484                         interrupt-controller;
 485                         #interrupt-cells = <2>;
 486                 };
 487         };
 488
 489         smp2p-lpass {
 490                 compatible = "qcom,smp2p";
 491                 qcom,smem = <443>, <429>;
 492
 493                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 494
 495                 mboxes = <&apss_shared 10>;
 496
 497                 qcom,local-pid = <0>;
 498                 qcom,remote-pid = <2>;
 499
 500                 adsp_smp2p_out: master-kernel {
 501                         qcom,entry-name = "master-kernel";
 502                         #qcom,smem-state-cells = <1>;
 503                 };
 504
 505                 adsp_smp2p_in: slave-kernel {
 506                         qcom,entry-name = "slave-kernel";
 507
 508                         interrupt-controller;
 509                         #interrupt-cells = <2>;
 510                 };
 511         };
 512
 513         smp2p-mpss {
 514                 compatible = "qcom,smp2p";
 515                 qcom,smem = <435>, <428>;
 516
 517                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 518
 519                 mboxes = <&apss_shared 14>;
 520
 521                 qcom,local-pid = <0>;
 522                 qcom,remote-pid = <1>;
 523
 524                 modem_smp2p_out: master-kernel {
 525                         qcom,entry-name = "master-kernel";
 526                         #qcom,smem-state-cells = <1>;
 527                 };
 528
 529                 modem_smp2p_in: slave-kernel {
 530                         qcom,entry-name = "slave-kernel";
 531
 532                         interrupt-controller;
 533                         #interrupt-cells = <2>;
 534                 };
 535         };
 536
 537         smp2p-slpi {
 538                 compatible = "qcom,smp2p";
 539                 qcom,smem = <481>, <430>;
 540
 541                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 542
 543                 mboxes = <&apss_shared 26>;
 544
 545                 qcom,local-pid = <0>;
 546                 qcom,remote-pid = <3>;
 547
 548                 slpi_smp2p_out: master-kernel {
 549                         qcom,entry-name = "master-kernel";
 550                         #qcom,smem-state-cells = <1>;
 551                 };
 552
 553                 slpi_smp2p_in: slave-kernel {
 554                         qcom,entry-name = "slave-kernel";
 555
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559         };
 560
 561         soc: soc@0 {
 562                 #address-cells = <2>;
 563                 #size-cells = <2>;
 564                 ranges = <0 0 0 0 0x10 0>;
 565                 dma-ranges = <0 0 0 0 0x10 0>;
 566                 compatible = "simple-bus";
 567
 568                 gcc: clock-controller@100000 {
 569                         compatible = "qcom,gcc-sm8150";
 570                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 571                         #clock-cells = <1>;
 572                         #reset-cells = <1>;
 573                         #power-domain-cells = <1>;
 574                         clock-names = "bi_tcxo",
 575                                       "sleep_clk";
 576                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 577                                  <&sleep_clk>;
 578                 };
 579
 580                 qupv3_id_0: geniqup@8c0000 {
 581                         compatible = "qcom,geni-se-qup";
 582                         reg = <0x0 0x008c0000 0x0 0x6000>;
 583                         clock-names = "m-ahb", "s-ahb";
 584                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 585                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 586                         iommus = <&apps_smmu 0xc3 0x0>;
 587                         #address-cells = <2>;
 588                         #size-cells = <2>;
 589                         ranges;
 590                         status = "disabled";
 591
 592                         i2c0: i2c@880000 {
 593                                 compatible = "qcom,geni-i2c";
 594                                 reg = <0 0x00880000 0 0x4000>;
 595                                 clock-names = "se";
 596                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 597                                 pinctrl-names = "default";
 598                                 pinctrl-0 = <&qup_i2c0_default>;
 599                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 600                                 #address-cells = <1>;
 601                                 #size-cells = <0>;
 602                                 status = "disabled";
 603                         };
 604
 605                         i2c1: i2c@884000 {
 606                                 compatible = "qcom,geni-i2c";
 607                                 reg = <0 0x00884000 0 0x4000>;
 608                                 clock-names = "se";
 609                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 610                                 pinctrl-names = "default";
 611                                 pinctrl-0 = <&qup_i2c1_default>;
 612                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 613                                 #address-cells = <1>;
 614                                 #size-cells = <0>;
 615                                 status = "disabled";
 616                         };
 617
 618                         i2c2: i2c@888000 {
 619                                 compatible = "qcom,geni-i2c";
 620                                 reg = <0 0x00888000 0 0x4000>;
 621                                 clock-names = "se";
 622                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 623                                 pinctrl-names = "default";
 624                                 pinctrl-0 = <&qup_i2c2_default>;
 625                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 626                                 #address-cells = <1>;
 627                                 #size-cells = <0>;
 628                                 status = "disabled";
 629                         };
 630
 631                         i2c3: i2c@88c000 {
 632                                 compatible = "qcom,geni-i2c";
 633                                 reg = <0 0x0088c000 0 0x4000>;
 634                                 clock-names = "se";
 635                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 636                                 pinctrl-names = "default";
 637                                 pinctrl-0 = <&qup_i2c3_default>;
 638                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 639                                 #address-cells = <1>;
 640                                 #size-cells = <0>;
 641                                 status = "disabled";
 642                         };
 643
 644                         i2c4: i2c@890000 {
 645                                 compatible = "qcom,geni-i2c";
 646                                 reg = <0 0x00890000 0 0x4000>;
 647                                 clock-names = "se";
 648                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 649                                 pinctrl-names = "default";
 650                                 pinctrl-0 = <&qup_i2c4_default>;
 651                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654                                 status = "disabled";
 655                         };
 656
 657                         i2c5: i2c@894000 {
 658                                 compatible = "qcom,geni-i2c";
 659                                 reg = <0 0x00894000 0 0x4000>;
 660                                 clock-names = "se";
 661                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 662                                 pinctrl-names = "default";
 663                                 pinctrl-0 = <&qup_i2c5_default>;
 664                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667                                 status = "disabled";
 668                         };
 669
 670                         i2c6: i2c@898000 {
 671                                 compatible = "qcom,geni-i2c";
 672                                 reg = <0 0x00898000 0 0x4000>;
 673                                 clock-names = "se";
 674                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 675                                 pinctrl-names = "default";
 676                                 pinctrl-0 = <&qup_i2c6_default>;
 677                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 678                                 #address-cells = <1>;
 679                                 #size-cells = <0>;
 680                                 status = "disabled";
 681                         };
 682
 683                         i2c7: i2c@89c000 {
 684                                 compatible = "qcom,geni-i2c";
 685                                 reg = <0 0x0089c000 0 0x4000>;
 686                                 clock-names = "se";
 687                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 688                                 pinctrl-names = "default";
 689                                 pinctrl-0 = <&qup_i2c7_default>;
 690                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 691                                 #address-cells = <1>;
 692                                 #size-cells = <0>;
 693                                 status = "disabled";
 694                         };
 695
 696                 };
 697
 698                 qupv3_id_1: geniqup@ac0000 {
 699                         compatible = "qcom,geni-se-qup";
 700                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 701                         clock-names = "m-ahb", "s-ahb";
 702                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 703                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 704                         iommus = <&apps_smmu 0x603 0x0>;
 705                         #address-cells = <2>;
 706                         #size-cells = <2>;
 707                         ranges;
 708                         status = "disabled";
 709
 710                         i2c8: i2c@a80000 {
 711                                 compatible = "qcom,geni-i2c";
 712                                 reg = <0 0x00a80000 0 0x4000>;
 713                                 clock-names = "se";
 714                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 715                                 pinctrl-names = "default";
 716                                 pinctrl-0 = <&qup_i2c8_default>;
 717                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 718                                 #address-cells = <1>;
 719                                 #size-cells = <0>;
 720                                 status = "disabled";
 721                         };
 722
 723                         i2c9: i2c@a84000 {
 724                                 compatible = "qcom,geni-i2c";
 725                                 reg = <0 0x00a84000 0 0x4000>;
 726                                 clock-names = "se";
 727                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 728                                 pinctrl-names = "default";
 729                                 pinctrl-0 = <&qup_i2c9_default>;
 730                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 731                                 #address-cells = <1>;
 732                                 #size-cells = <0>;
 733                                 status = "disabled";
 734                         };
 735
 736                         i2c10: i2c@a88000 {
 737                                 compatible = "qcom,geni-i2c";
 738                                 reg = <0 0x00a88000 0 0x4000>;
 739                                 clock-names = "se";
 740                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 741                                 pinctrl-names = "default";
 742                                 pinctrl-0 = <&qup_i2c10_default>;
 743                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 744                                 #address-cells = <1>;
 745                                 #size-cells = <0>;
 746                                 status = "disabled";
 747                         };
 748
 749                         i2c11: i2c@a8c000 {
 750                                 compatible = "qcom,geni-i2c";
 751                                 reg = <0 0x00a8c000 0 0x4000>;
 752                                 clock-names = "se";
 753                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 754                                 pinctrl-names = "default";
 755                                 pinctrl-0 = <&qup_i2c11_default>;
 756                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 757                                 #address-cells = <1>;
 758                                 #size-cells = <0>;
 759                                 status = "disabled";
 760                         };
 761
 762                         uart2: serial@a90000 {
 763                                 compatible = "qcom,geni-debug-uart";
 764                                 reg = <0x0 0x00a90000 0x0 0x4000>;
 765                                 clock-names = "se";
 766                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 767                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 768                                 status = "disabled";
 769                         };
 770
 771                         i2c12: i2c@a90000 {
 772                                 compatible = "qcom,geni-i2c";
 773                                 reg = <0 0x00a90000 0 0x4000>;
 774                                 clock-names = "se";
 775                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 776                                 pinctrl-names = "default";
 777                                 pinctrl-0 = <&qup_i2c12_default>;
 778                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 779                                 #address-cells = <1>;
 780                                 #size-cells = <0>;
 781                                 status = "disabled";
 782                         };
 783
 784                         i2c16: i2c@94000 {
 785                                 compatible = "qcom,geni-i2c";
 786                                 reg = <0 0x0094000 0 0x4000>;
 787                                 clock-names = "se";
 788                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 789                                 pinctrl-names = "default";
 790                                 pinctrl-0 = <&qup_i2c16_default>;
 791                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 792                                 #address-cells = <1>;
 793                                 #size-cells = <0>;
 794                                 status = "disabled";
 795                         };
 796                 };
 797
 798                 qupv3_id_2: geniqup@cc0000 {
 799                         compatible = "qcom,geni-se-qup";
 800                         reg = <0x0 0x00cc0000 0x0 0x6000>;
 801
 802                         clock-names = "m-ahb", "s-ahb";
 803                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 804                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 805                         iommus = <&apps_smmu 0x7a3 0x0>;
 806                         #address-cells = <2>;
 807                         #size-cells = <2>;
 808                         ranges;
 809                         status = "disabled";
 810
 811                         i2c17: i2c@c80000 {
 812                                 compatible = "qcom,geni-i2c";
 813                                 reg = <0 0x00c80000 0 0x4000>;
 814                                 clock-names = "se";
 815                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 816                                 pinctrl-names = "default";
 817                                 pinctrl-0 = <&qup_i2c17_default>;
 818                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 819                                 #address-cells = <1>;
 820                                 #size-cells = <0>;
 821                                 status = "disabled";
 822                         };
 823
 824                         i2c18: i2c@c84000 {
 825                                 compatible = "qcom,geni-i2c";
 826                                 reg = <0 0x00c84000 0 0x4000>;
 827                                 clock-names = "se";
 828                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 829                                 pinctrl-names = "default";
 830                                 pinctrl-0 = <&qup_i2c18_default>;
 831                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 832                                 #address-cells = <1>;
 833                                 #size-cells = <0>;
 834                                 status = "disabled";
 835                         };
 836
 837                         i2c19: i2c@c88000 {
 838                                 compatible = "qcom,geni-i2c";
 839                                 reg = <0 0x00c88000 0 0x4000>;
 840                                 clock-names = "se";
 841                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 842                                 pinctrl-names = "default";
 843                                 pinctrl-0 = <&qup_i2c19_default>;
 844                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 845                                 #address-cells = <1>;
 846                                 #size-cells = <0>;
 847                                 status = "disabled";
 848                         };
 849
 850                         i2c13: i2c@c8c000 {
 851                                 compatible = "qcom,geni-i2c";
 852                                 reg = <0 0x00c8c000 0 0x4000>;
 853                                 clock-names = "se";
 854                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 855                                 pinctrl-names = "default";
 856                                 pinctrl-0 = <&qup_i2c13_default>;
 857                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 858                                 #address-cells = <1>;
 859                                 #size-cells = <0>;
 860                                 status = "disabled";
 861                         };
 862
 863                         i2c14: i2c@c90000 {
 864                                 compatible = "qcom,geni-i2c";
 865                                 reg = <0 0x00c90000 0 0x4000>;
 866                                 clock-names = "se";
 867                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 868                                 pinctrl-names = "default";
 869                                 pinctrl-0 = <&qup_i2c14_default>;
 870                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 871                                 #address-cells = <1>;
 872                                 #size-cells = <0>;
 873                                 status = "disabled";
 874                         };
 875
 876                         i2c15: i2c@c94000 {
 877                                 compatible = "qcom,geni-i2c";
 878                                 reg = <0 0x00c94000 0 0x4000>;
 879                                 clock-names = "se";
 880                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 881                                 pinctrl-names = "default";
 882                                 pinctrl-0 = <&qup_i2c15_default>;
 883                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886                                 status = "disabled";
 887                         };
 888                 };
 889
 890                 config_noc: interconnect@1500000 {
 891                         compatible = "qcom,sm8150-config-noc";
 892                         reg = <0 0x01500000 0 0x7400>;
 893                         #interconnect-cells = <1>;
 894                         qcom,bcm-voters = <&apps_bcm_voter>;
 895                 };
 896
 897                 system_noc: interconnect@1620000 {
 898                         compatible = "qcom,sm8150-system-noc";
 899                         reg = <0 0x01620000 0 0x19400>;
 900                         #interconnect-cells = <1>;
 901                         qcom,bcm-voters = <&apps_bcm_voter>;
 902                 };
 903
 904                 mc_virt: interconnect@163a000 {
 905                         compatible = "qcom,sm8150-mc-virt";
 906                         reg = <0 0x0163a000 0 0x1000>;
 907                         #interconnect-cells = <1>;
 908                         qcom,bcm-voters = <&apps_bcm_voter>;
 909                 };
 910
 911                 aggre1_noc: interconnect@16e0000 {
 912                         compatible = "qcom,sm8150-aggre1-noc";
 913                         reg = <0 0x016e0000 0 0xd080>;
 914                         #interconnect-cells = <1>;
 915                         qcom,bcm-voters = <&apps_bcm_voter>;
 916                 };
 917
 918                 aggre2_noc: interconnect@1700000 {
 919                         compatible = "qcom,sm8150-aggre2-noc";
 920                         reg = <0 0x01700000 0 0x20000>;
 921                         #interconnect-cells = <1>;
 922                         qcom,bcm-voters = <&apps_bcm_voter>;
 923                 };
 924
 925                 compute_noc: interconnect@1720000 {
 926                         compatible = "qcom,sm8150-compute-noc";
 927                         reg = <0 0x01720000 0 0x7000>;
 928                         #interconnect-cells = <1>;
 929                         qcom,bcm-voters = <&apps_bcm_voter>;
 930                 };
 931
 932                 mmss_noc: interconnect@1740000 {
 933                         compatible = "qcom,sm8150-mmss-noc";
 934                         reg = <0 0x01740000 0 0x1c100>;
 935                         #interconnect-cells = <1>;
 936                         qcom,bcm-voters = <&apps_bcm_voter>;
 937                 };
 938
 939                 system-cache-controller@9200000 {
 940                         compatible = "qcom,sm8150-llcc";
 941                         reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
 942                         reg-names = "llcc_base", "llcc_broadcast_base";
 943                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 944                 };
 945
 946                 ufs_mem_hc: ufshc@1d84000 {
 947                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 948                                      "jedec,ufs-2.0";
 949                         reg = <0 0x01d84000 0 0x2500>;
 950                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 951                         phys = <&ufs_mem_phy_lanes>;
 952                         phy-names = "ufsphy";
 953                         lanes-per-direction = <2>;
 954                         #reset-cells = <1>;
 955                         resets = <&gcc GCC_UFS_PHY_BCR>;
 956                         reset-names = "rst";
 957
 958                         iommus = <&apps_smmu 0x300 0>;
 959
 960                         clock-names =
 961                                 "core_clk",
 962                                 "bus_aggr_clk",
 963                                 "iface_clk",
 964                                 "core_clk_unipro",
 965                                 "ref_clk",
 966                                 "tx_lane0_sync_clk",
 967                                 "rx_lane0_sync_clk",
 968                                 "rx_lane1_sync_clk";
 969                         clocks =
 970                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
 971                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 972                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
 973                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 974                                 <&rpmhcc RPMH_CXO_CLK>,
 975                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 976                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 977                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
 978                         freq-table-hz =
 979                                 <37500000 300000000>,
 980                                 <0 0>,
 981                                 <0 0>,
 982                                 <37500000 300000000>,
 983                                 <0 0>,
 984                                 <0 0>,
 985                                 <0 0>,
 986                                 <0 0>;
 987
 988                         status = "disabled";
 989                 };
 990
 991                 ufs_mem_phy: phy@1d87000 {
 992                         compatible = "qcom,sm8150-qmp-ufs-phy";
 993                         reg = <0 0x01d87000 0 0x1c0>;
 994                         #address-cells = <2>;
 995                         #size-cells = <2>;
 996                         ranges;
 997                         clock-names = "ref",
 998                                       "ref_aux";
 999                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1000                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1001
1002                         resets = <&ufs_mem_hc 0>;
1003                         reset-names = "ufsphy";
1004                         status = "disabled";
1005
1006                         ufs_mem_phy_lanes: lanes@1d87400 {
1007                                 reg = <0 0x01d87400 0 0x108>,
1008                                       <0 0x01d87600 0 0x1e0>,
1009                                       <0 0x01d87c00 0 0x1dc>,
1010                                       <0 0x01d87800 0 0x108>,
1011                                       <0 0x01d87a00 0 0x1e0>;
1012                                 #phy-cells = <0>;
1013                         };
1014                 };
1015
1016                 ipa_virt: interconnect@1e00000 {
1017                         compatible = "qcom,sm8150-ipa-virt";
1018                         reg = <0 0x01e00000 0 0x1000>;
1019                         #interconnect-cells = <1>;
1020                         qcom,bcm-voters = <&apps_bcm_voter>;
1021                 };
1022
1023                 tcsr_mutex_regs: syscon@1f40000 {
1024                         compatible = "syscon";
1025                         reg = <0x0 0x01f40000 0x0 0x40000>;
1026                 };
1027
1028                 remoteproc_slpi: remoteproc@2400000 {
1029                         compatible = "qcom,sm8150-slpi-pas";
1030                         reg = <0x0 0x02400000 0x0 0x4040>;
1031
1032                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
1033                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1034                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1035                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1036                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1037                         interrupt-names = "wdog", "fatal", "ready",
1038                                           "handover", "stop-ack";
1039
1040                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1041                         clock-names = "xo";
1042
1043                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1044                                         <&rpmhpd 3>,
1045                                         <&rpmhpd 2>;
1046                         power-domain-names = "load_state", "lcx", "lmx";
1047
1048                         memory-region = <&slpi_mem>;
1049
1050                         qcom,smem-states = <&slpi_smp2p_out 0>;
1051                         qcom,smem-state-names = "stop";
1052
1053                         status = "disabled";
1054
1055                         glink-edge {
1056                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
1057                                 label = "dsps";
1058                                 qcom,remote-pid = <3>;
1059                                 mboxes = <&apss_shared 24>;
1060                         };
1061                 };
1062
1063                 gpu: gpu@2c00000 {
1064                         /*
1065                          * note: the amd,imageon compatible makes it possible
1066                          * to use the drm/msm driver without the display node,
1067                          * make sure to remove it when display node is added
1068                          */
1069                         compatible = "qcom,adreno-640.1",
1070                                      "qcom,adreno",
1071                                      "amd,imageon";
1072                         #stream-id-cells = <16>;
1073
1074                         reg = <0 0x02c00000 0 0x40000>;
1075                         reg-names = "kgsl_3d0_reg_memory";
1076
1077                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1078
1079                         iommus = <&adreno_smmu 0 0x401>;
1080
1081                         operating-points-v2 = <&gpu_opp_table>;
1082
1083                         qcom,gmu = <&gmu>;
1084
1085                         zap-shader {
1086                                 memory-region = <&gpu_mem>;
1087                         };
1088
1089                         /* note: downstream checks gpu binning for 675 Mhz */
1090                         gpu_opp_table: opp-table {
1091                                 compatible = "operating-points-v2";
1092
1093                                 opp-675000000 {
1094                                         opp-hz = /bits/ 64 <675000000>;
1095                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1096                                 };
1097
1098                                 opp-585000000 {
1099                                         opp-hz = /bits/ 64 <585000000>;
1100                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1101                                 };
1102
1103                                 opp-499200000 {
1104                                         opp-hz = /bits/ 64 <499200000>;
1105                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1106                                 };
1107
1108                                 opp-427000000 {
1109                                         opp-hz = /bits/ 64 <427000000>;
1110                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1111                                 };
1112
1113                                 opp-345000000 {
1114                                         opp-hz = /bits/ 64 <345000000>;
1115                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1116                                 };
1117
1118                                 opp-257000000 {
1119                                         opp-hz = /bits/ 64 <257000000>;
1120                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1121                                 };
1122                         };
1123                 };
1124
1125                 gmu: gmu@2c6a000 {
1126                         compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
1127
1128                         reg = <0 0x02c6a000 0 0x30000>,
1129                               <0 0x0b290000 0 0x10000>,
1130                               <0 0x0b490000 0 0x10000>;
1131                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1132
1133                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1134                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1135                         interrupt-names = "hfi", "gmu";
1136
1137                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1138                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1139                                  <&gpucc GPU_CC_CXO_CLK>,
1140                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1141                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1142                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1143
1144                         power-domains = <&gpucc GPU_CX_GDSC>,
1145                                         <&gpucc GPU_GX_GDSC>;
1146                         power-domain-names = "cx", "gx";
1147
1148                         iommus = <&adreno_smmu 5 0x400>;
1149
1150                         operating-points-v2 = <&gmu_opp_table>;
1151
1152                         gmu_opp_table: opp-table {
1153                                 compatible = "operating-points-v2";
1154
1155                                 opp-200000000 {
1156                                         opp-hz = /bits/ 64 <200000000>;
1157                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1158                                 };
1159                         };
1160                 };
1161
1162                 gpucc: clock-controller@2c90000 {
1163                         compatible = "qcom,sm8150-gpucc";
1164                         reg = <0 0x02c90000 0 0x9000>;
1165                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1166                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1167                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1168                         clock-names = "bi_tcxo",
1169                                       "gcc_gpu_gpll0_clk_src",
1170                                       "gcc_gpu_gpll0_div_clk_src";
1171                         #clock-cells = <1>;
1172                         #reset-cells = <1>;
1173                         #power-domain-cells = <1>;
1174                 };
1175
1176                 adreno_smmu: iommu@2ca0000 {
1177                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
1178                         reg = <0 0x02ca0000 0 0x10000>;
1179                         #iommu-cells = <2>;
1180                         #global-interrupts = <1>;
1181                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
1182                                 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1183                                 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1184                                 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1185                                 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1186                                 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1187                                 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1188                                 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
1189                                 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
1190                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1191                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1192                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1193                         clock-names = "ahb", "bus", "iface";
1194
1195                         power-domains = <&gpucc GPU_CX_GDSC>;
1196                 };
1197
1198                 tlmm: pinctrl@3100000 {
1199                         compatible = "qcom,sm8150-pinctrl";
1200                         reg = <0x0 0x03100000 0x0 0x300000>,
1201                               <0x0 0x03500000 0x0 0x300000>,
1202                               <0x0 0x03900000 0x0 0x300000>,
1203                               <0x0 0x03D00000 0x0 0x300000>;
1204                         reg-names = "west", "east", "north", "south";
1205                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1206                         gpio-ranges = <&tlmm 0 0 176>;
1207                         gpio-controller;
1208                         #gpio-cells = <2>;
1209                         interrupt-controller;
1210                         #interrupt-cells = <2>;
1211
1212                         qup_i2c0_default: qup-i2c0-default {
1213                                 mux {
1214                                         pins = "gpio0", "gpio1";
1215                                         function = "qup0";
1216                                 };
1217
1218                                 config {
1219                                         pins = "gpio0", "gpio1";
1220                                         drive-strength = <0x02>;
1221                                         bias-disable;
1222                                 };
1223                         };
1224
1225                         qup_i2c1_default: qup-i2c1-default {
1226                                 mux {
1227                                         pins = "gpio114", "gpio115";
1228                                         function = "qup1";
1229                                 };
1230
1231                                 config {
1232                                         pins = "gpio114", "gpio115";
1233                                         drive-strength = <0x02>;
1234                                         bias-disable;
1235                                 };
1236                         };
1237
1238                         qup_i2c2_default: qup-i2c2-default {
1239                                 mux {
1240                                         pins = "gpio126", "gpio127";
1241                                         function = "qup2";
1242                                 };
1243
1244                                 config {
1245                                         pins = "gpio126", "gpio127";
1246                                         drive-strength = <0x02>;
1247                                         bias-disable;
1248                                 };
1249                         };
1250
1251                         qup_i2c3_default: qup-i2c3-default {
1252                                 mux {
1253                                         pins = "gpio144", "gpio145";
1254                                         function = "qup3";
1255                                 };
1256
1257                                 config {
1258                                         pins = "gpio144", "gpio145";
1259                                         drive-strength = <0x02>;
1260                                         bias-disable;
1261                                 };
1262                         };
1263
1264                         qup_i2c4_default: qup-i2c4-default {
1265                                 mux {
1266                                         pins = "gpio51", "gpio52";
1267                                         function = "qup4";
1268                                 };
1269
1270                                 config {
1271                                         pins = "gpio51", "gpio52";
1272                                         drive-strength = <0x02>;
1273                                         bias-disable;
1274                                 };
1275                         };
1276
1277                         qup_i2c5_default: qup-i2c5-default {
1278                                 mux {
1279                                         pins = "gpio121", "gpio122";
1280                                         function = "qup5";
1281                                 };
1282
1283                                 config {
1284                                         pins = "gpio121", "gpio122";
1285                                         drive-strength = <0x02>;
1286                                         bias-disable;
1287                                 };
1288                         };
1289
1290                         qup_i2c6_default: qup-i2c6-default {
1291                                 mux {
1292                                         pins = "gpio6", "gpio7";
1293                                         function = "qup6";
1294                                 };
1295
1296                                 config {
1297                                         pins = "gpio6", "gpio7";
1298                                         drive-strength = <0x02>;
1299                                         bias-disable;
1300                                 };
1301                         };
1302
1303                         qup_i2c7_default: qup-i2c7-default {
1304                                 mux {
1305                                         pins = "gpio98", "gpio99";
1306                                         function = "qup7";
1307                                 };
1308
1309                                 config {
1310                                         pins = "gpio98", "gpio99";
1311                                         drive-strength = <0x02>;
1312                                         bias-disable;
1313                                 };
1314                         };
1315
1316                         qup_i2c8_default: qup-i2c8-default {
1317                                 mux {
1318                                         pins = "gpio88", "gpio89";
1319                                         function = "qup8";
1320                                 };
1321
1322                                 config {
1323                                         pins = "gpio88", "gpio89";
1324                                         drive-strength = <0x02>;
1325                                         bias-disable;
1326                                 };
1327                         };
1328
1329                         qup_i2c9_default: qup-i2c9-default {
1330                                 mux {
1331                                         pins = "gpio39", "gpio40";
1332                                         function = "qup9";
1333                                 };
1334
1335                                 config {
1336                                         pins = "gpio39", "gpio40";
1337                                         drive-strength = <0x02>;
1338                                         bias-disable;
1339                                 };
1340                         };
1341
1342                         qup_i2c10_default: qup-i2c10-default {
1343                                 mux {
1344                                         pins = "gpio9", "gpio10";
1345                                         function = "qup10";
1346                                 };
1347
1348                                 config {
1349                                         pins = "gpio9", "gpio10";
1350                                         drive-strength = <0x02>;
1351                                         bias-disable;
1352                                 };
1353                         };
1354
1355                         qup_i2c11_default: qup-i2c11-default {
1356                                 mux {
1357                                         pins = "gpio94", "gpio95";
1358                                         function = "qup11";
1359                                 };
1360
1361                                 config {
1362                                         pins = "gpio94", "gpio95";
1363                                         drive-strength = <0x02>;
1364                                         bias-disable;
1365                                 };
1366                         };
1367
1368                         qup_i2c12_default: qup-i2c12-default {
1369                                 mux {
1370                                         pins = "gpio83", "gpio84";
1371                                         function = "qup12";
1372                                 };
1373
1374                                 config {
1375                                         pins = "gpio83", "gpio84";
1376                                         drive-strength = <0x02>;
1377                                         bias-disable;
1378                                 };
1379                         };
1380
1381                         qup_i2c13_default: qup-i2c13-default {
1382                                 mux {
1383                                         pins = "gpio43", "gpio44";
1384                                         function = "qup13";
1385                                 };
1386
1387                                 config {
1388                                         pins = "gpio43", "gpio44";
1389                                         drive-strength = <0x02>;
1390                                         bias-disable;
1391                                 };
1392                         };
1393
1394                         qup_i2c14_default: qup-i2c14-default {
1395                                 mux {
1396                                         pins = "gpio47", "gpio48";
1397                                         function = "qup14";
1398                                 };
1399
1400                                 config {
1401                                         pins = "gpio47", "gpio48";
1402                                         drive-strength = <0x02>;
1403                                         bias-disable;
1404                                 };
1405                         };
1406
1407                         qup_i2c15_default: qup-i2c15-default {
1408                                 mux {
1409                                         pins = "gpio27", "gpio28";
1410                                         function = "qup15";
1411                                 };
1412
1413                                 config {
1414                                         pins = "gpio27", "gpio28";
1415                                         drive-strength = <0x02>;
1416                                         bias-disable;
1417                                 };
1418                         };
1419
1420                         qup_i2c16_default: qup-i2c16-default {
1421                                 mux {
1422                                         pins = "gpio86", "gpio85";
1423                                         function = "qup16";
1424                                 };
1425
1426                                 config {
1427                                         pins = "gpio86", "gpio85";
1428                                         drive-strength = <0x02>;
1429                                         bias-disable;
1430                                 };
1431                         };
1432
1433                         qup_i2c17_default: qup-i2c17-default {
1434                                 mux {
1435                                         pins = "gpio55", "gpio56";
1436                                         function = "qup17";
1437                                 };
1438
1439                                 config {
1440                                         pins = "gpio55", "gpio56";
1441                                         drive-strength = <0x02>;
1442                                         bias-disable;
1443                                 };
1444                         };
1445
1446                         qup_i2c18_default: qup-i2c18-default {
1447                                 mux {
1448                                         pins = "gpio23", "gpio24";
1449                                         function = "qup18";
1450                                 };
1451
1452                                 config {
1453                                         pins = "gpio23", "gpio24";
1454                                         drive-strength = <0x02>;
1455                                         bias-disable;
1456                                 };
1457                         };
1458
1459                         qup_i2c19_default: qup-i2c19-default {
1460                                 mux {
1461                                         pins = "gpio57", "gpio58";
1462                                         function = "qup19";
1463                                 };
1464
1465                                 config {
1466                                         pins = "gpio57", "gpio58";
1467                                         drive-strength = <0x02>;
1468                                         bias-disable;
1469                                 };
1470                         };
1471                 };
1472
1473                 remoteproc_mpss: remoteproc@4080000 {
1474                         compatible = "qcom,sm8150-mpss-pas";
1475                         reg = <0x0 0x04080000 0x0 0x4040>;
1476
1477                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1478                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1479                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1480                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1481                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1482                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1483                         interrupt-names = "wdog", "fatal", "ready", "handover",
1484                                           "stop-ack", "shutdown-ack";
1485
1486                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1487                         clock-names = "xo";
1488
1489                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1490                                         <&rpmhpd 7>,
1491                                         <&rpmhpd 0>;
1492                         power-domain-names = "load_state", "cx", "mss";
1493
1494                         memory-region = <&mpss_mem>;
1495
1496                         qcom,smem-states = <&modem_smp2p_out 0>;
1497                         qcom,smem-state-names = "stop";
1498
1499                         glink-edge {
1500                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1501                                 label = "modem";
1502                                 qcom,remote-pid = <1>;
1503                                 mboxes = <&apss_shared 12>;
1504                         };
1505                 };
1506
1507                 stm@6002000 {
1508                         compatible = "arm,coresight-stm", "arm,primecell";
1509                         reg = <0 0x06002000 0 0x1000>,
1510                               <0 0x16280000 0 0x180000>;
1511                         reg-names = "stm-base", "stm-stimulus-base";
1512
1513                         clocks = <&aoss_qmp>;
1514                         clock-names = "apb_pclk";
1515
1516                         out-ports {
1517                                 port {
1518                                         stm_out: endpoint {
1519                                                 remote-endpoint = <&funnel0_in7>;
1520                                         };
1521                                 };
1522                         };
1523                 };
1524
1525                 funnel@6041000 {
1526                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1527                         reg = <0 0x06041000 0 0x1000>;
1528
1529                         clocks = <&aoss_qmp>;
1530                         clock-names = "apb_pclk";
1531
1532                         out-ports {
1533                                 port {
1534                                         funnel0_out: endpoint {
1535                                                 remote-endpoint = <&merge_funnel_in0>;
1536                                         };
1537                                 };
1538                         };
1539
1540                         in-ports {
1541                                 #address-cells = <1>;
1542                                 #size-cells = <0>;
1543
1544                                 port@7 {
1545                                         reg = <7>;
1546                                         funnel0_in7: endpoint {
1547                                                 remote-endpoint = <&stm_out>;
1548                                         };
1549                                 };
1550                         };
1551                 };
1552
1553                 funnel@6042000 {
1554                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1555                         reg = <0 0x06042000 0 0x1000>;
1556
1557                         clocks = <&aoss_qmp>;
1558                         clock-names = "apb_pclk";
1559
1560                         out-ports {
1561                                 port {
1562                                         funnel1_out: endpoint {
1563                                                 remote-endpoint = <&merge_funnel_in1>;
1564                                         };
1565                                 };
1566                         };
1567
1568                         in-ports {
1569                                 #address-cells = <1>;
1570                                 #size-cells = <0>;
1571
1572                                 port@4 {
1573                                         reg = <4>;
1574                                         funnel1_in4: endpoint {
1575                                                 remote-endpoint = <&swao_replicator_out>;
1576                                         };
1577                                 };
1578                         };
1579                 };
1580
1581                 funnel@6043000 {
1582                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1583                         reg = <0 0x06043000 0 0x1000>;
1584
1585                         clocks = <&aoss_qmp>;
1586                         clock-names = "apb_pclk";
1587
1588                         out-ports {
1589                                 port {
1590                                         funnel2_out: endpoint {
1591                                                 remote-endpoint = <&merge_funnel_in2>;
1592                                         };
1593                                 };
1594                         };
1595
1596                         in-ports {
1597                                 #address-cells = <1>;
1598                                 #size-cells = <0>;
1599
1600                                 port@2 {
1601                                         reg = <2>;
1602                                         funnel2_in2: endpoint {
1603                                                 remote-endpoint = <&apss_merge_funnel_out>;
1604                                         };
1605                                 };
1606                         };
1607                 };
1608
1609                 funnel@6045000 {
1610                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1611                         reg = <0 0x06045000 0 0x1000>;
1612
1613                         clocks = <&aoss_qmp>;
1614                         clock-names = "apb_pclk";
1615
1616                         out-ports {
1617                                 port {
1618                                         merge_funnel_out: endpoint {
1619                                                 remote-endpoint = <&etf_in>;
1620                                         };
1621                                 };
1622                         };
1623
1624                         in-ports {
1625                                 #address-cells = <1>;
1626                                 #size-cells = <0>;
1627
1628                                 port@0 {
1629                                         reg = <0>;
1630                                         merge_funnel_in0: endpoint {
1631                                                 remote-endpoint = <&funnel0_out>;
1632                                         };
1633                                 };
1634
1635                                 port@1 {
1636                                         reg = <1>;
1637                                         merge_funnel_in1: endpoint {
1638                                                 remote-endpoint = <&funnel1_out>;
1639                                         };
1640                                 };
1641
1642                                 port@2 {
1643                                         reg = <2>;
1644                                         merge_funnel_in2: endpoint {
1645                                                 remote-endpoint = <&funnel2_out>;
1646                                         };
1647                                 };
1648                         };
1649                 };
1650
1651                 replicator@6046000 {
1652                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1653                         reg = <0 0x06046000 0 0x1000>;
1654
1655                         clocks = <&aoss_qmp>;
1656                         clock-names = "apb_pclk";
1657
1658                         out-ports {
1659                                 #address-cells = <1>;
1660                                 #size-cells = <0>;
1661
1662                                 port@0 {
1663                                         reg = <0>;
1664                                         replicator_out0: endpoint {
1665                                                 remote-endpoint = <&etr_in>;
1666                                         };
1667                                 };
1668
1669                                 port@1 {
1670                                         reg = <1>;
1671                                         replicator_out1: endpoint {
1672                                                 remote-endpoint = <&replicator1_in>;
1673                                         };
1674                                 };
1675                         };
1676
1677                         in-ports {
1678                                 port {
1679                                         replicator_in0: endpoint {
1680                                                 remote-endpoint = <&etf_out>;
1681                                         };
1682                                 };
1683                         };
1684                 };
1685
1686                 etf@6047000 {
1687                         compatible = "arm,coresight-tmc", "arm,primecell";
1688                         reg = <0 0x06047000 0 0x1000>;
1689
1690                         clocks = <&aoss_qmp>;
1691                         clock-names = "apb_pclk";
1692
1693                         out-ports {
1694                                 port {
1695                                         etf_out: endpoint {
1696                                                 remote-endpoint = <&replicator_in0>;
1697                                         };
1698                                 };
1699                         };
1700
1701                         in-ports {
1702                                 port {
1703                                         etf_in: endpoint {
1704                                                 remote-endpoint = <&merge_funnel_out>;
1705                                         };
1706                                 };
1707                         };
1708                 };
1709
1710                 etr@6048000 {
1711                         compatible = "arm,coresight-tmc", "arm,primecell";
1712                         reg = <0 0x06048000 0 0x1000>;
1713                         iommus = <&apps_smmu 0x05e0 0x0>;
1714
1715                         clocks = <&aoss_qmp>;
1716                         clock-names = "apb_pclk";
1717                         arm,scatter-gather;
1718
1719                         in-ports {
1720                                 port {
1721                                         etr_in: endpoint {
1722                                                 remote-endpoint = <&replicator_out0>;
1723                                         };
1724                                 };
1725                         };
1726                 };
1727
1728                 replicator@604a000 {
1729                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1730                         reg = <0 0x0604a000 0 0x1000>;
1731
1732                         clocks = <&aoss_qmp>;
1733                         clock-names = "apb_pclk";
1734
1735                         out-ports {
1736                                 #address-cells = <1>;
1737                                 #size-cells = <0>;
1738
1739                                 port@1 {
1740                                         reg = <1>;
1741                                         replicator1_out: endpoint {
1742                                                 remote-endpoint = <&swao_funnel_in>;
1743                                         };
1744                                 };
1745                         };
1746
1747                         in-ports {
1748                                 #address-cells = <1>;
1749                                 #size-cells = <0>;
1750
1751                                 port@1 {
1752                                         reg = <1>;
1753                                         replicator1_in: endpoint {
1754                                                 remote-endpoint = <&replicator_out1>;
1755                                         };
1756                                 };
1757                         };
1758                 };
1759
1760                 funnel@6b08000 {
1761                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1762                         reg = <0 0x06b08000 0 0x1000>;
1763
1764                         clocks = <&aoss_qmp>;
1765                         clock-names = "apb_pclk";
1766
1767                         out-ports {
1768                                 port {
1769                                         swao_funnel_out: endpoint {
1770                                                 remote-endpoint = <&swao_etf_in>;
1771                                         };
1772                                 };
1773                         };
1774
1775                         in-ports {
1776                                 #address-cells = <1>;
1777                                 #size-cells = <0>;
1778
1779                                 port@6 {
1780                                         reg = <6>;
1781                                         swao_funnel_in: endpoint {
1782                                                 remote-endpoint = <&replicator1_out>;
1783                                         };
1784                                 };
1785                         };
1786                 };
1787
1788                 etf@6b09000 {
1789                         compatible = "arm,coresight-tmc", "arm,primecell";
1790                         reg = <0 0x06b09000 0 0x1000>;
1791
1792                         clocks = <&aoss_qmp>;
1793                         clock-names = "apb_pclk";
1794
1795                         out-ports {
1796                                 port {
1797                                         swao_etf_out: endpoint {
1798                                                 remote-endpoint = <&swao_replicator_in>;
1799                                         };
1800                                 };
1801                         };
1802
1803                         in-ports {
1804                                 port {
1805                                         swao_etf_in: endpoint {
1806                                                 remote-endpoint = <&swao_funnel_out>;
1807                                         };
1808                                 };
1809                         };
1810                 };
1811
1812                 replicator@6b0a000 {
1813                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1814                         reg = <0 0x06b0a000 0 0x1000>;
1815
1816                         clocks = <&aoss_qmp>;
1817                         clock-names = "apb_pclk";
1818                         qcom,replicator-loses-context;
1819
1820                         out-ports {
1821                                 port {
1822                                         swao_replicator_out: endpoint {
1823                                                 remote-endpoint = <&funnel1_in4>;
1824                                         };
1825                                 };
1826                         };
1827
1828                         in-ports {
1829                                 port {
1830                                         swao_replicator_in: endpoint {
1831                                                 remote-endpoint = <&swao_etf_out>;
1832                                         };
1833                                 };
1834                         };
1835                 };
1836
1837                 etm@7040000 {
1838                         compatible = "arm,coresight-etm4x", "arm,primecell";
1839                         reg = <0 0x07040000 0 0x1000>;
1840
1841                         cpu = <&CPU0>;
1842
1843                         clocks = <&aoss_qmp>;
1844                         clock-names = "apb_pclk";
1845                         arm,coresight-loses-context-with-cpu;
1846                         qcom,skip-power-up;
1847
1848                         out-ports {
1849                                 port {
1850                                         etm0_out: endpoint {
1851                                                 remote-endpoint = <&apss_funnel_in0>;
1852                                         };
1853                                 };
1854                         };
1855                 };
1856
1857                 etm@7140000 {
1858                         compatible = "arm,coresight-etm4x", "arm,primecell";
1859                         reg = <0 0x07140000 0 0x1000>;
1860
1861                         cpu = <&CPU1>;
1862
1863                         clocks = <&aoss_qmp>;
1864                         clock-names = "apb_pclk";
1865                         arm,coresight-loses-context-with-cpu;
1866                         qcom,skip-power-up;
1867
1868                         out-ports {
1869                                 port {
1870                                         etm1_out: endpoint {
1871                                                 remote-endpoint = <&apss_funnel_in1>;
1872                                         };
1873                                 };
1874                         };
1875                 };
1876
1877                 etm@7240000 {
1878                         compatible = "arm,coresight-etm4x", "arm,primecell";
1879                         reg = <0 0x07240000 0 0x1000>;
1880
1881                         cpu = <&CPU2>;
1882
1883                         clocks = <&aoss_qmp>;
1884                         clock-names = "apb_pclk";
1885                         arm,coresight-loses-context-with-cpu;
1886                         qcom,skip-power-up;
1887
1888                         out-ports {
1889                                 port {
1890                                         etm2_out: endpoint {
1891                                                 remote-endpoint = <&apss_funnel_in2>;
1892                                         };
1893                                 };
1894                         };
1895                 };
1896
1897                 etm@7340000 {
1898                         compatible = "arm,coresight-etm4x", "arm,primecell";
1899                         reg = <0 0x07340000 0 0x1000>;
1900
1901                         cpu = <&CPU3>;
1902
1903                         clocks = <&aoss_qmp>;
1904                         clock-names = "apb_pclk";
1905                         arm,coresight-loses-context-with-cpu;
1906                         qcom,skip-power-up;
1907
1908                         out-ports {
1909                                 port {
1910                                         etm3_out: endpoint {
1911                                                 remote-endpoint = <&apss_funnel_in3>;
1912                                         };
1913                                 };
1914                         };
1915                 };
1916
1917                 etm@7440000 {
1918                         compatible = "arm,coresight-etm4x", "arm,primecell";
1919                         reg = <0 0x07440000 0 0x1000>;
1920
1921                         cpu = <&CPU4>;
1922
1923                         clocks = <&aoss_qmp>;
1924                         clock-names = "apb_pclk";
1925                         arm,coresight-loses-context-with-cpu;
1926                         qcom,skip-power-up;
1927
1928                         out-ports {
1929                                 port {
1930                                         etm4_out: endpoint {
1931                                                 remote-endpoint = <&apss_funnel_in4>;
1932                                         };
1933                                 };
1934                         };
1935                 };
1936
1937                 etm@7540000 {
1938                         compatible = "arm,coresight-etm4x", "arm,primecell";
1939                         reg = <0 0x07540000 0 0x1000>;
1940
1941                         cpu = <&CPU5>;
1942
1943                         clocks = <&aoss_qmp>;
1944                         clock-names = "apb_pclk";
1945                         arm,coresight-loses-context-with-cpu;
1946                         qcom,skip-power-up;
1947
1948                         out-ports {
1949                                 port {
1950                                         etm5_out: endpoint {
1951                                                 remote-endpoint = <&apss_funnel_in5>;
1952                                         };
1953                                 };
1954                         };
1955                 };
1956
1957                 etm@7640000 {
1958                         compatible = "arm,coresight-etm4x", "arm,primecell";
1959                         reg = <0 0x07640000 0 0x1000>;
1960
1961                         cpu = <&CPU6>;
1962
1963                         clocks = <&aoss_qmp>;
1964                         clock-names = "apb_pclk";
1965                         arm,coresight-loses-context-with-cpu;
1966                         qcom,skip-power-up;
1967
1968                         out-ports {
1969                                 port {
1970                                         etm6_out: endpoint {
1971                                                 remote-endpoint = <&apss_funnel_in6>;
1972                                         };
1973                                 };
1974                         };
1975                 };
1976
1977                 etm@7740000 {
1978                         compatible = "arm,coresight-etm4x", "arm,primecell";
1979                         reg = <0 0x07740000 0 0x1000>;
1980
1981                         cpu = <&CPU7>;
1982
1983                         clocks = <&aoss_qmp>;
1984                         clock-names = "apb_pclk";
1985                         arm,coresight-loses-context-with-cpu;
1986                         qcom,skip-power-up;
1987
1988                         out-ports {
1989                                 port {
1990                                         etm7_out: endpoint {
1991                                                 remote-endpoint = <&apss_funnel_in7>;
1992                                         };
1993                                 };
1994                         };
1995                 };
1996
1997                 funnel@7800000 { /* APSS Funnel */
1998                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1999                         reg = <0 0x07800000 0 0x1000>;
2000
2001                         clocks = <&aoss_qmp>;
2002                         clock-names = "apb_pclk";
2003
2004                         out-ports {
2005                                 port {
2006                                         apss_funnel_out: endpoint {
2007                                                 remote-endpoint = <&apss_merge_funnel_in>;
2008                                         };
2009                                 };
2010                         };
2011
2012                         in-ports {
2013                                 #address-cells = <1>;
2014                                 #size-cells = <0>;
2015
2016                                 port@0 {
2017                                         reg = <0>;
2018                                         apss_funnel_in0: endpoint {
2019                                                 remote-endpoint = <&etm0_out>;
2020                                         };
2021                                 };
2022
2023                                 port@1 {
2024                                         reg = <1>;
2025                                         apss_funnel_in1: endpoint {
2026                                                 remote-endpoint = <&etm1_out>;
2027                                         };
2028                                 };
2029
2030                                 port@2 {
2031                                         reg = <2>;
2032                                         apss_funnel_in2: endpoint {
2033                                                 remote-endpoint = <&etm2_out>;
2034                                         };
2035                                 };
2036
2037                                 port@3 {
2038                                         reg = <3>;
2039                                         apss_funnel_in3: endpoint {
2040                                                 remote-endpoint = <&etm3_out>;
2041                                         };
2042                                 };
2043
2044                                 port@4 {
2045                                         reg = <4>;
2046                                         apss_funnel_in4: endpoint {
2047                                                 remote-endpoint = <&etm4_out>;
2048                                         };
2049                                 };
2050
2051                                 port@5 {
2052                                         reg = <5>;
2053                                         apss_funnel_in5: endpoint {
2054                                                 remote-endpoint = <&etm5_out>;
2055                                         };
2056                                 };
2057
2058                                 port@6 {
2059                                         reg = <6>;
2060                                         apss_funnel_in6: endpoint {
2061                                                 remote-endpoint = <&etm6_out>;
2062                                         };
2063                                 };
2064
2065                                 port@7 {
2066                                         reg = <7>;
2067                                         apss_funnel_in7: endpoint {
2068                                                 remote-endpoint = <&etm7_out>;
2069                                         };
2070                                 };
2071                         };
2072                 };
2073
2074                 funnel@7810000 {
2075                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2076                         reg = <0 0x07810000 0 0x1000>;
2077
2078                         clocks = <&aoss_qmp>;
2079                         clock-names = "apb_pclk";
2080
2081                         out-ports {
2082                                 port {
2083                                         apss_merge_funnel_out: endpoint {
2084                                                 remote-endpoint = <&funnel2_in2>;
2085                                         };
2086                                 };
2087                         };
2088
2089                         in-ports {
2090                                 port {
2091                                         apss_merge_funnel_in: endpoint {
2092                                                 remote-endpoint = <&apss_funnel_out>;
2093                                         };
2094                                 };
2095                         };
2096                 };
2097
2098                 remoteproc_cdsp: remoteproc@8300000 {
2099                         compatible = "qcom,sm8150-cdsp-pas";
2100                         reg = <0x0 0x08300000 0x0 0x4040>;
2101
2102                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2103                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2104                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2105                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2106                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2107                         interrupt-names = "wdog", "fatal", "ready",
2108                                           "handover", "stop-ack";
2109
2110                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2111                         clock-names = "xo";
2112
2113                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2114                                         <&rpmhpd 7>;
2115                         power-domain-names = "load_state", "cx";
2116
2117                         memory-region = <&cdsp_mem>;
2118
2119                         qcom,smem-states = <&cdsp_smp2p_out 0>;
2120                         qcom,smem-state-names = "stop";
2121
2122                         status = "disabled";
2123
2124                         glink-edge {
2125                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2126                                 label = "cdsp";
2127                                 qcom,remote-pid = <5>;
2128                                 mboxes = <&apss_shared 4>;
2129                         };
2130                 };
2131
2132                 usb_1_hsphy: phy@88e2000 {
2133                         compatible = "qcom,sm8150-usb-hs-phy",
2134                                      "qcom,usb-snps-hs-7nm-phy";
2135                         reg = <0 0x088e2000 0 0x400>;
2136                         status = "disabled";
2137                         #phy-cells = <0>;
2138
2139                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2140                         clock-names = "ref";
2141
2142                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2143                 };
2144
2145                 usb_2_hsphy: phy@88e3000 {
2146                         compatible = "qcom,sm8150-usb-hs-phy",
2147                                      "qcom,usb-snps-hs-7nm-phy";
2148                         reg = <0 0x088e3000 0 0x400>;
2149                         status = "disabled";
2150                         #phy-cells = <0>;
2151
2152                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2153                         clock-names = "ref";
2154
2155                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2156                 };
2157
2158                 usb_1_qmpphy: phy@88e9000 {
2159                         compatible = "qcom,sm8150-qmp-usb3-phy";
2160                         reg = <0 0x088e9000 0 0x18c>,
2161                               <0 0x088e8000 0 0x10>;
2162                         reg-names = "reg-base", "dp_com";
2163                         status = "disabled";
2164                         #address-cells = <2>;
2165                         #size-cells = <2>;
2166                         ranges;
2167
2168                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2169                                  <&rpmhcc RPMH_CXO_CLK>,
2170                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2171                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2172                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2173
2174                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2175                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2176                         reset-names = "phy", "common";
2177
2178                         usb_1_ssphy: lanes@88e9200 {
2179                                 reg = <0 0x088e9200 0 0x200>,
2180                                       <0 0x088e9400 0 0x200>,
2181                                       <0 0x088e9c00 0 0x218>,
2182                                       <0 0x088e9600 0 0x200>,
2183                                       <0 0x088e9800 0 0x200>,
2184                                       <0 0x088e9a00 0 0x100>;
2185                                 #clock-cells = <0>;
2186                                 #phy-cells = <0>;
2187                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2188                                 clock-names = "pipe0";
2189                                 clock-output-names = "usb3_phy_pipe_clk_src";
2190                         };
2191                 };
2192
2193                 dc_noc: interconnect@9160000 {
2194                         compatible = "qcom,sm8150-dc-noc";
2195                         reg = <0 0x09160000 0 0x3200>;
2196                         #interconnect-cells = <1>;
2197                         qcom,bcm-voters = <&apps_bcm_voter>;
2198                 };
2199
2200                 gem_noc: interconnect@9680000 {
2201                         compatible = "qcom,sm8150-gem-noc";
2202                         reg = <0 0x09680000 0 0x3e200>;
2203                         #interconnect-cells = <1>;
2204                         qcom,bcm-voters = <&apps_bcm_voter>;
2205                 };
2206
2207                 usb_2_qmpphy: phy@88eb000 {
2208                         compatible = "qcom,sm8150-qmp-usb3-uni-phy";
2209                         reg = <0 0x088eb000 0 0x200>;
2210                         status = "disabled";
2211                         #address-cells = <2>;
2212                         #size-cells = <2>;
2213                         ranges;
2214
2215                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2216                                  <&rpmhcc RPMH_CXO_CLK>,
2217                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2218                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2219                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2220
2221                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2222                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2223                         reset-names = "phy", "common";
2224
2225                         usb_2_ssphy: lane@88eb200 {
2226                                 reg = <0 0x088eb200 0 0x200>,
2227                                       <0 0x088eb400 0 0x200>,
2228                                       <0 0x088eb800 0 0x800>,
2229                                       <0 0x088eb600 0 0x200>;
2230                                 #clock-cells = <0>;
2231                                 #phy-cells = <0>;
2232                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2233                                 clock-names = "pipe0";
2234                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2235                         };
2236                 };
2237
2238                 usb_1: usb@a6f8800 {
2239                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
2240                         reg = <0 0x0a6f8800 0 0x400>;
2241                         status = "disabled";
2242                         #address-cells = <2>;
2243                         #size-cells = <2>;
2244                         ranges;
2245                         dma-ranges;
2246
2247                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2248                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2249                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2250                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2251                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2252                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2253                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2254                                       "sleep", "xo";
2255
2256                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2257                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2258                         assigned-clock-rates = <19200000>, <200000000>;
2259
2260                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2261                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2262                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2263                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2264                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2265                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2266
2267                         power-domains = <&gcc USB30_PRIM_GDSC>;
2268
2269                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2270
2271                         usb_1_dwc3: dwc3@a600000 {
2272                                 compatible = "snps,dwc3";
2273                                 reg = <0 0x0a600000 0 0xcd00>;
2274                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2275                                 iommus = <&apps_smmu 0x140 0>;
2276                                 snps,dis_u2_susphy_quirk;
2277                                 snps,dis_enblslpm_quirk;
2278                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2279                                 phy-names = "usb2-phy", "usb3-phy";
2280                         };
2281                 };
2282
2283                 usb_2: usb@a8f8800 {
2284                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
2285                         reg = <0 0x0a8f8800 0 0x400>;
2286                         status = "disabled";
2287                         #address-cells = <2>;
2288                         #size-cells = <2>;
2289                         ranges;
2290                         dma-ranges;
2291
2292                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2293                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2294                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2295                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2296                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2297                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2298                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2299                                       "sleep", "xo";
2300
2301                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2302                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2303                         assigned-clock-rates = <19200000>, <200000000>;
2304
2305                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2306                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2307                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
2308                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
2309                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2310                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2311
2312                         power-domains = <&gcc USB30_SEC_GDSC>;
2313
2314                         resets = <&gcc GCC_USB30_SEC_BCR>;
2315
2316                         usb_2_dwc3: dwc3@a800000 {
2317                                 compatible = "snps,dwc3";
2318                                 reg = <0 0x0a800000 0 0xcd00>;
2319                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2320                                 iommus = <&apps_smmu 0x160 0>;
2321                                 snps,dis_u2_susphy_quirk;
2322                                 snps,dis_enblslpm_quirk;
2323                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2324                                 phy-names = "usb2-phy", "usb3-phy";
2325                         };
2326                 };
2327
2328                 camnoc_virt: interconnect@ac00000 {
2329                         compatible = "qcom,sm8150-camnoc-virt";
2330                         reg = <0 0x0ac00000 0 0x1000>;
2331                         #interconnect-cells = <1>;
2332                         qcom,bcm-voters = <&apps_bcm_voter>;
2333                 };
2334
2335                 aoss_qmp: power-controller@c300000 {
2336                         compatible = "qcom,sm8150-aoss-qmp";
2337                         reg = <0x0 0x0c300000 0x0 0x100000>;
2338                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
2339                         mboxes = <&apss_shared 0>;
2340
2341                         #clock-cells = <0>;
2342                         #power-domain-cells = <1>;
2343                 };
2344
2345                 tsens0: thermal-sensor@c263000 {
2346                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
2347                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2348                               <0 0x0c222000 0 0x1ff>; /* SROT */
2349                         #qcom,sensors = <16>;
2350                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2351                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2352                         interrupt-names = "uplow", "critical";
2353                         #thermal-sensor-cells = <1>;
2354                 };
2355
2356                 tsens1: thermal-sensor@c265000 {
2357                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
2358                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2359                               <0 0x0c223000 0 0x1ff>; /* SROT */
2360                         #qcom,sensors = <8>;
2361                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2362                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2363                         interrupt-names = "uplow", "critical";
2364                         #thermal-sensor-cells = <1>;
2365                 };
2366
2367                 spmi_bus: spmi@c440000 {
2368                         compatible = "qcom,spmi-pmic-arb";
2369                         reg = <0x0 0x0c440000 0x0 0x0001100>,
2370                               <0x0 0x0c600000 0x0 0x2000000>,
2371                               <0x0 0x0e600000 0x0 0x0100000>,
2372                               <0x0 0x0e700000 0x0 0x00a0000>,
2373                               <0x0 0x0c40a000 0x0 0x0026000>;
2374                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2375                         interrupt-names = "periph_irq";
2376                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
2377                         qcom,ee = <0>;
2378                         qcom,channel = <0>;
2379                         #address-cells = <2>;
2380                         #size-cells = <0>;
2381                         interrupt-controller;
2382                         #interrupt-cells = <4>;
2383                         cell-index = <0>;
2384                 };
2385
2386                 apps_smmu: iommu@15000000 {
2387                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2388                         reg = <0 0x15000000 0 0x100000>;
2389                         #iommu-cells = <2>;
2390                         #global-interrupts = <1>;
2391                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2392                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2393                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2394                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2395                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2396                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2397                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2398                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2399                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2400                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2401                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2402                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2403                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2404                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2405                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2406                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2407                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2408                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2409                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2410                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2411                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2412                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2413                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2414                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2415                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2416                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2417                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2418                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2419                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2420                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2421                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2422                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2423                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2424                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2425                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2426                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2427                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2428                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2429                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2430                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2431                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2432                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2433                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2434                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2435                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2436                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2437                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2438                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2439                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2440                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2441                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2442                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2443                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2444                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2445                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2446                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2447                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2448                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2449                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2450                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2451                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2452                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2453                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2454                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2455                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2456                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2457                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2458                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2459                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2460                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2461                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2462                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2463                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2464                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2465                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2466                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2467                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2468                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2469                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2470                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2471                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
2472                 };
2473
2474                 remoteproc_adsp: remoteproc@17300000 {
2475                         compatible = "qcom,sm8150-adsp-pas";
2476                         reg = <0x0 0x17300000 0x0 0x4040>;
2477
2478                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2479                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2480                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2481                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2482                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2483                         interrupt-names = "wdog", "fatal", "ready",
2484                                           "handover", "stop-ack";
2485
2486                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2487                         clock-names = "xo";
2488
2489                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2490                                         <&rpmhpd 7>;
2491                         power-domain-names = "load_state", "cx";
2492
2493                         memory-region = <&adsp_mem>;
2494
2495                         qcom,smem-states = <&adsp_smp2p_out 0>;
2496                         qcom,smem-state-names = "stop";
2497
2498                         status = "disabled";
2499
2500                         glink-edge {
2501                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2502                                 label = "lpass";
2503                                 qcom,remote-pid = <2>;
2504                                 mboxes = <&apss_shared 8>;
2505                         };
2506                 };
2507
2508                 intc: interrupt-controller@17a00000 {
2509                         compatible = "arm,gic-v3";
2510                         interrupt-controller;
2511                         #interrupt-cells = <3>;
2512                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2513                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2514                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2515                 };
2516
2517                 apss_shared: mailbox@17c00000 {
2518                         compatible = "qcom,sm8150-apss-shared";
2519                         reg = <0x0 0x17c00000 0x0 0x1000>;
2520                         #mbox-cells = <1>;
2521                 };
2522
2523                 watchdog@17c10000 {
2524                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
2525                         reg = <0 0x17c10000 0 0x1000>;
2526                         clocks = <&sleep_clk>;
2527                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2528                 };
2529
2530                 timer@17c20000 {
2531                         #address-cells = <2>;
2532                         #size-cells = <2>;
2533                         ranges;
2534                         compatible = "arm,armv7-timer-mem";
2535                         reg = <0x0 0x17c20000 0x0 0x1000>;
2536                         clock-frequency = <19200000>;
2537
2538                         frame@17c21000{
2539                                 frame-number = <0>;
2540                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2541                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2542                                 reg = <0x0 0x17c21000 0x0 0x1000>,
2543                                       <0x0 0x17c22000 0x0 0x1000>;
2544                         };
2545
2546                         frame@17c23000 {
2547                                 frame-number = <1>;
2548                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2549                                 reg = <0x0 0x17c23000 0x0 0x1000>;
2550                                 status = "disabled";
2551                         };
2552
2553                         frame@17c25000 {
2554                                 frame-number = <2>;
2555                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2556                                 reg = <0x0 0x17c25000 0x0 0x1000>;
2557                                 status = "disabled";
2558                         };
2559
2560                         frame@17c27000 {
2561                                 frame-number = <3>;
2562                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2563                                 reg = <0x0 0x17c26000 0x0 0x1000>;
2564                                 status = "disabled";
2565                         };
2566
2567                         frame@17c29000 {
2568                                 frame-number = <4>;
2569                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2570                                 reg = <0x0 0x17c29000 0x0 0x1000>;
2571                                 status = "disabled";
2572                         };
2573
2574                         frame@17c2b000 {
2575                                 frame-number = <5>;
2576                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2577                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
2578                                 status = "disabled";
2579                         };
2580
2581                         frame@17c2d000 {
2582                                 frame-number = <6>;
2583                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2584                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
2585                                 status = "disabled";
2586                         };
2587                 };
2588
2589                 apps_rsc: rsc@18200000 {
2590                         label = "apps_rsc";
2591                         compatible = "qcom,rpmh-rsc";
2592                         reg = <0x0 0x18200000 0x0 0x10000>,
2593                               <0x0 0x18210000 0x0 0x10000>,
2594                               <0x0 0x18220000 0x0 0x10000>;
2595                         reg-names = "drv-0", "drv-1", "drv-2";
2596                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2597                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2598                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2599                         qcom,tcs-offset = <0xd00>;
2600                         qcom,drv-id = <2>;
2601                         qcom,tcs-config = <ACTIVE_TCS  2>,
2602                                           <SLEEP_TCS   1>,
2603                                           <WAKE_TCS    1>,
2604                                           <CONTROL_TCS 0>;
2605
2606                         rpmhcc: clock-controller {
2607                                 compatible = "qcom,sm8150-rpmh-clk";
2608                                 #clock-cells = <1>;
2609                                 clock-names = "xo";
2610                                 clocks = <&xo_board>;
2611                         };
2612
2613                         rpmhpd: power-controller {
2614                                 compatible = "qcom,sm8150-rpmhpd";
2615                                 #power-domain-cells = <1>;
2616                                 operating-points-v2 = <&rpmhpd_opp_table>;
2617
2618                                 rpmhpd_opp_table: opp-table {
2619                                         compatible = "operating-points-v2";
2620
2621                                         rpmhpd_opp_ret: opp1 {
2622                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2623                                         };
2624
2625                                         rpmhpd_opp_min_svs: opp2 {
2626                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2627                                         };
2628
2629                                         rpmhpd_opp_low_svs: opp3 {
2630                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2631                                         };
2632
2633                                         rpmhpd_opp_svs: opp4 {
2634                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2635                                         };
2636
2637                                         rpmhpd_opp_svs_l1: opp5 {
2638                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2639                                         };
2640
2641                                         rpmhpd_opp_svs_l2: opp6 {
2642                                                 opp-level = <224>;
2643                                         };
2644
2645                                         rpmhpd_opp_nom: opp7 {
2646                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2647                                         };
2648
2649                                         rpmhpd_opp_nom_l1: opp8 {
2650                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2651                                         };
2652
2653                                         rpmhpd_opp_nom_l2: opp9 {
2654                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2655                                         };
2656
2657                                         rpmhpd_opp_turbo: opp10 {
2658                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2659                                         };
2660
2661                                         rpmhpd_opp_turbo_l1: opp11 {
2662                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2663                                         };
2664                                 };
2665                         };
2666
2667                         apps_bcm_voter: bcm_voter {
2668                                 compatible = "qcom,bcm-voter";
2669                         };
2670                 };
2671
2672                 osm_l3: interconnect@18321000 {
2673                         compatible = "qcom,sm8150-osm-l3";
2674                         reg = <0 0x18321000 0 0x1400>;
2675
2676                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2677                         clock-names = "xo", "alternate";
2678
2679                         #interconnect-cells = <1>;
2680                 };
2681
2682                 cpufreq_hw: cpufreq@18323000 {
2683                         compatible = "qcom,cpufreq-hw";
2684                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
2685                               <0 0x18327800 0 0x1400>;
2686                         reg-names = "freq-domain0", "freq-domain1",
2687                                     "freq-domain2";
2688
2689                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2690                         clock-names = "xo", "alternate";
2691
2692                         #freq-domain-cells = <1>;
2693                 };
2694
2695                 wifi: wifi@18800000 {
2696                         compatible = "qcom,wcn3990-wifi";
2697                         reg = <0 0x18800000 0 0x800000>;
2698                         reg-names = "membase";
2699                         memory-region = <&wlan_mem>;
2700                         clock-names = "cxo_ref_clk_pin", "qdss";
2701                         clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
2702                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2703                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2704                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2705                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2706                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2707                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2708                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2709                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2710                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2711                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2712                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2713                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2714                         iommus = <&apps_smmu 0x0640 0x1>;
2715                         status = "disabled";
2716                 };
2717         };
2718
2719         timer {
2720                 compatible = "arm,armv8-timer";
2721                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
2722                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
2723                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
2724                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
2725         };
2726
2727         thermal-zones {
2728                 cpu0-thermal {
2729                         polling-delay-passive = <250>;
2730                         polling-delay = <1000>;
2731
2732                         thermal-sensors = <&tsens0 1>;
2733
2734                         trips {
2735                                 cpu0_alert0: trip-point0 {
2736                                         temperature = <90000>;
2737                                         hysteresis = <2000>;
2738                                         type = "passive";
2739                                 };
2740
2741                                 cpu0_alert1: trip-point1 {
2742                                         temperature = <95000>;
2743                                         hysteresis = <2000>;
2744                                         type = "passive";
2745                                 };
2746
2747                                 cpu0_crit: cpu_crit {
2748                                         temperature = <110000>;
2749                                         hysteresis = <1000>;
2750                                         type = "critical";
2751                                 };
2752                         };
2753
2754                         cooling-maps {
2755                                 map0 {
2756                                         trip = <&cpu0_alert0>;
2757                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2758                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2759                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2760                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2761                                 };
2762                                 map1 {
2763                                         trip = <&cpu0_alert1>;
2764                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2765                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2766                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2767                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2768                                 };
2769                         };
2770                 };
2771
2772                 cpu1-thermal {
2773                         polling-delay-passive = <250>;
2774                         polling-delay = <1000>;
2775
2776                         thermal-sensors = <&tsens0 2>;
2777
2778                         trips {
2779                                 cpu1_alert0: trip-point0 {
2780                                         temperature = <90000>;
2781                                         hysteresis = <2000>;
2782                                         type = "passive";
2783                                 };
2784
2785                                 cpu1_alert1: trip-point1 {
2786                                         temperature = <95000>;
2787                                         hysteresis = <2000>;
2788                                         type = "passive";
2789                                 };
2790
2791                                 cpu1_crit: cpu_crit {
2792                                         temperature = <110000>;
2793                                         hysteresis = <1000>;
2794                                         type = "critical";
2795                                 };
2796                         };
2797
2798                         cooling-maps {
2799                                 map0 {
2800                                         trip = <&cpu1_alert0>;
2801                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2802                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2803                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2804                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2805                                 };
2806                                 map1 {
2807                                         trip = <&cpu1_alert1>;
2808                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2809                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2810                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2811                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2812                                 };
2813                         };
2814                 };
2815
2816                 cpu2-thermal {
2817                         polling-delay-passive = <250>;
2818                         polling-delay = <1000>;
2819
2820                         thermal-sensors = <&tsens0 3>;
2821
2822                         trips {
2823                                 cpu2_alert0: trip-point0 {
2824                                         temperature = <90000>;
2825                                         hysteresis = <2000>;
2826                                         type = "passive";
2827                                 };
2828
2829                                 cpu2_alert1: trip-point1 {
2830                                         temperature = <95000>;
2831                                         hysteresis = <2000>;
2832                                         type = "passive";
2833                                 };
2834
2835                                 cpu2_crit: cpu_crit {
2836                                         temperature = <110000>;
2837                                         hysteresis = <1000>;
2838                                         type = "critical";
2839                                 };
2840                         };
2841
2842                         cooling-maps {
2843                                 map0 {
2844                                         trip = <&cpu2_alert0>;
2845                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2846                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2847                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2848                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2849                                 };
2850                                 map1 {
2851                                         trip = <&cpu2_alert1>;
2852                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2853                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2854                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2855                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2856                                 };
2857                         };
2858                 };
2859
2860                 cpu3-thermal {
2861                         polling-delay-passive = <250>;
2862                         polling-delay = <1000>;
2863
2864                         thermal-sensors = <&tsens0 4>;
2865
2866                         trips {
2867                                 cpu3_alert0: trip-point0 {
2868                                         temperature = <90000>;
2869                                         hysteresis = <2000>;
2870                                         type = "passive";
2871                                 };
2872
2873                                 cpu3_alert1: trip-point1 {
2874                                         temperature = <95000>;
2875                                         hysteresis = <2000>;
2876                                         type = "passive";
2877                                 };
2878
2879                                 cpu3_crit: cpu_crit {
2880                                         temperature = <110000>;
2881                                         hysteresis = <1000>;
2882                                         type = "critical";
2883                                 };
2884                         };
2885
2886                         cooling-maps {
2887                                 map0 {
2888                                         trip = <&cpu3_alert0>;
2889                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2890                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2891                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2892                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2893                                 };
2894                                 map1 {
2895                                         trip = <&cpu3_alert1>;
2896                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2897                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2898                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2899                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2900                                 };
2901                         };
2902                 };
2903
2904                 cpu4-top-thermal {
2905                         polling-delay-passive = <250>;
2906                         polling-delay = <1000>;
2907
2908                         thermal-sensors = <&tsens0 7>;
2909
2910                         trips {
2911                                 cpu4_top_alert0: trip-point0 {
2912                                         temperature = <90000>;
2913                                         hysteresis = <2000>;
2914                                         type = "passive";
2915                                 };
2916
2917                                 cpu4_top_alert1: trip-point1 {
2918                                         temperature = <95000>;
2919                                         hysteresis = <2000>;
2920                                         type = "passive";
2921                                 };
2922
2923                                 cpu4_top_crit: cpu_crit {
2924                                         temperature = <110000>;
2925                                         hysteresis = <1000>;
2926                                         type = "critical";
2927                                 };
2928                         };
2929
2930                         cooling-maps {
2931                                 map0 {
2932                                         trip = <&cpu4_top_alert0>;
2933                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2934                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2935                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2936                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2937                                 };
2938                                 map1 {
2939                                         trip = <&cpu4_top_alert1>;
2940                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2941                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2942                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2943                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2944                                 };
2945                         };
2946                 };
2947
2948                 cpu5-top-thermal {
2949                         polling-delay-passive = <250>;
2950                         polling-delay = <1000>;
2951
2952                         thermal-sensors = <&tsens0 8>;
2953
2954                         trips {
2955                                 cpu5_top_alert0: trip-point0 {
2956                                         temperature = <90000>;
2957                                         hysteresis = <2000>;
2958                                         type = "passive";
2959                                 };
2960
2961                                 cpu5_top_alert1: trip-point1 {
2962                                         temperature = <95000>;
2963                                         hysteresis = <2000>;
2964                                         type = "passive";
2965                                 };
2966
2967                                 cpu5_top_crit: cpu_crit {
2968                                         temperature = <110000>;
2969                                         hysteresis = <1000>;
2970                                         type = "critical";
2971                                 };
2972                         };
2973
2974                         cooling-maps {
2975                                 map0 {
2976                                         trip = <&cpu5_top_alert0>;
2977                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2978                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2979                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2980                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2981                                 };
2982                                 map1 {
2983                                         trip = <&cpu5_top_alert1>;
2984                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2985                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2986                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2987                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2988                                 };
2989                         };
2990                 };
2991
2992                 cpu6-top-thermal {
2993                         polling-delay-passive = <250>;
2994                         polling-delay = <1000>;
2995
2996                         thermal-sensors = <&tsens0 9>;
2997
2998                         trips {
2999                                 cpu6_top_alert0: trip-point0 {
3000                                         temperature = <90000>;
3001                                         hysteresis = <2000>;
3002                                         type = "passive";
3003                                 };
3004
3005                                 cpu6_top_alert1: trip-point1 {
3006                                         temperature = <95000>;
3007                                         hysteresis = <2000>;
3008                                         type = "passive";
3009                                 };
3010
3011                                 cpu6_top_crit: cpu_crit {
3012                                         temperature = <110000>;
3013                                         hysteresis = <1000>;
3014                                         type = "critical";
3015                                 };
3016                         };
3017
3018                         cooling-maps {
3019                                 map0 {
3020                                         trip = <&cpu6_top_alert0>;
3021                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3022                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3023                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3024                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3025                                 };
3026                                 map1 {
3027                                         trip = <&cpu6_top_alert1>;
3028                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3029                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3030                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3031                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3032                                 };
3033                         };
3034                 };
3035
3036                 cpu7-top-thermal {
3037                         polling-delay-passive = <250>;
3038                         polling-delay = <1000>;
3039
3040                         thermal-sensors = <&tsens0 10>;
3041
3042                         trips {
3043                                 cpu7_top_alert0: trip-point0 {
3044                                         temperature = <90000>;
3045                                         hysteresis = <2000>;
3046                                         type = "passive";
3047                                 };
3048
3049                                 cpu7_top_alert1: trip-point1 {
3050                                         temperature = <95000>;
3051                                         hysteresis = <2000>;
3052                                         type = "passive";
3053                                 };
3054
3055                                 cpu7_top_crit: cpu_crit {
3056                                         temperature = <110000>;
3057                                         hysteresis = <1000>;
3058                                         type = "critical";
3059                                 };
3060                         };
3061
3062                         cooling-maps {
3063                                 map0 {
3064                                         trip = <&cpu7_top_alert0>;
3065                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3066                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3067                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3068                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3069                                 };
3070                                 map1 {
3071                                         trip = <&cpu7_top_alert1>;
3072                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3073                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3074                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3075                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3076                                 };
3077                         };
3078                 };
3079
3080                 cpu4-bottom-thermal {
3081                         polling-delay-passive = <250>;
3082                         polling-delay = <1000>;
3083
3084                         thermal-sensors = <&tsens0 11>;
3085
3086                         trips {
3087                                 cpu4_bottom_alert0: trip-point0 {
3088                                         temperature = <90000>;
3089                                         hysteresis = <2000>;
3090                                         type = "passive";
3091                                 };
3092
3093                                 cpu4_bottom_alert1: trip-point1 {
3094                                         temperature = <95000>;
3095                                         hysteresis = <2000>;
3096                                         type = "passive";
3097                                 };
3098
3099                                 cpu4_bottom_crit: cpu_crit {
3100                                         temperature = <110000>;
3101                                         hysteresis = <1000>;
3102                                         type = "critical";
3103                                 };
3104                         };
3105
3106                         cooling-maps {
3107                                 map0 {
3108                                         trip = <&cpu4_bottom_alert0>;
3109                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3110                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3111                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3112                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3113                                 };
3114                                 map1 {
3115                                         trip = <&cpu4_bottom_alert1>;
3116                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3117                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3118                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3119                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3120                                 };
3121                         };
3122                 };
3123
3124                 cpu5-bottom-thermal {
3125                         polling-delay-passive = <250>;
3126                         polling-delay = <1000>;
3127
3128                         thermal-sensors = <&tsens0 12>;
3129
3130                         trips {
3131                                 cpu5_bottom_alert0: trip-point0 {
3132                                         temperature = <90000>;
3133                                         hysteresis = <2000>;
3134                                         type = "passive";
3135                                 };
3136
3137                                 cpu5_bottom_alert1: trip-point1 {
3138                                         temperature = <95000>;
3139                                         hysteresis = <2000>;
3140                                         type = "passive";
3141                                 };
3142
3143                                 cpu5_bottom_crit: cpu_crit {
3144                                         temperature = <110000>;
3145                                         hysteresis = <1000>;
3146                                         type = "critical";
3147                                 };
3148                         };
3149
3150                         cooling-maps {
3151                                 map0 {
3152                                         trip = <&cpu5_bottom_alert0>;
3153                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3154                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3155                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3156                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3157                                 };
3158                                 map1 {
3159                                         trip = <&cpu5_bottom_alert1>;
3160                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3161                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3162                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3163                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3164                                 };
3165                         };
3166                 };
3167
3168                 cpu6-bottom-thermal {
3169                         polling-delay-passive = <250>;
3170                         polling-delay = <1000>;
3171
3172                         thermal-sensors = <&tsens0 13>;
3173
3174                         trips {
3175                                 cpu6_bottom_alert0: trip-point0 {
3176                                         temperature = <90000>;
3177                                         hysteresis = <2000>;
3178                                         type = "passive";
3179                                 };
3180
3181                                 cpu6_bottom_alert1: trip-point1 {
3182                                         temperature = <95000>;
3183                                         hysteresis = <2000>;
3184                                         type = "passive";
3185                                 };
3186
3187                                 cpu6_bottom_crit: cpu_crit {
3188                                         temperature = <110000>;
3189                                         hysteresis = <1000>;
3190                                         type = "critical";
3191                                 };
3192                         };
3193
3194                         cooling-maps {
3195                                 map0 {
3196                                         trip = <&cpu6_bottom_alert0>;
3197                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3198                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3199                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3200                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3201                                 };
3202                                 map1 {
3203                                         trip = <&cpu6_bottom_alert1>;
3204                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3205                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3206                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3207                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3208                                 };
3209                         };
3210                 };
3211
3212                 cpu7-bottom-thermal {
3213                         polling-delay-passive = <250>;
3214                         polling-delay = <1000>;
3215
3216                         thermal-sensors = <&tsens0 14>;
3217
3218                         trips {
3219                                 cpu7_bottom_alert0: trip-point0 {
3220                                         temperature = <90000>;
3221                                         hysteresis = <2000>;
3222                                         type = "passive";
3223                                 };
3224
3225                                 cpu7_bottom_alert1: trip-point1 {
3226                                         temperature = <95000>;
3227                                         hysteresis = <2000>;
3228                                         type = "passive";
3229                                 };
3230
3231                                 cpu7_bottom_crit: cpu_crit {
3232                                         temperature = <110000>;
3233                                         hysteresis = <1000>;
3234                                         type = "critical";
3235                                 };
3236                         };
3237
3238                         cooling-maps {
3239                                 map0 {
3240                                         trip = <&cpu7_bottom_alert0>;
3241                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3242                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3243                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3244                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3245                                 };
3246                                 map1 {
3247                                         trip = <&cpu7_bottom_alert1>;
3248                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3249                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3250                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3251                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3252                                 };
3253                         };
3254                 };
3255
3256                 aoss0-thermal {
3257                         polling-delay-passive = <250>;
3258                         polling-delay = <1000>;
3259
3260                         thermal-sensors = <&tsens0 0>;
3261
3262                         trips {
3263                                 aoss0_alert0: trip-point0 {
3264                                         temperature = <90000>;
3265                                         hysteresis = <2000>;
3266                                         type = "hot";
3267                                 };
3268                         };
3269                 };
3270
3271                 cluster0-thermal {
3272                         polling-delay-passive = <250>;
3273                         polling-delay = <1000>;
3274
3275                         thermal-sensors = <&tsens0 5>;
3276
3277                         trips {
3278                                 cluster0_alert0: trip-point0 {
3279                                         temperature = <90000>;
3280                                         hysteresis = <2000>;
3281                                         type = "hot";
3282                                 };
3283                                 cluster0_crit: cluster0_crit {
3284                                         temperature = <110000>;
3285                                         hysteresis = <2000>;
3286                                         type = "critical";
3287                                 };
3288                         };
3289                 };
3290
3291                 cluster1-thermal {
3292                         polling-delay-passive = <250>;
3293                         polling-delay = <1000>;
3294
3295                         thermal-sensors = <&tsens0 6>;
3296
3297                         trips {
3298                                 cluster1_alert0: trip-point0 {
3299                                         temperature = <90000>;
3300                                         hysteresis = <2000>;
3301                                         type = "hot";
3302                                 };
3303                                 cluster1_crit: cluster1_crit {
3304                                         temperature = <110000>;
3305                                         hysteresis = <2000>;
3306                                         type = "critical";
3307                                 };
3308                         };
3309                 };
3310
3311                 gpu-thermal-top {
3312                         polling-delay-passive = <250>;
3313                         polling-delay = <1000>;
3314
3315                         thermal-sensors = <&tsens0 15>;
3316
3317                         trips {
3318                                 gpu1_alert0: trip-point0 {
3319                                         temperature = <90000>;
3320                                         hysteresis = <2000>;
3321                                         type = "hot";
3322                                 };
3323                         };
3324                 };
3325
3326                 aoss1-thermal {
3327                         polling-delay-passive = <250>;
3328                         polling-delay = <1000>;
3329
3330                         thermal-sensors = <&tsens1 0>;
3331
3332                         trips {
3333                                 aoss1_alert0: trip-point0 {
3334                                         temperature = <90000>;
3335                                         hysteresis = <2000>;
3336                                         type = "hot";
3337                                 };
3338                         };
3339                 };
3340
3341                 wlan-thermal {
3342                         polling-delay-passive = <250>;
3343                         polling-delay = <1000>;
3344
3345                         thermal-sensors = <&tsens1 1>;
3346
3347                         trips {
3348                                 wlan_alert0: trip-point0 {
3349                                         temperature = <90000>;
3350                                         hysteresis = <2000>;
3351                                         type = "hot";
3352                                 };
3353                         };
3354                 };
3355
3356                 video-thermal {
3357                         polling-delay-passive = <250>;
3358                         polling-delay = <1000>;
3359
3360                         thermal-sensors = <&tsens1 2>;
3361
3362                         trips {
3363                                 video_alert0: trip-point0 {
3364                                         temperature = <90000>;
3365                                         hysteresis = <2000>;
3366                                         type = "hot";
3367                                 };
3368                         };
3369                 };
3370
3371                 mem-thermal {
3372                         polling-delay-passive = <250>;
3373                         polling-delay = <1000>;
3374
3375                         thermal-sensors = <&tsens1 3>;
3376
3377                         trips {
3378                                 mem_alert0: trip-point0 {
3379                                         temperature = <90000>;
3380                                         hysteresis = <2000>;
3381                                         type = "hot";
3382                                 };
3383                         };
3384                 };
3385
3386                 q6-hvx-thermal {
3387                         polling-delay-passive = <250>;
3388                         polling-delay = <1000>;
3389
3390                         thermal-sensors = <&tsens1 4>;
3391
3392                         trips {
3393                                 q6_hvx_alert0: trip-point0 {
3394                                         temperature = <90000>;
3395                                         hysteresis = <2000>;
3396                                         type = "hot";
3397                                 };
3398                         };
3399                 };
3400
3401                 camera-thermal {
3402                         polling-delay-passive = <250>;
3403                         polling-delay = <1000>;
3404
3405                         thermal-sensors = <&tsens1 5>;
3406
3407                         trips {
3408                                 camera_alert0: trip-point0 {
3409                                         temperature = <90000>;
3410                                         hysteresis = <2000>;
3411                                         type = "hot";
3412                                 };
3413                         };
3414                 };
3415
3416                 compute-thermal {
3417                         polling-delay-passive = <250>;
3418                         polling-delay = <1000>;
3419
3420                         thermal-sensors = <&tsens1 6>;
3421
3422                         trips {
3423                                 compute_alert0: trip-point0 {
3424                                         temperature = <90000>;
3425                                         hysteresis = <2000>;
3426                                         type = "hot";
3427                                 };
3428                         };
3429                 };
3430
3431                 modem-thermal {
3432                         polling-delay-passive = <250>;
3433                         polling-delay = <1000>;
3434
3435                         thermal-sensors = <&tsens1 7>;
3436
3437                         trips {
3438                                 modem_alert0: trip-point0 {
3439                                         temperature = <90000>;
3440                                         hysteresis = <2000>;
3441                                         type = "hot";
3442                                 };
3443                         };
3444                 };
3445
3446                 npu-thermal {
3447                         polling-delay-passive = <250>;
3448                         polling-delay = <1000>;
3449
3450                         thermal-sensors = <&tsens1 8>;
3451
3452                         trips {
3453                                 npu_alert0: trip-point0 {
3454                                         temperature = <90000>;
3455                                         hysteresis = <2000>;
3456                                         type = "hot";
3457                                 };
3458                         };
3459                 };
3460
3461                 modem-vec-thermal {
3462                         polling-delay-passive = <250>;
3463                         polling-delay = <1000>;
3464
3465                         thermal-sensors = <&tsens1 9>;
3466
3467                         trips {
3468                                 modem_vec_alert0: trip-point0 {
3469                                         temperature = <90000>;
3470                                         hysteresis = <2000>;
3471                                         type = "hot";
3472                                 };
3473                         };
3474                 };
3475
3476                 modem-scl-thermal {
3477                         polling-delay-passive = <250>;
3478                         polling-delay = <1000>;
3479
3480                         thermal-sensors = <&tsens1 10>;
3481
3482                         trips {
3483                                 modem_scl_alert0: trip-point0 {
3484                                         temperature = <90000>;
3485                                         hysteresis = <2000>;
3486                                         type = "hot";
3487                                 };
3488                         };
3489                 };
3490
3491                 gpu-thermal-bottom {
3492                         polling-delay-passive = <250>;
3493                         polling-delay = <1000>;
3494
3495                         thermal-sensors = <&tsens1 11>;
3496
3497                         trips {
3498                                 gpu2_alert0: trip-point0 {
3499                                         temperature = <90000>;
3500                                         hysteresis = <2000>;
3501                                         type = "hot";
3502                                 };
3503                         };
3504                 };
3505         };
3506 };