1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-aoss-qmp.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8150.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
29 compatible = "fixed-clock";
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
49 compatible = "qcom,kryo485";
51 enable-method = "psci";
52 capacity-dmips-mhz = <488>;
53 dynamic-power-coefficient = <232>;
54 next-level-cache = <&L2_0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
56 operating-points-v2 = <&cpu0_opp_table>;
57 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
59 power-domains = <&CPU_PD0>;
60 power-domain-names = "psci";
64 next-level-cache = <&L3_0>;
73 compatible = "qcom,kryo485";
75 enable-method = "psci";
76 capacity-dmips-mhz = <488>;
77 dynamic-power-coefficient = <232>;
78 next-level-cache = <&L2_100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 operating-points-v2 = <&cpu0_opp_table>;
81 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
83 power-domains = <&CPU_PD1>;
84 power-domain-names = "psci";
88 next-level-cache = <&L3_0>;
95 compatible = "qcom,kryo485";
97 enable-method = "psci";
98 capacity-dmips-mhz = <488>;
99 dynamic-power-coefficient = <232>;
100 next-level-cache = <&L2_200>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 operating-points-v2 = <&cpu0_opp_table>;
103 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
105 power-domains = <&CPU_PD2>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
109 compatible = "cache";
110 next-level-cache = <&L3_0>;
116 compatible = "qcom,kryo485";
118 enable-method = "psci";
119 capacity-dmips-mhz = <488>;
120 dynamic-power-coefficient = <232>;
121 next-level-cache = <&L2_300>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 operating-points-v2 = <&cpu0_opp_table>;
124 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
125 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
126 power-domains = <&CPU_PD3>;
127 power-domain-names = "psci";
128 #cooling-cells = <2>;
130 compatible = "cache";
131 next-level-cache = <&L3_0>;
137 compatible = "qcom,kryo485";
139 enable-method = "psci";
140 capacity-dmips-mhz = <1024>;
141 dynamic-power-coefficient = <369>;
142 next-level-cache = <&L2_400>;
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 operating-points-v2 = <&cpu4_opp_table>;
145 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
146 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 power-domains = <&CPU_PD4>;
148 power-domain-names = "psci";
149 #cooling-cells = <2>;
151 compatible = "cache";
152 next-level-cache = <&L3_0>;
158 compatible = "qcom,kryo485";
160 enable-method = "psci";
161 capacity-dmips-mhz = <1024>;
162 dynamic-power-coefficient = <369>;
163 next-level-cache = <&L2_500>;
164 qcom,freq-domain = <&cpufreq_hw 1>;
165 operating-points-v2 = <&cpu4_opp_table>;
166 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
167 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
168 power-domains = <&CPU_PD5>;
169 power-domain-names = "psci";
170 #cooling-cells = <2>;
172 compatible = "cache";
173 next-level-cache = <&L3_0>;
179 compatible = "qcom,kryo485";
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L2_600>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_PD6>;
190 power-domain-names = "psci";
191 #cooling-cells = <2>;
193 compatible = "cache";
194 next-level-cache = <&L3_0>;
200 compatible = "qcom,kryo485";
202 enable-method = "psci";
203 capacity-dmips-mhz = <1024>;
204 dynamic-power-coefficient = <421>;
205 next-level-cache = <&L2_700>;
206 qcom,freq-domain = <&cpufreq_hw 2>;
207 operating-points-v2 = <&cpu7_opp_table>;
208 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
210 power-domains = <&CPU_PD7>;
211 power-domain-names = "psci";
212 #cooling-cells = <2>;
214 compatible = "cache";
215 next-level-cache = <&L3_0>;
256 entry-method = "psci";
258 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
259 compatible = "arm,idle-state";
260 idle-state-name = "little-rail-power-collapse";
261 arm,psci-suspend-param = <0x40000004>;
262 entry-latency-us = <355>;
263 exit-latency-us = <909>;
264 min-residency-us = <3934>;
268 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
269 compatible = "arm,idle-state";
270 idle-state-name = "big-rail-power-collapse";
271 arm,psci-suspend-param = <0x40000004>;
272 entry-latency-us = <241>;
273 exit-latency-us = <1461>;
274 min-residency-us = <4488>;
280 CLUSTER_SLEEP_0: cluster-sleep-0 {
281 compatible = "domain-idle-state";
282 idle-state-name = "cluster-power-collapse";
283 arm,psci-suspend-param = <0x4100c244>;
284 entry-latency-us = <3263>;
285 exit-latency-us = <6562>;
286 min-residency-us = <9987>;
292 cpu0_opp_table: cpu0_opp_table {
293 compatible = "operating-points-v2";
296 cpu0_opp1: opp-300000000 {
297 opp-hz = /bits/ 64 <300000000>;
298 opp-peak-kBps = <800000 9600000>;
301 cpu0_opp2: opp-403200000 {
302 opp-hz = /bits/ 64 <403200000>;
303 opp-peak-kBps = <800000 9600000>;
306 cpu0_opp3: opp-499200000 {
307 opp-hz = /bits/ 64 <499200000>;
308 opp-peak-kBps = <800000 12902400>;
311 cpu0_opp4: opp-576000000 {
312 opp-hz = /bits/ 64 <576000000>;
313 opp-peak-kBps = <800000 12902400>;
316 cpu0_opp5: opp-672000000 {
317 opp-hz = /bits/ 64 <672000000>;
318 opp-peak-kBps = <800000 15974400>;
321 cpu0_opp6: opp-768000000 {
322 opp-hz = /bits/ 64 <768000000>;
323 opp-peak-kBps = <1804000 19660800>;
326 cpu0_opp7: opp-844800000 {
327 opp-hz = /bits/ 64 <844800000>;
328 opp-peak-kBps = <1804000 19660800>;
331 cpu0_opp8: opp-940800000 {
332 opp-hz = /bits/ 64 <940800000>;
333 opp-peak-kBps = <1804000 22732800>;
336 cpu0_opp9: opp-1036800000 {
337 opp-hz = /bits/ 64 <1036800000>;
338 opp-peak-kBps = <1804000 22732800>;
341 cpu0_opp10: opp-1113600000 {
342 opp-hz = /bits/ 64 <1113600000>;
343 opp-peak-kBps = <2188000 25804800>;
346 cpu0_opp11: opp-1209600000 {
347 opp-hz = /bits/ 64 <1209600000>;
348 opp-peak-kBps = <2188000 31948800>;
351 cpu0_opp12: opp-1305600000 {
352 opp-hz = /bits/ 64 <1305600000>;
353 opp-peak-kBps = <3072000 31948800>;
356 cpu0_opp13: opp-1382400000 {
357 opp-hz = /bits/ 64 <1382400000>;
358 opp-peak-kBps = <3072000 31948800>;
361 cpu0_opp14: opp-1478400000 {
362 opp-hz = /bits/ 64 <1478400000>;
363 opp-peak-kBps = <3072000 31948800>;
366 cpu0_opp15: opp-1555200000 {
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-peak-kBps = <3072000 40550400>;
371 cpu0_opp16: opp-1632000000 {
372 opp-hz = /bits/ 64 <1632000000>;
373 opp-peak-kBps = <3072000 40550400>;
376 cpu0_opp17: opp-1708800000 {
377 opp-hz = /bits/ 64 <1708800000>;
378 opp-peak-kBps = <3072000 43008000>;
381 cpu0_opp18: opp-1785600000 {
382 opp-hz = /bits/ 64 <1785600000>;
383 opp-peak-kBps = <3072000 43008000>;
387 cpu4_opp_table: cpu4_opp_table {
388 compatible = "operating-points-v2";
391 cpu4_opp1: opp-710400000 {
392 opp-hz = /bits/ 64 <710400000>;
393 opp-peak-kBps = <1804000 15974400>;
396 cpu4_opp2: opp-825600000 {
397 opp-hz = /bits/ 64 <825600000>;
398 opp-peak-kBps = <2188000 19660800>;
401 cpu4_opp3: opp-940800000 {
402 opp-hz = /bits/ 64 <940800000>;
403 opp-peak-kBps = <2188000 22732800>;
406 cpu4_opp4: opp-1056000000 {
407 opp-hz = /bits/ 64 <1056000000>;
408 opp-peak-kBps = <3072000 25804800>;
411 cpu4_opp5: opp-1171200000 {
412 opp-hz = /bits/ 64 <1171200000>;
413 opp-peak-kBps = <3072000 31948800>;
416 cpu4_opp6: opp-1286400000 {
417 opp-hz = /bits/ 64 <1286400000>;
418 opp-peak-kBps = <4068000 31948800>;
421 cpu4_opp7: opp-1401600000 {
422 opp-hz = /bits/ 64 <1401600000>;
423 opp-peak-kBps = <4068000 31948800>;
426 cpu4_opp8: opp-1497600000 {
427 opp-hz = /bits/ 64 <1497600000>;
428 opp-peak-kBps = <4068000 40550400>;
431 cpu4_opp9: opp-1612800000 {
432 opp-hz = /bits/ 64 <1612800000>;
433 opp-peak-kBps = <4068000 40550400>;
436 cpu4_opp10: opp-1708800000 {
437 opp-hz = /bits/ 64 <1708800000>;
438 opp-peak-kBps = <4068000 43008000>;
441 cpu4_opp11: opp-1804800000 {
442 opp-hz = /bits/ 64 <1804800000>;
443 opp-peak-kBps = <6220000 43008000>;
446 cpu4_opp12: opp-1920000000 {
447 opp-hz = /bits/ 64 <1920000000>;
448 opp-peak-kBps = <6220000 49152000>;
451 cpu4_opp13: opp-2016000000 {
452 opp-hz = /bits/ 64 <2016000000>;
453 opp-peak-kBps = <7216000 49152000>;
456 cpu4_opp14: opp-2131200000 {
457 opp-hz = /bits/ 64 <2131200000>;
458 opp-peak-kBps = <8368000 49152000>;
461 cpu4_opp15: opp-2227200000 {
462 opp-hz = /bits/ 64 <2227200000>;
463 opp-peak-kBps = <8368000 51609600>;
466 cpu4_opp16: opp-2323200000 {
467 opp-hz = /bits/ 64 <2323200000>;
468 opp-peak-kBps = <8368000 51609600>;
471 cpu4_opp17: opp-2419200000 {
472 opp-hz = /bits/ 64 <2419200000>;
473 opp-peak-kBps = <8368000 51609600>;
477 cpu7_opp_table: cpu7_opp_table {
478 compatible = "operating-points-v2";
481 cpu7_opp1: opp-825600000 {
482 opp-hz = /bits/ 64 <825600000>;
483 opp-peak-kBps = <2188000 19660800>;
486 cpu7_opp2: opp-940800000 {
487 opp-hz = /bits/ 64 <940800000>;
488 opp-peak-kBps = <2188000 22732800>;
491 cpu7_opp3: opp-1056000000 {
492 opp-hz = /bits/ 64 <1056000000>;
493 opp-peak-kBps = <3072000 25804800>;
496 cpu7_opp4: opp-1171200000 {
497 opp-hz = /bits/ 64 <1171200000>;
498 opp-peak-kBps = <3072000 31948800>;
501 cpu7_opp5: opp-1286400000 {
502 opp-hz = /bits/ 64 <1286400000>;
503 opp-peak-kBps = <4068000 31948800>;
506 cpu7_opp6: opp-1401600000 {
507 opp-hz = /bits/ 64 <1401600000>;
508 opp-peak-kBps = <4068000 31948800>;
511 cpu7_opp7: opp-1497600000 {
512 opp-hz = /bits/ 64 <1497600000>;
513 opp-peak-kBps = <4068000 40550400>;
516 cpu7_opp8: opp-1612800000 {
517 opp-hz = /bits/ 64 <1612800000>;
518 opp-peak-kBps = <4068000 40550400>;
521 cpu7_opp9: opp-1708800000 {
522 opp-hz = /bits/ 64 <1708800000>;
523 opp-peak-kBps = <4068000 43008000>;
526 cpu7_opp10: opp-1804800000 {
527 opp-hz = /bits/ 64 <1804800000>;
528 opp-peak-kBps = <6220000 43008000>;
531 cpu7_opp11: opp-1920000000 {
532 opp-hz = /bits/ 64 <1920000000>;
533 opp-peak-kBps = <6220000 49152000>;
536 cpu7_opp12: opp-2016000000 {
537 opp-hz = /bits/ 64 <2016000000>;
538 opp-peak-kBps = <7216000 49152000>;
541 cpu7_opp13: opp-2131200000 {
542 opp-hz = /bits/ 64 <2131200000>;
543 opp-peak-kBps = <8368000 49152000>;
546 cpu7_opp14: opp-2227200000 {
547 opp-hz = /bits/ 64 <2227200000>;
548 opp-peak-kBps = <8368000 51609600>;
551 cpu7_opp15: opp-2323200000 {
552 opp-hz = /bits/ 64 <2323200000>;
553 opp-peak-kBps = <8368000 51609600>;
556 cpu7_opp16: opp-2419200000 {
557 opp-hz = /bits/ 64 <2419200000>;
558 opp-peak-kBps = <8368000 51609600>;
561 cpu7_opp17: opp-2534400000 {
562 opp-hz = /bits/ 64 <2534400000>;
563 opp-peak-kBps = <8368000 51609600>;
566 cpu7_opp18: opp-2649600000 {
567 opp-hz = /bits/ 64 <2649600000>;
568 opp-peak-kBps = <8368000 51609600>;
571 cpu7_opp19: opp-2745600000 {
572 opp-hz = /bits/ 64 <2745600000>;
573 opp-peak-kBps = <8368000 51609600>;
576 cpu7_opp20: opp-2841600000 {
577 opp-hz = /bits/ 64 <2841600000>;
578 opp-peak-kBps = <8368000 51609600>;
584 compatible = "qcom,scm-sm8150", "qcom,scm";
590 compatible = "qcom,tcsr-mutex";
591 syscon = <&tcsr_mutex_regs 0 0x1000>;
596 device_type = "memory";
597 /* We expect the bootloader to fill in the size */
598 reg = <0x0 0x80000000 0x0 0x0>;
602 compatible = "arm,armv8-pmuv3";
603 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
607 compatible = "arm,psci-1.0";
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 #power-domain-cells = <0>;
636 power-domains = <&CLUSTER_PD>;
637 domain-idle-states = <&BIG_CPU_SLEEP_0>;
641 #power-domain-cells = <0>;
642 power-domains = <&CLUSTER_PD>;
643 domain-idle-states = <&BIG_CPU_SLEEP_0>;
647 #power-domain-cells = <0>;
648 power-domains = <&CLUSTER_PD>;
649 domain-idle-states = <&BIG_CPU_SLEEP_0>;
653 #power-domain-cells = <0>;
654 power-domains = <&CLUSTER_PD>;
655 domain-idle-states = <&BIG_CPU_SLEEP_0>;
658 CLUSTER_PD: cpu-cluster0 {
659 #power-domain-cells = <0>;
660 domain-idle-states = <&CLUSTER_SLEEP_0>;
665 #address-cells = <2>;
669 hyp_mem: memory@85700000 {
670 reg = <0x0 0x85700000 0x0 0x600000>;
674 xbl_mem: memory@85d00000 {
675 reg = <0x0 0x85d00000 0x0 0x140000>;
679 aop_mem: memory@85f00000 {
680 reg = <0x0 0x85f00000 0x0 0x20000>;
684 aop_cmd_db: memory@85f20000 {
685 compatible = "qcom,cmd-db";
686 reg = <0x0 0x85f20000 0x0 0x20000>;
690 smem_mem: memory@86000000 {
691 reg = <0x0 0x86000000 0x0 0x200000>;
695 tz_mem: memory@86200000 {
696 reg = <0x0 0x86200000 0x0 0x3900000>;
700 rmtfs_mem: memory@89b00000 {
701 compatible = "qcom,rmtfs-mem";
702 reg = <0x0 0x89b00000 0x0 0x200000>;
705 qcom,client-id = <1>;
709 camera_mem: memory@8b700000 {
710 reg = <0x0 0x8b700000 0x0 0x500000>;
714 wlan_mem: memory@8bc00000 {
715 reg = <0x0 0x8bc00000 0x0 0x180000>;
719 npu_mem: memory@8bd80000 {
720 reg = <0x0 0x8bd80000 0x0 0x80000>;
724 adsp_mem: memory@8be00000 {
725 reg = <0x0 0x8be00000 0x0 0x1a00000>;
729 mpss_mem: memory@8d800000 {
730 reg = <0x0 0x8d800000 0x0 0x9600000>;
734 venus_mem: memory@96e00000 {
735 reg = <0x0 0x96e00000 0x0 0x500000>;
739 slpi_mem: memory@97300000 {
740 reg = <0x0 0x97300000 0x0 0x1400000>;
744 ipa_fw_mem: memory@98700000 {
745 reg = <0x0 0x98700000 0x0 0x10000>;
749 ipa_gsi_mem: memory@98710000 {
750 reg = <0x0 0x98710000 0x0 0x5000>;
754 gpu_mem: memory@98715000 {
755 reg = <0x0 0x98715000 0x0 0x2000>;
759 spss_mem: memory@98800000 {
760 reg = <0x0 0x98800000 0x0 0x100000>;
764 cdsp_mem: memory@98900000 {
765 reg = <0x0 0x98900000 0x0 0x1400000>;
769 qseecom_mem: memory@9e400000 {
770 reg = <0x0 0x9e400000 0x0 0x1400000>;
776 compatible = "qcom,smem";
777 memory-region = <&smem_mem>;
778 hwlocks = <&tcsr_mutex 3>;
782 compatible = "qcom,smp2p";
783 qcom,smem = <94>, <432>;
785 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
787 mboxes = <&apss_shared 6>;
789 qcom,local-pid = <0>;
790 qcom,remote-pid = <5>;
792 cdsp_smp2p_out: master-kernel {
793 qcom,entry-name = "master-kernel";
794 #qcom,smem-state-cells = <1>;
797 cdsp_smp2p_in: slave-kernel {
798 qcom,entry-name = "slave-kernel";
800 interrupt-controller;
801 #interrupt-cells = <2>;
806 compatible = "qcom,smp2p";
807 qcom,smem = <443>, <429>;
809 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
811 mboxes = <&apss_shared 10>;
813 qcom,local-pid = <0>;
814 qcom,remote-pid = <2>;
816 adsp_smp2p_out: master-kernel {
817 qcom,entry-name = "master-kernel";
818 #qcom,smem-state-cells = <1>;
821 adsp_smp2p_in: slave-kernel {
822 qcom,entry-name = "slave-kernel";
824 interrupt-controller;
825 #interrupt-cells = <2>;
830 compatible = "qcom,smp2p";
831 qcom,smem = <435>, <428>;
833 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
835 mboxes = <&apss_shared 14>;
837 qcom,local-pid = <0>;
838 qcom,remote-pid = <1>;
840 modem_smp2p_out: master-kernel {
841 qcom,entry-name = "master-kernel";
842 #qcom,smem-state-cells = <1>;
845 modem_smp2p_in: slave-kernel {
846 qcom,entry-name = "slave-kernel";
848 interrupt-controller;
849 #interrupt-cells = <2>;
854 compatible = "qcom,smp2p";
855 qcom,smem = <481>, <430>;
857 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
859 mboxes = <&apss_shared 26>;
861 qcom,local-pid = <0>;
862 qcom,remote-pid = <3>;
864 slpi_smp2p_out: master-kernel {
865 qcom,entry-name = "master-kernel";
866 #qcom,smem-state-cells = <1>;
869 slpi_smp2p_in: slave-kernel {
870 qcom,entry-name = "slave-kernel";
872 interrupt-controller;
873 #interrupt-cells = <2>;
878 #address-cells = <2>;
880 ranges = <0 0 0 0 0x10 0>;
881 dma-ranges = <0 0 0 0 0x10 0>;
882 compatible = "simple-bus";
884 gcc: clock-controller@100000 {
885 compatible = "qcom,gcc-sm8150";
886 reg = <0x0 0x00100000 0x0 0x1f0000>;
889 #power-domain-cells = <1>;
890 clock-names = "bi_tcxo",
892 clocks = <&rpmhcc RPMH_CXO_CLK>,
896 gpi_dma0: dma-controller@800000 {
897 compatible = "qcom,sm8150-gpi-dma";
898 reg = <0 0x800000 0 0x60000>;
899 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
904 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
913 dma-channel-mask = <0xfa>;
914 iommus = <&apps_smmu 0x00d6 0x0>;
919 qupv3_id_0: geniqup@8c0000 {
920 compatible = "qcom,geni-se-qup";
921 reg = <0x0 0x008c0000 0x0 0x6000>;
922 clock-names = "m-ahb", "s-ahb";
923 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
924 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
925 iommus = <&apps_smmu 0xc3 0x0>;
926 #address-cells = <2>;
932 compatible = "qcom,geni-i2c";
933 reg = <0 0x00880000 0 0x4000>;
935 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&qup_i2c0_default>;
938 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
939 #address-cells = <1>;
945 compatible = "qcom,geni-spi";
946 reg = <0 0x880000 0 0x4000>;
949 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
950 pinctrl-names = "default";
951 pinctrl-0 = <&qup_spi0_default>;
952 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
953 spi-max-frequency = <50000000>;
954 #address-cells = <1>;
960 compatible = "qcom,geni-i2c";
961 reg = <0 0x00884000 0 0x4000>;
963 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
964 pinctrl-names = "default";
965 pinctrl-0 = <&qup_i2c1_default>;
966 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
967 #address-cells = <1>;
973 compatible = "qcom,geni-spi";
974 reg = <0 0x884000 0 0x4000>;
977 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
978 pinctrl-names = "default";
979 pinctrl-0 = <&qup_spi1_default>;
980 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
981 spi-max-frequency = <50000000>;
982 #address-cells = <1>;
988 compatible = "qcom,geni-i2c";
989 reg = <0 0x00888000 0 0x4000>;
991 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c2_default>;
994 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
995 #address-cells = <1>;
1001 compatible = "qcom,geni-spi";
1002 reg = <0 0x888000 0 0x4000>;
1005 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&qup_spi2_default>;
1008 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1009 spi-max-frequency = <50000000>;
1010 #address-cells = <1>;
1012 status = "disabled";
1016 compatible = "qcom,geni-i2c";
1017 reg = <0 0x0088c000 0 0x4000>;
1019 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c3_default>;
1022 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1023 #address-cells = <1>;
1025 status = "disabled";
1029 compatible = "qcom,geni-spi";
1030 reg = <0 0x88c000 0 0x4000>;
1033 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1034 pinctrl-names = "default";
1035 pinctrl-0 = <&qup_spi3_default>;
1036 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1037 spi-max-frequency = <50000000>;
1038 #address-cells = <1>;
1040 status = "disabled";
1044 compatible = "qcom,geni-i2c";
1045 reg = <0 0x00890000 0 0x4000>;
1047 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1048 pinctrl-names = "default";
1049 pinctrl-0 = <&qup_i2c4_default>;
1050 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1051 #address-cells = <1>;
1053 status = "disabled";
1057 compatible = "qcom,geni-spi";
1058 reg = <0 0x890000 0 0x4000>;
1061 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_spi4_default>;
1064 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1065 spi-max-frequency = <50000000>;
1066 #address-cells = <1>;
1068 status = "disabled";
1072 compatible = "qcom,geni-i2c";
1073 reg = <0 0x00894000 0 0x4000>;
1075 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c5_default>;
1078 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1079 #address-cells = <1>;
1081 status = "disabled";
1085 compatible = "qcom,geni-spi";
1086 reg = <0 0x894000 0 0x4000>;
1089 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&qup_spi5_default>;
1092 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1093 spi-max-frequency = <50000000>;
1094 #address-cells = <1>;
1096 status = "disabled";
1100 compatible = "qcom,geni-i2c";
1101 reg = <0 0x00898000 0 0x4000>;
1103 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&qup_i2c6_default>;
1106 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1107 #address-cells = <1>;
1109 status = "disabled";
1113 compatible = "qcom,geni-spi";
1114 reg = <0 0x898000 0 0x4000>;
1117 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi6_default>;
1120 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1121 spi-max-frequency = <50000000>;
1122 #address-cells = <1>;
1124 status = "disabled";
1128 compatible = "qcom,geni-i2c";
1129 reg = <0 0x0089c000 0 0x4000>;
1131 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c7_default>;
1134 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1135 #address-cells = <1>;
1137 status = "disabled";
1141 compatible = "qcom,geni-spi";
1142 reg = <0 0x89c000 0 0x4000>;
1145 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&qup_spi7_default>;
1148 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1149 spi-max-frequency = <50000000>;
1150 #address-cells = <1>;
1152 status = "disabled";
1156 gpi_dma1: dma-controller@a00000 {
1157 compatible = "qcom,sm8150-gpi-dma";
1158 reg = <0 0xa00000 0 0x60000>;
1159 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1172 dma-channels = <13>;
1173 dma-channel-mask = <0xfa>;
1174 iommus = <&apps_smmu 0x0616 0x0>;
1176 status = "disabled";
1179 qupv3_id_1: geniqup@ac0000 {
1180 compatible = "qcom,geni-se-qup";
1181 reg = <0x0 0x00ac0000 0x0 0x6000>;
1182 clock-names = "m-ahb", "s-ahb";
1183 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1184 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1185 iommus = <&apps_smmu 0x603 0x0>;
1186 #address-cells = <2>;
1189 status = "disabled";
1192 compatible = "qcom,geni-i2c";
1193 reg = <0 0x00a80000 0 0x4000>;
1195 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_i2c8_default>;
1198 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1199 #address-cells = <1>;
1201 status = "disabled";
1205 compatible = "qcom,geni-spi";
1206 reg = <0 0xa80000 0 0x4000>;
1209 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&qup_spi8_default>;
1212 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1213 spi-max-frequency = <50000000>;
1214 #address-cells = <1>;
1216 status = "disabled";
1220 compatible = "qcom,geni-i2c";
1221 reg = <0 0x00a84000 0 0x4000>;
1223 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&qup_i2c9_default>;
1226 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1227 #address-cells = <1>;
1229 status = "disabled";
1233 compatible = "qcom,geni-spi";
1234 reg = <0 0xa84000 0 0x4000>;
1237 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&qup_spi9_default>;
1240 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1241 spi-max-frequency = <50000000>;
1242 #address-cells = <1>;
1244 status = "disabled";
1248 compatible = "qcom,geni-i2c";
1249 reg = <0 0x00a88000 0 0x4000>;
1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&qup_i2c10_default>;
1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1255 #address-cells = <1>;
1257 status = "disabled";
1261 compatible = "qcom,geni-spi";
1262 reg = <0 0xa88000 0 0x4000>;
1265 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_spi10_default>;
1268 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1269 spi-max-frequency = <50000000>;
1270 #address-cells = <1>;
1272 status = "disabled";
1276 compatible = "qcom,geni-i2c";
1277 reg = <0 0x00a8c000 0 0x4000>;
1279 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_i2c11_default>;
1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1283 #address-cells = <1>;
1285 status = "disabled";
1289 compatible = "qcom,geni-spi";
1290 reg = <0 0xa8c000 0 0x4000>;
1293 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&qup_spi11_default>;
1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1297 spi-max-frequency = <50000000>;
1298 #address-cells = <1>;
1300 status = "disabled";
1303 uart2: serial@a90000 {
1304 compatible = "qcom,geni-debug-uart";
1305 reg = <0x0 0x00a90000 0x0 0x4000>;
1307 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1309 status = "disabled";
1313 compatible = "qcom,geni-i2c";
1314 reg = <0 0x00a90000 0 0x4000>;
1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1317 pinctrl-names = "default";
1318 pinctrl-0 = <&qup_i2c12_default>;
1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1320 #address-cells = <1>;
1322 status = "disabled";
1326 compatible = "qcom,geni-spi";
1327 reg = <0 0xa90000 0 0x4000>;
1330 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1331 pinctrl-names = "default";
1332 pinctrl-0 = <&qup_spi12_default>;
1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1334 spi-max-frequency = <50000000>;
1335 #address-cells = <1>;
1337 status = "disabled";
1341 compatible = "qcom,geni-i2c";
1342 reg = <0 0x0094000 0 0x4000>;
1344 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c16_default>;
1347 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cells = <1>;
1350 status = "disabled";
1354 compatible = "qcom,geni-spi";
1355 reg = <0 0xa94000 0 0x4000>;
1358 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_spi16_default>;
1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1362 spi-max-frequency = <50000000>;
1363 #address-cells = <1>;
1365 status = "disabled";
1369 gpi_dma2: dma-controller@c00000 {
1370 compatible = "qcom,sm8150-gpi-dma";
1371 reg = <0 0xc00000 0 0x60000>;
1372 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1385 dma-channels = <13>;
1386 dma-channel-mask = <0xfa>;
1387 iommus = <&apps_smmu 0x07b6 0x0>;
1389 status = "disabled";
1392 qupv3_id_2: geniqup@cc0000 {
1393 compatible = "qcom,geni-se-qup";
1394 reg = <0x0 0x00cc0000 0x0 0x6000>;
1396 clock-names = "m-ahb", "s-ahb";
1397 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1398 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1399 iommus = <&apps_smmu 0x7a3 0x0>;
1400 #address-cells = <2>;
1403 status = "disabled";
1406 compatible = "qcom,geni-i2c";
1407 reg = <0 0x00c80000 0 0x4000>;
1409 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c17_default>;
1412 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1413 #address-cells = <1>;
1415 status = "disabled";
1419 compatible = "qcom,geni-spi";
1420 reg = <0 0xc80000 0 0x4000>;
1423 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&qup_spi17_default>;
1426 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1427 spi-max-frequency = <50000000>;
1428 #address-cells = <1>;
1430 status = "disabled";
1434 compatible = "qcom,geni-i2c";
1435 reg = <0 0x00c84000 0 0x4000>;
1437 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&qup_i2c18_default>;
1440 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1441 #address-cells = <1>;
1443 status = "disabled";
1447 compatible = "qcom,geni-spi";
1448 reg = <0 0xc84000 0 0x4000>;
1451 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1452 pinctrl-names = "default";
1453 pinctrl-0 = <&qup_spi18_default>;
1454 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1455 spi-max-frequency = <50000000>;
1456 #address-cells = <1>;
1458 status = "disabled";
1462 compatible = "qcom,geni-i2c";
1463 reg = <0 0x00c88000 0 0x4000>;
1465 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_i2c19_default>;
1468 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1469 #address-cells = <1>;
1471 status = "disabled";
1475 compatible = "qcom,geni-spi";
1476 reg = <0 0xc88000 0 0x4000>;
1479 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_spi19_default>;
1482 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1483 spi-max-frequency = <50000000>;
1484 #address-cells = <1>;
1486 status = "disabled";
1490 compatible = "qcom,geni-i2c";
1491 reg = <0 0x00c8c000 0 0x4000>;
1493 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1494 pinctrl-names = "default";
1495 pinctrl-0 = <&qup_i2c13_default>;
1496 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1497 #address-cells = <1>;
1499 status = "disabled";
1503 compatible = "qcom,geni-spi";
1504 reg = <0 0xc8c000 0 0x4000>;
1507 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&qup_spi13_default>;
1510 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1511 spi-max-frequency = <50000000>;
1512 #address-cells = <1>;
1514 status = "disabled";
1518 compatible = "qcom,geni-i2c";
1519 reg = <0 0x00c90000 0 0x4000>;
1521 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1522 pinctrl-names = "default";
1523 pinctrl-0 = <&qup_i2c14_default>;
1524 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1525 #address-cells = <1>;
1527 status = "disabled";
1531 compatible = "qcom,geni-spi";
1532 reg = <0 0xc90000 0 0x4000>;
1535 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1536 pinctrl-names = "default";
1537 pinctrl-0 = <&qup_spi14_default>;
1538 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1539 spi-max-frequency = <50000000>;
1540 #address-cells = <1>;
1542 status = "disabled";
1546 compatible = "qcom,geni-i2c";
1547 reg = <0 0x00c94000 0 0x4000>;
1549 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1550 pinctrl-names = "default";
1551 pinctrl-0 = <&qup_i2c15_default>;
1552 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1553 #address-cells = <1>;
1555 status = "disabled";
1559 compatible = "qcom,geni-spi";
1560 reg = <0 0xc94000 0 0x4000>;
1563 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_spi15_default>;
1566 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1567 spi-max-frequency = <50000000>;
1568 #address-cells = <1>;
1570 status = "disabled";
1574 config_noc: interconnect@1500000 {
1575 compatible = "qcom,sm8150-config-noc";
1576 reg = <0 0x01500000 0 0x7400>;
1577 #interconnect-cells = <1>;
1578 qcom,bcm-voters = <&apps_bcm_voter>;
1581 system_noc: interconnect@1620000 {
1582 compatible = "qcom,sm8150-system-noc";
1583 reg = <0 0x01620000 0 0x19400>;
1584 #interconnect-cells = <1>;
1585 qcom,bcm-voters = <&apps_bcm_voter>;
1588 mc_virt: interconnect@163a000 {
1589 compatible = "qcom,sm8150-mc-virt";
1590 reg = <0 0x0163a000 0 0x1000>;
1591 #interconnect-cells = <1>;
1592 qcom,bcm-voters = <&apps_bcm_voter>;
1595 aggre1_noc: interconnect@16e0000 {
1596 compatible = "qcom,sm8150-aggre1-noc";
1597 reg = <0 0x016e0000 0 0xd080>;
1598 #interconnect-cells = <1>;
1599 qcom,bcm-voters = <&apps_bcm_voter>;
1602 aggre2_noc: interconnect@1700000 {
1603 compatible = "qcom,sm8150-aggre2-noc";
1604 reg = <0 0x01700000 0 0x20000>;
1605 #interconnect-cells = <1>;
1606 qcom,bcm-voters = <&apps_bcm_voter>;
1609 compute_noc: interconnect@1720000 {
1610 compatible = "qcom,sm8150-compute-noc";
1611 reg = <0 0x01720000 0 0x7000>;
1612 #interconnect-cells = <1>;
1613 qcom,bcm-voters = <&apps_bcm_voter>;
1616 mmss_noc: interconnect@1740000 {
1617 compatible = "qcom,sm8150-mmss-noc";
1618 reg = <0 0x01740000 0 0x1c100>;
1619 #interconnect-cells = <1>;
1620 qcom,bcm-voters = <&apps_bcm_voter>;
1623 system-cache-controller@9200000 {
1624 compatible = "qcom,sm8150-llcc";
1625 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1626 reg-names = "llcc_base", "llcc_broadcast_base";
1627 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1630 ufs_mem_hc: ufshc@1d84000 {
1631 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
1633 reg = <0 0x01d84000 0 0x2500>,
1634 <0 0x01d90000 0 0x8000>;
1635 reg-names = "std", "ice";
1636 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1637 phys = <&ufs_mem_phy_lanes>;
1638 phy-names = "ufsphy";
1639 lanes-per-direction = <2>;
1641 resets = <&gcc GCC_UFS_PHY_BCR>;
1642 reset-names = "rst";
1644 iommus = <&apps_smmu 0x300 0>;
1652 "tx_lane0_sync_clk",
1653 "rx_lane0_sync_clk",
1654 "rx_lane1_sync_clk",
1657 <&gcc GCC_UFS_PHY_AXI_CLK>,
1658 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1659 <&gcc GCC_UFS_PHY_AHB_CLK>,
1660 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1661 <&rpmhcc RPMH_CXO_CLK>,
1662 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1664 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
1665 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1667 <37500000 300000000>,
1670 <37500000 300000000>,
1677 status = "disabled";
1680 ufs_mem_phy: phy@1d87000 {
1681 compatible = "qcom,sm8150-qmp-ufs-phy";
1682 reg = <0 0x01d87000 0 0x1c0>;
1683 #address-cells = <2>;
1686 clock-names = "ref",
1688 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1689 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1691 resets = <&ufs_mem_hc 0>;
1692 reset-names = "ufsphy";
1693 status = "disabled";
1695 ufs_mem_phy_lanes: lanes@1d87400 {
1696 reg = <0 0x01d87400 0 0x108>,
1697 <0 0x01d87600 0 0x1e0>,
1698 <0 0x01d87c00 0 0x1dc>,
1699 <0 0x01d87800 0 0x108>,
1700 <0 0x01d87a00 0 0x1e0>;
1705 ipa_virt: interconnect@1e00000 {
1706 compatible = "qcom,sm8150-ipa-virt";
1707 reg = <0 0x01e00000 0 0x1000>;
1708 #interconnect-cells = <1>;
1709 qcom,bcm-voters = <&apps_bcm_voter>;
1712 tcsr_mutex_regs: syscon@1f40000 {
1713 compatible = "syscon";
1714 reg = <0x0 0x01f40000 0x0 0x40000>;
1717 remoteproc_slpi: remoteproc@2400000 {
1718 compatible = "qcom,sm8150-slpi-pas";
1719 reg = <0x0 0x02400000 0x0 0x4040>;
1721 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
1722 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1723 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1724 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1725 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1726 interrupt-names = "wdog", "fatal", "ready",
1727 "handover", "stop-ack";
1729 clocks = <&rpmhcc RPMH_CXO_CLK>;
1732 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1735 power-domain-names = "load_state", "lcx", "lmx";
1737 memory-region = <&slpi_mem>;
1739 qcom,smem-states = <&slpi_smp2p_out 0>;
1740 qcom,smem-state-names = "stop";
1742 status = "disabled";
1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
1747 qcom,remote-pid = <3>;
1748 mboxes = <&apss_shared 24>;
1754 * note: the amd,imageon compatible makes it possible
1755 * to use the drm/msm driver without the display node,
1756 * make sure to remove it when display node is added
1758 compatible = "qcom,adreno-640.1",
1761 #stream-id-cells = <16>;
1763 reg = <0 0x02c00000 0 0x40000>;
1764 reg-names = "kgsl_3d0_reg_memory";
1766 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1768 iommus = <&adreno_smmu 0 0x401>;
1770 operating-points-v2 = <&gpu_opp_table>;
1774 status = "disabled";
1777 memory-region = <&gpu_mem>;
1780 /* note: downstream checks gpu binning for 675 Mhz */
1781 gpu_opp_table: opp-table {
1782 compatible = "operating-points-v2";
1785 opp-hz = /bits/ 64 <675000000>;
1786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1790 opp-hz = /bits/ 64 <585000000>;
1791 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1795 opp-hz = /bits/ 64 <499200000>;
1796 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1800 opp-hz = /bits/ 64 <427000000>;
1801 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1805 opp-hz = /bits/ 64 <345000000>;
1806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1810 opp-hz = /bits/ 64 <257000000>;
1811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1817 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
1819 reg = <0 0x02c6a000 0 0x30000>,
1820 <0 0x0b290000 0 0x10000>,
1821 <0 0x0b490000 0 0x10000>;
1822 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1824 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1826 interrupt-names = "hfi", "gmu";
1828 clocks = <&gpucc GPU_CC_AHB_CLK>,
1829 <&gpucc GPU_CC_CX_GMU_CLK>,
1830 <&gpucc GPU_CC_CXO_CLK>,
1831 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1832 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1833 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1835 power-domains = <&gpucc GPU_CX_GDSC>,
1836 <&gpucc GPU_GX_GDSC>;
1837 power-domain-names = "cx", "gx";
1839 iommus = <&adreno_smmu 5 0x400>;
1841 operating-points-v2 = <&gmu_opp_table>;
1843 status = "disabled";
1845 gmu_opp_table: opp-table {
1846 compatible = "operating-points-v2";
1849 opp-hz = /bits/ 64 <200000000>;
1850 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1855 gpucc: clock-controller@2c90000 {
1856 compatible = "qcom,sm8150-gpucc";
1857 reg = <0 0x02c90000 0 0x9000>;
1858 clocks = <&rpmhcc RPMH_CXO_CLK>,
1859 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1860 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1861 clock-names = "bi_tcxo",
1862 "gcc_gpu_gpll0_clk_src",
1863 "gcc_gpu_gpll0_div_clk_src";
1866 #power-domain-cells = <1>;
1869 adreno_smmu: iommu@2ca0000 {
1870 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
1871 reg = <0 0x02ca0000 0 0x10000>;
1873 #global-interrupts = <1>;
1874 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1880 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
1883 clocks = <&gpucc GPU_CC_AHB_CLK>,
1884 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1885 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1886 clock-names = "ahb", "bus", "iface";
1888 power-domains = <&gpucc GPU_CX_GDSC>;
1891 tlmm: pinctrl@3100000 {
1892 compatible = "qcom,sm8150-pinctrl";
1893 reg = <0x0 0x03100000 0x0 0x300000>,
1894 <0x0 0x03500000 0x0 0x300000>,
1895 <0x0 0x03900000 0x0 0x300000>,
1896 <0x0 0x03D00000 0x0 0x300000>;
1897 reg-names = "west", "east", "north", "south";
1898 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1899 gpio-ranges = <&tlmm 0 0 176>;
1902 interrupt-controller;
1903 #interrupt-cells = <2>;
1905 qup_i2c0_default: qup-i2c0-default {
1907 pins = "gpio0", "gpio1";
1912 pins = "gpio0", "gpio1";
1913 drive-strength = <0x02>;
1918 qup_spi0_default: qup-spi0-default {
1919 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1921 drive-strength = <6>;
1925 qup_i2c1_default: qup-i2c1-default {
1927 pins = "gpio114", "gpio115";
1932 pins = "gpio114", "gpio115";
1933 drive-strength = <0x02>;
1938 qup_spi1_default: qup-spi1-default {
1939 pins = "gpio114", "gpio115", "gpio116", "gpio117";
1941 drive-strength = <6>;
1945 qup_i2c2_default: qup-i2c2-default {
1947 pins = "gpio126", "gpio127";
1952 pins = "gpio126", "gpio127";
1953 drive-strength = <0x02>;
1958 qup_spi2_default: qup-spi2-default {
1959 pins = "gpio126", "gpio127", "gpio128", "gpio129";
1961 drive-strength = <6>;
1965 qup_i2c3_default: qup-i2c3-default {
1967 pins = "gpio144", "gpio145";
1972 pins = "gpio144", "gpio145";
1973 drive-strength = <0x02>;
1978 qup_spi3_default: qup-spi3-default {
1979 pins = "gpio144", "gpio145", "gpio146", "gpio147";
1981 drive-strength = <6>;
1985 qup_i2c4_default: qup-i2c4-default {
1987 pins = "gpio51", "gpio52";
1992 pins = "gpio51", "gpio52";
1993 drive-strength = <0x02>;
1998 qup_spi4_default: qup-spi4-default {
1999 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2001 drive-strength = <6>;
2005 qup_i2c5_default: qup-i2c5-default {
2007 pins = "gpio121", "gpio122";
2012 pins = "gpio121", "gpio122";
2013 drive-strength = <0x02>;
2018 qup_spi5_default: qup-spi5-default {
2019 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2021 drive-strength = <6>;
2025 qup_i2c6_default: qup-i2c6-default {
2027 pins = "gpio6", "gpio7";
2032 pins = "gpio6", "gpio7";
2033 drive-strength = <0x02>;
2038 qup_spi6_default: qup-spi6_default {
2039 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2041 drive-strength = <6>;
2045 qup_i2c7_default: qup-i2c7-default {
2047 pins = "gpio98", "gpio99";
2052 pins = "gpio98", "gpio99";
2053 drive-strength = <0x02>;
2058 qup_spi7_default: qup-spi7_default {
2059 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2061 drive-strength = <6>;
2065 qup_i2c8_default: qup-i2c8-default {
2067 pins = "gpio88", "gpio89";
2072 pins = "gpio88", "gpio89";
2073 drive-strength = <0x02>;
2078 qup_spi8_default: qup-spi8-default {
2079 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2081 drive-strength = <6>;
2085 qup_i2c9_default: qup-i2c9-default {
2087 pins = "gpio39", "gpio40";
2092 pins = "gpio39", "gpio40";
2093 drive-strength = <0x02>;
2098 qup_spi9_default: qup-spi9-default {
2099 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2101 drive-strength = <6>;
2105 qup_i2c10_default: qup-i2c10-default {
2107 pins = "gpio9", "gpio10";
2112 pins = "gpio9", "gpio10";
2113 drive-strength = <0x02>;
2118 qup_spi10_default: qup-spi10-default {
2119 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2121 drive-strength = <6>;
2125 qup_i2c11_default: qup-i2c11-default {
2127 pins = "gpio94", "gpio95";
2132 pins = "gpio94", "gpio95";
2133 drive-strength = <0x02>;
2138 qup_spi11_default: qup-spi11-default {
2139 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2141 drive-strength = <6>;
2145 qup_i2c12_default: qup-i2c12-default {
2147 pins = "gpio83", "gpio84";
2152 pins = "gpio83", "gpio84";
2153 drive-strength = <0x02>;
2158 qup_spi12_default: qup-spi12-default {
2159 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2161 drive-strength = <6>;
2165 qup_i2c13_default: qup-i2c13-default {
2167 pins = "gpio43", "gpio44";
2172 pins = "gpio43", "gpio44";
2173 drive-strength = <0x02>;
2178 qup_spi13_default: qup-spi13-default {
2179 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2181 drive-strength = <6>;
2185 qup_i2c14_default: qup-i2c14-default {
2187 pins = "gpio47", "gpio48";
2192 pins = "gpio47", "gpio48";
2193 drive-strength = <0x02>;
2198 qup_spi14_default: qup-spi14-default {
2199 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2201 drive-strength = <6>;
2205 qup_i2c15_default: qup-i2c15-default {
2207 pins = "gpio27", "gpio28";
2212 pins = "gpio27", "gpio28";
2213 drive-strength = <0x02>;
2218 qup_spi15_default: qup-spi15-default {
2219 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2221 drive-strength = <6>;
2225 qup_i2c16_default: qup-i2c16-default {
2227 pins = "gpio86", "gpio85";
2232 pins = "gpio86", "gpio85";
2233 drive-strength = <0x02>;
2238 qup_spi16_default: qup-spi16-default {
2239 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2241 drive-strength = <6>;
2245 qup_i2c17_default: qup-i2c17-default {
2247 pins = "gpio55", "gpio56";
2252 pins = "gpio55", "gpio56";
2253 drive-strength = <0x02>;
2258 qup_spi17_default: qup-spi17-default {
2259 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2261 drive-strength = <6>;
2265 qup_i2c18_default: qup-i2c18-default {
2267 pins = "gpio23", "gpio24";
2272 pins = "gpio23", "gpio24";
2273 drive-strength = <0x02>;
2278 qup_spi18_default: qup-spi18-default {
2279 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2281 drive-strength = <6>;
2285 qup_i2c19_default: qup-i2c19-default {
2287 pins = "gpio57", "gpio58";
2292 pins = "gpio57", "gpio58";
2293 drive-strength = <0x02>;
2298 qup_spi19_default: qup-spi19-default {
2299 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2301 drive-strength = <6>;
2306 remoteproc_mpss: remoteproc@4080000 {
2307 compatible = "qcom,sm8150-mpss-pas";
2308 reg = <0x0 0x04080000 0x0 0x4040>;
2310 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2311 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2312 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2313 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2314 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2315 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2316 interrupt-names = "wdog", "fatal", "ready", "handover",
2317 "stop-ack", "shutdown-ack";
2319 clocks = <&rpmhcc RPMH_CXO_CLK>;
2322 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2325 power-domain-names = "load_state", "cx", "mss";
2327 memory-region = <&mpss_mem>;
2329 qcom,smem-states = <&modem_smp2p_out 0>;
2330 qcom,smem-state-names = "stop";
2332 status = "disabled";
2335 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2337 qcom,remote-pid = <1>;
2338 mboxes = <&apss_shared 12>;
2343 compatible = "arm,coresight-stm", "arm,primecell";
2344 reg = <0 0x06002000 0 0x1000>,
2345 <0 0x16280000 0 0x180000>;
2346 reg-names = "stm-base", "stm-stimulus-base";
2348 clocks = <&aoss_qmp>;
2349 clock-names = "apb_pclk";
2354 remote-endpoint = <&funnel0_in7>;
2361 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2362 reg = <0 0x06041000 0 0x1000>;
2364 clocks = <&aoss_qmp>;
2365 clock-names = "apb_pclk";
2369 funnel0_out: endpoint {
2370 remote-endpoint = <&merge_funnel_in0>;
2376 #address-cells = <1>;
2381 funnel0_in7: endpoint {
2382 remote-endpoint = <&stm_out>;
2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2390 reg = <0 0x06042000 0 0x1000>;
2392 clocks = <&aoss_qmp>;
2393 clock-names = "apb_pclk";
2397 funnel1_out: endpoint {
2398 remote-endpoint = <&merge_funnel_in1>;
2404 #address-cells = <1>;
2409 funnel1_in4: endpoint {
2410 remote-endpoint = <&swao_replicator_out>;
2417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2418 reg = <0 0x06043000 0 0x1000>;
2420 clocks = <&aoss_qmp>;
2421 clock-names = "apb_pclk";
2425 funnel2_out: endpoint {
2426 remote-endpoint = <&merge_funnel_in2>;
2432 #address-cells = <1>;
2437 funnel2_in2: endpoint {
2438 remote-endpoint = <&apss_merge_funnel_out>;
2445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2446 reg = <0 0x06045000 0 0x1000>;
2448 clocks = <&aoss_qmp>;
2449 clock-names = "apb_pclk";
2453 merge_funnel_out: endpoint {
2454 remote-endpoint = <&etf_in>;
2460 #address-cells = <1>;
2465 merge_funnel_in0: endpoint {
2466 remote-endpoint = <&funnel0_out>;
2472 merge_funnel_in1: endpoint {
2473 remote-endpoint = <&funnel1_out>;
2479 merge_funnel_in2: endpoint {
2480 remote-endpoint = <&funnel2_out>;
2486 replicator@6046000 {
2487 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2488 reg = <0 0x06046000 0 0x1000>;
2490 clocks = <&aoss_qmp>;
2491 clock-names = "apb_pclk";
2494 #address-cells = <1>;
2499 replicator_out0: endpoint {
2500 remote-endpoint = <&etr_in>;
2506 replicator_out1: endpoint {
2507 remote-endpoint = <&replicator1_in>;
2514 replicator_in0: endpoint {
2515 remote-endpoint = <&etf_out>;
2522 compatible = "arm,coresight-tmc", "arm,primecell";
2523 reg = <0 0x06047000 0 0x1000>;
2525 clocks = <&aoss_qmp>;
2526 clock-names = "apb_pclk";
2531 remote-endpoint = <&replicator_in0>;
2539 remote-endpoint = <&merge_funnel_out>;
2546 compatible = "arm,coresight-tmc", "arm,primecell";
2547 reg = <0 0x06048000 0 0x1000>;
2548 iommus = <&apps_smmu 0x05e0 0x0>;
2550 clocks = <&aoss_qmp>;
2551 clock-names = "apb_pclk";
2557 remote-endpoint = <&replicator_out0>;
2563 replicator@604a000 {
2564 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2565 reg = <0 0x0604a000 0 0x1000>;
2567 clocks = <&aoss_qmp>;
2568 clock-names = "apb_pclk";
2571 #address-cells = <1>;
2576 replicator1_out: endpoint {
2577 remote-endpoint = <&swao_funnel_in>;
2583 #address-cells = <1>;
2588 replicator1_in: endpoint {
2589 remote-endpoint = <&replicator_out1>;
2596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2597 reg = <0 0x06b08000 0 0x1000>;
2599 clocks = <&aoss_qmp>;
2600 clock-names = "apb_pclk";
2604 swao_funnel_out: endpoint {
2605 remote-endpoint = <&swao_etf_in>;
2611 #address-cells = <1>;
2616 swao_funnel_in: endpoint {
2617 remote-endpoint = <&replicator1_out>;
2624 compatible = "arm,coresight-tmc", "arm,primecell";
2625 reg = <0 0x06b09000 0 0x1000>;
2627 clocks = <&aoss_qmp>;
2628 clock-names = "apb_pclk";
2632 swao_etf_out: endpoint {
2633 remote-endpoint = <&swao_replicator_in>;
2640 swao_etf_in: endpoint {
2641 remote-endpoint = <&swao_funnel_out>;
2647 replicator@6b0a000 {
2648 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2649 reg = <0 0x06b0a000 0 0x1000>;
2651 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pclk";
2653 qcom,replicator-loses-context;
2657 swao_replicator_out: endpoint {
2658 remote-endpoint = <&funnel1_in4>;
2665 swao_replicator_in: endpoint {
2666 remote-endpoint = <&swao_etf_out>;
2673 compatible = "arm,coresight-etm4x", "arm,primecell";
2674 reg = <0 0x07040000 0 0x1000>;
2678 clocks = <&aoss_qmp>;
2679 clock-names = "apb_pclk";
2680 arm,coresight-loses-context-with-cpu;
2685 etm0_out: endpoint {
2686 remote-endpoint = <&apss_funnel_in0>;
2693 compatible = "arm,coresight-etm4x", "arm,primecell";
2694 reg = <0 0x07140000 0 0x1000>;
2698 clocks = <&aoss_qmp>;
2699 clock-names = "apb_pclk";
2700 arm,coresight-loses-context-with-cpu;
2705 etm1_out: endpoint {
2706 remote-endpoint = <&apss_funnel_in1>;
2713 compatible = "arm,coresight-etm4x", "arm,primecell";
2714 reg = <0 0x07240000 0 0x1000>;
2718 clocks = <&aoss_qmp>;
2719 clock-names = "apb_pclk";
2720 arm,coresight-loses-context-with-cpu;
2725 etm2_out: endpoint {
2726 remote-endpoint = <&apss_funnel_in2>;
2733 compatible = "arm,coresight-etm4x", "arm,primecell";
2734 reg = <0 0x07340000 0 0x1000>;
2738 clocks = <&aoss_qmp>;
2739 clock-names = "apb_pclk";
2740 arm,coresight-loses-context-with-cpu;
2745 etm3_out: endpoint {
2746 remote-endpoint = <&apss_funnel_in3>;
2753 compatible = "arm,coresight-etm4x", "arm,primecell";
2754 reg = <0 0x07440000 0 0x1000>;
2758 clocks = <&aoss_qmp>;
2759 clock-names = "apb_pclk";
2760 arm,coresight-loses-context-with-cpu;
2765 etm4_out: endpoint {
2766 remote-endpoint = <&apss_funnel_in4>;
2773 compatible = "arm,coresight-etm4x", "arm,primecell";
2774 reg = <0 0x07540000 0 0x1000>;
2778 clocks = <&aoss_qmp>;
2779 clock-names = "apb_pclk";
2780 arm,coresight-loses-context-with-cpu;
2785 etm5_out: endpoint {
2786 remote-endpoint = <&apss_funnel_in5>;
2793 compatible = "arm,coresight-etm4x", "arm,primecell";
2794 reg = <0 0x07640000 0 0x1000>;
2798 clocks = <&aoss_qmp>;
2799 clock-names = "apb_pclk";
2800 arm,coresight-loses-context-with-cpu;
2805 etm6_out: endpoint {
2806 remote-endpoint = <&apss_funnel_in6>;
2813 compatible = "arm,coresight-etm4x", "arm,primecell";
2814 reg = <0 0x07740000 0 0x1000>;
2818 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pclk";
2820 arm,coresight-loses-context-with-cpu;
2825 etm7_out: endpoint {
2826 remote-endpoint = <&apss_funnel_in7>;
2832 funnel@7800000 { /* APSS Funnel */
2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2834 reg = <0 0x07800000 0 0x1000>;
2836 clocks = <&aoss_qmp>;
2837 clock-names = "apb_pclk";
2841 apss_funnel_out: endpoint {
2842 remote-endpoint = <&apss_merge_funnel_in>;
2848 #address-cells = <1>;
2853 apss_funnel_in0: endpoint {
2854 remote-endpoint = <&etm0_out>;
2860 apss_funnel_in1: endpoint {
2861 remote-endpoint = <&etm1_out>;
2867 apss_funnel_in2: endpoint {
2868 remote-endpoint = <&etm2_out>;
2874 apss_funnel_in3: endpoint {
2875 remote-endpoint = <&etm3_out>;
2881 apss_funnel_in4: endpoint {
2882 remote-endpoint = <&etm4_out>;
2888 apss_funnel_in5: endpoint {
2889 remote-endpoint = <&etm5_out>;
2895 apss_funnel_in6: endpoint {
2896 remote-endpoint = <&etm6_out>;
2902 apss_funnel_in7: endpoint {
2903 remote-endpoint = <&etm7_out>;
2910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2911 reg = <0 0x07810000 0 0x1000>;
2913 clocks = <&aoss_qmp>;
2914 clock-names = "apb_pclk";
2918 apss_merge_funnel_out: endpoint {
2919 remote-endpoint = <&funnel2_in2>;
2926 apss_merge_funnel_in: endpoint {
2927 remote-endpoint = <&apss_funnel_out>;
2933 remoteproc_cdsp: remoteproc@8300000 {
2934 compatible = "qcom,sm8150-cdsp-pas";
2935 reg = <0x0 0x08300000 0x0 0x4040>;
2937 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2938 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2939 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2940 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2941 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2942 interrupt-names = "wdog", "fatal", "ready",
2943 "handover", "stop-ack";
2945 clocks = <&rpmhcc RPMH_CXO_CLK>;
2948 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2950 power-domain-names = "load_state", "cx";
2952 memory-region = <&cdsp_mem>;
2954 qcom,smem-states = <&cdsp_smp2p_out 0>;
2955 qcom,smem-state-names = "stop";
2957 status = "disabled";
2960 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2962 qcom,remote-pid = <5>;
2963 mboxes = <&apss_shared 4>;
2967 usb_1_hsphy: phy@88e2000 {
2968 compatible = "qcom,sm8150-usb-hs-phy",
2969 "qcom,usb-snps-hs-7nm-phy";
2970 reg = <0 0x088e2000 0 0x400>;
2971 status = "disabled";
2974 clocks = <&rpmhcc RPMH_CXO_CLK>;
2975 clock-names = "ref";
2977 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2980 usb_2_hsphy: phy@88e3000 {
2981 compatible = "qcom,sm8150-usb-hs-phy",
2982 "qcom,usb-snps-hs-7nm-phy";
2983 reg = <0 0x088e3000 0 0x400>;
2984 status = "disabled";
2987 clocks = <&rpmhcc RPMH_CXO_CLK>;
2988 clock-names = "ref";
2990 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2993 usb_1_qmpphy: phy@88e9000 {
2994 compatible = "qcom,sm8150-qmp-usb3-phy";
2995 reg = <0 0x088e9000 0 0x18c>,
2996 <0 0x088e8000 0 0x10>;
2997 reg-names = "reg-base", "dp_com";
2998 status = "disabled";
2999 #address-cells = <2>;
3003 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3004 <&rpmhcc RPMH_CXO_CLK>,
3005 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3006 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3007 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3009 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3010 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3011 reset-names = "phy", "common";
3013 usb_1_ssphy: lanes@88e9200 {
3014 reg = <0 0x088e9200 0 0x200>,
3015 <0 0x088e9400 0 0x200>,
3016 <0 0x088e9c00 0 0x218>,
3017 <0 0x088e9600 0 0x200>,
3018 <0 0x088e9800 0 0x200>,
3019 <0 0x088e9a00 0 0x100>;
3022 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3023 clock-names = "pipe0";
3024 clock-output-names = "usb3_phy_pipe_clk_src";
3028 usb_2_qmpphy: phy@88eb000 {
3029 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3030 reg = <0 0x088eb000 0 0x200>;
3031 status = "disabled";
3032 #address-cells = <2>;
3036 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3037 <&rpmhcc RPMH_CXO_CLK>,
3038 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3039 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3040 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3042 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3043 <&gcc GCC_USB3_PHY_SEC_BCR>;
3044 reset-names = "phy", "common";
3046 usb_2_ssphy: lane@88eb200 {
3047 reg = <0 0x088eb200 0 0x200>,
3048 <0 0x088eb400 0 0x200>,
3049 <0 0x088eb800 0 0x800>,
3050 <0 0x088eb600 0 0x200>;
3053 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3054 clock-names = "pipe0";
3055 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3059 dc_noc: interconnect@9160000 {
3060 compatible = "qcom,sm8150-dc-noc";
3061 reg = <0 0x09160000 0 0x3200>;
3062 #interconnect-cells = <1>;
3063 qcom,bcm-voters = <&apps_bcm_voter>;
3066 gem_noc: interconnect@9680000 {
3067 compatible = "qcom,sm8150-gem-noc";
3068 reg = <0 0x09680000 0 0x3e200>;
3069 #interconnect-cells = <1>;
3070 qcom,bcm-voters = <&apps_bcm_voter>;
3073 usb_1: usb@a6f8800 {
3074 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3075 reg = <0 0x0a6f8800 0 0x400>;
3076 status = "disabled";
3077 #address-cells = <2>;
3082 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3083 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3084 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3085 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3086 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3087 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3088 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3091 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3092 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3093 assigned-clock-rates = <19200000>, <200000000>;
3095 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3096 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3097 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3098 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3099 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3100 "dm_hs_phy_irq", "dp_hs_phy_irq";
3102 power-domains = <&gcc USB30_PRIM_GDSC>;
3104 resets = <&gcc GCC_USB30_PRIM_BCR>;
3106 usb_1_dwc3: dwc3@a600000 {
3107 compatible = "snps,dwc3";
3108 reg = <0 0x0a600000 0 0xcd00>;
3109 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3110 iommus = <&apps_smmu 0x140 0>;
3111 snps,dis_u2_susphy_quirk;
3112 snps,dis_enblslpm_quirk;
3113 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3114 phy-names = "usb2-phy", "usb3-phy";
3118 usb_2: usb@a8f8800 {
3119 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3120 reg = <0 0x0a8f8800 0 0x400>;
3121 status = "disabled";
3122 #address-cells = <2>;
3127 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3128 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3129 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3130 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3131 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3132 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3133 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3136 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3137 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3138 assigned-clock-rates = <19200000>, <200000000>;
3140 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3141 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3142 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3143 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3144 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3145 "dm_hs_phy_irq", "dp_hs_phy_irq";
3147 power-domains = <&gcc USB30_SEC_GDSC>;
3149 resets = <&gcc GCC_USB30_SEC_BCR>;
3151 usb_2_dwc3: usb@a800000 {
3152 compatible = "snps,dwc3";
3153 reg = <0 0x0a800000 0 0xcd00>;
3154 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3155 iommus = <&apps_smmu 0x160 0>;
3156 snps,dis_u2_susphy_quirk;
3157 snps,dis_enblslpm_quirk;
3158 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3159 phy-names = "usb2-phy", "usb3-phy";
3163 camnoc_virt: interconnect@ac00000 {
3164 compatible = "qcom,sm8150-camnoc-virt";
3165 reg = <0 0x0ac00000 0 0x1000>;
3166 #interconnect-cells = <1>;
3167 qcom,bcm-voters = <&apps_bcm_voter>;
3170 aoss_qmp: power-controller@c300000 {
3171 compatible = "qcom,sm8150-aoss-qmp";
3172 reg = <0x0 0x0c300000 0x0 0x100000>;
3173 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3174 mboxes = <&apss_shared 0>;
3177 #power-domain-cells = <1>;
3180 tsens0: thermal-sensor@c263000 {
3181 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3182 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3183 <0 0x0c222000 0 0x1ff>; /* SROT */
3184 #qcom,sensors = <16>;
3185 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3186 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3187 interrupt-names = "uplow", "critical";
3188 #thermal-sensor-cells = <1>;
3191 tsens1: thermal-sensor@c265000 {
3192 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3193 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3194 <0 0x0c223000 0 0x1ff>; /* SROT */
3195 #qcom,sensors = <8>;
3196 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3197 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3198 interrupt-names = "uplow", "critical";
3199 #thermal-sensor-cells = <1>;
3202 spmi_bus: spmi@c440000 {
3203 compatible = "qcom,spmi-pmic-arb";
3204 reg = <0x0 0x0c440000 0x0 0x0001100>,
3205 <0x0 0x0c600000 0x0 0x2000000>,
3206 <0x0 0x0e600000 0x0 0x0100000>,
3207 <0x0 0x0e700000 0x0 0x00a0000>,
3208 <0x0 0x0c40a000 0x0 0x0026000>;
3209 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3210 interrupt-names = "periph_irq";
3211 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3214 #address-cells = <2>;
3216 interrupt-controller;
3217 #interrupt-cells = <4>;
3221 apps_smmu: iommu@15000000 {
3222 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
3223 reg = <0 0x15000000 0 0x100000>;
3225 #global-interrupts = <1>;
3226 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3227 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3228 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3229 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3230 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3231 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3232 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3233 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3234 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3235 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3236 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3237 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3238 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3239 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3240 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3241 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3242 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3243 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3244 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3245 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3251 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3252 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3253 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3254 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3255 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3256 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3257 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3258 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3259 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3260 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3261 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3262 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3263 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3264 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3265 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3266 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3267 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3268 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3270 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3271 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3272 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3273 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3274 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3275 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3276 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3277 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3278 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3279 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3280 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3281 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3282 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3283 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3284 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3285 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3286 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3287 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3288 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3289 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3290 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3291 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3292 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3293 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3294 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3295 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3297 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3298 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3299 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3300 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3301 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3302 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3303 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3304 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3305 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3306 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
3309 remoteproc_adsp: remoteproc@17300000 {
3310 compatible = "qcom,sm8150-adsp-pas";
3311 reg = <0x0 0x17300000 0x0 0x4040>;
3313 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3314 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3315 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3316 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3317 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3318 interrupt-names = "wdog", "fatal", "ready",
3319 "handover", "stop-ack";
3321 clocks = <&rpmhcc RPMH_CXO_CLK>;
3324 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3326 power-domain-names = "load_state", "cx";
3328 memory-region = <&adsp_mem>;
3330 qcom,smem-states = <&adsp_smp2p_out 0>;
3331 qcom,smem-state-names = "stop";
3333 status = "disabled";
3336 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3338 qcom,remote-pid = <2>;
3339 mboxes = <&apss_shared 8>;
3343 intc: interrupt-controller@17a00000 {
3344 compatible = "arm,gic-v3";
3345 interrupt-controller;
3346 #interrupt-cells = <3>;
3347 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3348 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3352 apss_shared: mailbox@17c00000 {
3353 compatible = "qcom,sm8150-apss-shared";
3354 reg = <0x0 0x17c00000 0x0 0x1000>;
3359 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
3360 reg = <0 0x17c10000 0 0x1000>;
3361 clocks = <&sleep_clk>;
3362 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3366 #address-cells = <2>;
3369 compatible = "arm,armv7-timer-mem";
3370 reg = <0x0 0x17c20000 0x0 0x1000>;
3371 clock-frequency = <19200000>;
3375 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3376 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3377 reg = <0x0 0x17c21000 0x0 0x1000>,
3378 <0x0 0x17c22000 0x0 0x1000>;
3383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3384 reg = <0x0 0x17c23000 0x0 0x1000>;
3385 status = "disabled";
3390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3391 reg = <0x0 0x17c25000 0x0 0x1000>;
3392 status = "disabled";
3397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3398 reg = <0x0 0x17c26000 0x0 0x1000>;
3399 status = "disabled";
3404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3405 reg = <0x0 0x17c29000 0x0 0x1000>;
3406 status = "disabled";
3411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3412 reg = <0x0 0x17c2b000 0x0 0x1000>;
3413 status = "disabled";
3418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3419 reg = <0x0 0x17c2d000 0x0 0x1000>;
3420 status = "disabled";
3424 apps_rsc: rsc@18200000 {
3426 compatible = "qcom,rpmh-rsc";
3427 reg = <0x0 0x18200000 0x0 0x10000>,
3428 <0x0 0x18210000 0x0 0x10000>,
3429 <0x0 0x18220000 0x0 0x10000>;
3430 reg-names = "drv-0", "drv-1", "drv-2";
3431 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3432 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3433 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3434 qcom,tcs-offset = <0xd00>;
3436 qcom,tcs-config = <ACTIVE_TCS 2>,
3441 rpmhcc: clock-controller {
3442 compatible = "qcom,sm8150-rpmh-clk";
3445 clocks = <&xo_board>;
3448 rpmhpd: power-controller {
3449 compatible = "qcom,sm8150-rpmhpd";
3450 #power-domain-cells = <1>;
3451 operating-points-v2 = <&rpmhpd_opp_table>;
3453 rpmhpd_opp_table: opp-table {
3454 compatible = "operating-points-v2";
3456 rpmhpd_opp_ret: opp1 {
3457 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3460 rpmhpd_opp_min_svs: opp2 {
3461 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3464 rpmhpd_opp_low_svs: opp3 {
3465 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3468 rpmhpd_opp_svs: opp4 {
3469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3472 rpmhpd_opp_svs_l1: opp5 {
3473 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3476 rpmhpd_opp_svs_l2: opp6 {
3480 rpmhpd_opp_nom: opp7 {
3481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3484 rpmhpd_opp_nom_l1: opp8 {
3485 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3488 rpmhpd_opp_nom_l2: opp9 {
3489 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3492 rpmhpd_opp_turbo: opp10 {
3493 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3496 rpmhpd_opp_turbo_l1: opp11 {
3497 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3502 apps_bcm_voter: bcm_voter {
3503 compatible = "qcom,bcm-voter";
3507 osm_l3: interconnect@18321000 {
3508 compatible = "qcom,sm8150-osm-l3";
3509 reg = <0 0x18321000 0 0x1400>;
3511 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3512 clock-names = "xo", "alternate";
3514 #interconnect-cells = <1>;
3517 cpufreq_hw: cpufreq@18323000 {
3518 compatible = "qcom,cpufreq-hw";
3519 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
3520 <0 0x18327800 0 0x1400>;
3521 reg-names = "freq-domain0", "freq-domain1",
3524 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3525 clock-names = "xo", "alternate";
3527 #freq-domain-cells = <1>;
3530 wifi: wifi@18800000 {
3531 compatible = "qcom,wcn3990-wifi";
3532 reg = <0 0x18800000 0 0x800000>;
3533 reg-names = "membase";
3534 memory-region = <&wlan_mem>;
3535 clock-names = "cxo_ref_clk_pin", "qdss";
3536 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
3537 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3538 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3539 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3540 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3546 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3547 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3549 iommus = <&apps_smmu 0x0640 0x1>;
3550 status = "disabled";
3555 compatible = "arm,armv8-timer";
3556 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
3557 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
3558 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
3559 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
3564 polling-delay-passive = <250>;
3565 polling-delay = <1000>;
3567 thermal-sensors = <&tsens0 1>;
3570 cpu0_alert0: trip-point0 {
3571 temperature = <90000>;
3572 hysteresis = <2000>;
3576 cpu0_alert1: trip-point1 {
3577 temperature = <95000>;
3578 hysteresis = <2000>;
3582 cpu0_crit: cpu_crit {
3583 temperature = <110000>;
3584 hysteresis = <1000>;
3591 trip = <&cpu0_alert0>;
3592 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3593 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3594 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3595 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3598 trip = <&cpu0_alert1>;
3599 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3600 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3601 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3602 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3608 polling-delay-passive = <250>;
3609 polling-delay = <1000>;
3611 thermal-sensors = <&tsens0 2>;
3614 cpu1_alert0: trip-point0 {
3615 temperature = <90000>;
3616 hysteresis = <2000>;
3620 cpu1_alert1: trip-point1 {
3621 temperature = <95000>;
3622 hysteresis = <2000>;
3626 cpu1_crit: cpu_crit {
3627 temperature = <110000>;
3628 hysteresis = <1000>;
3635 trip = <&cpu1_alert0>;
3636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3642 trip = <&cpu1_alert1>;
3643 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3644 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3646 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3652 polling-delay-passive = <250>;
3653 polling-delay = <1000>;
3655 thermal-sensors = <&tsens0 3>;
3658 cpu2_alert0: trip-point0 {
3659 temperature = <90000>;
3660 hysteresis = <2000>;
3664 cpu2_alert1: trip-point1 {
3665 temperature = <95000>;
3666 hysteresis = <2000>;
3670 cpu2_crit: cpu_crit {
3671 temperature = <110000>;
3672 hysteresis = <1000>;
3679 trip = <&cpu2_alert0>;
3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3686 trip = <&cpu2_alert1>;
3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3696 polling-delay-passive = <250>;
3697 polling-delay = <1000>;
3699 thermal-sensors = <&tsens0 4>;
3702 cpu3_alert0: trip-point0 {
3703 temperature = <90000>;
3704 hysteresis = <2000>;
3708 cpu3_alert1: trip-point1 {
3709 temperature = <95000>;
3710 hysteresis = <2000>;
3714 cpu3_crit: cpu_crit {
3715 temperature = <110000>;
3716 hysteresis = <1000>;
3723 trip = <&cpu3_alert0>;
3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3730 trip = <&cpu3_alert1>;
3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3732 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3733 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3734 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3740 polling-delay-passive = <250>;
3741 polling-delay = <1000>;
3743 thermal-sensors = <&tsens0 7>;
3746 cpu4_top_alert0: trip-point0 {
3747 temperature = <90000>;
3748 hysteresis = <2000>;
3752 cpu4_top_alert1: trip-point1 {
3753 temperature = <95000>;
3754 hysteresis = <2000>;
3758 cpu4_top_crit: cpu_crit {
3759 temperature = <110000>;
3760 hysteresis = <1000>;
3767 trip = <&cpu4_top_alert0>;
3768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3774 trip = <&cpu4_top_alert1>;
3775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3776 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3784 polling-delay-passive = <250>;
3785 polling-delay = <1000>;
3787 thermal-sensors = <&tsens0 8>;
3790 cpu5_top_alert0: trip-point0 {
3791 temperature = <90000>;
3792 hysteresis = <2000>;
3796 cpu5_top_alert1: trip-point1 {
3797 temperature = <95000>;
3798 hysteresis = <2000>;
3802 cpu5_top_crit: cpu_crit {
3803 temperature = <110000>;
3804 hysteresis = <1000>;
3811 trip = <&cpu5_top_alert0>;
3812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3818 trip = <&cpu5_top_alert1>;
3819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3820 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3821 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3822 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3828 polling-delay-passive = <250>;
3829 polling-delay = <1000>;
3831 thermal-sensors = <&tsens0 9>;
3834 cpu6_top_alert0: trip-point0 {
3835 temperature = <90000>;
3836 hysteresis = <2000>;
3840 cpu6_top_alert1: trip-point1 {
3841 temperature = <95000>;
3842 hysteresis = <2000>;
3846 cpu6_top_crit: cpu_crit {
3847 temperature = <110000>;
3848 hysteresis = <1000>;
3855 trip = <&cpu6_top_alert0>;
3856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3862 trip = <&cpu6_top_alert1>;
3863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3865 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3866 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3872 polling-delay-passive = <250>;
3873 polling-delay = <1000>;
3875 thermal-sensors = <&tsens0 10>;
3878 cpu7_top_alert0: trip-point0 {
3879 temperature = <90000>;
3880 hysteresis = <2000>;
3884 cpu7_top_alert1: trip-point1 {
3885 temperature = <95000>;
3886 hysteresis = <2000>;
3890 cpu7_top_crit: cpu_crit {
3891 temperature = <110000>;
3892 hysteresis = <1000>;
3899 trip = <&cpu7_top_alert0>;
3900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3901 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3902 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3903 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3906 trip = <&cpu7_top_alert1>;
3907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3909 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3910 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3915 cpu4-bottom-thermal {
3916 polling-delay-passive = <250>;
3917 polling-delay = <1000>;
3919 thermal-sensors = <&tsens0 11>;
3922 cpu4_bottom_alert0: trip-point0 {
3923 temperature = <90000>;
3924 hysteresis = <2000>;
3928 cpu4_bottom_alert1: trip-point1 {
3929 temperature = <95000>;
3930 hysteresis = <2000>;
3934 cpu4_bottom_crit: cpu_crit {
3935 temperature = <110000>;
3936 hysteresis = <1000>;
3943 trip = <&cpu4_bottom_alert0>;
3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3950 trip = <&cpu4_bottom_alert1>;
3951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3959 cpu5-bottom-thermal {
3960 polling-delay-passive = <250>;
3961 polling-delay = <1000>;
3963 thermal-sensors = <&tsens0 12>;
3966 cpu5_bottom_alert0: trip-point0 {
3967 temperature = <90000>;
3968 hysteresis = <2000>;
3972 cpu5_bottom_alert1: trip-point1 {
3973 temperature = <95000>;
3974 hysteresis = <2000>;
3978 cpu5_bottom_crit: cpu_crit {
3979 temperature = <110000>;
3980 hysteresis = <1000>;
3987 trip = <&cpu5_bottom_alert0>;
3988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3994 trip = <&cpu5_bottom_alert1>;
3995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3996 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3997 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4003 cpu6-bottom-thermal {
4004 polling-delay-passive = <250>;
4005 polling-delay = <1000>;
4007 thermal-sensors = <&tsens0 13>;
4010 cpu6_bottom_alert0: trip-point0 {
4011 temperature = <90000>;
4012 hysteresis = <2000>;
4016 cpu6_bottom_alert1: trip-point1 {
4017 temperature = <95000>;
4018 hysteresis = <2000>;
4022 cpu6_bottom_crit: cpu_crit {
4023 temperature = <110000>;
4024 hysteresis = <1000>;
4031 trip = <&cpu6_bottom_alert0>;
4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4038 trip = <&cpu6_bottom_alert1>;
4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4047 cpu7-bottom-thermal {
4048 polling-delay-passive = <250>;
4049 polling-delay = <1000>;
4051 thermal-sensors = <&tsens0 14>;
4054 cpu7_bottom_alert0: trip-point0 {
4055 temperature = <90000>;
4056 hysteresis = <2000>;
4060 cpu7_bottom_alert1: trip-point1 {
4061 temperature = <95000>;
4062 hysteresis = <2000>;
4066 cpu7_bottom_crit: cpu_crit {
4067 temperature = <110000>;
4068 hysteresis = <1000>;
4075 trip = <&cpu7_bottom_alert0>;
4076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4082 trip = <&cpu7_bottom_alert1>;
4083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4092 polling-delay-passive = <250>;
4093 polling-delay = <1000>;
4095 thermal-sensors = <&tsens0 0>;
4098 aoss0_alert0: trip-point0 {
4099 temperature = <90000>;
4100 hysteresis = <2000>;
4107 polling-delay-passive = <250>;
4108 polling-delay = <1000>;
4110 thermal-sensors = <&tsens0 5>;
4113 cluster0_alert0: trip-point0 {
4114 temperature = <90000>;
4115 hysteresis = <2000>;
4118 cluster0_crit: cluster0_crit {
4119 temperature = <110000>;
4120 hysteresis = <2000>;
4127 polling-delay-passive = <250>;
4128 polling-delay = <1000>;
4130 thermal-sensors = <&tsens0 6>;
4133 cluster1_alert0: trip-point0 {
4134 temperature = <90000>;
4135 hysteresis = <2000>;
4138 cluster1_crit: cluster1_crit {
4139 temperature = <110000>;
4140 hysteresis = <2000>;
4147 polling-delay-passive = <250>;
4148 polling-delay = <1000>;
4150 thermal-sensors = <&tsens0 15>;
4153 gpu1_alert0: trip-point0 {
4154 temperature = <90000>;
4155 hysteresis = <2000>;
4162 polling-delay-passive = <250>;
4163 polling-delay = <1000>;
4165 thermal-sensors = <&tsens1 0>;
4168 aoss1_alert0: trip-point0 {
4169 temperature = <90000>;
4170 hysteresis = <2000>;
4177 polling-delay-passive = <250>;
4178 polling-delay = <1000>;
4180 thermal-sensors = <&tsens1 1>;
4183 wlan_alert0: trip-point0 {
4184 temperature = <90000>;
4185 hysteresis = <2000>;
4192 polling-delay-passive = <250>;
4193 polling-delay = <1000>;
4195 thermal-sensors = <&tsens1 2>;
4198 video_alert0: trip-point0 {
4199 temperature = <90000>;
4200 hysteresis = <2000>;
4207 polling-delay-passive = <250>;
4208 polling-delay = <1000>;
4210 thermal-sensors = <&tsens1 3>;
4213 mem_alert0: trip-point0 {
4214 temperature = <90000>;
4215 hysteresis = <2000>;
4222 polling-delay-passive = <250>;
4223 polling-delay = <1000>;
4225 thermal-sensors = <&tsens1 4>;
4228 q6_hvx_alert0: trip-point0 {
4229 temperature = <90000>;
4230 hysteresis = <2000>;
4237 polling-delay-passive = <250>;
4238 polling-delay = <1000>;
4240 thermal-sensors = <&tsens1 5>;
4243 camera_alert0: trip-point0 {
4244 temperature = <90000>;
4245 hysteresis = <2000>;
4252 polling-delay-passive = <250>;
4253 polling-delay = <1000>;
4255 thermal-sensors = <&tsens1 6>;
4258 compute_alert0: trip-point0 {
4259 temperature = <90000>;
4260 hysteresis = <2000>;
4267 polling-delay-passive = <250>;
4268 polling-delay = <1000>;
4270 thermal-sensors = <&tsens1 7>;
4273 modem_alert0: trip-point0 {
4274 temperature = <90000>;
4275 hysteresis = <2000>;
4282 polling-delay-passive = <250>;
4283 polling-delay = <1000>;
4285 thermal-sensors = <&tsens1 8>;
4288 npu_alert0: trip-point0 {
4289 temperature = <90000>;
4290 hysteresis = <2000>;
4297 polling-delay-passive = <250>;
4298 polling-delay = <1000>;
4300 thermal-sensors = <&tsens1 9>;
4303 modem_vec_alert0: trip-point0 {
4304 temperature = <90000>;
4305 hysteresis = <2000>;
4312 polling-delay-passive = <250>;
4313 polling-delay = <1000>;
4315 thermal-sensors = <&tsens1 10>;
4318 modem_scl_alert0: trip-point0 {
4319 temperature = <90000>;
4320 hysteresis = <2000>;
4326 gpu-thermal-bottom {
4327 polling-delay-passive = <250>;
4328 polling-delay = <1000>;
4330 thermal-sensors = <&tsens1 11>;
4333 gpu2_alert0: trip-point0 {
4334 temperature = <90000>;
4335 hysteresis = <2000>;