arch/arm64/boot/dts/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/dma/qcom-gpi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/qcom-aoss-qmp.h>
  10 #include <dt-bindings/power/qcom-rpmpd.h>
  11 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <38400000>;
  31                         clock-output-names = "xo_board";
  32                 };
  33
  34                 sleep_clk: sleep-clk {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <32764>;
  38                         clock-output-names = "sleep_clk";
  39                 };
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 CPU0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "qcom,kryo485";
  49                         reg = <0x0 0x0>;
  50                         enable-method = "psci";
  51                         capacity-dmips-mhz = <488>;
  52                         dynamic-power-coefficient = <232>;
  53                         next-level-cache = <&L2_0>;
  54                         qcom,freq-domain = <&cpufreq_hw 0>;
  55                         power-domains = <&CPU_PD0>;
  56                         power-domain-names = "psci";
  57                         #cooling-cells = <2>;
  58                         L2_0: l2-cache {
  59                                 compatible = "cache";
  60                                 next-level-cache = <&L3_0>;
  61                                 L3_0: l3-cache {
  62                                       compatible = "cache";
  63                                 };
  64                         };
  65                 };
  66
  67                 CPU1: cpu@100 {
  68                         device_type = "cpu";
  69                         compatible = "qcom,kryo485";
  70                         reg = <0x0 0x100>;
  71                         enable-method = "psci";
  72                         capacity-dmips-mhz = <488>;
  73                         dynamic-power-coefficient = <232>;
  74                         next-level-cache = <&L2_100>;
  75                         qcom,freq-domain = <&cpufreq_hw 0>;
  76                         power-domains = <&CPU_PD1>;
  77                         power-domain-names = "psci";
  78                         #cooling-cells = <2>;
  79                         L2_100: l2-cache {
  80                                 compatible = "cache";
  81                                 next-level-cache = <&L3_0>;
  82                         };
  83
  84                 };
  85
  86                 CPU2: cpu@200 {
  87                         device_type = "cpu";
  88                         compatible = "qcom,kryo485";
  89                         reg = <0x0 0x200>;
  90                         enable-method = "psci";
  91                         capacity-dmips-mhz = <488>;
  92                         dynamic-power-coefficient = <232>;
  93                         next-level-cache = <&L2_200>;
  94                         qcom,freq-domain = <&cpufreq_hw 0>;
  95                         power-domains = <&CPU_PD2>;
  96                         power-domain-names = "psci";
  97                         #cooling-cells = <2>;
  98                         L2_200: l2-cache {
  99                                 compatible = "cache";
 100                                 next-level-cache = <&L3_0>;
 101                         };
 102                 };
 103
 104                 CPU3: cpu@300 {
 105                         device_type = "cpu";
 106                         compatible = "qcom,kryo485";
 107                         reg = <0x0 0x300>;
 108                         enable-method = "psci";
 109                         capacity-dmips-mhz = <488>;
 110                         dynamic-power-coefficient = <232>;
 111                         next-level-cache = <&L2_300>;
 112                         qcom,freq-domain = <&cpufreq_hw 0>;
 113                         power-domains = <&CPU_PD3>;
 114                         power-domain-names = "psci";
 115                         #cooling-cells = <2>;
 116                         L2_300: l2-cache {
 117                                 compatible = "cache";
 118                                 next-level-cache = <&L3_0>;
 119                         };
 120                 };
 121
 122                 CPU4: cpu@400 {
 123                         device_type = "cpu";
 124                         compatible = "qcom,kryo485";
 125                         reg = <0x0 0x400>;
 126                         enable-method = "psci";
 127                         capacity-dmips-mhz = <1024>;
 128                         dynamic-power-coefficient = <369>;
 129                         next-level-cache = <&L2_400>;
 130                         qcom,freq-domain = <&cpufreq_hw 1>;
 131                         power-domains = <&CPU_PD4>;
 132                         power-domain-names = "psci";
 133                         #cooling-cells = <2>;
 134                         L2_400: l2-cache {
 135                                 compatible = "cache";
 136                                 next-level-cache = <&L3_0>;
 137                         };
 138                 };
 139
 140                 CPU5: cpu@500 {
 141                         device_type = "cpu";
 142                         compatible = "qcom,kryo485";
 143                         reg = <0x0 0x500>;
 144                         enable-method = "psci";
 145                         capacity-dmips-mhz = <1024>;
 146                         dynamic-power-coefficient = <369>;
 147                         next-level-cache = <&L2_500>;
 148                         qcom,freq-domain = <&cpufreq_hw 1>;
 149                         power-domains = <&CPU_PD5>;
 150                         power-domain-names = "psci";
 151                         #cooling-cells = <2>;
 152                         L2_500: l2-cache {
 153                                 compatible = "cache";
 154                                 next-level-cache = <&L3_0>;
 155                         };
 156                 };
 157
 158                 CPU6: cpu@600 {
 159                         device_type = "cpu";
 160                         compatible = "qcom,kryo485";
 161                         reg = <0x0 0x600>;
 162                         enable-method = "psci";
 163                         capacity-dmips-mhz = <1024>;
 164                         dynamic-power-coefficient = <369>;
 165                         next-level-cache = <&L2_600>;
 166                         qcom,freq-domain = <&cpufreq_hw 1>;
 167                         power-domains = <&CPU_PD6>;
 168                         power-domain-names = "psci";
 169                         #cooling-cells = <2>;
 170                         L2_600: l2-cache {
 171                                 compatible = "cache";
 172                                 next-level-cache = <&L3_0>;
 173                         };
 174                 };
 175
 176                 CPU7: cpu@700 {
 177                         device_type = "cpu";
 178                         compatible = "qcom,kryo485";
 179                         reg = <0x0 0x700>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1024>;
 182                         dynamic-power-coefficient = <421>;
 183                         next-level-cache = <&L2_700>;
 184                         qcom,freq-domain = <&cpufreq_hw 2>;
 185                         power-domains = <&CPU_PD7>;
 186                         power-domain-names = "psci";
 187                         #cooling-cells = <2>;
 188                         L2_700: l2-cache {
 189                                 compatible = "cache";
 190                                 next-level-cache = <&L3_0>;
 191                         };
 192                 };
 193
 194                 cpu-map {
 195                         cluster0 {
 196                                 core0 {
 197                                         cpu = <&CPU0>;
 198                                 };
 199
 200                                 core1 {
 201                                         cpu = <&CPU1>;
 202                                 };
 203
 204                                 core2 {
 205                                         cpu = <&CPU2>;
 206                                 };
 207
 208                                 core3 {
 209                                         cpu = <&CPU3>;
 210                                 };
 211
 212                                 core4 {
 213                                         cpu = <&CPU4>;
 214                                 };
 215
 216                                 core5 {
 217                                         cpu = <&CPU5>;
 218                                 };
 219
 220                                 core6 {
 221                                         cpu = <&CPU6>;
 222                                 };
 223
 224                                 core7 {
 225                                         cpu = <&CPU7>;
 226                                 };
 227                         };
 228                 };
 229
 230                 idle-states {
 231                         entry-method = "psci";
 232
 233                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 234                                 compatible = "arm,idle-state";
 235                                 idle-state-name = "little-rail-power-collapse";
 236                                 arm,psci-suspend-param = <0x40000004>;
 237                                 entry-latency-us = <355>;
 238                                 exit-latency-us = <909>;
 239                                 min-residency-us = <3934>;
 240                                 local-timer-stop;
 241                         };
 242
 243                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 244                                 compatible = "arm,idle-state";
 245                                 idle-state-name = "big-rail-power-collapse";
 246                                 arm,psci-suspend-param = <0x40000004>;
 247                                 entry-latency-us = <241>;
 248                                 exit-latency-us = <1461>;
 249                                 min-residency-us = <4488>;
 250                                 local-timer-stop;
 251                         };
 252                 };
 253
 254                 domain-idle-states {
 255                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 256                                 compatible = "domain-idle-state";
 257                                 idle-state-name = "cluster-power-collapse";
 258                                 arm,psci-suspend-param = <0x4100c244>;
 259                                 entry-latency-us = <3263>;
 260                                 exit-latency-us = <6562>;
 261                                 min-residency-us = <9987>;
 262                                 local-timer-stop;
 263                         };
 264                 };
 265         };
 266
 267         firmware {
 268                 scm: scm {
 269                         compatible = "qcom,scm-sm8150", "qcom,scm";
 270                         #reset-cells = <1>;
 271                 };
 272         };
 273
 274         tcsr_mutex: hwlock {
 275                 compatible = "qcom,tcsr-mutex";
 276                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 277                 #hwlock-cells = <1>;
 278         };
 279
 280         memory@80000000 {
 281                 device_type = "memory";
 282                 /* We expect the bootloader to fill in the size */
 283                 reg = <0x0 0x80000000 0x0 0x0>;
 284         };
 285
 286         pmu {
 287                 compatible = "arm,armv8-pmuv3";
 288                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 289         };
 290
 291         psci {
 292                 compatible = "arm,psci-1.0";
 293                 method = "smc";
 294
 295                 CPU_PD0: cpu0 {
 296                         #power-domain-cells = <0>;
 297                         power-domains = <&CLUSTER_PD>;
 298                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 299                 };
 300
 301                 CPU_PD1: cpu1 {
 302                         #power-domain-cells = <0>;
 303                         power-domains = <&CLUSTER_PD>;
 304                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 305                 };
 306
 307                 CPU_PD2: cpu2 {
 308                         #power-domain-cells = <0>;
 309                         power-domains = <&CLUSTER_PD>;
 310                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 311                 };
 312
 313                 CPU_PD3: cpu3 {
 314                         #power-domain-cells = <0>;
 315                         power-domains = <&CLUSTER_PD>;
 316                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 317                 };
 318
 319                 CPU_PD4: cpu4 {
 320                         #power-domain-cells = <0>;
 321                         power-domains = <&CLUSTER_PD>;
 322                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 323                 };
 324
 325                 CPU_PD5: cpu5 {
 326                         #power-domain-cells = <0>;
 327                         power-domains = <&CLUSTER_PD>;
 328                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 329                 };
 330
 331                 CPU_PD6: cpu6 {
 332                         #power-domain-cells = <0>;
 333                         power-domains = <&CLUSTER_PD>;
 334                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 335                 };
 336
 337                 CPU_PD7: cpu7 {
 338                         #power-domain-cells = <0>;
 339                         power-domains = <&CLUSTER_PD>;
 340                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 341                 };
 342
 343                 CLUSTER_PD: cpu-cluster0 {
 344                         #power-domain-cells = <0>;
 345                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 346                 };
 347         };
 348
 349         reserved-memory {
 350                 #address-cells = <2>;
 351                 #size-cells = <2>;
 352                 ranges;
 353
 354                 hyp_mem: memory@85700000 {
 355                         reg = <0x0 0x85700000 0x0 0x600000>;
 356                         no-map;
 357                 };
 358
 359                 xbl_mem: memory@85d00000 {
 360                         reg = <0x0 0x85d00000 0x0 0x140000>;
 361                         no-map;
 362                 };
 363
 364                 aop_mem: memory@85f00000 {
 365                         reg = <0x0 0x85f00000 0x0 0x20000>;
 366                         no-map;
 367                 };
 368
 369                 aop_cmd_db: memory@85f20000 {
 370                         compatible = "qcom,cmd-db";
 371                         reg = <0x0 0x85f20000 0x0 0x20000>;
 372                         no-map;
 373                 };
 374
 375                 smem_mem: memory@86000000 {
 376                         reg = <0x0 0x86000000 0x0 0x200000>;
 377                         no-map;
 378                 };
 379
 380                 tz_mem: memory@86200000 {
 381                         reg = <0x0 0x86200000 0x0 0x3900000>;
 382                         no-map;
 383                 };
 384
 385                 rmtfs_mem: memory@89b00000 {
 386                         compatible = "qcom,rmtfs-mem";
 387                         reg = <0x0 0x89b00000 0x0 0x200000>;
 388                         no-map;
 389
 390                         qcom,client-id = <1>;
 391                         qcom,vmid = <15>;
 392                 };
 393
 394                 camera_mem: memory@8b700000 {
 395                         reg = <0x0 0x8b700000 0x0 0x500000>;
 396                         no-map;
 397                 };
 398
 399                 wlan_mem: memory@8bc00000 {
 400                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 401                         no-map;
 402                 };
 403
 404                 npu_mem: memory@8bd80000 {
 405                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 406                         no-map;
 407                 };
 408
 409                 adsp_mem: memory@8be00000 {
 410                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 411                         no-map;
 412                 };
 413
 414                 mpss_mem: memory@8d800000 {
 415                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 416                         no-map;
 417                 };
 418
 419                 venus_mem: memory@96e00000 {
 420                         reg = <0x0 0x96e00000 0x0 0x500000>;
 421                         no-map;
 422                 };
 423
 424                 slpi_mem: memory@97300000 {
 425                         reg = <0x0 0x97300000 0x0 0x1400000>;
 426                         no-map;
 427                 };
 428
 429                 ipa_fw_mem: memory@98700000 {
 430                         reg = <0x0 0x98700000 0x0 0x10000>;
 431                         no-map;
 432                 };
 433
 434                 ipa_gsi_mem: memory@98710000 {
 435                         reg = <0x0 0x98710000 0x0 0x5000>;
 436                         no-map;
 437                 };
 438
 439                 gpu_mem: memory@98715000 {
 440                         reg = <0x0 0x98715000 0x0 0x2000>;
 441                         no-map;
 442                 };
 443
 444                 spss_mem: memory@98800000 {
 445                         reg = <0x0 0x98800000 0x0 0x100000>;
 446                         no-map;
 447                 };
 448
 449                 cdsp_mem: memory@98900000 {
 450                         reg = <0x0 0x98900000 0x0 0x1400000>;
 451                         no-map;
 452                 };
 453
 454                 qseecom_mem: memory@9e400000 {
 455                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 456                         no-map;
 457                 };
 458         };
 459
 460         smem {
 461                 compatible = "qcom,smem";
 462                 memory-region = <&smem_mem>;
 463                 hwlocks = <&tcsr_mutex 3>;
 464         };
 465
 466         smp2p-cdsp {
 467                 compatible = "qcom,smp2p";
 468                 qcom,smem = <94>, <432>;
 469
 470                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 471
 472                 mboxes = <&apss_shared 6>;
 473
 474                 qcom,local-pid = <0>;
 475                 qcom,remote-pid = <5>;
 476
 477                 cdsp_smp2p_out: master-kernel {
 478                         qcom,entry-name = "master-kernel";
 479                         #qcom,smem-state-cells = <1>;
 480                 };
 481
 482                 cdsp_smp2p_in: slave-kernel {
 483                         qcom,entry-name = "slave-kernel";
 484
 485                         interrupt-controller;
 486                         #interrupt-cells = <2>;
 487                 };
 488         };
 489
 490         smp2p-lpass {
 491                 compatible = "qcom,smp2p";
 492                 qcom,smem = <443>, <429>;
 493
 494                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 495
 496                 mboxes = <&apss_shared 10>;
 497
 498                 qcom,local-pid = <0>;
 499                 qcom,remote-pid = <2>;
 500
 501                 adsp_smp2p_out: master-kernel {
 502                         qcom,entry-name = "master-kernel";
 503                         #qcom,smem-state-cells = <1>;
 504                 };
 505
 506                 adsp_smp2p_in: slave-kernel {
 507                         qcom,entry-name = "slave-kernel";
 508
 509                         interrupt-controller;
 510                         #interrupt-cells = <2>;
 511                 };
 512         };
 513
 514         smp2p-mpss {
 515                 compatible = "qcom,smp2p";
 516                 qcom,smem = <435>, <428>;
 517
 518                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 519
 520                 mboxes = <&apss_shared 14>;
 521
 522                 qcom,local-pid = <0>;
 523                 qcom,remote-pid = <1>;
 524
 525                 modem_smp2p_out: master-kernel {
 526                         qcom,entry-name = "master-kernel";
 527                         #qcom,smem-state-cells = <1>;
 528                 };
 529
 530                 modem_smp2p_in: slave-kernel {
 531                         qcom,entry-name = "slave-kernel";
 532
 533                         interrupt-controller;
 534                         #interrupt-cells = <2>;
 535                 };
 536         };
 537
 538         smp2p-slpi {
 539                 compatible = "qcom,smp2p";
 540                 qcom,smem = <481>, <430>;
 541
 542                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 543
 544                 mboxes = <&apss_shared 26>;
 545
 546                 qcom,local-pid = <0>;
 547                 qcom,remote-pid = <3>;
 548
 549                 slpi_smp2p_out: master-kernel {
 550                         qcom,entry-name = "master-kernel";
 551                         #qcom,smem-state-cells = <1>;
 552                 };
 553
 554                 slpi_smp2p_in: slave-kernel {
 555                         qcom,entry-name = "slave-kernel";
 556
 557                         interrupt-controller;
 558                         #interrupt-cells = <2>;
 559                 };
 560         };
 561
 562         soc: soc@0 {
 563                 #address-cells = <2>;
 564                 #size-cells = <2>;
 565                 ranges = <0 0 0 0 0x10 0>;
 566                 dma-ranges = <0 0 0 0 0x10 0>;
 567                 compatible = "simple-bus";
 568
 569                 gcc: clock-controller@100000 {
 570                         compatible = "qcom,gcc-sm8150";
 571                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 572                         #clock-cells = <1>;
 573                         #reset-cells = <1>;
 574                         #power-domain-cells = <1>;
 575                         clock-names = "bi_tcxo",
 576                                       "sleep_clk";
 577                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 578                                  <&sleep_clk>;
 579                 };
 580
 581                 gpi_dma0: dma-controller@800000 {
 582                         compatible = "qcom,sm8150-gpi-dma";
 583                         reg = <0 0x800000 0 0x60000>;
 584                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 597                         dma-channels = <13>;
 598                         dma-channel-mask = <0xfa>;
 599                         iommus = <&apps_smmu 0x00d6 0x0>;
 600                         #dma-cells = <3>;
 601                         status = "disabled";
 602                 };
 603
 604                 qupv3_id_0: geniqup@8c0000 {
 605                         compatible = "qcom,geni-se-qup";
 606                         reg = <0x0 0x008c0000 0x0 0x6000>;
 607                         clock-names = "m-ahb", "s-ahb";
 608                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 609                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 610                         iommus = <&apps_smmu 0xc3 0x0>;
 611                         #address-cells = <2>;
 612                         #size-cells = <2>;
 613                         ranges;
 614                         status = "disabled";
 615
 616                         i2c0: i2c@880000 {
 617                                 compatible = "qcom,geni-i2c";
 618                                 reg = <0 0x00880000 0 0x4000>;
 619                                 clock-names = "se";
 620                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 621                                 pinctrl-names = "default";
 622                                 pinctrl-0 = <&qup_i2c0_default>;
 623                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 624                                 #address-cells = <1>;
 625                                 #size-cells = <0>;
 626                                 status = "disabled";
 627                         };
 628
 629                         i2c1: i2c@884000 {
 630                                 compatible = "qcom,geni-i2c";
 631                                 reg = <0 0x00884000 0 0x4000>;
 632                                 clock-names = "se";
 633                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 634                                 pinctrl-names = "default";
 635                                 pinctrl-0 = <&qup_i2c1_default>;
 636                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 637                                 #address-cells = <1>;
 638                                 #size-cells = <0>;
 639                                 status = "disabled";
 640                         };
 641
 642                         i2c2: i2c@888000 {
 643                                 compatible = "qcom,geni-i2c";
 644                                 reg = <0 0x00888000 0 0x4000>;
 645                                 clock-names = "se";
 646                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 647                                 pinctrl-names = "default";
 648                                 pinctrl-0 = <&qup_i2c2_default>;
 649                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 650                                 #address-cells = <1>;
 651                                 #size-cells = <0>;
 652                                 status = "disabled";
 653                         };
 654
 655                         i2c3: i2c@88c000 {
 656                                 compatible = "qcom,geni-i2c";
 657                                 reg = <0 0x0088c000 0 0x4000>;
 658                                 clock-names = "se";
 659                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 660                                 pinctrl-names = "default";
 661                                 pinctrl-0 = <&qup_i2c3_default>;
 662                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665                                 status = "disabled";
 666                         };
 667
 668                         i2c4: i2c@890000 {
 669                                 compatible = "qcom,geni-i2c";
 670                                 reg = <0 0x00890000 0 0x4000>;
 671                                 clock-names = "se";
 672                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 673                                 pinctrl-names = "default";
 674                                 pinctrl-0 = <&qup_i2c4_default>;
 675                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 status = "disabled";
 679                         };
 680
 681                         i2c5: i2c@894000 {
 682                                 compatible = "qcom,geni-i2c";
 683                                 reg = <0 0x00894000 0 0x4000>;
 684                                 clock-names = "se";
 685                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 686                                 pinctrl-names = "default";
 687                                 pinctrl-0 = <&qup_i2c5_default>;
 688                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 689                                 #address-cells = <1>;
 690                                 #size-cells = <0>;
 691                                 status = "disabled";
 692                         };
 693
 694                         i2c6: i2c@898000 {
 695                                 compatible = "qcom,geni-i2c";
 696                                 reg = <0 0x00898000 0 0x4000>;
 697                                 clock-names = "se";
 698                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 699                                 pinctrl-names = "default";
 700                                 pinctrl-0 = <&qup_i2c6_default>;
 701                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 702                                 #address-cells = <1>;
 703                                 #size-cells = <0>;
 704                                 status = "disabled";
 705                         };
 706
 707                         i2c7: i2c@89c000 {
 708                                 compatible = "qcom,geni-i2c";
 709                                 reg = <0 0x0089c000 0 0x4000>;
 710                                 clock-names = "se";
 711                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 712                                 pinctrl-names = "default";
 713                                 pinctrl-0 = <&qup_i2c7_default>;
 714                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717                                 status = "disabled";
 718                         };
 719
 720                 };
 721
 722                 gpi_dma1: dma-controller@a00000 {
 723                         compatible = "qcom,sm8150-gpi-dma";
 724                         reg = <0 0xa00000 0 0x60000>;
 725                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 726                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 730                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 738                         dma-channels = <13>;
 739                         dma-channel-mask = <0xfa>;
 740                         iommus = <&apps_smmu 0x0616 0x0>;
 741                         #dma-cells = <3>;
 742                         status = "disabled";
 743                 };
 744
 745                 qupv3_id_1: geniqup@ac0000 {
 746                         compatible = "qcom,geni-se-qup";
 747                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 748                         clock-names = "m-ahb", "s-ahb";
 749                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 750                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 751                         iommus = <&apps_smmu 0x603 0x0>;
 752                         #address-cells = <2>;
 753                         #size-cells = <2>;
 754                         ranges;
 755                         status = "disabled";
 756
 757                         i2c8: i2c@a80000 {
 758                                 compatible = "qcom,geni-i2c";
 759                                 reg = <0 0x00a80000 0 0x4000>;
 760                                 clock-names = "se";
 761                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 762                                 pinctrl-names = "default";
 763                                 pinctrl-0 = <&qup_i2c8_default>;
 764                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 765                                 #address-cells = <1>;
 766                                 #size-cells = <0>;
 767                                 status = "disabled";
 768                         };
 769
 770                         i2c9: i2c@a84000 {
 771                                 compatible = "qcom,geni-i2c";
 772                                 reg = <0 0x00a84000 0 0x4000>;
 773                                 clock-names = "se";
 774                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 775                                 pinctrl-names = "default";
 776                                 pinctrl-0 = <&qup_i2c9_default>;
 777                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 778                                 #address-cells = <1>;
 779                                 #size-cells = <0>;
 780                                 status = "disabled";
 781                         };
 782
 783                         i2c10: i2c@a88000 {
 784                                 compatible = "qcom,geni-i2c";
 785                                 reg = <0 0x00a88000 0 0x4000>;
 786                                 clock-names = "se";
 787                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 788                                 pinctrl-names = "default";
 789                                 pinctrl-0 = <&qup_i2c10_default>;
 790                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                                 status = "disabled";
 794                         };
 795
 796                         i2c11: i2c@a8c000 {
 797                                 compatible = "qcom,geni-i2c";
 798                                 reg = <0 0x00a8c000 0 0x4000>;
 799                                 clock-names = "se";
 800                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 801                                 pinctrl-names = "default";
 802                                 pinctrl-0 = <&qup_i2c11_default>;
 803                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806                                 status = "disabled";
 807                         };
 808
 809                         uart2: serial@a90000 {
 810                                 compatible = "qcom,geni-debug-uart";
 811                                 reg = <0x0 0x00a90000 0x0 0x4000>;
 812                                 clock-names = "se";
 813                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 814                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 815                                 status = "disabled";
 816                         };
 817
 818                         i2c12: i2c@a90000 {
 819                                 compatible = "qcom,geni-i2c";
 820                                 reg = <0 0x00a90000 0 0x4000>;
 821                                 clock-names = "se";
 822                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 823                                 pinctrl-names = "default";
 824                                 pinctrl-0 = <&qup_i2c12_default>;
 825                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 826                                 #address-cells = <1>;
 827                                 #size-cells = <0>;
 828                                 status = "disabled";
 829                         };
 830
 831                         i2c16: i2c@94000 {
 832                                 compatible = "qcom,geni-i2c";
 833                                 reg = <0 0x0094000 0 0x4000>;
 834                                 clock-names = "se";
 835                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 836                                 pinctrl-names = "default";
 837                                 pinctrl-0 = <&qup_i2c16_default>;
 838                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 839                                 #address-cells = <1>;
 840                                 #size-cells = <0>;
 841                                 status = "disabled";
 842                         };
 843                 };
 844
 845                 gpi_dma2: dma-controller@c00000 {
 846                         compatible = "qcom,sm8150-gpi-dma";
 847                         reg = <0 0xc00000 0 0x60000>;
 848                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 849                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 850                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 851                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 852                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 853                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 854                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 855                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 856                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 857                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 858                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 859                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
 860                                      <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
 861                         dma-channels = <13>;
 862                         dma-channel-mask = <0xfa>;
 863                         iommus = <&apps_smmu 0x07b6 0x0>;
 864                         #dma-cells = <3>;
 865                         status = "disabled";
 866                 };
 867
 868                 qupv3_id_2: geniqup@cc0000 {
 869                         compatible = "qcom,geni-se-qup";
 870                         reg = <0x0 0x00cc0000 0x0 0x6000>;
 871
 872                         clock-names = "m-ahb", "s-ahb";
 873                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 874                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 875                         iommus = <&apps_smmu 0x7a3 0x0>;
 876                         #address-cells = <2>;
 877                         #size-cells = <2>;
 878                         ranges;
 879                         status = "disabled";
 880
 881                         i2c17: i2c@c80000 {
 882                                 compatible = "qcom,geni-i2c";
 883                                 reg = <0 0x00c80000 0 0x4000>;
 884                                 clock-names = "se";
 885                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 886                                 pinctrl-names = "default";
 887                                 pinctrl-0 = <&qup_i2c17_default>;
 888                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 status = "disabled";
 892                         };
 893
 894                         i2c18: i2c@c84000 {
 895                                 compatible = "qcom,geni-i2c";
 896                                 reg = <0 0x00c84000 0 0x4000>;
 897                                 clock-names = "se";
 898                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 899                                 pinctrl-names = "default";
 900                                 pinctrl-0 = <&qup_i2c18_default>;
 901                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 status = "disabled";
 905                         };
 906
 907                         i2c19: i2c@c88000 {
 908                                 compatible = "qcom,geni-i2c";
 909                                 reg = <0 0x00c88000 0 0x4000>;
 910                                 clock-names = "se";
 911                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&qup_i2c19_default>;
 914                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 status = "disabled";
 918                         };
 919
 920                         i2c13: i2c@c8c000 {
 921                                 compatible = "qcom,geni-i2c";
 922                                 reg = <0 0x00c8c000 0 0x4000>;
 923                                 clock-names = "se";
 924                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 925                                 pinctrl-names = "default";
 926                                 pinctrl-0 = <&qup_i2c13_default>;
 927                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 928                                 #address-cells = <1>;
 929                                 #size-cells = <0>;
 930                                 status = "disabled";
 931                         };
 932
 933                         i2c14: i2c@c90000 {
 934                                 compatible = "qcom,geni-i2c";
 935                                 reg = <0 0x00c90000 0 0x4000>;
 936                                 clock-names = "se";
 937                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 938                                 pinctrl-names = "default";
 939                                 pinctrl-0 = <&qup_i2c14_default>;
 940                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 941                                 #address-cells = <1>;
 942                                 #size-cells = <0>;
 943                                 status = "disabled";
 944                         };
 945
 946                         i2c15: i2c@c94000 {
 947                                 compatible = "qcom,geni-i2c";
 948                                 reg = <0 0x00c94000 0 0x4000>;
 949                                 clock-names = "se";
 950                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 951                                 pinctrl-names = "default";
 952                                 pinctrl-0 = <&qup_i2c15_default>;
 953                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 954                                 #address-cells = <1>;
 955                                 #size-cells = <0>;
 956                                 status = "disabled";
 957                         };
 958                 };
 959
 960                 config_noc: interconnect@1500000 {
 961                         compatible = "qcom,sm8150-config-noc";
 962                         reg = <0 0x01500000 0 0x7400>;
 963                         #interconnect-cells = <1>;
 964                         qcom,bcm-voters = <&apps_bcm_voter>;
 965                 };
 966
 967                 system_noc: interconnect@1620000 {
 968                         compatible = "qcom,sm8150-system-noc";
 969                         reg = <0 0x01620000 0 0x19400>;
 970                         #interconnect-cells = <1>;
 971                         qcom,bcm-voters = <&apps_bcm_voter>;
 972                 };
 973
 974                 mc_virt: interconnect@163a000 {
 975                         compatible = "qcom,sm8150-mc-virt";
 976                         reg = <0 0x0163a000 0 0x1000>;
 977                         #interconnect-cells = <1>;
 978                         qcom,bcm-voters = <&apps_bcm_voter>;
 979                 };
 980
 981                 aggre1_noc: interconnect@16e0000 {
 982                         compatible = "qcom,sm8150-aggre1-noc";
 983                         reg = <0 0x016e0000 0 0xd080>;
 984                         #interconnect-cells = <1>;
 985                         qcom,bcm-voters = <&apps_bcm_voter>;
 986                 };
 987
 988                 aggre2_noc: interconnect@1700000 {
 989                         compatible = "qcom,sm8150-aggre2-noc";
 990                         reg = <0 0x01700000 0 0x20000>;
 991                         #interconnect-cells = <1>;
 992                         qcom,bcm-voters = <&apps_bcm_voter>;
 993                 };
 994
 995                 compute_noc: interconnect@1720000 {
 996                         compatible = "qcom,sm8150-compute-noc";
 997                         reg = <0 0x01720000 0 0x7000>;
 998                         #interconnect-cells = <1>;
 999                         qcom,bcm-voters = <&apps_bcm_voter>;
1000                 };
1001
1002                 mmss_noc: interconnect@1740000 {
1003                         compatible = "qcom,sm8150-mmss-noc";
1004                         reg = <0 0x01740000 0 0x1c100>;
1005                         #interconnect-cells = <1>;
1006                         qcom,bcm-voters = <&apps_bcm_voter>;
1007                 };
1008
1009                 system-cache-controller@9200000 {
1010                         compatible = "qcom,sm8150-llcc";
1011                         reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1012                         reg-names = "llcc_base", "llcc_broadcast_base";
1013                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1014                 };
1015
1016                 ufs_mem_hc: ufshc@1d84000 {
1017                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
1018                                      "jedec,ufs-2.0";
1019                         reg = <0 0x01d84000 0 0x2500>;
1020                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1021                         phys = <&ufs_mem_phy_lanes>;
1022                         phy-names = "ufsphy";
1023                         lanes-per-direction = <2>;
1024                         #reset-cells = <1>;
1025                         resets = <&gcc GCC_UFS_PHY_BCR>;
1026                         reset-names = "rst";
1027
1028                         iommus = <&apps_smmu 0x300 0>;
1029
1030                         clock-names =
1031                                 "core_clk",
1032                                 "bus_aggr_clk",
1033                                 "iface_clk",
1034                                 "core_clk_unipro",
1035                                 "ref_clk",
1036                                 "tx_lane0_sync_clk",
1037                                 "rx_lane0_sync_clk",
1038                                 "rx_lane1_sync_clk";
1039                         clocks =
1040                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1041                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1042                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1043                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1044                                 <&rpmhcc RPMH_CXO_CLK>,
1045                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1046                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1047                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1048                         freq-table-hz =
1049                                 <37500000 300000000>,
1050                                 <0 0>,
1051                                 <0 0>,
1052                                 <37500000 300000000>,
1053                                 <0 0>,
1054                                 <0 0>,
1055                                 <0 0>,
1056                                 <0 0>;
1057
1058                         status = "disabled";
1059                 };
1060
1061                 ufs_mem_phy: phy@1d87000 {
1062                         compatible = "qcom,sm8150-qmp-ufs-phy";
1063                         reg = <0 0x01d87000 0 0x1c0>;
1064                         #address-cells = <2>;
1065                         #size-cells = <2>;
1066                         ranges;
1067                         clock-names = "ref",
1068                                       "ref_aux";
1069                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1070                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1071
1072                         resets = <&ufs_mem_hc 0>;
1073                         reset-names = "ufsphy";
1074                         status = "disabled";
1075
1076                         ufs_mem_phy_lanes: lanes@1d87400 {
1077                                 reg = <0 0x01d87400 0 0x108>,
1078                                       <0 0x01d87600 0 0x1e0>,
1079                                       <0 0x01d87c00 0 0x1dc>,
1080                                       <0 0x01d87800 0 0x108>,
1081                                       <0 0x01d87a00 0 0x1e0>;
1082                                 #phy-cells = <0>;
1083                         };
1084                 };
1085
1086                 ipa_virt: interconnect@1e00000 {
1087                         compatible = "qcom,sm8150-ipa-virt";
1088                         reg = <0 0x01e00000 0 0x1000>;
1089                         #interconnect-cells = <1>;
1090                         qcom,bcm-voters = <&apps_bcm_voter>;
1091                 };
1092
1093                 tcsr_mutex_regs: syscon@1f40000 {
1094                         compatible = "syscon";
1095                         reg = <0x0 0x01f40000 0x0 0x40000>;
1096                 };
1097
1098                 remoteproc_slpi: remoteproc@2400000 {
1099                         compatible = "qcom,sm8150-slpi-pas";
1100                         reg = <0x0 0x02400000 0x0 0x4040>;
1101
1102                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
1103                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1104                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1105                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1106                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1107                         interrupt-names = "wdog", "fatal", "ready",
1108                                           "handover", "stop-ack";
1109
1110                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1111                         clock-names = "xo";
1112
1113                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1114                                         <&rpmhpd 3>,
1115                                         <&rpmhpd 2>;
1116                         power-domain-names = "load_state", "lcx", "lmx";
1117
1118                         memory-region = <&slpi_mem>;
1119
1120                         qcom,smem-states = <&slpi_smp2p_out 0>;
1121                         qcom,smem-state-names = "stop";
1122
1123                         status = "disabled";
1124
1125                         glink-edge {
1126                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
1127                                 label = "dsps";
1128                                 qcom,remote-pid = <3>;
1129                                 mboxes = <&apss_shared 24>;
1130                         };
1131                 };
1132
1133                 gpu: gpu@2c00000 {
1134                         /*
1135                          * note: the amd,imageon compatible makes it possible
1136                          * to use the drm/msm driver without the display node,
1137                          * make sure to remove it when display node is added
1138                          */
1139                         compatible = "qcom,adreno-640.1",
1140                                      "qcom,adreno",
1141                                      "amd,imageon";
1142                         #stream-id-cells = <16>;
1143
1144                         reg = <0 0x02c00000 0 0x40000>;
1145                         reg-names = "kgsl_3d0_reg_memory";
1146
1147                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1148
1149                         iommus = <&adreno_smmu 0 0x401>;
1150
1151                         operating-points-v2 = <&gpu_opp_table>;
1152
1153                         qcom,gmu = <&gmu>;
1154
1155                         zap-shader {
1156                                 memory-region = <&gpu_mem>;
1157                         };
1158
1159                         /* note: downstream checks gpu binning for 675 Mhz */
1160                         gpu_opp_table: opp-table {
1161                                 compatible = "operating-points-v2";
1162
1163                                 opp-675000000 {
1164                                         opp-hz = /bits/ 64 <675000000>;
1165                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1166                                 };
1167
1168                                 opp-585000000 {
1169                                         opp-hz = /bits/ 64 <585000000>;
1170                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1171                                 };
1172
1173                                 opp-499200000 {
1174                                         opp-hz = /bits/ 64 <499200000>;
1175                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1176                                 };
1177
1178                                 opp-427000000 {
1179                                         opp-hz = /bits/ 64 <427000000>;
1180                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1181                                 };
1182
1183                                 opp-345000000 {
1184                                         opp-hz = /bits/ 64 <345000000>;
1185                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1186                                 };
1187
1188                                 opp-257000000 {
1189                                         opp-hz = /bits/ 64 <257000000>;
1190                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1191                                 };
1192                         };
1193                 };
1194
1195                 gmu: gmu@2c6a000 {
1196                         compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
1197
1198                         reg = <0 0x02c6a000 0 0x30000>,
1199                               <0 0x0b290000 0 0x10000>,
1200                               <0 0x0b490000 0 0x10000>;
1201                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1202
1203                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1205                         interrupt-names = "hfi", "gmu";
1206
1207                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1208                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1209                                  <&gpucc GPU_CC_CXO_CLK>,
1210                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1211                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1212                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1213
1214                         power-domains = <&gpucc GPU_CX_GDSC>,
1215                                         <&gpucc GPU_GX_GDSC>;
1216                         power-domain-names = "cx", "gx";
1217
1218                         iommus = <&adreno_smmu 5 0x400>;
1219
1220                         operating-points-v2 = <&gmu_opp_table>;
1221
1222                         gmu_opp_table: opp-table {
1223                                 compatible = "operating-points-v2";
1224
1225                                 opp-200000000 {
1226                                         opp-hz = /bits/ 64 <200000000>;
1227                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1228                                 };
1229                         };
1230                 };
1231
1232                 gpucc: clock-controller@2c90000 {
1233                         compatible = "qcom,sm8150-gpucc";
1234                         reg = <0 0x02c90000 0 0x9000>;
1235                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1236                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1237                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1238                         clock-names = "bi_tcxo",
1239                                       "gcc_gpu_gpll0_clk_src",
1240                                       "gcc_gpu_gpll0_div_clk_src";
1241                         #clock-cells = <1>;
1242                         #reset-cells = <1>;
1243                         #power-domain-cells = <1>;
1244                 };
1245
1246                 adreno_smmu: iommu@2ca0000 {
1247                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
1248                         reg = <0 0x02ca0000 0 0x10000>;
1249                         #iommu-cells = <2>;
1250                         #global-interrupts = <1>;
1251                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
1252                                 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1253                                 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1254                                 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1255                                 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1256                                 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1257                                 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1258                                 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
1259                                 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
1260                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1261                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1262                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1263                         clock-names = "ahb", "bus", "iface";
1264
1265                         power-domains = <&gpucc GPU_CX_GDSC>;
1266                 };
1267
1268                 tlmm: pinctrl@3100000 {
1269                         compatible = "qcom,sm8150-pinctrl";
1270                         reg = <0x0 0x03100000 0x0 0x300000>,
1271                               <0x0 0x03500000 0x0 0x300000>,
1272                               <0x0 0x03900000 0x0 0x300000>,
1273                               <0x0 0x03D00000 0x0 0x300000>;
1274                         reg-names = "west", "east", "north", "south";
1275                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1276                         gpio-ranges = <&tlmm 0 0 176>;
1277                         gpio-controller;
1278                         #gpio-cells = <2>;
1279                         interrupt-controller;
1280                         #interrupt-cells = <2>;
1281
1282                         qup_i2c0_default: qup-i2c0-default {
1283                                 mux {
1284                                         pins = "gpio0", "gpio1";
1285                                         function = "qup0";
1286                                 };
1287
1288                                 config {
1289                                         pins = "gpio0", "gpio1";
1290                                         drive-strength = <0x02>;
1291                                         bias-disable;
1292                                 };
1293                         };
1294
1295                         qup_i2c1_default: qup-i2c1-default {
1296                                 mux {
1297                                         pins = "gpio114", "gpio115";
1298                                         function = "qup1";
1299                                 };
1300
1301                                 config {
1302                                         pins = "gpio114", "gpio115";
1303                                         drive-strength = <0x02>;
1304                                         bias-disable;
1305                                 };
1306                         };
1307
1308                         qup_i2c2_default: qup-i2c2-default {
1309                                 mux {
1310                                         pins = "gpio126", "gpio127";
1311                                         function = "qup2";
1312                                 };
1313
1314                                 config {
1315                                         pins = "gpio126", "gpio127";
1316                                         drive-strength = <0x02>;
1317                                         bias-disable;
1318                                 };
1319                         };
1320
1321                         qup_i2c3_default: qup-i2c3-default {
1322                                 mux {
1323                                         pins = "gpio144", "gpio145";
1324                                         function = "qup3";
1325                                 };
1326
1327                                 config {
1328                                         pins = "gpio144", "gpio145";
1329                                         drive-strength = <0x02>;
1330                                         bias-disable;
1331                                 };
1332                         };
1333
1334                         qup_i2c4_default: qup-i2c4-default {
1335                                 mux {
1336                                         pins = "gpio51", "gpio52";
1337                                         function = "qup4";
1338                                 };
1339
1340                                 config {
1341                                         pins = "gpio51", "gpio52";
1342                                         drive-strength = <0x02>;
1343                                         bias-disable;
1344                                 };
1345                         };
1346
1347                         qup_i2c5_default: qup-i2c5-default {
1348                                 mux {
1349                                         pins = "gpio121", "gpio122";
1350                                         function = "qup5";
1351                                 };
1352
1353                                 config {
1354                                         pins = "gpio121", "gpio122";
1355                                         drive-strength = <0x02>;
1356                                         bias-disable;
1357                                 };
1358                         };
1359
1360                         qup_i2c6_default: qup-i2c6-default {
1361                                 mux {
1362                                         pins = "gpio6", "gpio7";
1363                                         function = "qup6";
1364                                 };
1365
1366                                 config {
1367                                         pins = "gpio6", "gpio7";
1368                                         drive-strength = <0x02>;
1369                                         bias-disable;
1370                                 };
1371                         };
1372
1373                         qup_i2c7_default: qup-i2c7-default {
1374                                 mux {
1375                                         pins = "gpio98", "gpio99";
1376                                         function = "qup7";
1377                                 };
1378
1379                                 config {
1380                                         pins = "gpio98", "gpio99";
1381                                         drive-strength = <0x02>;
1382                                         bias-disable;
1383                                 };
1384                         };
1385
1386                         qup_i2c8_default: qup-i2c8-default {
1387                                 mux {
1388                                         pins = "gpio88", "gpio89";
1389                                         function = "qup8";
1390                                 };
1391
1392                                 config {
1393                                         pins = "gpio88", "gpio89";
1394                                         drive-strength = <0x02>;
1395                                         bias-disable;
1396                                 };
1397                         };
1398
1399                         qup_i2c9_default: qup-i2c9-default {
1400                                 mux {
1401                                         pins = "gpio39", "gpio40";
1402                                         function = "qup9";
1403                                 };
1404
1405                                 config {
1406                                         pins = "gpio39", "gpio40";
1407                                         drive-strength = <0x02>;
1408                                         bias-disable;
1409                                 };
1410                         };
1411
1412                         qup_i2c10_default: qup-i2c10-default {
1413                                 mux {
1414                                         pins = "gpio9", "gpio10";
1415                                         function = "qup10";
1416                                 };
1417
1418                                 config {
1419                                         pins = "gpio9", "gpio10";
1420                                         drive-strength = <0x02>;
1421                                         bias-disable;
1422                                 };
1423                         };
1424
1425                         qup_i2c11_default: qup-i2c11-default {
1426                                 mux {
1427                                         pins = "gpio94", "gpio95";
1428                                         function = "qup11";
1429                                 };
1430
1431                                 config {
1432                                         pins = "gpio94", "gpio95";
1433                                         drive-strength = <0x02>;
1434                                         bias-disable;
1435                                 };
1436                         };
1437
1438                         qup_i2c12_default: qup-i2c12-default {
1439                                 mux {
1440                                         pins = "gpio83", "gpio84";
1441                                         function = "qup12";
1442                                 };
1443
1444                                 config {
1445                                         pins = "gpio83", "gpio84";
1446                                         drive-strength = <0x02>;
1447                                         bias-disable;
1448                                 };
1449                         };
1450
1451                         qup_i2c13_default: qup-i2c13-default {
1452                                 mux {
1453                                         pins = "gpio43", "gpio44";
1454                                         function = "qup13";
1455                                 };
1456
1457                                 config {
1458                                         pins = "gpio43", "gpio44";
1459                                         drive-strength = <0x02>;
1460                                         bias-disable;
1461                                 };
1462                         };
1463
1464                         qup_i2c14_default: qup-i2c14-default {
1465                                 mux {
1466                                         pins = "gpio47", "gpio48";
1467                                         function = "qup14";
1468                                 };
1469
1470                                 config {
1471                                         pins = "gpio47", "gpio48";
1472                                         drive-strength = <0x02>;
1473                                         bias-disable;
1474                                 };
1475                         };
1476
1477                         qup_i2c15_default: qup-i2c15-default {
1478                                 mux {
1479                                         pins = "gpio27", "gpio28";
1480                                         function = "qup15";
1481                                 };
1482
1483                                 config {
1484                                         pins = "gpio27", "gpio28";
1485                                         drive-strength = <0x02>;
1486                                         bias-disable;
1487                                 };
1488                         };
1489
1490                         qup_i2c16_default: qup-i2c16-default {
1491                                 mux {
1492                                         pins = "gpio86", "gpio85";
1493                                         function = "qup16";
1494                                 };
1495
1496                                 config {
1497                                         pins = "gpio86", "gpio85";
1498                                         drive-strength = <0x02>;
1499                                         bias-disable;
1500                                 };
1501                         };
1502
1503                         qup_i2c17_default: qup-i2c17-default {
1504                                 mux {
1505                                         pins = "gpio55", "gpio56";
1506                                         function = "qup17";
1507                                 };
1508
1509                                 config {
1510                                         pins = "gpio55", "gpio56";
1511                                         drive-strength = <0x02>;
1512                                         bias-disable;
1513                                 };
1514                         };
1515
1516                         qup_i2c18_default: qup-i2c18-default {
1517                                 mux {
1518                                         pins = "gpio23", "gpio24";
1519                                         function = "qup18";
1520                                 };
1521
1522                                 config {
1523                                         pins = "gpio23", "gpio24";
1524                                         drive-strength = <0x02>;
1525                                         bias-disable;
1526                                 };
1527                         };
1528
1529                         qup_i2c19_default: qup-i2c19-default {
1530                                 mux {
1531                                         pins = "gpio57", "gpio58";
1532                                         function = "qup19";
1533                                 };
1534
1535                                 config {
1536                                         pins = "gpio57", "gpio58";
1537                                         drive-strength = <0x02>;
1538                                         bias-disable;
1539                                 };
1540                         };
1541                 };
1542
1543                 remoteproc_mpss: remoteproc@4080000 {
1544                         compatible = "qcom,sm8150-mpss-pas";
1545                         reg = <0x0 0x04080000 0x0 0x4040>;
1546
1547                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1548                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1549                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1550                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1551                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1552                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1553                         interrupt-names = "wdog", "fatal", "ready", "handover",
1554                                           "stop-ack", "shutdown-ack";
1555
1556                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1557                         clock-names = "xo";
1558
1559                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1560                                         <&rpmhpd 7>,
1561                                         <&rpmhpd 0>;
1562                         power-domain-names = "load_state", "cx", "mss";
1563
1564                         memory-region = <&mpss_mem>;
1565
1566                         qcom,smem-states = <&modem_smp2p_out 0>;
1567                         qcom,smem-state-names = "stop";
1568
1569                         glink-edge {
1570                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1571                                 label = "modem";
1572                                 qcom,remote-pid = <1>;
1573                                 mboxes = <&apss_shared 12>;
1574                         };
1575                 };
1576
1577                 stm@6002000 {
1578                         compatible = "arm,coresight-stm", "arm,primecell";
1579                         reg = <0 0x06002000 0 0x1000>,
1580                               <0 0x16280000 0 0x180000>;
1581                         reg-names = "stm-base", "stm-stimulus-base";
1582
1583                         clocks = <&aoss_qmp>;
1584                         clock-names = "apb_pclk";
1585
1586                         out-ports {
1587                                 port {
1588                                         stm_out: endpoint {
1589                                                 remote-endpoint = <&funnel0_in7>;
1590                                         };
1591                                 };
1592                         };
1593                 };
1594
1595                 funnel@6041000 {
1596                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1597                         reg = <0 0x06041000 0 0x1000>;
1598
1599                         clocks = <&aoss_qmp>;
1600                         clock-names = "apb_pclk";
1601
1602                         out-ports {
1603                                 port {
1604                                         funnel0_out: endpoint {
1605                                                 remote-endpoint = <&merge_funnel_in0>;
1606                                         };
1607                                 };
1608                         };
1609
1610                         in-ports {
1611                                 #address-cells = <1>;
1612                                 #size-cells = <0>;
1613
1614                                 port@7 {
1615                                         reg = <7>;
1616                                         funnel0_in7: endpoint {
1617                                                 remote-endpoint = <&stm_out>;
1618                                         };
1619                                 };
1620                         };
1621                 };
1622
1623                 funnel@6042000 {
1624                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1625                         reg = <0 0x06042000 0 0x1000>;
1626
1627                         clocks = <&aoss_qmp>;
1628                         clock-names = "apb_pclk";
1629
1630                         out-ports {
1631                                 port {
1632                                         funnel1_out: endpoint {
1633                                                 remote-endpoint = <&merge_funnel_in1>;
1634                                         };
1635                                 };
1636                         };
1637
1638                         in-ports {
1639                                 #address-cells = <1>;
1640                                 #size-cells = <0>;
1641
1642                                 port@4 {
1643                                         reg = <4>;
1644                                         funnel1_in4: endpoint {
1645                                                 remote-endpoint = <&swao_replicator_out>;
1646                                         };
1647                                 };
1648                         };
1649                 };
1650
1651                 funnel@6043000 {
1652                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1653                         reg = <0 0x06043000 0 0x1000>;
1654
1655                         clocks = <&aoss_qmp>;
1656                         clock-names = "apb_pclk";
1657
1658                         out-ports {
1659                                 port {
1660                                         funnel2_out: endpoint {
1661                                                 remote-endpoint = <&merge_funnel_in2>;
1662                                         };
1663                                 };
1664                         };
1665
1666                         in-ports {
1667                                 #address-cells = <1>;
1668                                 #size-cells = <0>;
1669
1670                                 port@2 {
1671                                         reg = <2>;
1672                                         funnel2_in2: endpoint {
1673                                                 remote-endpoint = <&apss_merge_funnel_out>;
1674                                         };
1675                                 };
1676                         };
1677                 };
1678
1679                 funnel@6045000 {
1680                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1681                         reg = <0 0x06045000 0 0x1000>;
1682
1683                         clocks = <&aoss_qmp>;
1684                         clock-names = "apb_pclk";
1685
1686                         out-ports {
1687                                 port {
1688                                         merge_funnel_out: endpoint {
1689                                                 remote-endpoint = <&etf_in>;
1690                                         };
1691                                 };
1692                         };
1693
1694                         in-ports {
1695                                 #address-cells = <1>;
1696                                 #size-cells = <0>;
1697
1698                                 port@0 {
1699                                         reg = <0>;
1700                                         merge_funnel_in0: endpoint {
1701                                                 remote-endpoint = <&funnel0_out>;
1702                                         };
1703                                 };
1704
1705                                 port@1 {
1706                                         reg = <1>;
1707                                         merge_funnel_in1: endpoint {
1708                                                 remote-endpoint = <&funnel1_out>;
1709                                         };
1710                                 };
1711
1712                                 port@2 {
1713                                         reg = <2>;
1714                                         merge_funnel_in2: endpoint {
1715                                                 remote-endpoint = <&funnel2_out>;
1716                                         };
1717                                 };
1718                         };
1719                 };
1720
1721                 replicator@6046000 {
1722                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1723                         reg = <0 0x06046000 0 0x1000>;
1724
1725                         clocks = <&aoss_qmp>;
1726                         clock-names = "apb_pclk";
1727
1728                         out-ports {
1729                                 #address-cells = <1>;
1730                                 #size-cells = <0>;
1731
1732                                 port@0 {
1733                                         reg = <0>;
1734                                         replicator_out0: endpoint {
1735                                                 remote-endpoint = <&etr_in>;
1736                                         };
1737                                 };
1738
1739                                 port@1 {
1740                                         reg = <1>;
1741                                         replicator_out1: endpoint {
1742                                                 remote-endpoint = <&replicator1_in>;
1743                                         };
1744                                 };
1745                         };
1746
1747                         in-ports {
1748                                 port {
1749                                         replicator_in0: endpoint {
1750                                                 remote-endpoint = <&etf_out>;
1751                                         };
1752                                 };
1753                         };
1754                 };
1755
1756                 etf@6047000 {
1757                         compatible = "arm,coresight-tmc", "arm,primecell";
1758                         reg = <0 0x06047000 0 0x1000>;
1759
1760                         clocks = <&aoss_qmp>;
1761                         clock-names = "apb_pclk";
1762
1763                         out-ports {
1764                                 port {
1765                                         etf_out: endpoint {
1766                                                 remote-endpoint = <&replicator_in0>;
1767                                         };
1768                                 };
1769                         };
1770
1771                         in-ports {
1772                                 port {
1773                                         etf_in: endpoint {
1774                                                 remote-endpoint = <&merge_funnel_out>;
1775                                         };
1776                                 };
1777                         };
1778                 };
1779
1780                 etr@6048000 {
1781                         compatible = "arm,coresight-tmc", "arm,primecell";
1782                         reg = <0 0x06048000 0 0x1000>;
1783                         iommus = <&apps_smmu 0x05e0 0x0>;
1784
1785                         clocks = <&aoss_qmp>;
1786                         clock-names = "apb_pclk";
1787                         arm,scatter-gather;
1788
1789                         in-ports {
1790                                 port {
1791                                         etr_in: endpoint {
1792                                                 remote-endpoint = <&replicator_out0>;
1793                                         };
1794                                 };
1795                         };
1796                 };
1797
1798                 replicator@604a000 {
1799                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1800                         reg = <0 0x0604a000 0 0x1000>;
1801
1802                         clocks = <&aoss_qmp>;
1803                         clock-names = "apb_pclk";
1804
1805                         out-ports {
1806                                 #address-cells = <1>;
1807                                 #size-cells = <0>;
1808
1809                                 port@1 {
1810                                         reg = <1>;
1811                                         replicator1_out: endpoint {
1812                                                 remote-endpoint = <&swao_funnel_in>;
1813                                         };
1814                                 };
1815                         };
1816
1817                         in-ports {
1818                                 #address-cells = <1>;
1819                                 #size-cells = <0>;
1820
1821                                 port@1 {
1822                                         reg = <1>;
1823                                         replicator1_in: endpoint {
1824                                                 remote-endpoint = <&replicator_out1>;
1825                                         };
1826                                 };
1827                         };
1828                 };
1829
1830                 funnel@6b08000 {
1831                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1832                         reg = <0 0x06b08000 0 0x1000>;
1833
1834                         clocks = <&aoss_qmp>;
1835                         clock-names = "apb_pclk";
1836
1837                         out-ports {
1838                                 port {
1839                                         swao_funnel_out: endpoint {
1840                                                 remote-endpoint = <&swao_etf_in>;
1841                                         };
1842                                 };
1843                         };
1844
1845                         in-ports {
1846                                 #address-cells = <1>;
1847                                 #size-cells = <0>;
1848
1849                                 port@6 {
1850                                         reg = <6>;
1851                                         swao_funnel_in: endpoint {
1852                                                 remote-endpoint = <&replicator1_out>;
1853                                         };
1854                                 };
1855                         };
1856                 };
1857
1858                 etf@6b09000 {
1859                         compatible = "arm,coresight-tmc", "arm,primecell";
1860                         reg = <0 0x06b09000 0 0x1000>;
1861
1862                         clocks = <&aoss_qmp>;
1863                         clock-names = "apb_pclk";
1864
1865                         out-ports {
1866                                 port {
1867                                         swao_etf_out: endpoint {
1868                                                 remote-endpoint = <&swao_replicator_in>;
1869                                         };
1870                                 };
1871                         };
1872
1873                         in-ports {
1874                                 port {
1875                                         swao_etf_in: endpoint {
1876                                                 remote-endpoint = <&swao_funnel_out>;
1877                                         };
1878                                 };
1879                         };
1880                 };
1881
1882                 replicator@6b0a000 {
1883                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1884                         reg = <0 0x06b0a000 0 0x1000>;
1885
1886                         clocks = <&aoss_qmp>;
1887                         clock-names = "apb_pclk";
1888                         qcom,replicator-loses-context;
1889
1890                         out-ports {
1891                                 port {
1892                                         swao_replicator_out: endpoint {
1893                                                 remote-endpoint = <&funnel1_in4>;
1894                                         };
1895                                 };
1896                         };
1897
1898                         in-ports {
1899                                 port {
1900                                         swao_replicator_in: endpoint {
1901                                                 remote-endpoint = <&swao_etf_out>;
1902                                         };
1903                                 };
1904                         };
1905                 };
1906
1907                 etm@7040000 {
1908                         compatible = "arm,coresight-etm4x", "arm,primecell";
1909                         reg = <0 0x07040000 0 0x1000>;
1910
1911                         cpu = <&CPU0>;
1912
1913                         clocks = <&aoss_qmp>;
1914                         clock-names = "apb_pclk";
1915                         arm,coresight-loses-context-with-cpu;
1916                         qcom,skip-power-up;
1917
1918                         out-ports {
1919                                 port {
1920                                         etm0_out: endpoint {
1921                                                 remote-endpoint = <&apss_funnel_in0>;
1922                                         };
1923                                 };
1924                         };
1925                 };
1926
1927                 etm@7140000 {
1928                         compatible = "arm,coresight-etm4x", "arm,primecell";
1929                         reg = <0 0x07140000 0 0x1000>;
1930
1931                         cpu = <&CPU1>;
1932
1933                         clocks = <&aoss_qmp>;
1934                         clock-names = "apb_pclk";
1935                         arm,coresight-loses-context-with-cpu;
1936                         qcom,skip-power-up;
1937
1938                         out-ports {
1939                                 port {
1940                                         etm1_out: endpoint {
1941                                                 remote-endpoint = <&apss_funnel_in1>;
1942                                         };
1943                                 };
1944                         };
1945                 };
1946
1947                 etm@7240000 {
1948                         compatible = "arm,coresight-etm4x", "arm,primecell";
1949                         reg = <0 0x07240000 0 0x1000>;
1950
1951                         cpu = <&CPU2>;
1952
1953                         clocks = <&aoss_qmp>;
1954                         clock-names = "apb_pclk";
1955                         arm,coresight-loses-context-with-cpu;
1956                         qcom,skip-power-up;
1957
1958                         out-ports {
1959                                 port {
1960                                         etm2_out: endpoint {
1961                                                 remote-endpoint = <&apss_funnel_in2>;
1962                                         };
1963                                 };
1964                         };
1965                 };
1966
1967                 etm@7340000 {
1968                         compatible = "arm,coresight-etm4x", "arm,primecell";
1969                         reg = <0 0x07340000 0 0x1000>;
1970
1971                         cpu = <&CPU3>;
1972
1973                         clocks = <&aoss_qmp>;
1974                         clock-names = "apb_pclk";
1975                         arm,coresight-loses-context-with-cpu;
1976                         qcom,skip-power-up;
1977
1978                         out-ports {
1979                                 port {
1980                                         etm3_out: endpoint {
1981                                                 remote-endpoint = <&apss_funnel_in3>;
1982                                         };
1983                                 };
1984                         };
1985                 };
1986
1987                 etm@7440000 {
1988                         compatible = "arm,coresight-etm4x", "arm,primecell";
1989                         reg = <0 0x07440000 0 0x1000>;
1990
1991                         cpu = <&CPU4>;
1992
1993                         clocks = <&aoss_qmp>;
1994                         clock-names = "apb_pclk";
1995                         arm,coresight-loses-context-with-cpu;
1996                         qcom,skip-power-up;
1997
1998                         out-ports {
1999                                 port {
2000                                         etm4_out: endpoint {
2001                                                 remote-endpoint = <&apss_funnel_in4>;
2002                                         };
2003                                 };
2004                         };
2005                 };
2006
2007                 etm@7540000 {
2008                         compatible = "arm,coresight-etm4x", "arm,primecell";
2009                         reg = <0 0x07540000 0 0x1000>;
2010
2011                         cpu = <&CPU5>;
2012
2013                         clocks = <&aoss_qmp>;
2014                         clock-names = "apb_pclk";
2015                         arm,coresight-loses-context-with-cpu;
2016                         qcom,skip-power-up;
2017
2018                         out-ports {
2019                                 port {
2020                                         etm5_out: endpoint {
2021                                                 remote-endpoint = <&apss_funnel_in5>;
2022                                         };
2023                                 };
2024                         };
2025                 };
2026
2027                 etm@7640000 {
2028                         compatible = "arm,coresight-etm4x", "arm,primecell";
2029                         reg = <0 0x07640000 0 0x1000>;
2030
2031                         cpu = <&CPU6>;
2032
2033                         clocks = <&aoss_qmp>;
2034                         clock-names = "apb_pclk";
2035                         arm,coresight-loses-context-with-cpu;
2036                         qcom,skip-power-up;
2037
2038                         out-ports {
2039                                 port {
2040                                         etm6_out: endpoint {
2041                                                 remote-endpoint = <&apss_funnel_in6>;
2042                                         };
2043                                 };
2044                         };
2045                 };
2046
2047                 etm@7740000 {
2048                         compatible = "arm,coresight-etm4x", "arm,primecell";
2049                         reg = <0 0x07740000 0 0x1000>;
2050
2051                         cpu = <&CPU7>;
2052
2053                         clocks = <&aoss_qmp>;
2054                         clock-names = "apb_pclk";
2055                         arm,coresight-loses-context-with-cpu;
2056                         qcom,skip-power-up;
2057
2058                         out-ports {
2059                                 port {
2060                                         etm7_out: endpoint {
2061                                                 remote-endpoint = <&apss_funnel_in7>;
2062                                         };
2063                                 };
2064                         };
2065                 };
2066
2067                 funnel@7800000 { /* APSS Funnel */
2068                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2069                         reg = <0 0x07800000 0 0x1000>;
2070
2071                         clocks = <&aoss_qmp>;
2072                         clock-names = "apb_pclk";
2073
2074                         out-ports {
2075                                 port {
2076                                         apss_funnel_out: endpoint {
2077                                                 remote-endpoint = <&apss_merge_funnel_in>;
2078                                         };
2079                                 };
2080                         };
2081
2082                         in-ports {
2083                                 #address-cells = <1>;
2084                                 #size-cells = <0>;
2085
2086                                 port@0 {
2087                                         reg = <0>;
2088                                         apss_funnel_in0: endpoint {
2089                                                 remote-endpoint = <&etm0_out>;
2090                                         };
2091                                 };
2092
2093                                 port@1 {
2094                                         reg = <1>;
2095                                         apss_funnel_in1: endpoint {
2096                                                 remote-endpoint = <&etm1_out>;
2097                                         };
2098                                 };
2099
2100                                 port@2 {
2101                                         reg = <2>;
2102                                         apss_funnel_in2: endpoint {
2103                                                 remote-endpoint = <&etm2_out>;
2104                                         };
2105                                 };
2106
2107                                 port@3 {
2108                                         reg = <3>;
2109                                         apss_funnel_in3: endpoint {
2110                                                 remote-endpoint = <&etm3_out>;
2111                                         };
2112                                 };
2113
2114                                 port@4 {
2115                                         reg = <4>;
2116                                         apss_funnel_in4: endpoint {
2117                                                 remote-endpoint = <&etm4_out>;
2118                                         };
2119                                 };
2120
2121                                 port@5 {
2122                                         reg = <5>;
2123                                         apss_funnel_in5: endpoint {
2124                                                 remote-endpoint = <&etm5_out>;
2125                                         };
2126                                 };
2127
2128                                 port@6 {
2129                                         reg = <6>;
2130                                         apss_funnel_in6: endpoint {
2131                                                 remote-endpoint = <&etm6_out>;
2132                                         };
2133                                 };
2134
2135                                 port@7 {
2136                                         reg = <7>;
2137                                         apss_funnel_in7: endpoint {
2138                                                 remote-endpoint = <&etm7_out>;
2139                                         };
2140                                 };
2141                         };
2142                 };
2143
2144                 funnel@7810000 {
2145                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2146                         reg = <0 0x07810000 0 0x1000>;
2147
2148                         clocks = <&aoss_qmp>;
2149                         clock-names = "apb_pclk";
2150
2151                         out-ports {
2152                                 port {
2153                                         apss_merge_funnel_out: endpoint {
2154                                                 remote-endpoint = <&funnel2_in2>;
2155                                         };
2156                                 };
2157                         };
2158
2159                         in-ports {
2160                                 port {
2161                                         apss_merge_funnel_in: endpoint {
2162                                                 remote-endpoint = <&apss_funnel_out>;
2163                                         };
2164                                 };
2165                         };
2166                 };
2167
2168                 remoteproc_cdsp: remoteproc@8300000 {
2169                         compatible = "qcom,sm8150-cdsp-pas";
2170                         reg = <0x0 0x08300000 0x0 0x4040>;
2171
2172                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2173                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2174                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2175                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2176                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2177                         interrupt-names = "wdog", "fatal", "ready",
2178                                           "handover", "stop-ack";
2179
2180                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2181                         clock-names = "xo";
2182
2183                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2184                                         <&rpmhpd 7>;
2185                         power-domain-names = "load_state", "cx";
2186
2187                         memory-region = <&cdsp_mem>;
2188
2189                         qcom,smem-states = <&cdsp_smp2p_out 0>;
2190                         qcom,smem-state-names = "stop";
2191
2192                         status = "disabled";
2193
2194                         glink-edge {
2195                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2196                                 label = "cdsp";
2197                                 qcom,remote-pid = <5>;
2198                                 mboxes = <&apss_shared 4>;
2199                         };
2200                 };
2201
2202                 usb_1_hsphy: phy@88e2000 {
2203                         compatible = "qcom,sm8150-usb-hs-phy",
2204                                      "qcom,usb-snps-hs-7nm-phy";
2205                         reg = <0 0x088e2000 0 0x400>;
2206                         status = "disabled";
2207                         #phy-cells = <0>;
2208
2209                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2210                         clock-names = "ref";
2211
2212                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2213                 };
2214
2215                 usb_2_hsphy: phy@88e3000 {
2216                         compatible = "qcom,sm8150-usb-hs-phy",
2217                                      "qcom,usb-snps-hs-7nm-phy";
2218                         reg = <0 0x088e3000 0 0x400>;
2219                         status = "disabled";
2220                         #phy-cells = <0>;
2221
2222                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2223                         clock-names = "ref";
2224
2225                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2226                 };
2227
2228                 usb_1_qmpphy: phy@88e9000 {
2229                         compatible = "qcom,sm8150-qmp-usb3-phy";
2230                         reg = <0 0x088e9000 0 0x18c>,
2231                               <0 0x088e8000 0 0x10>;
2232                         reg-names = "reg-base", "dp_com";
2233                         status = "disabled";
2234                         #address-cells = <2>;
2235                         #size-cells = <2>;
2236                         ranges;
2237
2238                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2239                                  <&rpmhcc RPMH_CXO_CLK>,
2240                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2241                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2242                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2243
2244                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2245                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2246                         reset-names = "phy", "common";
2247
2248                         usb_1_ssphy: lanes@88e9200 {
2249                                 reg = <0 0x088e9200 0 0x200>,
2250                                       <0 0x088e9400 0 0x200>,
2251                                       <0 0x088e9c00 0 0x218>,
2252                                       <0 0x088e9600 0 0x200>,
2253                                       <0 0x088e9800 0 0x200>,
2254                                       <0 0x088e9a00 0 0x100>;
2255                                 #clock-cells = <0>;
2256                                 #phy-cells = <0>;
2257                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2258                                 clock-names = "pipe0";
2259                                 clock-output-names = "usb3_phy_pipe_clk_src";
2260                         };
2261                 };
2262
2263                 dc_noc: interconnect@9160000 {
2264                         compatible = "qcom,sm8150-dc-noc";
2265                         reg = <0 0x09160000 0 0x3200>;
2266                         #interconnect-cells = <1>;
2267                         qcom,bcm-voters = <&apps_bcm_voter>;
2268                 };
2269
2270                 gem_noc: interconnect@9680000 {
2271                         compatible = "qcom,sm8150-gem-noc";
2272                         reg = <0 0x09680000 0 0x3e200>;
2273                         #interconnect-cells = <1>;
2274                         qcom,bcm-voters = <&apps_bcm_voter>;
2275                 };
2276
2277                 usb_2_qmpphy: phy@88eb000 {
2278                         compatible = "qcom,sm8150-qmp-usb3-uni-phy";
2279                         reg = <0 0x088eb000 0 0x200>;
2280                         status = "disabled";
2281                         #address-cells = <2>;
2282                         #size-cells = <2>;
2283                         ranges;
2284
2285                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2286                                  <&rpmhcc RPMH_CXO_CLK>,
2287                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2288                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2289                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2290
2291                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2292                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2293                         reset-names = "phy", "common";
2294
2295                         usb_2_ssphy: lane@88eb200 {
2296                                 reg = <0 0x088eb200 0 0x200>,
2297                                       <0 0x088eb400 0 0x200>,
2298                                       <0 0x088eb800 0 0x800>,
2299                                       <0 0x088eb600 0 0x200>;
2300                                 #clock-cells = <0>;
2301                                 #phy-cells = <0>;
2302                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2303                                 clock-names = "pipe0";
2304                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2305                         };
2306                 };
2307
2308                 usb_1: usb@a6f8800 {
2309                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
2310                         reg = <0 0x0a6f8800 0 0x400>;
2311                         status = "disabled";
2312                         #address-cells = <2>;
2313                         #size-cells = <2>;
2314                         ranges;
2315                         dma-ranges;
2316
2317                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2318                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2319                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2320                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2321                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2322                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2323                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2324                                       "sleep", "xo";
2325
2326                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2327                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2328                         assigned-clock-rates = <19200000>, <200000000>;
2329
2330                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2331                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2332                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2333                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2334                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2335                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2336
2337                         power-domains = <&gcc USB30_PRIM_GDSC>;
2338
2339                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2340
2341                         usb_1_dwc3: dwc3@a600000 {
2342                                 compatible = "snps,dwc3";
2343                                 reg = <0 0x0a600000 0 0xcd00>;
2344                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2345                                 iommus = <&apps_smmu 0x140 0>;
2346                                 snps,dis_u2_susphy_quirk;
2347                                 snps,dis_enblslpm_quirk;
2348                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2349                                 phy-names = "usb2-phy", "usb3-phy";
2350                         };
2351                 };
2352
2353                 usb_2: usb@a8f8800 {
2354                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
2355                         reg = <0 0x0a8f8800 0 0x400>;
2356                         status = "disabled";
2357                         #address-cells = <2>;
2358                         #size-cells = <2>;
2359                         ranges;
2360                         dma-ranges;
2361
2362                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2363                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2364                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2365                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2366                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2367                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2368                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2369                                       "sleep", "xo";
2370
2371                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2372                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2373                         assigned-clock-rates = <19200000>, <200000000>;
2374
2375                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2376                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2377                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
2378                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
2379                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2380                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2381
2382                         power-domains = <&gcc USB30_SEC_GDSC>;
2383
2384                         resets = <&gcc GCC_USB30_SEC_BCR>;
2385
2386                         usb_2_dwc3: dwc3@a800000 {
2387                                 compatible = "snps,dwc3";
2388                                 reg = <0 0x0a800000 0 0xcd00>;
2389                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2390                                 iommus = <&apps_smmu 0x160 0>;
2391                                 snps,dis_u2_susphy_quirk;
2392                                 snps,dis_enblslpm_quirk;
2393                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2394                                 phy-names = "usb2-phy", "usb3-phy";
2395                         };
2396                 };
2397
2398                 camnoc_virt: interconnect@ac00000 {
2399                         compatible = "qcom,sm8150-camnoc-virt";
2400                         reg = <0 0x0ac00000 0 0x1000>;
2401                         #interconnect-cells = <1>;
2402                         qcom,bcm-voters = <&apps_bcm_voter>;
2403                 };
2404
2405                 aoss_qmp: power-controller@c300000 {
2406                         compatible = "qcom,sm8150-aoss-qmp";
2407                         reg = <0x0 0x0c300000 0x0 0x100000>;
2408                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
2409                         mboxes = <&apss_shared 0>;
2410
2411                         #clock-cells = <0>;
2412                         #power-domain-cells = <1>;
2413                 };
2414
2415                 tsens0: thermal-sensor@c263000 {
2416                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
2417                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2418                               <0 0x0c222000 0 0x1ff>; /* SROT */
2419                         #qcom,sensors = <16>;
2420                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2421                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2422                         interrupt-names = "uplow", "critical";
2423                         #thermal-sensor-cells = <1>;
2424                 };
2425
2426                 tsens1: thermal-sensor@c265000 {
2427                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
2428                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2429                               <0 0x0c223000 0 0x1ff>; /* SROT */
2430                         #qcom,sensors = <8>;
2431                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2432                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2433                         interrupt-names = "uplow", "critical";
2434                         #thermal-sensor-cells = <1>;
2435                 };
2436
2437                 spmi_bus: spmi@c440000 {
2438                         compatible = "qcom,spmi-pmic-arb";
2439                         reg = <0x0 0x0c440000 0x0 0x0001100>,
2440                               <0x0 0x0c600000 0x0 0x2000000>,
2441                               <0x0 0x0e600000 0x0 0x0100000>,
2442                               <0x0 0x0e700000 0x0 0x00a0000>,
2443                               <0x0 0x0c40a000 0x0 0x0026000>;
2444                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2445                         interrupt-names = "periph_irq";
2446                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
2447                         qcom,ee = <0>;
2448                         qcom,channel = <0>;
2449                         #address-cells = <2>;
2450                         #size-cells = <0>;
2451                         interrupt-controller;
2452                         #interrupt-cells = <4>;
2453                         cell-index = <0>;
2454                 };
2455
2456                 apps_smmu: iommu@15000000 {
2457                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2458                         reg = <0 0x15000000 0 0x100000>;
2459                         #iommu-cells = <2>;
2460                         #global-interrupts = <1>;
2461                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2462                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2463                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2464                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2465                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2466                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2467                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2468                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2469                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2470                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2471                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2472                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2473                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2474                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2475                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2476                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2477                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2478                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2479                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2480                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2481                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2482                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2483                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2484                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2485                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2486                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2487                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2488                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2489                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2490                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2491                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2492                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2493                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2494                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2495                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2496                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2497                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2498                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2499                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2500                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2501                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2502                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2503                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2504                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2505                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2506                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2507                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2508                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2509                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2510                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2511                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2512                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2513                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2514                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2515                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2516                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2517                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2518                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2519                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2520                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2521                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2522                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2523                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2524                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2525                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2526                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2527                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2528                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2529                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2530                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2531                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2532                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2533                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2534                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2535                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2536                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2537                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2538                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2539                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2540                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2541                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
2542                 };
2543
2544                 remoteproc_adsp: remoteproc@17300000 {
2545                         compatible = "qcom,sm8150-adsp-pas";
2546                         reg = <0x0 0x17300000 0x0 0x4040>;
2547
2548                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2549                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2550                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2551                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2552                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2553                         interrupt-names = "wdog", "fatal", "ready",
2554                                           "handover", "stop-ack";
2555
2556                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2557                         clock-names = "xo";
2558
2559                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2560                                         <&rpmhpd 7>;
2561                         power-domain-names = "load_state", "cx";
2562
2563                         memory-region = <&adsp_mem>;
2564
2565                         qcom,smem-states = <&adsp_smp2p_out 0>;
2566                         qcom,smem-state-names = "stop";
2567
2568                         status = "disabled";
2569
2570                         glink-edge {
2571                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2572                                 label = "lpass";
2573                                 qcom,remote-pid = <2>;
2574                                 mboxes = <&apss_shared 8>;
2575                         };
2576                 };
2577
2578                 intc: interrupt-controller@17a00000 {
2579                         compatible = "arm,gic-v3";
2580                         interrupt-controller;
2581                         #interrupt-cells = <3>;
2582                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2583                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2584                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2585                 };
2586
2587                 apss_shared: mailbox@17c00000 {
2588                         compatible = "qcom,sm8150-apss-shared";
2589                         reg = <0x0 0x17c00000 0x0 0x1000>;
2590                         #mbox-cells = <1>;
2591                 };
2592
2593                 watchdog@17c10000 {
2594                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
2595                         reg = <0 0x17c10000 0 0x1000>;
2596                         clocks = <&sleep_clk>;
2597                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2598                 };
2599
2600                 timer@17c20000 {
2601                         #address-cells = <2>;
2602                         #size-cells = <2>;
2603                         ranges;
2604                         compatible = "arm,armv7-timer-mem";
2605                         reg = <0x0 0x17c20000 0x0 0x1000>;
2606                         clock-frequency = <19200000>;
2607
2608                         frame@17c21000{
2609                                 frame-number = <0>;
2610                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2611                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2612                                 reg = <0x0 0x17c21000 0x0 0x1000>,
2613                                       <0x0 0x17c22000 0x0 0x1000>;
2614                         };
2615
2616                         frame@17c23000 {
2617                                 frame-number = <1>;
2618                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2619                                 reg = <0x0 0x17c23000 0x0 0x1000>;
2620                                 status = "disabled";
2621                         };
2622
2623                         frame@17c25000 {
2624                                 frame-number = <2>;
2625                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2626                                 reg = <0x0 0x17c25000 0x0 0x1000>;
2627                                 status = "disabled";
2628                         };
2629
2630                         frame@17c27000 {
2631                                 frame-number = <3>;
2632                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2633                                 reg = <0x0 0x17c26000 0x0 0x1000>;
2634                                 status = "disabled";
2635                         };
2636
2637                         frame@17c29000 {
2638                                 frame-number = <4>;
2639                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2640                                 reg = <0x0 0x17c29000 0x0 0x1000>;
2641                                 status = "disabled";
2642                         };
2643
2644                         frame@17c2b000 {
2645                                 frame-number = <5>;
2646                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2647                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
2648                                 status = "disabled";
2649                         };
2650
2651                         frame@17c2d000 {
2652                                 frame-number = <6>;
2653                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2654                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
2655                                 status = "disabled";
2656                         };
2657                 };
2658
2659                 apps_rsc: rsc@18200000 {
2660                         label = "apps_rsc";
2661                         compatible = "qcom,rpmh-rsc";
2662                         reg = <0x0 0x18200000 0x0 0x10000>,
2663                               <0x0 0x18210000 0x0 0x10000>,
2664                               <0x0 0x18220000 0x0 0x10000>;
2665                         reg-names = "drv-0", "drv-1", "drv-2";
2666                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2667                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2668                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2669                         qcom,tcs-offset = <0xd00>;
2670                         qcom,drv-id = <2>;
2671                         qcom,tcs-config = <ACTIVE_TCS  2>,
2672                                           <SLEEP_TCS   1>,
2673                                           <WAKE_TCS    1>,
2674                                           <CONTROL_TCS 0>;
2675
2676                         rpmhcc: clock-controller {
2677                                 compatible = "qcom,sm8150-rpmh-clk";
2678                                 #clock-cells = <1>;
2679                                 clock-names = "xo";
2680                                 clocks = <&xo_board>;
2681                         };
2682
2683                         rpmhpd: power-controller {
2684                                 compatible = "qcom,sm8150-rpmhpd";
2685                                 #power-domain-cells = <1>;
2686                                 operating-points-v2 = <&rpmhpd_opp_table>;
2687
2688                                 rpmhpd_opp_table: opp-table {
2689                                         compatible = "operating-points-v2";
2690
2691                                         rpmhpd_opp_ret: opp1 {
2692                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2693                                         };
2694
2695                                         rpmhpd_opp_min_svs: opp2 {
2696                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2697                                         };
2698
2699                                         rpmhpd_opp_low_svs: opp3 {
2700                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2701                                         };
2702
2703                                         rpmhpd_opp_svs: opp4 {
2704                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2705                                         };
2706
2707                                         rpmhpd_opp_svs_l1: opp5 {
2708                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2709                                         };
2710
2711                                         rpmhpd_opp_svs_l2: opp6 {
2712                                                 opp-level = <224>;
2713                                         };
2714
2715                                         rpmhpd_opp_nom: opp7 {
2716                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2717                                         };
2718
2719                                         rpmhpd_opp_nom_l1: opp8 {
2720                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2721                                         };
2722
2723                                         rpmhpd_opp_nom_l2: opp9 {
2724                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2725                                         };
2726
2727                                         rpmhpd_opp_turbo: opp10 {
2728                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2729                                         };
2730
2731                                         rpmhpd_opp_turbo_l1: opp11 {
2732                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2733                                         };
2734                                 };
2735                         };
2736
2737                         apps_bcm_voter: bcm_voter {
2738                                 compatible = "qcom,bcm-voter";
2739                         };
2740                 };
2741
2742                 osm_l3: interconnect@18321000 {
2743                         compatible = "qcom,sm8150-osm-l3";
2744                         reg = <0 0x18321000 0 0x1400>;
2745
2746                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2747                         clock-names = "xo", "alternate";
2748
2749                         #interconnect-cells = <1>;
2750                 };
2751
2752                 cpufreq_hw: cpufreq@18323000 {
2753                         compatible = "qcom,cpufreq-hw";
2754                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
2755                               <0 0x18327800 0 0x1400>;
2756                         reg-names = "freq-domain0", "freq-domain1",
2757                                     "freq-domain2";
2758
2759                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2760                         clock-names = "xo", "alternate";
2761
2762                         #freq-domain-cells = <1>;
2763                 };
2764
2765                 wifi: wifi@18800000 {
2766                         compatible = "qcom,wcn3990-wifi";
2767                         reg = <0 0x18800000 0 0x800000>;
2768                         reg-names = "membase";
2769                         memory-region = <&wlan_mem>;
2770                         clock-names = "cxo_ref_clk_pin", "qdss";
2771                         clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
2772                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2773                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2774                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2775                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2776                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2777                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2778                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2779                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2780                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2781                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2782                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2783                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2784                         iommus = <&apps_smmu 0x0640 0x1>;
2785                         status = "disabled";
2786                 };
2787         };
2788
2789         timer {
2790                 compatible = "arm,armv8-timer";
2791                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
2792                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
2793                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
2794                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
2795         };
2796
2797         thermal-zones {
2798                 cpu0-thermal {
2799                         polling-delay-passive = <250>;
2800                         polling-delay = <1000>;
2801
2802                         thermal-sensors = <&tsens0 1>;
2803
2804                         trips {
2805                                 cpu0_alert0: trip-point0 {
2806                                         temperature = <90000>;
2807                                         hysteresis = <2000>;
2808                                         type = "passive";
2809                                 };
2810
2811                                 cpu0_alert1: trip-point1 {
2812                                         temperature = <95000>;
2813                                         hysteresis = <2000>;
2814                                         type = "passive";
2815                                 };
2816
2817                                 cpu0_crit: cpu_crit {
2818                                         temperature = <110000>;
2819                                         hysteresis = <1000>;
2820                                         type = "critical";
2821                                 };
2822                         };
2823
2824                         cooling-maps {
2825                                 map0 {
2826                                         trip = <&cpu0_alert0>;
2827                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2828                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2829                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2830                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2831                                 };
2832                                 map1 {
2833                                         trip = <&cpu0_alert1>;
2834                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2835                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2836                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2837                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2838                                 };
2839                         };
2840                 };
2841
2842                 cpu1-thermal {
2843                         polling-delay-passive = <250>;
2844                         polling-delay = <1000>;
2845
2846                         thermal-sensors = <&tsens0 2>;
2847
2848                         trips {
2849                                 cpu1_alert0: trip-point0 {
2850                                         temperature = <90000>;
2851                                         hysteresis = <2000>;
2852                                         type = "passive";
2853                                 };
2854
2855                                 cpu1_alert1: trip-point1 {
2856                                         temperature = <95000>;
2857                                         hysteresis = <2000>;
2858                                         type = "passive";
2859                                 };
2860
2861                                 cpu1_crit: cpu_crit {
2862                                         temperature = <110000>;
2863                                         hysteresis = <1000>;
2864                                         type = "critical";
2865                                 };
2866                         };
2867
2868                         cooling-maps {
2869                                 map0 {
2870                                         trip = <&cpu1_alert0>;
2871                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2872                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2873                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2874                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2875                                 };
2876                                 map1 {
2877                                         trip = <&cpu1_alert1>;
2878                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2879                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2880                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2881                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2882                                 };
2883                         };
2884                 };
2885
2886                 cpu2-thermal {
2887                         polling-delay-passive = <250>;
2888                         polling-delay = <1000>;
2889
2890                         thermal-sensors = <&tsens0 3>;
2891
2892                         trips {
2893                                 cpu2_alert0: trip-point0 {
2894                                         temperature = <90000>;
2895                                         hysteresis = <2000>;
2896                                         type = "passive";
2897                                 };
2898
2899                                 cpu2_alert1: trip-point1 {
2900                                         temperature = <95000>;
2901                                         hysteresis = <2000>;
2902                                         type = "passive";
2903                                 };
2904
2905                                 cpu2_crit: cpu_crit {
2906                                         temperature = <110000>;
2907                                         hysteresis = <1000>;
2908                                         type = "critical";
2909                                 };
2910                         };
2911
2912                         cooling-maps {
2913                                 map0 {
2914                                         trip = <&cpu2_alert0>;
2915                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2916                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2917                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2918                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2919                                 };
2920                                 map1 {
2921                                         trip = <&cpu2_alert1>;
2922                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2923                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2924                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2925                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2926                                 };
2927                         };
2928                 };
2929
2930                 cpu3-thermal {
2931                         polling-delay-passive = <250>;
2932                         polling-delay = <1000>;
2933
2934                         thermal-sensors = <&tsens0 4>;
2935
2936                         trips {
2937                                 cpu3_alert0: trip-point0 {
2938                                         temperature = <90000>;
2939                                         hysteresis = <2000>;
2940                                         type = "passive";
2941                                 };
2942
2943                                 cpu3_alert1: trip-point1 {
2944                                         temperature = <95000>;
2945                                         hysteresis = <2000>;
2946                                         type = "passive";
2947                                 };
2948
2949                                 cpu3_crit: cpu_crit {
2950                                         temperature = <110000>;
2951                                         hysteresis = <1000>;
2952                                         type = "critical";
2953                                 };
2954                         };
2955
2956                         cooling-maps {
2957                                 map0 {
2958                                         trip = <&cpu3_alert0>;
2959                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2960                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2961                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2962                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2963                                 };
2964                                 map1 {
2965                                         trip = <&cpu3_alert1>;
2966                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2967                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2968                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2969                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2970                                 };
2971                         };
2972                 };
2973
2974                 cpu4-top-thermal {
2975                         polling-delay-passive = <250>;
2976                         polling-delay = <1000>;
2977
2978                         thermal-sensors = <&tsens0 7>;
2979
2980                         trips {
2981                                 cpu4_top_alert0: trip-point0 {
2982                                         temperature = <90000>;
2983                                         hysteresis = <2000>;
2984                                         type = "passive";
2985                                 };
2986
2987                                 cpu4_top_alert1: trip-point1 {
2988                                         temperature = <95000>;
2989                                         hysteresis = <2000>;
2990                                         type = "passive";
2991                                 };
2992
2993                                 cpu4_top_crit: cpu_crit {
2994                                         temperature = <110000>;
2995                                         hysteresis = <1000>;
2996                                         type = "critical";
2997                                 };
2998                         };
2999
3000                         cooling-maps {
3001                                 map0 {
3002                                         trip = <&cpu4_top_alert0>;
3003                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3004                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3005                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3006                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3007                                 };
3008                                 map1 {
3009                                         trip = <&cpu4_top_alert1>;
3010                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3011                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3012                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3013                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3014                                 };
3015                         };
3016                 };
3017
3018                 cpu5-top-thermal {
3019                         polling-delay-passive = <250>;
3020                         polling-delay = <1000>;
3021
3022                         thermal-sensors = <&tsens0 8>;
3023
3024                         trips {
3025                                 cpu5_top_alert0: trip-point0 {
3026                                         temperature = <90000>;
3027                                         hysteresis = <2000>;
3028                                         type = "passive";
3029                                 };
3030
3031                                 cpu5_top_alert1: trip-point1 {
3032                                         temperature = <95000>;
3033                                         hysteresis = <2000>;
3034                                         type = "passive";
3035                                 };
3036
3037                                 cpu5_top_crit: cpu_crit {
3038                                         temperature = <110000>;
3039                                         hysteresis = <1000>;
3040                                         type = "critical";
3041                                 };
3042                         };
3043
3044                         cooling-maps {
3045                                 map0 {
3046                                         trip = <&cpu5_top_alert0>;
3047                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3048                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3049                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3050                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3051                                 };
3052                                 map1 {
3053                                         trip = <&cpu5_top_alert1>;
3054                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3055                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3056                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3057                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3058                                 };
3059                         };
3060                 };
3061
3062                 cpu6-top-thermal {
3063                         polling-delay-passive = <250>;
3064                         polling-delay = <1000>;
3065
3066                         thermal-sensors = <&tsens0 9>;
3067
3068                         trips {
3069                                 cpu6_top_alert0: trip-point0 {
3070                                         temperature = <90000>;
3071                                         hysteresis = <2000>;
3072                                         type = "passive";
3073                                 };
3074
3075                                 cpu6_top_alert1: trip-point1 {
3076                                         temperature = <95000>;
3077                                         hysteresis = <2000>;
3078                                         type = "passive";
3079                                 };
3080
3081                                 cpu6_top_crit: cpu_crit {
3082                                         temperature = <110000>;
3083                                         hysteresis = <1000>;
3084                                         type = "critical";
3085                                 };
3086                         };
3087
3088                         cooling-maps {
3089                                 map0 {
3090                                         trip = <&cpu6_top_alert0>;
3091                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3092                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3093                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3094                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3095                                 };
3096                                 map1 {
3097                                         trip = <&cpu6_top_alert1>;
3098                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3099                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3100                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3101                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3102                                 };
3103                         };
3104                 };
3105
3106                 cpu7-top-thermal {
3107                         polling-delay-passive = <250>;
3108                         polling-delay = <1000>;
3109
3110                         thermal-sensors = <&tsens0 10>;
3111
3112                         trips {
3113                                 cpu7_top_alert0: trip-point0 {
3114                                         temperature = <90000>;
3115                                         hysteresis = <2000>;
3116                                         type = "passive";
3117                                 };
3118
3119                                 cpu7_top_alert1: trip-point1 {
3120                                         temperature = <95000>;
3121                                         hysteresis = <2000>;
3122                                         type = "passive";
3123                                 };
3124
3125                                 cpu7_top_crit: cpu_crit {
3126                                         temperature = <110000>;
3127                                         hysteresis = <1000>;
3128                                         type = "critical";
3129                                 };
3130                         };
3131
3132                         cooling-maps {
3133                                 map0 {
3134                                         trip = <&cpu7_top_alert0>;
3135                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3136                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3137                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3138                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3139                                 };
3140                                 map1 {
3141                                         trip = <&cpu7_top_alert1>;
3142                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3143                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3144                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3145                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3146                                 };
3147                         };
3148                 };
3149
3150                 cpu4-bottom-thermal {
3151                         polling-delay-passive = <250>;
3152                         polling-delay = <1000>;
3153
3154                         thermal-sensors = <&tsens0 11>;
3155
3156                         trips {
3157                                 cpu4_bottom_alert0: trip-point0 {
3158                                         temperature = <90000>;
3159                                         hysteresis = <2000>;
3160                                         type = "passive";
3161                                 };
3162
3163                                 cpu4_bottom_alert1: trip-point1 {
3164                                         temperature = <95000>;
3165                                         hysteresis = <2000>;
3166                                         type = "passive";
3167                                 };
3168
3169                                 cpu4_bottom_crit: cpu_crit {
3170                                         temperature = <110000>;
3171                                         hysteresis = <1000>;
3172                                         type = "critical";
3173                                 };
3174                         };
3175
3176                         cooling-maps {
3177                                 map0 {
3178                                         trip = <&cpu4_bottom_alert0>;
3179                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3180                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3181                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3182                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3183                                 };
3184                                 map1 {
3185                                         trip = <&cpu4_bottom_alert1>;
3186                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3187                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3188                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3189                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3190                                 };
3191                         };
3192                 };
3193
3194                 cpu5-bottom-thermal {
3195                         polling-delay-passive = <250>;
3196                         polling-delay = <1000>;
3197
3198                         thermal-sensors = <&tsens0 12>;
3199
3200                         trips {
3201                                 cpu5_bottom_alert0: trip-point0 {
3202                                         temperature = <90000>;
3203                                         hysteresis = <2000>;
3204                                         type = "passive";
3205                                 };
3206
3207                                 cpu5_bottom_alert1: trip-point1 {
3208                                         temperature = <95000>;
3209                                         hysteresis = <2000>;
3210                                         type = "passive";
3211                                 };
3212
3213                                 cpu5_bottom_crit: cpu_crit {
3214                                         temperature = <110000>;
3215                                         hysteresis = <1000>;
3216                                         type = "critical";
3217                                 };
3218                         };
3219
3220                         cooling-maps {
3221                                 map0 {
3222                                         trip = <&cpu5_bottom_alert0>;
3223                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3224                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3225                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3226                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3227                                 };
3228                                 map1 {
3229                                         trip = <&cpu5_bottom_alert1>;
3230                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3231                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3232                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3233                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3234                                 };
3235                         };
3236                 };
3237
3238                 cpu6-bottom-thermal {
3239                         polling-delay-passive = <250>;
3240                         polling-delay = <1000>;
3241
3242                         thermal-sensors = <&tsens0 13>;
3243
3244                         trips {
3245                                 cpu6_bottom_alert0: trip-point0 {
3246                                         temperature = <90000>;
3247                                         hysteresis = <2000>;
3248                                         type = "passive";
3249                                 };
3250
3251                                 cpu6_bottom_alert1: trip-point1 {
3252                                         temperature = <95000>;
3253                                         hysteresis = <2000>;
3254                                         type = "passive";
3255                                 };
3256
3257                                 cpu6_bottom_crit: cpu_crit {
3258                                         temperature = <110000>;
3259                                         hysteresis = <1000>;
3260                                         type = "critical";
3261                                 };
3262                         };
3263
3264                         cooling-maps {
3265                                 map0 {
3266                                         trip = <&cpu6_bottom_alert0>;
3267                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3268                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3269                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3270                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3271                                 };
3272                                 map1 {
3273                                         trip = <&cpu6_bottom_alert1>;
3274                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3275                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3276                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3277                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3278                                 };
3279                         };
3280                 };
3281
3282                 cpu7-bottom-thermal {
3283                         polling-delay-passive = <250>;
3284                         polling-delay = <1000>;
3285
3286                         thermal-sensors = <&tsens0 14>;
3287
3288                         trips {
3289                                 cpu7_bottom_alert0: trip-point0 {
3290                                         temperature = <90000>;
3291                                         hysteresis = <2000>;
3292                                         type = "passive";
3293                                 };
3294
3295                                 cpu7_bottom_alert1: trip-point1 {
3296                                         temperature = <95000>;
3297                                         hysteresis = <2000>;
3298                                         type = "passive";
3299                                 };
3300
3301                                 cpu7_bottom_crit: cpu_crit {
3302                                         temperature = <110000>;
3303                                         hysteresis = <1000>;
3304                                         type = "critical";
3305                                 };
3306                         };
3307
3308                         cooling-maps {
3309                                 map0 {
3310                                         trip = <&cpu7_bottom_alert0>;
3311                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3312                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3313                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3314                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3315                                 };
3316                                 map1 {
3317                                         trip = <&cpu7_bottom_alert1>;
3318                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3319                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3320                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3321                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3322                                 };
3323                         };
3324                 };
3325
3326                 aoss0-thermal {
3327                         polling-delay-passive = <250>;
3328                         polling-delay = <1000>;
3329
3330                         thermal-sensors = <&tsens0 0>;
3331
3332                         trips {
3333                                 aoss0_alert0: trip-point0 {
3334                                         temperature = <90000>;
3335                                         hysteresis = <2000>;
3336                                         type = "hot";
3337                                 };
3338                         };
3339                 };
3340
3341                 cluster0-thermal {
3342                         polling-delay-passive = <250>;
3343                         polling-delay = <1000>;
3344
3345                         thermal-sensors = <&tsens0 5>;
3346
3347                         trips {
3348                                 cluster0_alert0: trip-point0 {
3349                                         temperature = <90000>;
3350                                         hysteresis = <2000>;
3351                                         type = "hot";
3352                                 };
3353                                 cluster0_crit: cluster0_crit {
3354                                         temperature = <110000>;
3355                                         hysteresis = <2000>;
3356                                         type = "critical";
3357                                 };
3358                         };
3359                 };
3360
3361                 cluster1-thermal {
3362                         polling-delay-passive = <250>;
3363                         polling-delay = <1000>;
3364
3365                         thermal-sensors = <&tsens0 6>;
3366
3367                         trips {
3368                                 cluster1_alert0: trip-point0 {
3369                                         temperature = <90000>;
3370                                         hysteresis = <2000>;
3371                                         type = "hot";
3372                                 };
3373                                 cluster1_crit: cluster1_crit {
3374                                         temperature = <110000>;
3375                                         hysteresis = <2000>;
3376                                         type = "critical";
3377                                 };
3378                         };
3379                 };
3380
3381                 gpu-thermal-top {
3382                         polling-delay-passive = <250>;
3383                         polling-delay = <1000>;
3384
3385                         thermal-sensors = <&tsens0 15>;
3386
3387                         trips {
3388                                 gpu1_alert0: trip-point0 {
3389                                         temperature = <90000>;
3390                                         hysteresis = <2000>;
3391                                         type = "hot";
3392                                 };
3393                         };
3394                 };
3395
3396                 aoss1-thermal {
3397                         polling-delay-passive = <250>;
3398                         polling-delay = <1000>;
3399
3400                         thermal-sensors = <&tsens1 0>;
3401
3402                         trips {
3403                                 aoss1_alert0: trip-point0 {
3404                                         temperature = <90000>;
3405                                         hysteresis = <2000>;
3406                                         type = "hot";
3407                                 };
3408                         };
3409                 };
3410
3411                 wlan-thermal {
3412                         polling-delay-passive = <250>;
3413                         polling-delay = <1000>;
3414
3415                         thermal-sensors = <&tsens1 1>;
3416
3417                         trips {
3418                                 wlan_alert0: trip-point0 {
3419                                         temperature = <90000>;
3420                                         hysteresis = <2000>;
3421                                         type = "hot";
3422                                 };
3423                         };
3424                 };
3425
3426                 video-thermal {
3427                         polling-delay-passive = <250>;
3428                         polling-delay = <1000>;
3429
3430                         thermal-sensors = <&tsens1 2>;
3431
3432                         trips {
3433                                 video_alert0: trip-point0 {
3434                                         temperature = <90000>;
3435                                         hysteresis = <2000>;
3436                                         type = "hot";
3437                                 };
3438                         };
3439                 };
3440
3441                 mem-thermal {
3442                         polling-delay-passive = <250>;
3443                         polling-delay = <1000>;
3444
3445                         thermal-sensors = <&tsens1 3>;
3446
3447                         trips {
3448                                 mem_alert0: trip-point0 {
3449                                         temperature = <90000>;
3450                                         hysteresis = <2000>;
3451                                         type = "hot";
3452                                 };
3453                         };
3454                 };
3455
3456                 q6-hvx-thermal {
3457                         polling-delay-passive = <250>;
3458                         polling-delay = <1000>;
3459
3460                         thermal-sensors = <&tsens1 4>;
3461
3462                         trips {
3463                                 q6_hvx_alert0: trip-point0 {
3464                                         temperature = <90000>;
3465                                         hysteresis = <2000>;
3466                                         type = "hot";
3467                                 };
3468                         };
3469                 };
3470
3471                 camera-thermal {
3472                         polling-delay-passive = <250>;
3473                         polling-delay = <1000>;
3474
3475                         thermal-sensors = <&tsens1 5>;
3476
3477                         trips {
3478                                 camera_alert0: trip-point0 {
3479                                         temperature = <90000>;
3480                                         hysteresis = <2000>;
3481                                         type = "hot";
3482                                 };
3483                         };
3484                 };
3485
3486                 compute-thermal {
3487                         polling-delay-passive = <250>;
3488                         polling-delay = <1000>;
3489
3490                         thermal-sensors = <&tsens1 6>;
3491
3492                         trips {
3493                                 compute_alert0: trip-point0 {
3494                                         temperature = <90000>;
3495                                         hysteresis = <2000>;
3496                                         type = "hot";
3497                                 };
3498                         };
3499                 };
3500
3501                 modem-thermal {
3502                         polling-delay-passive = <250>;
3503                         polling-delay = <1000>;
3504
3505                         thermal-sensors = <&tsens1 7>;
3506
3507                         trips {
3508                                 modem_alert0: trip-point0 {
3509                                         temperature = <90000>;
3510                                         hysteresis = <2000>;
3511                                         type = "hot";
3512                                 };
3513                         };
3514                 };
3515
3516                 npu-thermal {
3517                         polling-delay-passive = <250>;
3518                         polling-delay = <1000>;
3519
3520                         thermal-sensors = <&tsens1 8>;
3521
3522                         trips {
3523                                 npu_alert0: trip-point0 {
3524                                         temperature = <90000>;
3525                                         hysteresis = <2000>;
3526                                         type = "hot";
3527                                 };
3528                         };
3529                 };
3530
3531                 modem-vec-thermal {
3532                         polling-delay-passive = <250>;
3533                         polling-delay = <1000>;
3534
3535                         thermal-sensors = <&tsens1 9>;
3536
3537                         trips {
3538                                 modem_vec_alert0: trip-point0 {
3539                                         temperature = <90000>;
3540                                         hysteresis = <2000>;
3541                                         type = "hot";
3542                                 };
3543                         };
3544                 };
3545
3546                 modem-scl-thermal {
3547                         polling-delay-passive = <250>;
3548                         polling-delay = <1000>;
3549
3550                         thermal-sensors = <&tsens1 10>;
3551
3552                         trips {
3553                                 modem_scl_alert0: trip-point0 {
3554                                         temperature = <90000>;
3555                                         hysteresis = <2000>;
3556                                         type = "hot";
3557                                 };
3558                         };
3559                 };
3560
3561                 gpu-thermal-bottom {
3562                         polling-delay-passive = <250>;
3563                         polling-delay = <1000>;
3564
3565                         thermal-sensors = <&tsens1 11>;
3566
3567                         trips {
3568                                 gpu2_alert0: trip-point0 {
3569                                         temperature = <90000>;
3570                                         hysteresis = <2000>;
3571                                         type = "hot";
3572                                 };
3573                         };
3574                 };
3575         };
3576 };