1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
6 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/mailbox/qcom-ipcc.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <76800000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep-clk {
28 compatible = "fixed-clock";
29 clock-frequency = <32764>;
40 compatible = "qcom,kryo560";
42 enable-method = "psci";
43 capacity-dmips-mhz = <1024>;
44 dynamic-power-coefficient = <100>;
45 next-level-cache = <&L2_0>;
46 qcom,freq-domain = <&cpufreq_hw 0>;
50 next-level-cache = <&L3_0>;
59 compatible = "qcom,kryo560";
61 enable-method = "psci";
62 capacity-dmips-mhz = <1024>;
63 dynamic-power-coefficient = <100>;
64 next-level-cache = <&L2_100>;
65 qcom,freq-domain = <&cpufreq_hw 0>;
69 next-level-cache = <&L3_0>;
75 compatible = "qcom,kryo560";
77 enable-method = "psci";
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 next-level-cache = <&L2_200>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
85 next-level-cache = <&L3_0>;
91 compatible = "qcom,kryo560";
93 enable-method = "psci";
94 capacity-dmips-mhz = <1024>;
95 dynamic-power-coefficient = <100>;
96 next-level-cache = <&L2_300>;
97 qcom,freq-domain = <&cpufreq_hw 0>;
100 compatible = "cache";
101 next-level-cache = <&L3_0>;
107 compatible = "qcom,kryo560";
109 enable-method = "psci";
110 capacity-dmips-mhz = <1024>;
111 dynamic-power-coefficient = <100>;
112 next-level-cache = <&L2_400>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
114 #cooling-cells = <2>;
116 compatible = "cache";
117 next-level-cache = <&L3_0>;
123 compatible = "qcom,kryo560";
125 enable-method = "psci";
126 capacity-dmips-mhz = <1024>;
127 dynamic-power-coefficient = <100>;
128 next-level-cache = <&L2_500>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
130 #cooling-cells = <2>;
132 compatible = "cache";
133 next-level-cache = <&L3_0>;
140 compatible = "qcom,kryo560";
142 enable-method = "psci";
143 capacity-dmips-mhz = <1894>;
144 dynamic-power-coefficient = <703>;
145 next-level-cache = <&L2_600>;
146 qcom,freq-domain = <&cpufreq_hw 1>;
147 #cooling-cells = <2>;
149 compatible = "cache";
150 next-level-cache = <&L3_0>;
156 compatible = "qcom,kryo560";
158 enable-method = "psci";
159 capacity-dmips-mhz = <1894>;
160 dynamic-power-coefficient = <703>;
161 next-level-cache = <&L2_700>;
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>;
165 compatible = "cache";
166 next-level-cache = <&L3_0>;
209 compatible = "qcom,scm-sm6350", "qcom,scm";
215 device_type = "memory";
216 /* We expect the bootloader to fill in the size */
217 reg = <0x0 0x80000000 0x0 0x0>;
221 compatible = "arm,armv8-pmuv3";
222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
226 compatible = "arm,psci-1.0";
230 reserved_memory: reserved-memory {
231 #address-cells = <2>;
235 hyp_mem: memory@80000000 {
236 reg = <0 0x80000000 0 0x600000>;
240 xbl_aop_mem: memory@80700000 {
241 reg = <0 0x80700000 0 0x160000>;
245 cmd_db: memory@80860000 {
246 compatible = "qcom,cmd-db";
247 reg = <0 0x80860000 0 0x20000>;
251 sec_apps_mem: memory@808ff000 {
252 reg = <0 0x808ff000 0 0x1000>;
256 smem_mem: memory@80900000 {
257 reg = <0 0x80900000 0 0x200000>;
261 cdsp_sec_mem: memory@80b00000 {
262 reg = <0 0x80b00000 0 0x1e00000>;
266 pil_camera_mem: memory@86000000 {
267 reg = <0 0x86000000 0 0x500000>;
271 pil_npu_mem: memory@86500000 {
272 reg = <0 0x86500000 0 0x500000>;
276 pil_video_mem: memory@86a00000 {
277 reg = <0 0x86a00000 0 0x500000>;
281 pil_cdsp_mem: memory@86f00000 {
282 reg = <0 0x86f00000 0 0x1e00000>;
286 pil_adsp_mem: memory@88d00000 {
287 reg = <0 0x88d00000 0 0x2800000>;
291 wlan_fw_mem: memory@8b500000 {
292 reg = <0 0x8b500000 0 0x200000>;
296 pil_ipa_fw_mem: memory@8b700000 {
297 reg = <0 0x8b700000 0 0x10000>;
301 pil_ipa_gsi_mem: memory@8b710000 {
302 reg = <0 0x8b710000 0 0x5400>;
306 pil_gpu_mem: memory@8b715400 {
307 reg = <0 0x8b715400 0 0x2000>;
311 pil_modem_mem: memory@8b800000 {
312 reg = <0 0x8b800000 0 0xf800000>;
316 cont_splash_memory: memory@a0000000 {
317 reg = <0 0xa0000000 0 0x2300000>;
321 dfps_data_memory: memory@a2300000 {
322 reg = <0 0xa2300000 0 0x100000>;
326 removed_region: memory@c0000000 {
327 reg = <0 0xc0000000 0 0x3900000>;
331 debug_region: memory@ffb00000 {
332 reg = <0 0xffb00000 0 0xc0000>;
336 last_log_region: memory@ffbc0000 {
337 reg = <0 0xffbc0000 0 0x40000>;
341 ramoops: ramoops@ffc00000 {
342 compatible = "removed-dma-pool", "ramoops";
343 reg = <0 0xffc00000 0 0x00100000>;
344 record-size = <0x1000>;
345 console-size = <0x40000>;
347 msg-size = <0x20000 0x20000>;
352 cmdline_region: memory@ffd00000 {
353 reg = <0 0xffd00000 0 0x1000>;
359 compatible = "qcom,smem";
360 memory-region = <&smem_mem>;
361 hwlocks = <&tcsr_mutex 3>;
365 compatible = "qcom,smp2p";
366 qcom,smem = <443>, <429>;
367 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
368 IPCC_MPROC_SIGNAL_SMP2P
369 IRQ_TYPE_EDGE_RISING>;
370 mboxes = <&ipcc IPCC_CLIENT_LPASS
371 IPCC_MPROC_SIGNAL_SMP2P>;
373 qcom,local-pid = <0>;
374 qcom,remote-pid = <2>;
376 smp2p_adsp_out: master-kernel {
377 qcom,entry-name = "master-kernel";
378 #qcom,smem-state-cells = <1>;
381 smp2p_adsp_in: slave-kernel {
382 qcom,entry-name = "slave-kernel";
383 interrupt-controller;
384 #interrupt-cells = <2>;
389 compatible = "qcom,smp2p";
390 qcom,smem = <94>, <432>;
391 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
392 IPCC_MPROC_SIGNAL_SMP2P
393 IRQ_TYPE_EDGE_RISING>;
394 mboxes = <&ipcc IPCC_CLIENT_CDSP
395 IPCC_MPROC_SIGNAL_SMP2P>;
397 qcom,local-pid = <0>;
398 qcom,remote-pid = <5>;
400 smp2p_cdsp_out: master-kernel {
401 qcom,entry-name = "master-kernel";
402 #qcom,smem-state-cells = <1>;
405 smp2p_cdsp_in: slave-kernel {
406 qcom,entry-name = "slave-kernel";
407 interrupt-controller;
408 #interrupt-cells = <2>;
413 compatible = "qcom,smp2p";
414 qcom,smem = <435>, <428>;
416 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
417 IPCC_MPROC_SIGNAL_SMP2P
418 IRQ_TYPE_EDGE_RISING>;
419 mboxes = <&ipcc IPCC_CLIENT_MPSS
420 IPCC_MPROC_SIGNAL_SMP2P>;
422 qcom,local-pid = <0>;
423 qcom,remote-pid = <1>;
425 modem_smp2p_out: master-kernel {
426 qcom,entry-name = "master-kernel";
427 #qcom,smem-state-cells = <1>;
430 modem_smp2p_in: slave-kernel {
431 qcom,entry-name = "slave-kernel";
433 interrupt-controller;
434 #interrupt-cells = <2>;
439 #address-cells = <2>;
441 ranges = <0 0 0 0 0x10 0>;
442 dma-ranges = <0 0 0 0 0x10 0>;
443 compatible = "simple-bus";
445 gcc: clock-controller@100000 {
446 compatible = "qcom,gcc-sm6350";
447 reg = <0 0x00100000 0 0x1f0000>;
450 #power-domain-cells = <1>;
451 clock-names = "bi_tcxo",
454 clocks = <&rpmhcc RPMH_CXO_CLK>,
455 <&rpmhcc RPMH_CXO_CLK_A>,
459 ipcc: mailbox@408000 {
460 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
461 reg = <0 0x00408000 0 0x1000>;
462 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-controller;
464 #interrupt-cells = <3>;
469 compatible = "qcom,prng-ee";
470 reg = <0 0x00793000 0 0x1000>;
471 clocks = <&gcc GCC_PRNG_AHB_CLK>;
472 clock-names = "core";
476 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
477 reg = <0 0x007c4000 0 0x1000>,
478 <0 0x007c5000 0 0x1000>,
479 <0 0x007c8000 0 0x8000>;
480 reg-names = "hc", "cqhci", "ice";
482 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-names = "hc_irq", "pwr_irq";
486 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
487 <&gcc GCC_SDCC1_APPS_CLK>,
488 <&rpmhcc RPMH_CXO_CLK>;
489 clock-names = "iface", "core", "xo";
490 qcom,dll-config = <0x000f642c>;
491 qcom,ddr-config = <0x80040868>;
492 power-domains = <&rpmhpd 0>;
493 operating-points-v2 = <&sdhc1_opp_table>;
500 sdhc1_opp_table: opp-table {
501 compatible = "operating-points-v2";
504 opp-hz = /bits/ 64 <19200000>;
505 required-opps = <&rpmhpd_opp_min_svs>;
509 opp-hz = /bits/ 64 <100000000>;
510 required-opps = <&rpmhpd_opp_low_svs>;
514 opp-hz = /bits/ 64 <384000000>;
515 required-opps = <&rpmhpd_opp_svs_l1>;
520 qupv3_id_0: geniqup@8c0000 {
521 compatible = "qcom,geni-se-qup";
522 reg = <0x0 0x8c0000 0x0 0x2000>;
523 clock-names = "m-ahb", "s-ahb";
524 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
525 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
526 #address-cells = <2>;
528 iommus = <&apps_smmu 0x43 0x0>;
533 compatible = "qcom,geni-i2c";
534 reg = <0 0x00880000 0 0x4000>;
536 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&qup_i2c0_default>;
539 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
540 #address-cells = <1>;
546 compatible = "qcom,geni-i2c";
547 reg = <0 0x00888000 0 0x4000>;
549 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&qup_i2c2_default>;
552 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
559 qupv3_id_1: geniqup@9c0000 {
560 compatible = "qcom,geni-se-qup";
561 reg = <0x0 0x9c0000 0x0 0x2000>;
562 clock-names = "m-ahb", "s-ahb";
563 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
564 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
565 #address-cells = <2>;
567 iommus = <&apps_smmu 0x4c3 0x0>;
572 compatible = "qcom,geni-i2c";
573 reg = <0 0x00980000 0 0x4000>;
575 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&qup_i2c6_default>;
578 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
585 compatible = "qcom,geni-i2c";
586 reg = <0 0x00984000 0 0x4000>;
588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&qup_i2c7_default>;
591 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
592 #address-cells = <1>;
598 compatible = "qcom,geni-i2c";
599 reg = <0 0x00988000 0 0x4000>;
601 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&qup_i2c8_default>;
604 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
605 #address-cells = <1>;
610 uart9: serial@98c000 {
611 compatible = "qcom,geni-debug-uart";
612 reg = <0 0x98c000 0 0x4000>;
614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&qup_uart9_default>;
617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
622 compatible = "qcom,geni-i2c";
623 reg = <0 0x00990000 0 0x4000>;
625 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&qup_i2c10_default>;
628 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
629 #address-cells = <1>;
636 ufs_mem_hc: ufs@1d84000 {
637 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
639 reg = <0 0x01d84000 0 0x3000>,
640 <0 0x01d90000 0 0x8000>;
641 reg-names = "std", "ice";
642 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
643 phys = <&ufs_mem_phy_lanes>;
644 phy-names = "ufsphy";
645 lanes-per-direction = <2>;
647 resets = <&gcc GCC_UFS_PHY_BCR>;
650 power-domains = <&gcc UFS_PHY_GDSC>;
652 iommus = <&apps_smmu 0x80 0x0>;
654 clock-names = "core_clk",
663 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
664 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
665 <&gcc GCC_UFS_PHY_AHB_CLK>,
666 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
667 <&rpmhcc RPMH_QLINK_CLK>,
668 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
669 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
670 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
671 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
673 <50000000 200000000>,
676 <37500000 150000000>,
677 <75000000 300000000>,
686 ufs_mem_phy: phy@1d87000 {
687 compatible = "qcom,sm6350-qmp-ufs-phy";
688 reg = <0 0x01d87000 0 0x18c>;
689 #address-cells = <2>;
695 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
696 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
698 resets = <&ufs_mem_hc 0>;
699 reset-names = "ufsphy";
703 ufs_mem_phy_lanes: phy@1d87400 {
704 reg = <0 0x01d87400 0 0x128>,
705 <0 0x01d87600 0 0x1fc>,
706 <0 0x01d87c00 0 0x1dc>,
707 <0 0x01d87800 0 0x128>,
708 <0 0x01d87a00 0 0x1fc>;
713 tcsr_mutex: hwlock@1f40000 {
714 compatible = "qcom,tcsr-mutex";
715 reg = <0x0 0x01f40000 0x0 0x40000>;
719 adsp: remoteproc@3000000 {
720 compatible = "qcom,sm6350-adsp-pas";
721 reg = <0 0x03000000 0 0x100>;
723 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
724 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
725 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
726 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
727 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
728 interrupt-names = "wdog", "fatal", "ready",
729 "handover", "stop-ack";
731 clocks = <&rpmhcc RPMH_CXO_CLK>;
734 power-domains = <&rpmhpd SM6350_LCX>,
735 <&rpmhpd SM6350_LMX>;
736 power-domain-names = "lcx", "lmx";
738 memory-region = <&pil_adsp_mem>;
740 qcom,qmp = <&aoss_qmp>;
742 qcom,smem-states = <&smp2p_adsp_out 0>;
743 qcom,smem-state-names = "stop";
748 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
749 IPCC_MPROC_SIGNAL_GLINK_QMP
750 IRQ_TYPE_EDGE_RISING>;
751 mboxes = <&ipcc IPCC_CLIENT_LPASS
752 IPCC_MPROC_SIGNAL_GLINK_QMP>;
755 qcom,remote-pid = <2>;
758 compatible = "qcom,fastrpc";
759 qcom,glink-channels = "fastrpcglink-apps-dsp";
761 #address-cells = <1>;
765 compatible = "qcom,fastrpc-compute-cb";
767 iommus = <&apps_smmu 0x1003 0x0>;
771 compatible = "qcom,fastrpc-compute-cb";
773 iommus = <&apps_smmu 0x1004 0x0>;
777 compatible = "qcom,fastrpc-compute-cb";
779 iommus = <&apps_smmu 0x1005 0x0>;
780 qcom,nsessions = <5>;
786 mpss: remoteproc@4080000 {
787 compatible = "qcom,sm6350-mpss-pas";
788 reg = <0x0 0x04080000 0x0 0x4040>;
790 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
791 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
792 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
793 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
794 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
795 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
796 interrupt-names = "wdog", "fatal", "ready", "handover",
797 "stop-ack", "shutdown-ack";
799 clocks = <&rpmhcc RPMH_CXO_CLK>;
802 power-domains = <&rpmhpd SM6350_CX>,
803 <&rpmhpd SM6350_MSS>;
804 power-domain-names = "cx", "mss";
806 memory-region = <&pil_modem_mem>;
808 qcom,qmp = <&aoss_qmp>;
810 qcom,smem-states = <&modem_smp2p_out 0>;
811 qcom,smem-state-names = "stop";
816 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
817 IPCC_MPROC_SIGNAL_GLINK_QMP
818 IRQ_TYPE_EDGE_RISING>;
819 mboxes = <&ipcc IPCC_CLIENT_MPSS
820 IPCC_MPROC_SIGNAL_GLINK_QMP>;
822 qcom,remote-pid = <1>;
826 cdsp: remoteproc@8300000 {
827 compatible = "qcom,sm6350-cdsp-pas";
828 reg = <0 0x08300000 0 0x10000>;
830 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
831 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
832 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
833 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
834 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
835 interrupt-names = "wdog", "fatal", "ready",
836 "handover", "stop-ack";
838 clocks = <&rpmhcc RPMH_CXO_CLK>;
841 power-domains = <&rpmhpd SM6350_CX>,
843 power-domain-names = "cx", "mx";
845 memory-region = <&pil_cdsp_mem>;
847 qcom,qmp = <&aoss_qmp>;
849 qcom,smem-states = <&smp2p_cdsp_out 0>;
850 qcom,smem-state-names = "stop";
855 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
856 IPCC_MPROC_SIGNAL_GLINK_QMP
857 IRQ_TYPE_EDGE_RISING>;
858 mboxes = <&ipcc IPCC_CLIENT_CDSP
859 IPCC_MPROC_SIGNAL_GLINK_QMP>;
862 qcom,remote-pid = <5>;
865 compatible = "qcom,fastrpc";
866 qcom,glink-channels = "fastrpcglink-apps-dsp";
868 #address-cells = <1>;
872 compatible = "qcom,fastrpc-compute-cb";
874 iommus = <&apps_smmu 0x1401 0x20>;
878 compatible = "qcom,fastrpc-compute-cb";
880 iommus = <&apps_smmu 0x1402 0x20>;
884 compatible = "qcom,fastrpc-compute-cb";
886 iommus = <&apps_smmu 0x1403 0x20>;
890 compatible = "qcom,fastrpc-compute-cb";
892 iommus = <&apps_smmu 0x1404 0x20>;
896 compatible = "qcom,fastrpc-compute-cb";
898 iommus = <&apps_smmu 0x1405 0x20>;
902 compatible = "qcom,fastrpc-compute-cb";
904 iommus = <&apps_smmu 0x1406 0x20>;
908 compatible = "qcom,fastrpc-compute-cb";
910 iommus = <&apps_smmu 0x1407 0x20>;
914 compatible = "qcom,fastrpc-compute-cb";
916 iommus = <&apps_smmu 0x1408 0x20>;
919 /* note: secure cb9 in downstream */
924 sdhc_2: mmc@8804000 {
925 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
926 reg = <0 0x08804000 0 0x1000>;
928 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
930 interrupt-names = "hc_irq", "pwr_irq";
932 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
933 <&gcc GCC_SDCC2_APPS_CLK>,
934 <&rpmhcc RPMH_CXO_CLK>;
935 clock-names = "iface", "core", "xo";
936 qcom,dll-config = <0x0007642c>;
937 qcom,ddr-config = <0x80040868>;
938 power-domains = <&rpmhpd 0>;
939 operating-points-v2 = <&sdhc2_opp_table>;
944 sdhc2_opp_table: opp-table {
945 compatible = "operating-points-v2";
948 opp-hz = /bits/ 64 <100000000>;
949 required-opps = <&rpmhpd_opp_svs_l1>;
953 opp-hz = /bits/ 64 <202000000>;
954 required-opps = <&rpmhpd_opp_nom>;
959 usb_1_hsphy: phy@88e3000 {
960 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
961 reg = <0 0x088e3000 0 0x400>;
965 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
966 clock-names = "cfg_ahb", "ref";
968 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
971 usb_1_qmpphy: phy@88e9000 {
972 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
973 reg = <0 0x088e9000 0 0x200>,
974 <0 0x088e8000 0 0x40>,
975 <0 0x088ea000 0 0x200>;
977 #address-cells = <2>;
981 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
983 <&rpmhcc RPMH_QLINK_CLK>,
984 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
985 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
987 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
988 <&gcc GCC_USB3_PHY_PRIM_BCR>;
989 reset-names = "phy", "common";
991 usb_1_ssphy: usb3-phy@88e9200 {
992 reg = <0 0x088e9200 0 0x200>,
993 <0 0x088e9400 0 0x200>,
994 <0 0x088e9c00 0 0x400>,
995 <0 0x088e9600 0 0x200>,
996 <0 0x088e9800 0 0x200>,
997 <0 0x088e9a00 0 0x100>;
1000 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1001 clock-names = "pipe0";
1002 clock-output-names = "usb3_phy_pipe_clk_src";
1005 dp_phy: dp-phy@88ea200 {
1006 reg = <0 0x088ea200 0 0x200>,
1007 <0 0x088ea400 0 0x200>,
1008 <0 0x088eac00 0 0x400>,
1009 <0 0x088ea600 0 0x200>,
1010 <0 0x088ea800 0 0x200>,
1011 <0 0x088eaa00 0 0x100>;
1014 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1015 clock-names = "pipe0";
1016 clock-output-names = "usb3_phy_pipe_clk_src";
1020 system-cache-controller@9200000 {
1021 compatible = "qcom,sm6350-llcc";
1022 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1023 reg-names = "llcc_base", "llcc_broadcast_base";
1026 usb_1: usb@a6f8800 {
1027 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1028 reg = <0 0x0a6f8800 0 0x400>;
1029 status = "disabled";
1030 #address-cells = <2>;
1034 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1035 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1036 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1037 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1038 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1039 clock-names = "cfg_noc",
1045 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1046 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1047 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1048 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
1050 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1051 "dm_hs_phy_irq", "dp_hs_phy_irq";
1053 power-domains = <&gcc USB30_PRIM_GDSC>;
1055 resets = <&gcc GCC_USB30_PRIM_BCR>;
1057 usb_1_dwc3: usb@a600000 {
1058 compatible = "snps,dwc3";
1059 reg = <0 0x0a600000 0 0xcd00>;
1060 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1061 iommus = <&apps_smmu 0x540 0x0>;
1062 snps,dis_u2_susphy_quirk;
1063 snps,dis_enblslpm_quirk;
1064 snps,has-lpm-erratum;
1065 snps,hird-threshold = /bits/ 8 <0x10>;
1066 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1067 phy-names = "usb2-phy", "usb3-phy";
1071 pdc: interrupt-controller@b220000 {
1072 compatible = "qcom,sm6350-pdc", "qcom,pdc";
1073 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
1074 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1075 <125 63 1>, <126 655 12>, <138 139 15>;
1076 #interrupt-cells = <2>;
1077 interrupt-parent = <&intc>;
1078 interrupt-controller;
1081 tsens0: thermal-sensor@c263000 {
1082 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
1083 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1084 <0 0x0c222000 0 0x8>; /* SROT */
1085 #qcom,sensors = <16>;
1086 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1087 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1088 interrupt-names = "uplow", "critical";
1089 #thermal-sensor-cells = <1>;
1092 tsens1: thermal-sensor@c265000 {
1093 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
1094 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1095 <0 0x0c223000 0 0x8>; /* SROT */
1096 #qcom,sensors = <16>;
1097 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1098 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1099 interrupt-names = "uplow", "critical";
1100 #thermal-sensor-cells = <1>;
1103 aoss_qmp: power-controller@c300000 {
1104 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
1105 reg = <0 0x0c300000 0 0x1000>;
1106 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1107 IRQ_TYPE_EDGE_RISING>;
1108 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1113 spmi_bus: spmi@c440000 {
1114 compatible = "qcom,spmi-pmic-arb";
1115 reg = <0 0xc440000 0 0x1100>,
1116 <0 0xc600000 0 0x2000000>,
1117 <0 0xe600000 0 0x100000>,
1118 <0 0xe700000 0 0xa0000>,
1119 <0 0xc40a000 0 0x26000>;
1120 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1121 interrupt-names = "periph_irq";
1122 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1125 #address-cells = <2>;
1127 interrupt-controller;
1128 #interrupt-cells = <4>;
1131 tlmm: pinctrl@f100000 {
1132 compatible = "qcom,sm6350-tlmm";
1133 reg = <0 0x0f100000 0 0x300000>;
1134 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1145 interrupt-controller;
1146 #interrupt-cells = <2>;
1147 gpio-ranges = <&tlmm 0 0 157>;
1149 qup_uart9_default: qup-uart9-default {
1150 pins = "gpio25", "gpio26";
1151 function = "qup13_f2";
1152 drive-strength = <2>;
1156 qup_i2c0_default: qup-i2c0-default {
1157 pins = "gpio0", "gpio1";
1159 drive-strength = <2>;
1163 qup_i2c2_default: qup-i2c2-default {
1164 pins = "gpio45", "gpio46";
1166 drive-strength = <2>;
1170 qup_i2c6_default: qup-i2c6-default {
1171 pins = "gpio13", "gpio14";
1173 drive-strength = <2>;
1177 qup_i2c7_default: qup-i2c7-default {
1178 pins = "gpio27", "gpio28";
1180 drive-strength = <2>;
1184 qup_i2c8_default: qup-i2c8-default {
1185 pins = "gpio19", "gpio20";
1187 drive-strength = <2>;
1191 qup_i2c10_default: qup-i2c10-default {
1192 pins = "gpio4", "gpio5";
1194 drive-strength = <2>;
1199 apps_smmu: iommu@15000000 {
1200 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
1201 reg = <0 0x15000000 0 0x100000>;
1203 #global-interrupts = <1>;
1204 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1287 intc: interrupt-controller@17a00000 {
1288 compatible = "arm,gic-v3";
1289 #interrupt-cells = <3>;
1290 interrupt-controller;
1291 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1292 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1293 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
1297 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
1298 reg = <0 0x17c10000 0 0x1000>;
1299 clocks = <&sleep_clk>;
1300 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1304 compatible = "arm,armv7-timer-mem";
1305 reg = <0x0 0x17c20000 0x0 0x1000>;
1306 clock-frequency = <19200000>;
1307 #address-cells = <1>;
1309 ranges = <0 0 0 0x20000000>;
1313 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1315 reg = <0x17c21000 0x1000>,
1316 <0x17c22000 0x1000>;
1321 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1322 reg = <0x17c23000 0x1000>;
1323 status = "disabled";
1328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1329 reg = <0x17c25000 0x1000>;
1330 status = "disabled";
1335 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1336 reg = <0x17c27000 0x1000>;
1337 status = "disabled";
1342 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1343 reg = <0x17c29000 0x1000>;
1344 status = "disabled";
1349 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1350 reg = <0x17c2b000 0x1000>;
1351 status = "disabled";
1356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1357 reg = <0x17c2d000 0x1000>;
1358 status = "disabled";
1362 wifi: wifi@18800000 {
1363 compatible = "qcom,wcn3990-wifi";
1364 reg = <0 0x18800000 0 0x800000>;
1365 reg-names = "membase";
1366 memory-region = <&wlan_fw_mem>;
1367 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1379 iommus = <&apps_smmu 0x20 0x1>;
1380 qcom,msa-fixed-perm;
1381 status = "disabled";
1384 apps_rsc: rsc@18200000 {
1385 compatible = "qcom,rpmh-rsc";
1387 reg = <0x0 0x18200000 0x0 0x10000>,
1388 <0x0 0x18210000 0x0 0x10000>,
1389 <0x0 0x18220000 0x0 0x10000>;
1390 reg-names = "drv-0", "drv-1", "drv-2";
1391 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1394 qcom,tcs-offset = <0xd00>;
1396 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1397 <WAKE_TCS 3>, <CONTROL_TCS 1>;
1399 rpmhcc: clock-controller {
1400 compatible = "qcom,sm6350-rpmh-clk";
1403 clocks = <&xo_board>;
1406 rpmhpd: power-controller {
1407 compatible = "qcom,sm6350-rpmhpd";
1408 #power-domain-cells = <1>;
1409 operating-points-v2 = <&rpmhpd_opp_table>;
1411 rpmhpd_opp_table: opp-table {
1412 compatible = "operating-points-v2";
1414 rpmhpd_opp_ret: opp1 {
1415 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1418 rpmhpd_opp_min_svs: opp2 {
1419 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1422 rpmhpd_opp_low_svs: opp3 {
1423 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1426 rpmhpd_opp_svs: opp4 {
1427 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1430 rpmhpd_opp_svs_l1: opp5 {
1431 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1434 rpmhpd_opp_nom: opp6 {
1435 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1438 rpmhpd_opp_nom_l1: opp7 {
1439 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1442 rpmhpd_opp_nom_l2: opp8 {
1443 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1446 rpmhpd_opp_turbo: opp9 {
1447 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1450 rpmhpd_opp_turbo_l1: opp10 {
1451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1456 apps_bcm_voter: bcm-voter {
1457 compatible = "qcom,bcm-voter";
1461 cpufreq_hw: cpufreq@18323000 {
1462 compatible = "qcom,cpufreq-hw";
1463 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
1464 reg-names = "freq-domain0", "freq-domain1";
1465 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1466 clock-names = "xo", "alternate";
1468 #freq-domain-cells = <1>;
1473 compatible = "arm,armv8-timer";
1474 clock-frequency = <19200000>;
1475 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1476 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1477 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1478 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;