1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
13 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep-clk {
28 compatible = "fixed-clock";
30 clock-frequency = <32000>;
31 clock-output-names = "sleep_clk";
41 compatible = "qcom,kryo260";
43 enable-method = "psci";
44 capacity-dmips-mhz = <1024>;
45 next-level-cache = <&L2_0>;
53 compatible = "qcom,kryo260";
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
62 compatible = "qcom,kryo260";
64 enable-method = "psci";
65 capacity-dmips-mhz = <1024>;
66 next-level-cache = <&L2_0>;
71 compatible = "qcom,kryo260";
73 enable-method = "psci";
74 capacity-dmips-mhz = <1024>;
75 next-level-cache = <&L2_0>;
80 compatible = "qcom,kryo260";
82 enable-method = "psci";
83 capacity-dmips-mhz = <1638>;
84 next-level-cache = <&L2_1>;
92 compatible = "qcom,kryo260";
94 enable-method = "psci";
95 capacity-dmips-mhz = <1638>;
96 next-level-cache = <&L2_1>;
101 compatible = "qcom,kryo260";
103 enable-method = "psci";
104 capacity-dmips-mhz = <1638>;
105 next-level-cache = <&L2_1>;
110 compatible = "qcom,kryo260";
112 enable-method = "psci";
113 capacity-dmips-mhz = <1638>;
114 next-level-cache = <&L2_1>;
158 compatible = "qcom,scm-sm6125", "qcom,scm";
164 /* We expect the bootloader to fill in the size */
165 reg = <0x0 0x40000000 0x0 0x0>;
166 device_type = "memory";
170 compatible = "arm,armv8-pmuv3";
171 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
175 compatible = "arm,psci-1.0";
179 reserved_memory: reserved-memory {
180 #address-cells = <2>;
184 hyp_mem: memory@45700000 {
185 reg = <0x0 0x45700000 0x0 0x600000>;
189 xbl_aop_mem: memory@45e00000 {
190 reg = <0x0 0x45e00000 0x0 0x140000>;
194 sec_apps_mem: memory@45fff000 {
195 reg = <0x0 0x45fff000 0x0 0x1000>;
199 smem_mem: memory@46000000 {
200 reg = <0x0 0x46000000 0x0 0x200000>;
204 reserved_mem1: memory@46200000 {
205 reg = <0x0 0x46200000 0x0 0x2d00000>;
209 camera_mem: memory@4ab00000 {
210 reg = <0x0 0x4ab00000 0x0 0x500000>;
214 modem_mem: memory@4b000000 {
215 reg = <0x0 0x4b000000 0x0 0x7e00000>;
219 venus_mem: memory@52e00000 {
220 reg = <0x0 0x52e00000 0x0 0x500000>;
224 wlan_msa_mem: memory@53300000 {
225 reg = <0x0 0x53300000 0x0 0x200000>;
229 cdsp_mem: memory@53500000 {
230 reg = <0x0 0x53500000 0x0 0x1e00000>;
234 adsp_pil_mem: memory@55300000 {
235 reg = <0x0 0x55300000 0x0 0x1e00000>;
239 ipa_fw_mem: memory@57100000 {
240 reg = <0x0 0x57100000 0x0 0x10000>;
244 ipa_gsi_mem: memory@57110000 {
245 reg = <0x0 0x57110000 0x0 0x5000>;
249 gpu_mem: memory@57115000 {
250 reg = <0x0 0x57115000 0x0 0x2000>;
254 cont_splash_mem: memory@5c000000 {
255 reg = <0x0 0x5c000000 0x0 0x00f00000>;
259 dfps_data_mem: memory@5cf00000 {
260 reg = <0x0 0x5cf00000 0x0 0x0100000>;
264 cdsp_sec_mem: memory@5f800000 {
265 reg = <0x0 0x5f800000 0x0 0x1e00000>;
269 qseecom_mem: memory@5e400000 {
270 reg = <0x0 0x5e400000 0x0 0x1400000>;
274 sdsp_mem: memory@f3000000 {
275 reg = <0x0 0xf3000000 0x0 0x400000>;
279 adsp_mem: memory@f3400000 {
280 reg = <0x0 0xf3400000 0x0 0x800000>;
284 qseecom_ta_mem: memory@13fc00000 {
285 reg = <0x1 0x3fc00000 0x0 0x400000>;
291 compatible = "qcom,glink-rpm";
293 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
294 qcom,rpm-msg-ram = <&rpm_msg_ram>;
295 mboxes = <&apcs_glb 0>;
297 rpm_requests: rpm-requests {
298 compatible = "qcom,rpm-sm6125";
299 qcom,glink-channels = "rpm_requests";
301 rpmcc: clock-controller {
302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
309 compatible = "qcom,smem";
310 memory-region = <&smem_mem>;
311 hwlocks = <&tcsr_mutex 3>;
315 #address-cells = <1>;
317 ranges = <0x00 0x00 0x00 0xffffffff>;
318 compatible = "simple-bus";
320 tcsr_mutex: hwlock@340000 {
321 compatible = "qcom,tcsr-mutex";
322 reg = <0x00340000 0x20000>;
326 tlmm: pinctrl@500000 {
327 compatible = "qcom,sm6125-tlmm";
328 reg = <0x00500000 0x400000>,
329 <0x00900000 0x400000>,
330 <0x00d00000 0x400000>;
331 reg-names = "west", "south", "east";
332 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
334 gpio-ranges = <&tlmm 0 0 134>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
339 sdc2_state_off: sdc2-off {
343 drive-strength = <2>;
349 drive-strength = <2>;
355 drive-strength = <2>;
360 gcc: clock-controller@1400000 {
361 compatible = "qcom,gcc-sm6125";
362 reg = <0x01400000 0x1f0000>;
365 #power-domain-cells = <1>;
366 clock-names = "bi_tcxo", "sleep_clk";
367 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
370 hsusb_phy1: phy@1613000 {
371 compatible = "qcom,msm8996-qusb2-phy";
372 reg = <0x01613000 0x180>;
375 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
376 <&gcc GCC_AHB2PHY_USB_CLK>;
377 clock-names = "ref", "cfg_ahb";
379 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
383 rpm_msg_ram: memory@45f0000 {
384 compatible = "qcom,rpm-msg-ram";
385 reg = <0x045f0000 0x7000>;
388 sdhc_1: sdhci@4744000 {
389 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
390 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
391 reg-names = "hc", "core";
393 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-names = "hc_irq", "pwr_irq";
397 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
398 <&gcc GCC_SDCC1_APPS_CLK>,
400 clock-names = "iface", "core", "xo";
406 sdhc_2: sdhci@4784000 {
407 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
408 reg = <0x04784000 0x1000>;
411 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "hc_irq", "pwr_irq";
415 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
416 <&gcc GCC_SDCC2_APPS_CLK>,
418 clock-names = "iface", "core", "xo";
420 pinctrl-0 = <&sdc2_state_on>;
421 pinctrl-1 = <&sdc2_state_off>;
422 pinctrl-names = "default", "sleep";
429 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
430 reg = <0x04ef8800 0x400>;
431 #address-cells = <1>;
435 clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
436 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
437 <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
438 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
439 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
440 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
442 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
443 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
444 assigned-clock-rates = <19200000>, <66666667>;
446 power-domains = <&gcc USB30_PRIM_GDSC>;
447 qcom,select-utmi-as-pipe-clk;
450 usb3_dwc3: usb@4e00000 {
451 compatible = "snps,dwc3";
452 reg = <0x04e00000 0xcd00>;
453 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
454 phys = <&hsusb_phy1>;
455 phy-names = "usb2-phy";
456 snps,dis_u2_susphy_quirk;
457 snps,dis_enblslpm_quirk;
458 maximum-speed = "high-speed";
459 dr_mode = "peripheral";
463 spmi_bus: spmi@1c40000 {
464 compatible = "qcom,spmi-pmic-arb";
465 reg = <0x01c40000 0x1100>,
466 <0x01e00000 0x2000000>,
467 <0x03e00000 0x100000>,
468 <0x03f00000 0xa0000>,
469 <0x01c0a000 0x26000>;
470 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
471 interrupt-names = "periph_irq";
472 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <2>;
477 interrupt-controller;
478 #interrupt-cells = <4>;
482 apcs_glb: mailbox@f111000 {
483 compatible = "qcom,sm6125-apcs-hmss-global";
484 reg = <0x0f111000 0x1000>;
490 compatible = "arm,armv7-timer-mem";
491 #address-cells = <1>;
494 reg = <0x0f120000 0x1000>;
495 clock-frequency = <19200000>;
499 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
501 reg = <0x0f121000 0x1000>,
507 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
508 reg = <0x0f123000 0x1000>;
514 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
515 reg = <0x0f124000 0x1000>;
521 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
522 reg = <0x0f125000 0x1000>;
528 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
529 reg = <0x0f126000 0x1000>;
535 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
536 reg = <0x0f127000 0x1000>;
542 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
543 reg = <0x0f128000 0x1000>;
548 intc: interrupt-controller@f200000 {
549 compatible = "arm,gic-v3";
550 reg = <0x0f200000 0x20000>,
551 <0x0f300000 0x100000>;
552 #interrupt-cells = <3>;
553 interrupt-controller;
554 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
559 compatible = "arm,armv8-timer";
560 interrupts = <GIC_PPI 1 0xf08
564 clock-frequency = <19200000>;