1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
13 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep-clk {
28 compatible = "fixed-clock";
30 clock-frequency = <32000>;
31 clock-output-names = "sleep_clk";
41 compatible = "qcom,kryo260";
43 enable-method = "psci";
44 capacity-dmips-mhz = <1024>;
45 next-level-cache = <&L2_0>;
53 compatible = "qcom,kryo260";
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
62 compatible = "qcom,kryo260";
64 enable-method = "psci";
65 capacity-dmips-mhz = <1024>;
66 next-level-cache = <&L2_0>;
71 compatible = "qcom,kryo260";
73 enable-method = "psci";
74 capacity-dmips-mhz = <1024>;
75 next-level-cache = <&L2_0>;
80 compatible = "qcom,kryo260";
82 enable-method = "psci";
83 capacity-dmips-mhz = <1638>;
84 next-level-cache = <&L2_1>;
92 compatible = "qcom,kryo260";
94 enable-method = "psci";
95 capacity-dmips-mhz = <1638>;
96 next-level-cache = <&L2_1>;
101 compatible = "qcom,kryo260";
103 enable-method = "psci";
104 capacity-dmips-mhz = <1638>;
105 next-level-cache = <&L2_1>;
110 compatible = "qcom,kryo260";
112 enable-method = "psci";
113 capacity-dmips-mhz = <1638>;
114 next-level-cache = <&L2_1>;
158 compatible = "qcom,scm-sm6125", "qcom,scm";
164 /* We expect the bootloader to fill in the size */
165 reg = <0x0 0x40000000 0x0 0x0>;
166 device_type = "memory";
170 compatible = "arm,armv8-pmuv3";
171 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
175 compatible = "arm,psci-1.0";
179 reserved_memory: reserved-memory {
180 #address-cells = <2>;
184 hyp_mem: memory@45700000 {
185 reg = <0x0 0x45700000 0x0 0x600000>;
189 xbl_aop_mem: memory@45e00000 {
190 reg = <0x0 0x45e00000 0x0 0x140000>;
194 sec_apps_mem: memory@45fff000 {
195 reg = <0x0 0x45fff000 0x0 0x1000>;
199 smem_mem: memory@46000000 {
200 reg = <0x0 0x46000000 0x0 0x200000>;
204 reserved_mem1: memory@46200000 {
205 reg = <0x0 0x46200000 0x0 0x2d00000>;
209 camera_mem: memory@4ab00000 {
210 reg = <0x0 0x4ab00000 0x0 0x500000>;
214 modem_mem: memory@4b000000 {
215 reg = <0x0 0x4b000000 0x0 0x7e00000>;
219 venus_mem: memory@52e00000 {
220 reg = <0x0 0x52e00000 0x0 0x500000>;
224 wlan_msa_mem: memory@53300000 {
225 reg = <0x0 0x53300000 0x0 0x200000>;
229 cdsp_mem: memory@53500000 {
230 reg = <0x0 0x53500000 0x0 0x1e00000>;
234 adsp_pil_mem: memory@55300000 {
235 reg = <0x0 0x55300000 0x0 0x1e00000>;
239 ipa_fw_mem: memory@57100000 {
240 reg = <0x0 0x57100000 0x0 0x10000>;
244 ipa_gsi_mem: memory@57110000 {
245 reg = <0x0 0x57110000 0x0 0x5000>;
249 gpu_mem: memory@57115000 {
250 reg = <0x0 0x57115000 0x0 0x2000>;
254 cont_splash_mem: memory@5c000000 {
255 reg = <0x0 0x5c000000 0x0 0x00f00000>;
259 dfps_data_mem: memory@5cf00000 {
260 reg = <0x0 0x5cf00000 0x0 0x0100000>;
264 cdsp_sec_mem: memory@5f800000 {
265 reg = <0x0 0x5f800000 0x0 0x1e00000>;
269 qseecom_mem: memory@5e400000 {
270 reg = <0x0 0x5e400000 0x0 0x1400000>;
274 sdsp_mem: memory@f3000000 {
275 reg = <0x0 0xf3000000 0x0 0x400000>;
279 adsp_mem: memory@f3400000 {
280 reg = <0x0 0xf3400000 0x0 0x800000>;
284 qseecom_ta_mem: memory@13fc00000 {
285 reg = <0x1 0x3fc00000 0x0 0x400000>;
291 compatible = "qcom,glink-rpm";
293 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
294 qcom,rpm-msg-ram = <&rpm_msg_ram>;
295 mboxes = <&apcs_glb 0>;
297 rpm_requests: rpm-requests {
298 compatible = "qcom,rpm-sm6125";
299 qcom,glink-channels = "rpm_requests";
301 rpmcc: clock-controller {
302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
306 rpmpd: power-controller {
307 compatible = "qcom,sm6125-rpmpd";
308 #power-domain-cells = <1>;
309 operating-points-v2 = <&rpmpd_opp_table>;
311 rpmpd_opp_table: opp-table {
312 compatible = "operating-points-v2";
314 rpmpd_opp_ret: opp1 {
315 opp-level = <RPM_SMD_LEVEL_RETENTION>;
318 rpmpd_opp_ret_plus: opp2 {
319 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
322 rpmpd_opp_min_svs: opp3 {
323 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
326 rpmpd_opp_low_svs: opp4 {
327 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
330 rpmpd_opp_svs: opp5 {
331 opp-level = <RPM_SMD_LEVEL_SVS>;
334 rpmpd_opp_svs_plus: opp6 {
335 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
338 rpmpd_opp_nom: opp7 {
339 opp-level = <RPM_SMD_LEVEL_NOM>;
342 rpmpd_opp_nom_plus: opp8 {
343 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
346 rpmpd_opp_turbo: opp9 {
347 opp-level = <RPM_SMD_LEVEL_TURBO>;
350 rpmpd_opp_turbo_no_cpr: opp10 {
351 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
359 compatible = "qcom,smem";
360 memory-region = <&smem_mem>;
361 hwlocks = <&tcsr_mutex 3>;
365 #address-cells = <1>;
367 ranges = <0x00 0x00 0x00 0xffffffff>;
368 compatible = "simple-bus";
370 tcsr_mutex: hwlock@340000 {
371 compatible = "qcom,tcsr-mutex";
372 reg = <0x00340000 0x20000>;
376 tlmm: pinctrl@500000 {
377 compatible = "qcom,sm6125-tlmm";
378 reg = <0x00500000 0x400000>,
379 <0x00900000 0x400000>,
380 <0x00d00000 0x400000>;
381 reg-names = "west", "south", "east";
382 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
384 gpio-ranges = <&tlmm 0 0 134>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
389 sdc2_state_off: sdc2-off {
393 drive-strength = <2>;
399 drive-strength = <2>;
405 drive-strength = <2>;
410 gcc: clock-controller@1400000 {
411 compatible = "qcom,gcc-sm6125";
412 reg = <0x01400000 0x1f0000>;
415 #power-domain-cells = <1>;
416 clock-names = "bi_tcxo", "sleep_clk";
417 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
420 hsusb_phy1: phy@1613000 {
421 compatible = "qcom,msm8996-qusb2-phy";
422 reg = <0x01613000 0x180>;
425 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
426 <&gcc GCC_AHB2PHY_USB_CLK>;
427 clock-names = "ref", "cfg_ahb";
429 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
433 rpm_msg_ram: sram@45f0000 {
434 compatible = "qcom,rpm-msg-ram";
435 reg = <0x045f0000 0x7000>;
438 sdhc_1: sdhci@4744000 {
439 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
440 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
441 reg-names = "hc", "core";
443 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "hc_irq", "pwr_irq";
447 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
448 <&gcc GCC_SDCC1_APPS_CLK>,
450 clock-names = "iface", "core", "xo";
452 power-domains = <&rpmpd SM6125_VDDCX>;
459 sdhc_2: sdhci@4784000 {
460 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
461 reg = <0x04784000 0x1000>;
464 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-names = "hc_irq", "pwr_irq";
468 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
469 <&gcc GCC_SDCC2_APPS_CLK>,
471 clock-names = "iface", "core", "xo";
473 pinctrl-0 = <&sdc2_state_on>;
474 pinctrl-1 = <&sdc2_state_off>;
475 pinctrl-names = "default", "sleep";
477 power-domains = <&rpmpd SM6125_VDDCX>;
484 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
485 reg = <0x04ef8800 0x400>;
486 #address-cells = <1>;
490 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
491 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
492 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
493 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
494 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
495 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
496 clock-names = "cfg_noc",
503 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
504 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
505 assigned-clock-rates = <19200000>, <66666667>;
507 power-domains = <&gcc USB30_PRIM_GDSC>;
508 qcom,select-utmi-as-pipe-clk;
511 usb3_dwc3: usb@4e00000 {
512 compatible = "snps,dwc3";
513 reg = <0x04e00000 0xcd00>;
514 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
515 phys = <&hsusb_phy1>;
516 phy-names = "usb2-phy";
517 snps,dis_u2_susphy_quirk;
518 snps,dis_enblslpm_quirk;
519 maximum-speed = "high-speed";
520 dr_mode = "peripheral";
525 compatible = "qcom,rpm-stats";
526 reg = <0x04690000 0x10000>;
529 spmi_bus: spmi@1c40000 {
530 compatible = "qcom,spmi-pmic-arb";
531 reg = <0x01c40000 0x1100>,
532 <0x01e00000 0x2000000>,
533 <0x03e00000 0x100000>,
534 <0x03f00000 0xa0000>,
535 <0x01c0a000 0x26000>;
536 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
537 interrupt-names = "periph_irq";
538 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <2>;
543 interrupt-controller;
544 #interrupt-cells = <4>;
548 apcs_glb: mailbox@f111000 {
549 compatible = "qcom,sm6125-apcs-hmss-global";
550 reg = <0x0f111000 0x1000>;
556 compatible = "arm,armv7-timer-mem";
557 #address-cells = <1>;
560 reg = <0x0f120000 0x1000>;
561 clock-frequency = <19200000>;
565 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
567 reg = <0x0f121000 0x1000>,
573 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
574 reg = <0x0f123000 0x1000>;
580 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
581 reg = <0x0f124000 0x1000>;
587 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
588 reg = <0x0f125000 0x1000>;
594 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
595 reg = <0x0f126000 0x1000>;
601 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
602 reg = <0x0f127000 0x1000>;
608 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
609 reg = <0x0f128000 0x1000>;
614 intc: interrupt-controller@f200000 {
615 compatible = "arm,gic-v3";
616 reg = <0x0f200000 0x20000>,
617 <0x0f300000 0x100000>;
618 #interrupt-cells = <3>;
619 interrupt-controller;
620 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
625 compatible = "arm,armv8-timer";
626 interrupts = <GIC_PPI 1 0xf08
630 clock-frequency = <19200000>;