arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sdm845.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,apr.h>
  23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         aliases {
  34                 i2c0 = &i2c0;
  35                 i2c1 = &i2c1;
  36                 i2c2 = &i2c2;
  37                 i2c3 = &i2c3;
  38                 i2c4 = &i2c4;
  39                 i2c5 = &i2c5;
  40                 i2c6 = &i2c6;
  41                 i2c7 = &i2c7;
  42                 i2c8 = &i2c8;
  43                 i2c9 = &i2c9;
  44                 i2c10 = &i2c10;
  45                 i2c11 = &i2c11;
  46                 i2c12 = &i2c12;
  47                 i2c13 = &i2c13;
  48                 i2c14 = &i2c14;
  49                 i2c15 = &i2c15;
  50                 spi0 = &spi0;
  51                 spi1 = &spi1;
  52                 spi2 = &spi2;
  53                 spi3 = &spi3;
  54                 spi4 = &spi4;
  55                 spi5 = &spi5;
  56                 spi6 = &spi6;
  57                 spi7 = &spi7;
  58                 spi8 = &spi8;
  59                 spi9 = &spi9;
  60                 spi10 = &spi10;
  61                 spi11 = &spi11;
  62                 spi12 = &spi12;
  63                 spi13 = &spi13;
  64                 spi14 = &spi14;
  65                 spi15 = &spi15;
  66         };
  67
  68         chosen { };
  69
  70         memory@80000000 {
  71                 device_type = "memory";
  72                 /* We expect the bootloader to fill in the size */
  73                 reg = <0 0x80000000 0 0>;
  74         };
  75
  76         reserved-memory {
  77                 #address-cells = <2>;
  78                 #size-cells = <2>;
  79                 ranges;
  80
  81                 hyp_mem: memory@85700000 {
  82                         reg = <0 0x85700000 0 0x600000>;
  83                         no-map;
  84                 };
  85
  86                 xbl_mem: memory@85e00000 {
  87                         reg = <0 0x85e00000 0 0x100000>;
  88                         no-map;
  89                 };
  90
  91                 aop_mem: memory@85fc0000 {
  92                         reg = <0 0x85fc0000 0 0x20000>;
  93                         no-map;
  94                 };
  95
  96                 aop_cmd_db_mem: memory@85fe0000 {
  97                         compatible = "qcom,cmd-db";
  98                         reg = <0x0 0x85fe0000 0 0x20000>;
  99                         no-map;
 100                 };
 101
 102                 smem_mem: memory@86000000 {
 103                         reg = <0x0 0x86000000 0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 tz_mem: memory@86200000 {
 108                         reg = <0 0x86200000 0 0x2d00000>;
 109                         no-map;
 110                 };
 111
 112                 rmtfs_mem: memory@88f00000 {
 113                         compatible = "qcom,rmtfs-mem";
 114                         reg = <0 0x88f00000 0 0x200000>;
 115                         no-map;
 116
 117                         qcom,client-id = <1>;
 118                         qcom,vmid = <15>;
 119                 };
 120
 121                 qseecom_mem: memory@8ab00000 {
 122                         reg = <0 0x8ab00000 0 0x1400000>;
 123                         no-map;
 124                 };
 125
 126                 camera_mem: memory@8bf00000 {
 127                         reg = <0 0x8bf00000 0 0x500000>;
 128                         no-map;
 129                 };
 130
 131                 ipa_fw_mem: memory@8c400000 {
 132                         reg = <0 0x8c400000 0 0x10000>;
 133                         no-map;
 134                 };
 135
 136                 ipa_gsi_mem: memory@8c410000 {
 137                         reg = <0 0x8c410000 0 0x5000>;
 138                         no-map;
 139                 };
 140
 141                 gpu_mem: memory@8c415000 {
 142                         reg = <0 0x8c415000 0 0x2000>;
 143                         no-map;
 144                 };
 145
 146                 adsp_mem: memory@8c500000 {
 147                         reg = <0 0x8c500000 0 0x1a00000>;
 148                         no-map;
 149                 };
 150
 151                 wlan_msa_mem: memory@8df00000 {
 152                         reg = <0 0x8df00000 0 0x100000>;
 153                         no-map;
 154                 };
 155
 156                 mpss_region: memory@8e000000 {
 157                         reg = <0 0x8e000000 0 0x7800000>;
 158                         no-map;
 159                 };
 160
 161                 venus_mem: memory@95800000 {
 162                         reg = <0 0x95800000 0 0x500000>;
 163                         no-map;
 164                 };
 165
 166                 cdsp_mem: memory@95d00000 {
 167                         reg = <0 0x95d00000 0 0x800000>;
 168                         no-map;
 169                 };
 170
 171                 mba_region: memory@96500000 {
 172                         reg = <0 0x96500000 0 0x200000>;
 173                         no-map;
 174                 };
 175
 176                 slpi_mem: memory@96700000 {
 177                         reg = <0 0x96700000 0 0x1400000>;
 178                         no-map;
 179                 };
 180
 181                 spss_mem: memory@97b00000 {
 182                         reg = <0 0x97b00000 0 0x100000>;
 183                         no-map;
 184                 };
 185         };
 186
 187         cpus {
 188                 #address-cells = <2>;
 189                 #size-cells = <0>;
 190
 191                 CPU0: cpu@0 {
 192                         device_type = "cpu";
 193                         compatible = "qcom,kryo385";
 194                         reg = <0x0 0x0>;
 195                         enable-method = "psci";
 196                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 197                                            &LITTLE_CPU_SLEEP_1
 198                                            &CLUSTER_SLEEP_0>;
 199                         capacity-dmips-mhz = <607>;
 200                         dynamic-power-coefficient = <100>;
 201                         qcom,freq-domain = <&cpufreq_hw 0>;
 202                         operating-points-v2 = <&cpu0_opp_table>;
 203                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 204                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 205                         #cooling-cells = <2>;
 206                         next-level-cache = <&L2_0>;
 207                         L2_0: l2-cache {
 208                                 compatible = "cache";
 209                                 next-level-cache = <&L3_0>;
 210                                 L3_0: l3-cache {
 211                                       compatible = "cache";
 212                                 };
 213                         };
 214                 };
 215
 216                 CPU1: cpu@100 {
 217                         device_type = "cpu";
 218                         compatible = "qcom,kryo385";
 219                         reg = <0x0 0x100>;
 220                         enable-method = "psci";
 221                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 222                                            &LITTLE_CPU_SLEEP_1
 223                                            &CLUSTER_SLEEP_0>;
 224                         capacity-dmips-mhz = <607>;
 225                         dynamic-power-coefficient = <100>;
 226                         qcom,freq-domain = <&cpufreq_hw 0>;
 227                         operating-points-v2 = <&cpu0_opp_table>;
 228                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 229                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 230                         #cooling-cells = <2>;
 231                         next-level-cache = <&L2_100>;
 232                         L2_100: l2-cache {
 233                                 compatible = "cache";
 234                                 next-level-cache = <&L3_0>;
 235                         };
 236                 };
 237
 238                 CPU2: cpu@200 {
 239                         device_type = "cpu";
 240                         compatible = "qcom,kryo385";
 241                         reg = <0x0 0x200>;
 242                         enable-method = "psci";
 243                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 244                                            &LITTLE_CPU_SLEEP_1
 245                                            &CLUSTER_SLEEP_0>;
 246                         capacity-dmips-mhz = <607>;
 247                         dynamic-power-coefficient = <100>;
 248                         qcom,freq-domain = <&cpufreq_hw 0>;
 249                         operating-points-v2 = <&cpu0_opp_table>;
 250                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 251                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 252                         #cooling-cells = <2>;
 253                         next-level-cache = <&L2_200>;
 254                         L2_200: l2-cache {
 255                                 compatible = "cache";
 256                                 next-level-cache = <&L3_0>;
 257                         };
 258                 };
 259
 260                 CPU3: cpu@300 {
 261                         device_type = "cpu";
 262                         compatible = "qcom,kryo385";
 263                         reg = <0x0 0x300>;
 264                         enable-method = "psci";
 265                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 266                                            &LITTLE_CPU_SLEEP_1
 267                                            &CLUSTER_SLEEP_0>;
 268                         capacity-dmips-mhz = <607>;
 269                         dynamic-power-coefficient = <100>;
 270                         qcom,freq-domain = <&cpufreq_hw 0>;
 271                         operating-points-v2 = <&cpu0_opp_table>;
 272                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 273                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 274                         #cooling-cells = <2>;
 275                         next-level-cache = <&L2_300>;
 276                         L2_300: l2-cache {
 277                                 compatible = "cache";
 278                                 next-level-cache = <&L3_0>;
 279                         };
 280                 };
 281
 282                 CPU4: cpu@400 {
 283                         device_type = "cpu";
 284                         compatible = "qcom,kryo385";
 285                         reg = <0x0 0x400>;
 286                         enable-method = "psci";
 287                         capacity-dmips-mhz = <1024>;
 288                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 289                                            &BIG_CPU_SLEEP_1
 290                                            &CLUSTER_SLEEP_0>;
 291                         dynamic-power-coefficient = <396>;
 292                         qcom,freq-domain = <&cpufreq_hw 1>;
 293                         operating-points-v2 = <&cpu4_opp_table>;
 294                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 295                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 296                         #cooling-cells = <2>;
 297                         next-level-cache = <&L2_400>;
 298                         L2_400: l2-cache {
 299                                 compatible = "cache";
 300                                 next-level-cache = <&L3_0>;
 301                         };
 302                 };
 303
 304                 CPU5: cpu@500 {
 305                         device_type = "cpu";
 306                         compatible = "qcom,kryo385";
 307                         reg = <0x0 0x500>;
 308                         enable-method = "psci";
 309                         capacity-dmips-mhz = <1024>;
 310                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 311                                            &BIG_CPU_SLEEP_1
 312                                            &CLUSTER_SLEEP_0>;
 313                         dynamic-power-coefficient = <396>;
 314                         qcom,freq-domain = <&cpufreq_hw 1>;
 315                         operating-points-v2 = <&cpu4_opp_table>;
 316                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 317                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 318                         #cooling-cells = <2>;
 319                         next-level-cache = <&L2_500>;
 320                         L2_500: l2-cache {
 321                                 compatible = "cache";
 322                                 next-level-cache = <&L3_0>;
 323                         };
 324                 };
 325
 326                 CPU6: cpu@600 {
 327                         device_type = "cpu";
 328                         compatible = "qcom,kryo385";
 329                         reg = <0x0 0x600>;
 330                         enable-method = "psci";
 331                         capacity-dmips-mhz = <1024>;
 332                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 333                                            &BIG_CPU_SLEEP_1
 334                                            &CLUSTER_SLEEP_0>;
 335                         dynamic-power-coefficient = <396>;
 336                         qcom,freq-domain = <&cpufreq_hw 1>;
 337                         operating-points-v2 = <&cpu4_opp_table>;
 338                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 339                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 340                         #cooling-cells = <2>;
 341                         next-level-cache = <&L2_600>;
 342                         L2_600: l2-cache {
 343                                 compatible = "cache";
 344                                 next-level-cache = <&L3_0>;
 345                         };
 346                 };
 347
 348                 CPU7: cpu@700 {
 349                         device_type = "cpu";
 350                         compatible = "qcom,kryo385";
 351                         reg = <0x0 0x700>;
 352                         enable-method = "psci";
 353                         capacity-dmips-mhz = <1024>;
 354                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 355                                            &BIG_CPU_SLEEP_1
 356                                            &CLUSTER_SLEEP_0>;
 357                         dynamic-power-coefficient = <396>;
 358                         qcom,freq-domain = <&cpufreq_hw 1>;
 359                         operating-points-v2 = <&cpu4_opp_table>;
 360                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 361                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 362                         #cooling-cells = <2>;
 363                         next-level-cache = <&L2_700>;
 364                         L2_700: l2-cache {
 365                                 compatible = "cache";
 366                                 next-level-cache = <&L3_0>;
 367                         };
 368                 };
 369
 370                 cpu-map {
 371                         cluster0 {
 372                                 core0 {
 373                                         cpu = <&CPU0>;
 374                                 };
 375
 376                                 core1 {
 377                                         cpu = <&CPU1>;
 378                                 };
 379
 380                                 core2 {
 381                                         cpu = <&CPU2>;
 382                                 };
 383
 384                                 core3 {
 385                                         cpu = <&CPU3>;
 386                                 };
 387
 388                                 core4 {
 389                                         cpu = <&CPU4>;
 390                                 };
 391
 392                                 core5 {
 393                                         cpu = <&CPU5>;
 394                                 };
 395
 396                                 core6 {
 397                                         cpu = <&CPU6>;
 398                                 };
 399
 400                                 core7 {
 401                                         cpu = <&CPU7>;
 402                                 };
 403                         };
 404                 };
 405
 406                 idle-states {
 407                         entry-method = "psci";
 408
 409                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 410                                 compatible = "arm,idle-state";
 411                                 idle-state-name = "little-power-down";
 412                                 arm,psci-suspend-param = <0x40000003>;
 413                                 entry-latency-us = <350>;
 414                                 exit-latency-us = <461>;
 415                                 min-residency-us = <1890>;
 416                                 local-timer-stop;
 417                         };
 418
 419                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 420                                 compatible = "arm,idle-state";
 421                                 idle-state-name = "little-rail-power-down";
 422                                 arm,psci-suspend-param = <0x40000004>;
 423                                 entry-latency-us = <360>;
 424                                 exit-latency-us = <531>;
 425                                 min-residency-us = <3934>;
 426                                 local-timer-stop;
 427                         };
 428
 429                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 430                                 compatible = "arm,idle-state";
 431                                 idle-state-name = "big-power-down";
 432                                 arm,psci-suspend-param = <0x40000003>;
 433                                 entry-latency-us = <264>;
 434                                 exit-latency-us = <621>;
 435                                 min-residency-us = <952>;
 436                                 local-timer-stop;
 437                         };
 438
 439                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 440                                 compatible = "arm,idle-state";
 441                                 idle-state-name = "big-rail-power-down";
 442                                 arm,psci-suspend-param = <0x40000004>;
 443                                 entry-latency-us = <702>;
 444                                 exit-latency-us = <1061>;
 445                                 min-residency-us = <4488>;
 446                                 local-timer-stop;
 447                         };
 448
 449                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 450                                 compatible = "arm,idle-state";
 451                                 idle-state-name = "cluster-power-down";
 452                                 arm,psci-suspend-param = <0x400000F4>;
 453                                 entry-latency-us = <3263>;
 454                                 exit-latency-us = <6562>;
 455                                 min-residency-us = <9987>;
 456                                 local-timer-stop;
 457                         };
 458                 };
 459         };
 460
 461         cpu0_opp_table: cpu0_opp_table {
 462                 compatible = "operating-points-v2";
 463                 opp-shared;
 464
 465                 cpu0_opp1: opp-300000000 {
 466                         opp-hz = /bits/ 64 <300000000>;
 467                         opp-peak-kBps = <800000 4800000>;
 468                 };
 469
 470                 cpu0_opp2: opp-403200000 {
 471                         opp-hz = /bits/ 64 <403200000>;
 472                         opp-peak-kBps = <800000 4800000>;
 473                 };
 474
 475                 cpu0_opp3: opp-480000000 {
 476                         opp-hz = /bits/ 64 <480000000>;
 477                         opp-peak-kBps = <800000 6451200>;
 478                 };
 479
 480                 cpu0_opp4: opp-576000000 {
 481                         opp-hz = /bits/ 64 <576000000>;
 482                         opp-peak-kBps = <800000 6451200>;
 483                 };
 484
 485                 cpu0_opp5: opp-652800000 {
 486                         opp-hz = /bits/ 64 <652800000>;
 487                         opp-peak-kBps = <800000 7680000>;
 488                 };
 489
 490                 cpu0_opp6: opp-748800000 {
 491                         opp-hz = /bits/ 64 <748800000>;
 492                         opp-peak-kBps = <1804000 9216000>;
 493                 };
 494
 495                 cpu0_opp7: opp-825600000 {
 496                         opp-hz = /bits/ 64 <825600000>;
 497                         opp-peak-kBps = <1804000 9216000>;
 498                 };
 499
 500                 cpu0_opp8: opp-902400000 {
 501                         opp-hz = /bits/ 64 <902400000>;
 502                         opp-peak-kBps = <1804000 10444800>;
 503                 };
 504
 505                 cpu0_opp9: opp-979200000 {
 506                         opp-hz = /bits/ 64 <979200000>;
 507                         opp-peak-kBps = <1804000 11980800>;
 508                 };
 509
 510                 cpu0_opp10: opp-1056000000 {
 511                         opp-hz = /bits/ 64 <1056000000>;
 512                         opp-peak-kBps = <1804000 11980800>;
 513                 };
 514
 515                 cpu0_opp11: opp-1132800000 {
 516                         opp-hz = /bits/ 64 <1132800000>;
 517                         opp-peak-kBps = <2188000 13516800>;
 518                 };
 519
 520                 cpu0_opp12: opp-1228800000 {
 521                         opp-hz = /bits/ 64 <1228800000>;
 522                         opp-peak-kBps = <2188000 15052800>;
 523                 };
 524
 525                 cpu0_opp13: opp-1324800000 {
 526                         opp-hz = /bits/ 64 <1324800000>;
 527                         opp-peak-kBps = <2188000 16588800>;
 528                 };
 529
 530                 cpu0_opp14: opp-1420800000 {
 531                         opp-hz = /bits/ 64 <1420800000>;
 532                         opp-peak-kBps = <3072000 18124800>;
 533                 };
 534
 535                 cpu0_opp15: opp-1516800000 {
 536                         opp-hz = /bits/ 64 <1516800000>;
 537                         opp-peak-kBps = <3072000 19353600>;
 538                 };
 539
 540                 cpu0_opp16: opp-1612800000 {
 541                         opp-hz = /bits/ 64 <1612800000>;
 542                         opp-peak-kBps = <4068000 19353600>;
 543                 };
 544
 545                 cpu0_opp17: opp-1689600000 {
 546                         opp-hz = /bits/ 64 <1689600000>;
 547                         opp-peak-kBps = <4068000 20889600>;
 548                 };
 549
 550                 cpu0_opp18: opp-1766400000 {
 551                         opp-hz = /bits/ 64 <1766400000>;
 552                         opp-peak-kBps = <4068000 22425600>;
 553                 };
 554         };
 555
 556         cpu4_opp_table: cpu4_opp_table {
 557                 compatible = "operating-points-v2";
 558                 opp-shared;
 559
 560                 cpu4_opp1: opp-300000000 {
 561                         opp-hz = /bits/ 64 <300000000>;
 562                         opp-peak-kBps = <800000 4800000>;
 563                 };
 564
 565                 cpu4_opp2: opp-403200000 {
 566                         opp-hz = /bits/ 64 <403200000>;
 567                         opp-peak-kBps = <800000 4800000>;
 568                 };
 569
 570                 cpu4_opp3: opp-480000000 {
 571                         opp-hz = /bits/ 64 <480000000>;
 572                         opp-peak-kBps = <1804000 4800000>;
 573                 };
 574
 575                 cpu4_opp4: opp-576000000 {
 576                         opp-hz = /bits/ 64 <576000000>;
 577                         opp-peak-kBps = <1804000 4800000>;
 578                 };
 579
 580                 cpu4_opp5: opp-652800000 {
 581                         opp-hz = /bits/ 64 <652800000>;
 582                         opp-peak-kBps = <1804000 4800000>;
 583                 };
 584
 585                 cpu4_opp6: opp-748800000 {
 586                         opp-hz = /bits/ 64 <748800000>;
 587                         opp-peak-kBps = <1804000 4800000>;
 588                 };
 589
 590                 cpu4_opp7: opp-825600000 {
 591                         opp-hz = /bits/ 64 <825600000>;
 592                         opp-peak-kBps = <2188000 9216000>;
 593                 };
 594
 595                 cpu4_opp8: opp-902400000 {
 596                         opp-hz = /bits/ 64 <902400000>;
 597                         opp-peak-kBps = <2188000 9216000>;
 598                 };
 599
 600                 cpu4_opp9: opp-979200000 {
 601                         opp-hz = /bits/ 64 <979200000>;
 602                         opp-peak-kBps = <2188000 9216000>;
 603                 };
 604
 605                 cpu4_opp10: opp-1056000000 {
 606                         opp-hz = /bits/ 64 <1056000000>;
 607                         opp-peak-kBps = <3072000 9216000>;
 608                 };
 609
 610                 cpu4_opp11: opp-1132800000 {
 611                         opp-hz = /bits/ 64 <1132800000>;
 612                         opp-peak-kBps = <3072000 11980800>;
 613                 };
 614
 615                 cpu4_opp12: opp-1209600000 {
 616                         opp-hz = /bits/ 64 <1209600000>;
 617                         opp-peak-kBps = <4068000 11980800>;
 618                 };
 619
 620                 cpu4_opp13: opp-1286400000 {
 621                         opp-hz = /bits/ 64 <1286400000>;
 622                         opp-peak-kBps = <4068000 11980800>;
 623                 };
 624
 625                 cpu4_opp14: opp-1363200000 {
 626                         opp-hz = /bits/ 64 <1363200000>;
 627                         opp-peak-kBps = <4068000 15052800>;
 628                 };
 629
 630                 cpu4_opp15: opp-1459200000 {
 631                         opp-hz = /bits/ 64 <1459200000>;
 632                         opp-peak-kBps = <4068000 15052800>;
 633                 };
 634
 635                 cpu4_opp16: opp-1536000000 {
 636                         opp-hz = /bits/ 64 <1536000000>;
 637                         opp-peak-kBps = <5412000 15052800>;
 638                 };
 639
 640                 cpu4_opp17: opp-1612800000 {
 641                         opp-hz = /bits/ 64 <1612800000>;
 642                         opp-peak-kBps = <5412000 15052800>;
 643                 };
 644
 645                 cpu4_opp18: opp-1689600000 {
 646                         opp-hz = /bits/ 64 <1689600000>;
 647                         opp-peak-kBps = <5412000 19353600>;
 648                 };
 649
 650                 cpu4_opp19: opp-1766400000 {
 651                         opp-hz = /bits/ 64 <1766400000>;
 652                         opp-peak-kBps = <6220000 19353600>;
 653                 };
 654
 655                 cpu4_opp20: opp-1843200000 {
 656                         opp-hz = /bits/ 64 <1843200000>;
 657                         opp-peak-kBps = <6220000 19353600>;
 658                 };
 659
 660                 cpu4_opp21: opp-1920000000 {
 661                         opp-hz = /bits/ 64 <1920000000>;
 662                         opp-peak-kBps = <7216000 19353600>;
 663                 };
 664
 665                 cpu4_opp22: opp-1996800000 {
 666                         opp-hz = /bits/ 64 <1996800000>;
 667                         opp-peak-kBps = <7216000 20889600>;
 668                 };
 669
 670                 cpu4_opp23: opp-2092800000 {
 671                         opp-hz = /bits/ 64 <2092800000>;
 672                         opp-peak-kBps = <7216000 20889600>;
 673                 };
 674
 675                 cpu4_opp24: opp-2169600000 {
 676                         opp-hz = /bits/ 64 <2169600000>;
 677                         opp-peak-kBps = <7216000 20889600>;
 678                 };
 679
 680                 cpu4_opp25: opp-2246400000 {
 681                         opp-hz = /bits/ 64 <2246400000>;
 682                         opp-peak-kBps = <7216000 20889600>;
 683                 };
 684
 685                 cpu4_opp26: opp-2323200000 {
 686                         opp-hz = /bits/ 64 <2323200000>;
 687                         opp-peak-kBps = <7216000 20889600>;
 688                 };
 689
 690                 cpu4_opp27: opp-2400000000 {
 691                         opp-hz = /bits/ 64 <2400000000>;
 692                         opp-peak-kBps = <7216000 22425600>;
 693                 };
 694
 695                 cpu4_opp28: opp-2476800000 {
 696                         opp-hz = /bits/ 64 <2476800000>;
 697                         opp-peak-kBps = <7216000 22425600>;
 698                 };
 699
 700                 cpu4_opp29: opp-2553600000 {
 701                         opp-hz = /bits/ 64 <2553600000>;
 702                         opp-peak-kBps = <7216000 22425600>;
 703                 };
 704
 705                 cpu4_opp30: opp-2649600000 {
 706                         opp-hz = /bits/ 64 <2649600000>;
 707                         opp-peak-kBps = <7216000 22425600>;
 708                 };
 709
 710                 cpu4_opp31: opp-2745600000 {
 711                         opp-hz = /bits/ 64 <2745600000>;
 712                         opp-peak-kBps = <7216000 25497600>;
 713                 };
 714
 715                 cpu4_opp32: opp-2803200000 {
 716                         opp-hz = /bits/ 64 <2803200000>;
 717                         opp-peak-kBps = <7216000 25497600>;
 718                 };
 719         };
 720
 721         pmu {
 722                 compatible = "arm,armv8-pmuv3";
 723                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 724         };
 725
 726         timer {
 727                 compatible = "arm,armv8-timer";
 728                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 729                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 730                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 731                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 732         };
 733
 734         clocks {
 735                 xo_board: xo-board {
 736                         compatible = "fixed-clock";
 737                         #clock-cells = <0>;
 738                         clock-frequency = <38400000>;
 739                         clock-output-names = "xo_board";
 740                 };
 741
 742                 sleep_clk: sleep-clk {
 743                         compatible = "fixed-clock";
 744                         #clock-cells = <0>;
 745                         clock-frequency = <32764>;
 746                 };
 747         };
 748
 749         firmware {
 750                 scm {
 751                         compatible = "qcom,scm-sdm845", "qcom,scm";
 752                 };
 753         };
 754
 755         adsp_pas: remoteproc-adsp {
 756                 compatible = "qcom,sdm845-adsp-pas";
 757
 758                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 759                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 760                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 761                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 762                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 763                 interrupt-names = "wdog", "fatal", "ready",
 764                                   "handover", "stop-ack";
 765
 766                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 767                 clock-names = "xo";
 768
 769                 memory-region = <&adsp_mem>;
 770
 771                 qcom,smem-states = <&adsp_smp2p_out 0>;
 772                 qcom,smem-state-names = "stop";
 773
 774                 status = "disabled";
 775
 776                 glink-edge {
 777                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 778                         label = "lpass";
 779                         qcom,remote-pid = <2>;
 780                         mboxes = <&apss_shared 8>;
 781
 782                         apr {
 783                                 compatible = "qcom,apr-v2";
 784                                 qcom,glink-channels = "apr_audio_svc";
 785                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
 786                                 #address-cells = <1>;
 787                                 #size-cells = <0>;
 788                                 qcom,intents = <512 20>;
 789
 790                                 apr-service@3 {
 791                                         reg = <APR_SVC_ADSP_CORE>;
 792                                         compatible = "qcom,q6core";
 793                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 794                                 };
 795
 796                                 q6afe: apr-service@4 {
 797                                         compatible = "qcom,q6afe";
 798                                         reg = <APR_SVC_AFE>;
 799                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 800                                         q6afedai: dais {
 801                                                 compatible = "qcom,q6afe-dais";
 802                                                 #address-cells = <1>;
 803                                                 #size-cells = <0>;
 804                                                 #sound-dai-cells = <1>;
 805                                         };
 806                                 };
 807
 808                                 q6asm: apr-service@7 {
 809                                         compatible = "qcom,q6asm";
 810                                         reg = <APR_SVC_ASM>;
 811                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 812                                         q6asmdai: dais {
 813                                                 compatible = "qcom,q6asm-dais";
 814                                                 #address-cells = <1>;
 815                                                 #size-cells = <0>;
 816                                                 #sound-dai-cells = <1>;
 817                                                 iommus = <&apps_smmu 0x1821 0x0>;
 818                                         };
 819                                 };
 820
 821                                 q6adm: apr-service@8 {
 822                                         compatible = "qcom,q6adm";
 823                                         reg = <APR_SVC_ADM>;
 824                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 825                                         q6routing: routing {
 826                                                 compatible = "qcom,q6adm-routing";
 827                                                 #sound-dai-cells = <0>;
 828                                         };
 829                                 };
 830                         };
 831
 832                         fastrpc {
 833                                 compatible = "qcom,fastrpc";
 834                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 835                                 label = "adsp";
 836                                 #address-cells = <1>;
 837                                 #size-cells = <0>;
 838
 839                                 compute-cb@3 {
 840                                         compatible = "qcom,fastrpc-compute-cb";
 841                                         reg = <3>;
 842                                         iommus = <&apps_smmu 0x1823 0x0>;
 843                                 };
 844
 845                                 compute-cb@4 {
 846                                         compatible = "qcom,fastrpc-compute-cb";
 847                                         reg = <4>;
 848                                         iommus = <&apps_smmu 0x1824 0x0>;
 849                                 };
 850                         };
 851                 };
 852         };
 853
 854         cdsp_pas: remoteproc-cdsp {
 855                 compatible = "qcom,sdm845-cdsp-pas";
 856
 857                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 858                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 859                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 860                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 861                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 862                 interrupt-names = "wdog", "fatal", "ready",
 863                                   "handover", "stop-ack";
 864
 865                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 866                 clock-names = "xo";
 867
 868                 memory-region = <&cdsp_mem>;
 869
 870                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 871                 qcom,smem-state-names = "stop";
 872
 873                 status = "disabled";
 874
 875                 glink-edge {
 876                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 877                         label = "turing";
 878                         qcom,remote-pid = <5>;
 879                         mboxes = <&apss_shared 4>;
 880                         fastrpc {
 881                                 compatible = "qcom,fastrpc";
 882                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 883                                 label = "cdsp";
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886
 887                                 compute-cb@1 {
 888                                         compatible = "qcom,fastrpc-compute-cb";
 889                                         reg = <1>;
 890                                         iommus = <&apps_smmu 0x1401 0x30>;
 891                                 };
 892
 893                                 compute-cb@2 {
 894                                         compatible = "qcom,fastrpc-compute-cb";
 895                                         reg = <2>;
 896                                         iommus = <&apps_smmu 0x1402 0x30>;
 897                                 };
 898
 899                                 compute-cb@3 {
 900                                         compatible = "qcom,fastrpc-compute-cb";
 901                                         reg = <3>;
 902                                         iommus = <&apps_smmu 0x1403 0x30>;
 903                                 };
 904
 905                                 compute-cb@4 {
 906                                         compatible = "qcom,fastrpc-compute-cb";
 907                                         reg = <4>;
 908                                         iommus = <&apps_smmu 0x1404 0x30>;
 909                                 };
 910
 911                                 compute-cb@5 {
 912                                         compatible = "qcom,fastrpc-compute-cb";
 913                                         reg = <5>;
 914                                         iommus = <&apps_smmu 0x1405 0x30>;
 915                                 };
 916
 917                                 compute-cb@6 {
 918                                         compatible = "qcom,fastrpc-compute-cb";
 919                                         reg = <6>;
 920                                         iommus = <&apps_smmu 0x1406 0x30>;
 921                                 };
 922
 923                                 compute-cb@7 {
 924                                         compatible = "qcom,fastrpc-compute-cb";
 925                                         reg = <7>;
 926                                         iommus = <&apps_smmu 0x1407 0x30>;
 927                                 };
 928
 929                                 compute-cb@8 {
 930                                         compatible = "qcom,fastrpc-compute-cb";
 931                                         reg = <8>;
 932                                         iommus = <&apps_smmu 0x1408 0x30>;
 933                                 };
 934                         };
 935                 };
 936         };
 937
 938         tcsr_mutex: hwlock {
 939                 compatible = "qcom,tcsr-mutex";
 940                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 941                 #hwlock-cells = <1>;
 942         };
 943
 944         smem {
 945                 compatible = "qcom,smem";
 946                 memory-region = <&smem_mem>;
 947                 hwlocks = <&tcsr_mutex 3>;
 948         };
 949
 950         smp2p-cdsp {
 951                 compatible = "qcom,smp2p";
 952                 qcom,smem = <94>, <432>;
 953
 954                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 955
 956                 mboxes = <&apss_shared 6>;
 957
 958                 qcom,local-pid = <0>;
 959                 qcom,remote-pid = <5>;
 960
 961                 cdsp_smp2p_out: master-kernel {
 962                         qcom,entry-name = "master-kernel";
 963                         #qcom,smem-state-cells = <1>;
 964                 };
 965
 966                 cdsp_smp2p_in: slave-kernel {
 967                         qcom,entry-name = "slave-kernel";
 968
 969                         interrupt-controller;
 970                         #interrupt-cells = <2>;
 971                 };
 972         };
 973
 974         smp2p-lpass {
 975                 compatible = "qcom,smp2p";
 976                 qcom,smem = <443>, <429>;
 977
 978                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 979
 980                 mboxes = <&apss_shared 10>;
 981
 982                 qcom,local-pid = <0>;
 983                 qcom,remote-pid = <2>;
 984
 985                 adsp_smp2p_out: master-kernel {
 986                         qcom,entry-name = "master-kernel";
 987                         #qcom,smem-state-cells = <1>;
 988                 };
 989
 990                 adsp_smp2p_in: slave-kernel {
 991                         qcom,entry-name = "slave-kernel";
 992
 993                         interrupt-controller;
 994                         #interrupt-cells = <2>;
 995                 };
 996         };
 997
 998         smp2p-mpss {
 999                 compatible = "qcom,smp2p";
1000                 qcom,smem = <435>, <428>;
1001                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1002                 mboxes = <&apss_shared 14>;
1003                 qcom,local-pid = <0>;
1004                 qcom,remote-pid = <1>;
1005
1006                 modem_smp2p_out: master-kernel {
1007                         qcom,entry-name = "master-kernel";
1008                         #qcom,smem-state-cells = <1>;
1009                 };
1010
1011                 modem_smp2p_in: slave-kernel {
1012                         qcom,entry-name = "slave-kernel";
1013                         interrupt-controller;
1014                         #interrupt-cells = <2>;
1015                 };
1016
1017                 ipa_smp2p_out: ipa-ap-to-modem {
1018                         qcom,entry-name = "ipa";
1019                         #qcom,smem-state-cells = <1>;
1020                 };
1021
1022                 ipa_smp2p_in: ipa-modem-to-ap {
1023                         qcom,entry-name = "ipa";
1024                         interrupt-controller;
1025                         #interrupt-cells = <2>;
1026                 };
1027         };
1028
1029         smp2p-slpi {
1030                 compatible = "qcom,smp2p";
1031                 qcom,smem = <481>, <430>;
1032                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1033                 mboxes = <&apss_shared 26>;
1034                 qcom,local-pid = <0>;
1035                 qcom,remote-pid = <3>;
1036
1037                 slpi_smp2p_out: master-kernel {
1038                         qcom,entry-name = "master-kernel";
1039                         #qcom,smem-state-cells = <1>;
1040                 };
1041
1042                 slpi_smp2p_in: slave-kernel {
1043                         qcom,entry-name = "slave-kernel";
1044                         interrupt-controller;
1045                         #interrupt-cells = <2>;
1046                 };
1047         };
1048
1049         psci {
1050                 compatible = "arm,psci-1.0";
1051                 method = "smc";
1052         };
1053
1054         soc: soc@0 {
1055                 #address-cells = <2>;
1056                 #size-cells = <2>;
1057                 ranges = <0 0 0 0 0x10 0>;
1058                 dma-ranges = <0 0 0 0 0x10 0>;
1059                 compatible = "simple-bus";
1060
1061                 gcc: clock-controller@100000 {
1062                         compatible = "qcom,gcc-sdm845";
1063                         reg = <0 0x00100000 0 0x1f0000>;
1064                         #clock-cells = <1>;
1065                         #reset-cells = <1>;
1066                         #power-domain-cells = <1>;
1067                 };
1068
1069                 qfprom@784000 {
1070                         compatible = "qcom,qfprom";
1071                         reg = <0 0x00784000 0 0x8ff>;
1072                         #address-cells = <1>;
1073                         #size-cells = <1>;
1074
1075                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1076                                 reg = <0x1eb 0x1>;
1077                                 bits = <1 4>;
1078                         };
1079
1080                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1081                                 reg = <0x1eb 0x2>;
1082                                 bits = <6 4>;
1083                         };
1084                 };
1085
1086                 rng: rng@793000 {
1087                         compatible = "qcom,prng-ee";
1088                         reg = <0 0x00793000 0 0x1000>;
1089                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1090                         clock-names = "core";
1091                 };
1092
1093                 qup_opp_table: qup-opp-table {
1094                         compatible = "operating-points-v2";
1095
1096                         opp-50000000 {
1097                                 opp-hz = /bits/ 64 <50000000>;
1098                                 required-opps = <&rpmhpd_opp_min_svs>;
1099                         };
1100
1101                         opp-75000000 {
1102                                 opp-hz = /bits/ 64 <75000000>;
1103                                 required-opps = <&rpmhpd_opp_low_svs>;
1104                         };
1105
1106                         opp-100000000 {
1107                                 opp-hz = /bits/ 64 <100000000>;
1108                                 required-opps = <&rpmhpd_opp_svs>;
1109                         };
1110
1111                         opp-128000000 {
1112                                 opp-hz = /bits/ 64 <128000000>;
1113                                 required-opps = <&rpmhpd_opp_nom>;
1114                         };
1115                 };
1116
1117                 qupv3_id_0: geniqup@8c0000 {
1118                         compatible = "qcom,geni-se-qup";
1119                         reg = <0 0x008c0000 0 0x6000>;
1120                         clock-names = "m-ahb", "s-ahb";
1121                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1122                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1123                         iommus = <&apps_smmu 0x3 0x0>;
1124                         #address-cells = <2>;
1125                         #size-cells = <2>;
1126                         ranges;
1127                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1128                         interconnect-names = "qup-core";
1129                         status = "disabled";
1130
1131                         i2c0: i2c@880000 {
1132                                 compatible = "qcom,geni-i2c";
1133                                 reg = <0 0x00880000 0 0x4000>;
1134                                 clock-names = "se";
1135                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1136                                 pinctrl-names = "default";
1137                                 pinctrl-0 = <&qup_i2c0_default>;
1138                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 power-domains = <&rpmhpd SDM845_CX>;
1142                                 operating-points-v2 = <&qup_opp_table>;
1143                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1144                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1145                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1146                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1147                                 status = "disabled";
1148                         };
1149
1150                         spi0: spi@880000 {
1151                                 compatible = "qcom,geni-spi";
1152                                 reg = <0 0x00880000 0 0x4000>;
1153                                 clock-names = "se";
1154                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1155                                 pinctrl-names = "default";
1156                                 pinctrl-0 = <&qup_spi0_default>;
1157                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1158                                 #address-cells = <1>;
1159                                 #size-cells = <0>;
1160                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1161                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1162                                 interconnect-names = "qup-core", "qup-config";
1163                                 status = "disabled";
1164                         };
1165
1166                         uart0: serial@880000 {
1167                                 compatible = "qcom,geni-uart";
1168                                 reg = <0 0x00880000 0 0x4000>;
1169                                 clock-names = "se";
1170                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1171                                 pinctrl-names = "default";
1172                                 pinctrl-0 = <&qup_uart0_default>;
1173                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1174                                 power-domains = <&rpmhpd SDM845_CX>;
1175                                 operating-points-v2 = <&qup_opp_table>;
1176                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1177                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1178                                 interconnect-names = "qup-core", "qup-config";
1179                                 status = "disabled";
1180                         };
1181
1182                         i2c1: i2c@884000 {
1183                                 compatible = "qcom,geni-i2c";
1184                                 reg = <0 0x00884000 0 0x4000>;
1185                                 clock-names = "se";
1186                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1187                                 pinctrl-names = "default";
1188                                 pinctrl-0 = <&qup_i2c1_default>;
1189                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1190                                 #address-cells = <1>;
1191                                 #size-cells = <0>;
1192                                 power-domains = <&rpmhpd SDM845_CX>;
1193                                 operating-points-v2 = <&qup_opp_table>;
1194                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1195                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1196                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1197                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198                                 status = "disabled";
1199                         };
1200
1201                         spi1: spi@884000 {
1202                                 compatible = "qcom,geni-spi";
1203                                 reg = <0 0x00884000 0 0x4000>;
1204                                 clock-names = "se";
1205                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1206                                 pinctrl-names = "default";
1207                                 pinctrl-0 = <&qup_spi1_default>;
1208                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1209                                 #address-cells = <1>;
1210                                 #size-cells = <0>;
1211                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1212                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1213                                 interconnect-names = "qup-core", "qup-config";
1214                                 status = "disabled";
1215                         };
1216
1217                         uart1: serial@884000 {
1218                                 compatible = "qcom,geni-uart";
1219                                 reg = <0 0x00884000 0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1222                                 pinctrl-names = "default";
1223                                 pinctrl-0 = <&qup_uart1_default>;
1224                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225                                 power-domains = <&rpmhpd SDM845_CX>;
1226                                 operating-points-v2 = <&qup_opp_table>;
1227                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1228                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1229                                 interconnect-names = "qup-core", "qup-config";
1230                                 status = "disabled";
1231                         };
1232
1233                         i2c2: i2c@888000 {
1234                                 compatible = "qcom,geni-i2c";
1235                                 reg = <0 0x00888000 0 0x4000>;
1236                                 clock-names = "se";
1237                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1238                                 pinctrl-names = "default";
1239                                 pinctrl-0 = <&qup_i2c2_default>;
1240                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1241                                 #address-cells = <1>;
1242                                 #size-cells = <0>;
1243                                 power-domains = <&rpmhpd SDM845_CX>;
1244                                 operating-points-v2 = <&qup_opp_table>;
1245                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1246                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1247                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1248                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249                                 status = "disabled";
1250                         };
1251
1252                         spi2: spi@888000 {
1253                                 compatible = "qcom,geni-spi";
1254                                 reg = <0 0x00888000 0 0x4000>;
1255                                 clock-names = "se";
1256                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1257                                 pinctrl-names = "default";
1258                                 pinctrl-0 = <&qup_spi2_default>;
1259                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1260                                 #address-cells = <1>;
1261                                 #size-cells = <0>;
1262                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1263                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1264                                 interconnect-names = "qup-core", "qup-config";
1265                                 status = "disabled";
1266                         };
1267
1268                         uart2: serial@888000 {
1269                                 compatible = "qcom,geni-uart";
1270                                 reg = <0 0x00888000 0 0x4000>;
1271                                 clock-names = "se";
1272                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1273                                 pinctrl-names = "default";
1274                                 pinctrl-0 = <&qup_uart2_default>;
1275                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1276                                 power-domains = <&rpmhpd SDM845_CX>;
1277                                 operating-points-v2 = <&qup_opp_table>;
1278                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1279                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1280                                 interconnect-names = "qup-core", "qup-config";
1281                                 status = "disabled";
1282                         };
1283
1284                         i2c3: i2c@88c000 {
1285                                 compatible = "qcom,geni-i2c";
1286                                 reg = <0 0x0088c000 0 0x4000>;
1287                                 clock-names = "se";
1288                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1289                                 pinctrl-names = "default";
1290                                 pinctrl-0 = <&qup_i2c3_default>;
1291                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1292                                 #address-cells = <1>;
1293                                 #size-cells = <0>;
1294                                 power-domains = <&rpmhpd SDM845_CX>;
1295                                 operating-points-v2 = <&qup_opp_table>;
1296                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1297                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1298                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1299                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1300                                 status = "disabled";
1301                         };
1302
1303                         spi3: spi@88c000 {
1304                                 compatible = "qcom,geni-spi";
1305                                 reg = <0 0x0088c000 0 0x4000>;
1306                                 clock-names = "se";
1307                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1308                                 pinctrl-names = "default";
1309                                 pinctrl-0 = <&qup_spi3_default>;
1310                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1311                                 #address-cells = <1>;
1312                                 #size-cells = <0>;
1313                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1314                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1315                                 interconnect-names = "qup-core", "qup-config";
1316                                 status = "disabled";
1317                         };
1318
1319                         uart3: serial@88c000 {
1320                                 compatible = "qcom,geni-uart";
1321                                 reg = <0 0x0088c000 0 0x4000>;
1322                                 clock-names = "se";
1323                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1324                                 pinctrl-names = "default";
1325                                 pinctrl-0 = <&qup_uart3_default>;
1326                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1327                                 power-domains = <&rpmhpd SDM845_CX>;
1328                                 operating-points-v2 = <&qup_opp_table>;
1329                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1330                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1331                                 interconnect-names = "qup-core", "qup-config";
1332                                 status = "disabled";
1333                         };
1334
1335                         i2c4: i2c@890000 {
1336                                 compatible = "qcom,geni-i2c";
1337                                 reg = <0 0x00890000 0 0x4000>;
1338                                 clock-names = "se";
1339                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1340                                 pinctrl-names = "default";
1341                                 pinctrl-0 = <&qup_i2c4_default>;
1342                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1343                                 #address-cells = <1>;
1344                                 #size-cells = <0>;
1345                                 power-domains = <&rpmhpd SDM845_CX>;
1346                                 operating-points-v2 = <&qup_opp_table>;
1347                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1348                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1349                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1350                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1351                                 status = "disabled";
1352                         };
1353
1354                         spi4: spi@890000 {
1355                                 compatible = "qcom,geni-spi";
1356                                 reg = <0 0x00890000 0 0x4000>;
1357                                 clock-names = "se";
1358                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1359                                 pinctrl-names = "default";
1360                                 pinctrl-0 = <&qup_spi4_default>;
1361                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1362                                 #address-cells = <1>;
1363                                 #size-cells = <0>;
1364                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1365                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1366                                 interconnect-names = "qup-core", "qup-config";
1367                                 status = "disabled";
1368                         };
1369
1370                         uart4: serial@890000 {
1371                                 compatible = "qcom,geni-uart";
1372                                 reg = <0 0x00890000 0 0x4000>;
1373                                 clock-names = "se";
1374                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1375                                 pinctrl-names = "default";
1376                                 pinctrl-0 = <&qup_uart4_default>;
1377                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1378                                 power-domains = <&rpmhpd SDM845_CX>;
1379                                 operating-points-v2 = <&qup_opp_table>;
1380                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1381                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1382                                 interconnect-names = "qup-core", "qup-config";
1383                                 status = "disabled";
1384                         };
1385
1386                         i2c5: i2c@894000 {
1387                                 compatible = "qcom,geni-i2c";
1388                                 reg = <0 0x00894000 0 0x4000>;
1389                                 clock-names = "se";
1390                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1391                                 pinctrl-names = "default";
1392                                 pinctrl-0 = <&qup_i2c5_default>;
1393                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1394                                 #address-cells = <1>;
1395                                 #size-cells = <0>;
1396                                 power-domains = <&rpmhpd SDM845_CX>;
1397                                 operating-points-v2 = <&qup_opp_table>;
1398                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1399                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1400                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1401                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1402                                 status = "disabled";
1403                         };
1404
1405                         spi5: spi@894000 {
1406                                 compatible = "qcom,geni-spi";
1407                                 reg = <0 0x00894000 0 0x4000>;
1408                                 clock-names = "se";
1409                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1410                                 pinctrl-names = "default";
1411                                 pinctrl-0 = <&qup_spi5_default>;
1412                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1413                                 #address-cells = <1>;
1414                                 #size-cells = <0>;
1415                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1416                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1417                                 interconnect-names = "qup-core", "qup-config";
1418                                 status = "disabled";
1419                         };
1420
1421                         uart5: serial@894000 {
1422                                 compatible = "qcom,geni-uart";
1423                                 reg = <0 0x00894000 0 0x4000>;
1424                                 clock-names = "se";
1425                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1426                                 pinctrl-names = "default";
1427                                 pinctrl-0 = <&qup_uart5_default>;
1428                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1429                                 power-domains = <&rpmhpd SDM845_CX>;
1430                                 operating-points-v2 = <&qup_opp_table>;
1431                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1432                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1433                                 interconnect-names = "qup-core", "qup-config";
1434                                 status = "disabled";
1435                         };
1436
1437                         i2c6: i2c@898000 {
1438                                 compatible = "qcom,geni-i2c";
1439                                 reg = <0 0x00898000 0 0x4000>;
1440                                 clock-names = "se";
1441                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1442                                 pinctrl-names = "default";
1443                                 pinctrl-0 = <&qup_i2c6_default>;
1444                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1445                                 #address-cells = <1>;
1446                                 #size-cells = <0>;
1447                                 power-domains = <&rpmhpd SDM845_CX>;
1448                                 operating-points-v2 = <&qup_opp_table>;
1449                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1450                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1451                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1452                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1453                                 status = "disabled";
1454                         };
1455
1456                         spi6: spi@898000 {
1457                                 compatible = "qcom,geni-spi";
1458                                 reg = <0 0x00898000 0 0x4000>;
1459                                 clock-names = "se";
1460                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1461                                 pinctrl-names = "default";
1462                                 pinctrl-0 = <&qup_spi6_default>;
1463                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1464                                 #address-cells = <1>;
1465                                 #size-cells = <0>;
1466                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1467                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1468                                 interconnect-names = "qup-core", "qup-config";
1469                                 status = "disabled";
1470                         };
1471
1472                         uart6: serial@898000 {
1473                                 compatible = "qcom,geni-uart";
1474                                 reg = <0 0x00898000 0 0x4000>;
1475                                 clock-names = "se";
1476                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_uart6_default>;
1479                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1480                                 power-domains = <&rpmhpd SDM845_CX>;
1481                                 operating-points-v2 = <&qup_opp_table>;
1482                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1483                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1484                                 interconnect-names = "qup-core", "qup-config";
1485                                 status = "disabled";
1486                         };
1487
1488                         i2c7: i2c@89c000 {
1489                                 compatible = "qcom,geni-i2c";
1490                                 reg = <0 0x0089c000 0 0x4000>;
1491                                 clock-names = "se";
1492                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1493                                 pinctrl-names = "default";
1494                                 pinctrl-0 = <&qup_i2c7_default>;
1495                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1496                                 #address-cells = <1>;
1497                                 #size-cells = <0>;
1498                                 power-domains = <&rpmhpd SDM845_CX>;
1499                                 operating-points-v2 = <&qup_opp_table>;
1500                                 status = "disabled";
1501                         };
1502
1503                         spi7: spi@89c000 {
1504                                 compatible = "qcom,geni-spi";
1505                                 reg = <0 0x0089c000 0 0x4000>;
1506                                 clock-names = "se";
1507                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1508                                 pinctrl-names = "default";
1509                                 pinctrl-0 = <&qup_spi7_default>;
1510                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1511                                 #address-cells = <1>;
1512                                 #size-cells = <0>;
1513                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1514                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1515                                 interconnect-names = "qup-core", "qup-config";
1516                                 status = "disabled";
1517                         };
1518
1519                         uart7: serial@89c000 {
1520                                 compatible = "qcom,geni-uart";
1521                                 reg = <0 0x0089c000 0 0x4000>;
1522                                 clock-names = "se";
1523                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1524                                 pinctrl-names = "default";
1525                                 pinctrl-0 = <&qup_uart7_default>;
1526                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1527                                 power-domains = <&rpmhpd SDM845_CX>;
1528                                 operating-points-v2 = <&qup_opp_table>;
1529                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1530                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1531                                 interconnect-names = "qup-core", "qup-config";
1532                                 status = "disabled";
1533                         };
1534                 };
1535
1536                 qupv3_id_1: geniqup@ac0000 {
1537                         compatible = "qcom,geni-se-qup";
1538                         reg = <0 0x00ac0000 0 0x6000>;
1539                         clock-names = "m-ahb", "s-ahb";
1540                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1541                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1542                         iommus = <&apps_smmu 0x6c3 0x0>;
1543                         #address-cells = <2>;
1544                         #size-cells = <2>;
1545                         ranges;
1546                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1547                         interconnect-names = "qup-core";
1548                         status = "disabled";
1549
1550                         i2c8: i2c@a80000 {
1551                                 compatible = "qcom,geni-i2c";
1552                                 reg = <0 0x00a80000 0 0x4000>;
1553                                 clock-names = "se";
1554                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1555                                 pinctrl-names = "default";
1556                                 pinctrl-0 = <&qup_i2c8_default>;
1557                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1558                                 #address-cells = <1>;
1559                                 #size-cells = <0>;
1560                                 power-domains = <&rpmhpd SDM845_CX>;
1561                                 operating-points-v2 = <&qup_opp_table>;
1562                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1563                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1564                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1565                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1566                                 status = "disabled";
1567                         };
1568
1569                         spi8: spi@a80000 {
1570                                 compatible = "qcom,geni-spi";
1571                                 reg = <0 0x00a80000 0 0x4000>;
1572                                 clock-names = "se";
1573                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1574                                 pinctrl-names = "default";
1575                                 pinctrl-0 = <&qup_spi8_default>;
1576                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1577                                 #address-cells = <1>;
1578                                 #size-cells = <0>;
1579                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1580                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1581                                 interconnect-names = "qup-core", "qup-config";
1582                                 status = "disabled";
1583                         };
1584
1585                         uart8: serial@a80000 {
1586                                 compatible = "qcom,geni-uart";
1587                                 reg = <0 0x00a80000 0 0x4000>;
1588                                 clock-names = "se";
1589                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1590                                 pinctrl-names = "default";
1591                                 pinctrl-0 = <&qup_uart8_default>;
1592                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1593                                 power-domains = <&rpmhpd SDM845_CX>;
1594                                 operating-points-v2 = <&qup_opp_table>;
1595                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1596                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1597                                 interconnect-names = "qup-core", "qup-config";
1598                                 status = "disabled";
1599                         };
1600
1601                         i2c9: i2c@a84000 {
1602                                 compatible = "qcom,geni-i2c";
1603                                 reg = <0 0x00a84000 0 0x4000>;
1604                                 clock-names = "se";
1605                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1606                                 pinctrl-names = "default";
1607                                 pinctrl-0 = <&qup_i2c9_default>;
1608                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1609                                 #address-cells = <1>;
1610                                 #size-cells = <0>;
1611                                 power-domains = <&rpmhpd SDM845_CX>;
1612                                 operating-points-v2 = <&qup_opp_table>;
1613                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1614                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1615                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1616                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1617                                 status = "disabled";
1618                         };
1619
1620                         spi9: spi@a84000 {
1621                                 compatible = "qcom,geni-spi";
1622                                 reg = <0 0x00a84000 0 0x4000>;
1623                                 clock-names = "se";
1624                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1625                                 pinctrl-names = "default";
1626                                 pinctrl-0 = <&qup_spi9_default>;
1627                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1631                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1632                                 interconnect-names = "qup-core", "qup-config";
1633                                 status = "disabled";
1634                         };
1635
1636                         uart9: serial@a84000 {
1637                                 compatible = "qcom,geni-debug-uart";
1638                                 reg = <0 0x00a84000 0 0x4000>;
1639                                 clock-names = "se";
1640                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1641                                 pinctrl-names = "default";
1642                                 pinctrl-0 = <&qup_uart9_default>;
1643                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1644                                 power-domains = <&rpmhpd SDM845_CX>;
1645                                 operating-points-v2 = <&qup_opp_table>;
1646                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1647                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1648                                 interconnect-names = "qup-core", "qup-config";
1649                                 status = "disabled";
1650                         };
1651
1652                         i2c10: i2c@a88000 {
1653                                 compatible = "qcom,geni-i2c";
1654                                 reg = <0 0x00a88000 0 0x4000>;
1655                                 clock-names = "se";
1656                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1657                                 pinctrl-names = "default";
1658                                 pinctrl-0 = <&qup_i2c10_default>;
1659                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1660                                 #address-cells = <1>;
1661                                 #size-cells = <0>;
1662                                 power-domains = <&rpmhpd SDM845_CX>;
1663                                 operating-points-v2 = <&qup_opp_table>;
1664                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1665                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1666                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1667                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1668                                 status = "disabled";
1669                         };
1670
1671                         spi10: spi@a88000 {
1672                                 compatible = "qcom,geni-spi";
1673                                 reg = <0 0x00a88000 0 0x4000>;
1674                                 clock-names = "se";
1675                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1676                                 pinctrl-names = "default";
1677                                 pinctrl-0 = <&qup_spi10_default>;
1678                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1679                                 #address-cells = <1>;
1680                                 #size-cells = <0>;
1681                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1682                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1683                                 interconnect-names = "qup-core", "qup-config";
1684                                 status = "disabled";
1685                         };
1686
1687                         uart10: serial@a88000 {
1688                                 compatible = "qcom,geni-uart";
1689                                 reg = <0 0x00a88000 0 0x4000>;
1690                                 clock-names = "se";
1691                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1692                                 pinctrl-names = "default";
1693                                 pinctrl-0 = <&qup_uart10_default>;
1694                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1695                                 power-domains = <&rpmhpd SDM845_CX>;
1696                                 operating-points-v2 = <&qup_opp_table>;
1697                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1698                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1699                                 interconnect-names = "qup-core", "qup-config";
1700                                 status = "disabled";
1701                         };
1702
1703                         i2c11: i2c@a8c000 {
1704                                 compatible = "qcom,geni-i2c";
1705                                 reg = <0 0x00a8c000 0 0x4000>;
1706                                 clock-names = "se";
1707                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1708                                 pinctrl-names = "default";
1709                                 pinctrl-0 = <&qup_i2c11_default>;
1710                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1711                                 #address-cells = <1>;
1712                                 #size-cells = <0>;
1713                                 power-domains = <&rpmhpd SDM845_CX>;
1714                                 operating-points-v2 = <&qup_opp_table>;
1715                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1716                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1717                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1718                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1719                                 status = "disabled";
1720                         };
1721
1722                         spi11: spi@a8c000 {
1723                                 compatible = "qcom,geni-spi";
1724                                 reg = <0 0x00a8c000 0 0x4000>;
1725                                 clock-names = "se";
1726                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1727                                 pinctrl-names = "default";
1728                                 pinctrl-0 = <&qup_spi11_default>;
1729                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1730                                 #address-cells = <1>;
1731                                 #size-cells = <0>;
1732                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1733                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1734                                 interconnect-names = "qup-core", "qup-config";
1735                                 status = "disabled";
1736                         };
1737
1738                         uart11: serial@a8c000 {
1739                                 compatible = "qcom,geni-uart";
1740                                 reg = <0 0x00a8c000 0 0x4000>;
1741                                 clock-names = "se";
1742                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1743                                 pinctrl-names = "default";
1744                                 pinctrl-0 = <&qup_uart11_default>;
1745                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1746                                 power-domains = <&rpmhpd SDM845_CX>;
1747                                 operating-points-v2 = <&qup_opp_table>;
1748                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1749                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1750                                 interconnect-names = "qup-core", "qup-config";
1751                                 status = "disabled";
1752                         };
1753
1754                         i2c12: i2c@a90000 {
1755                                 compatible = "qcom,geni-i2c";
1756                                 reg = <0 0x00a90000 0 0x4000>;
1757                                 clock-names = "se";
1758                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1759                                 pinctrl-names = "default";
1760                                 pinctrl-0 = <&qup_i2c12_default>;
1761                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1762                                 #address-cells = <1>;
1763                                 #size-cells = <0>;
1764                                 power-domains = <&rpmhpd SDM845_CX>;
1765                                 operating-points-v2 = <&qup_opp_table>;
1766                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1767                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1768                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1769                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1770                                 status = "disabled";
1771                         };
1772
1773                         spi12: spi@a90000 {
1774                                 compatible = "qcom,geni-spi";
1775                                 reg = <0 0x00a90000 0 0x4000>;
1776                                 clock-names = "se";
1777                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1778                                 pinctrl-names = "default";
1779                                 pinctrl-0 = <&qup_spi12_default>;
1780                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1781                                 #address-cells = <1>;
1782                                 #size-cells = <0>;
1783                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1784                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1785                                 interconnect-names = "qup-core", "qup-config";
1786                                 status = "disabled";
1787                         };
1788
1789                         uart12: serial@a90000 {
1790                                 compatible = "qcom,geni-uart";
1791                                 reg = <0 0x00a90000 0 0x4000>;
1792                                 clock-names = "se";
1793                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1794                                 pinctrl-names = "default";
1795                                 pinctrl-0 = <&qup_uart12_default>;
1796                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1797                                 power-domains = <&rpmhpd SDM845_CX>;
1798                                 operating-points-v2 = <&qup_opp_table>;
1799                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1800                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1801                                 interconnect-names = "qup-core", "qup-config";
1802                                 status = "disabled";
1803                         };
1804
1805                         i2c13: i2c@a94000 {
1806                                 compatible = "qcom,geni-i2c";
1807                                 reg = <0 0x00a94000 0 0x4000>;
1808                                 clock-names = "se";
1809                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1810                                 pinctrl-names = "default";
1811                                 pinctrl-0 = <&qup_i2c13_default>;
1812                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1813                                 #address-cells = <1>;
1814                                 #size-cells = <0>;
1815                                 power-domains = <&rpmhpd SDM845_CX>;
1816                                 operating-points-v2 = <&qup_opp_table>;
1817                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1818                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1819                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1820                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1821                                 status = "disabled";
1822                         };
1823
1824                         spi13: spi@a94000 {
1825                                 compatible = "qcom,geni-spi";
1826                                 reg = <0 0x00a94000 0 0x4000>;
1827                                 clock-names = "se";
1828                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1829                                 pinctrl-names = "default";
1830                                 pinctrl-0 = <&qup_spi13_default>;
1831                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1832                                 #address-cells = <1>;
1833                                 #size-cells = <0>;
1834                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1835                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1836                                 interconnect-names = "qup-core", "qup-config";
1837                                 status = "disabled";
1838                         };
1839
1840                         uart13: serial@a94000 {
1841                                 compatible = "qcom,geni-uart";
1842                                 reg = <0 0x00a94000 0 0x4000>;
1843                                 clock-names = "se";
1844                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1845                                 pinctrl-names = "default";
1846                                 pinctrl-0 = <&qup_uart13_default>;
1847                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1848                                 power-domains = <&rpmhpd SDM845_CX>;
1849                                 operating-points-v2 = <&qup_opp_table>;
1850                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1851                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1852                                 interconnect-names = "qup-core", "qup-config";
1853                                 status = "disabled";
1854                         };
1855
1856                         i2c14: i2c@a98000 {
1857                                 compatible = "qcom,geni-i2c";
1858                                 reg = <0 0x00a98000 0 0x4000>;
1859                                 clock-names = "se";
1860                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1861                                 pinctrl-names = "default";
1862                                 pinctrl-0 = <&qup_i2c14_default>;
1863                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1864                                 #address-cells = <1>;
1865                                 #size-cells = <0>;
1866                                 power-domains = <&rpmhpd SDM845_CX>;
1867                                 operating-points-v2 = <&qup_opp_table>;
1868                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1869                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1870                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1871                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1872                                 status = "disabled";
1873                         };
1874
1875                         spi14: spi@a98000 {
1876                                 compatible = "qcom,geni-spi";
1877                                 reg = <0 0x00a98000 0 0x4000>;
1878                                 clock-names = "se";
1879                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1880                                 pinctrl-names = "default";
1881                                 pinctrl-0 = <&qup_spi14_default>;
1882                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1883                                 #address-cells = <1>;
1884                                 #size-cells = <0>;
1885                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1886                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1887                                 interconnect-names = "qup-core", "qup-config";
1888                                 status = "disabled";
1889                         };
1890
1891                         uart14: serial@a98000 {
1892                                 compatible = "qcom,geni-uart";
1893                                 reg = <0 0x00a98000 0 0x4000>;
1894                                 clock-names = "se";
1895                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1896                                 pinctrl-names = "default";
1897                                 pinctrl-0 = <&qup_uart14_default>;
1898                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1899                                 power-domains = <&rpmhpd SDM845_CX>;
1900                                 operating-points-v2 = <&qup_opp_table>;
1901                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1902                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1903                                 interconnect-names = "qup-core", "qup-config";
1904                                 status = "disabled";
1905                         };
1906
1907                         i2c15: i2c@a9c000 {
1908                                 compatible = "qcom,geni-i2c";
1909                                 reg = <0 0x00a9c000 0 0x4000>;
1910                                 clock-names = "se";
1911                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912                                 pinctrl-names = "default";
1913                                 pinctrl-0 = <&qup_i2c15_default>;
1914                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1915                                 #address-cells = <1>;
1916                                 #size-cells = <0>;
1917                                 power-domains = <&rpmhpd SDM845_CX>;
1918                                 operating-points-v2 = <&qup_opp_table>;
1919                                 status = "disabled";
1920                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1921                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1922                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1923                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1924                         };
1925
1926                         spi15: spi@a9c000 {
1927                                 compatible = "qcom,geni-spi";
1928                                 reg = <0 0x00a9c000 0 0x4000>;
1929                                 clock-names = "se";
1930                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1931                                 pinctrl-names = "default";
1932                                 pinctrl-0 = <&qup_spi15_default>;
1933                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1934                                 #address-cells = <1>;
1935                                 #size-cells = <0>;
1936                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1937                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1938                                 interconnect-names = "qup-core", "qup-config";
1939                                 status = "disabled";
1940                         };
1941
1942                         uart15: serial@a9c000 {
1943                                 compatible = "qcom,geni-uart";
1944                                 reg = <0 0x00a9c000 0 0x4000>;
1945                                 clock-names = "se";
1946                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1947                                 pinctrl-names = "default";
1948                                 pinctrl-0 = <&qup_uart15_default>;
1949                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1950                                 power-domains = <&rpmhpd SDM845_CX>;
1951                                 operating-points-v2 = <&qup_opp_table>;
1952                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1953                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1954                                 interconnect-names = "qup-core", "qup-config";
1955                                 status = "disabled";
1956                         };
1957                 };
1958
1959                 system-cache-controller@1100000 {
1960                         compatible = "qcom,sdm845-llcc";
1961                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1962                         reg-names = "llcc_base", "llcc_broadcast_base";
1963                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1964                 };
1965
1966                 pcie0: pci@1c00000 {
1967                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1968                         reg = <0 0x01c00000 0 0x2000>,
1969                               <0 0x60000000 0 0xf1d>,
1970                               <0 0x60000f20 0 0xa8>,
1971                               <0 0x60100000 0 0x100000>;
1972                         reg-names = "parf", "dbi", "elbi", "config";
1973                         device_type = "pci";
1974                         linux,pci-domain = <0>;
1975                         bus-range = <0x00 0xff>;
1976                         num-lanes = <1>;
1977
1978                         #address-cells = <3>;
1979                         #size-cells = <2>;
1980
1981                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1982                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1983
1984                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1985                         interrupt-names = "msi";
1986                         #interrupt-cells = <1>;
1987                         interrupt-map-mask = <0 0 0 0x7>;
1988                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1989                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1990                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1991                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1992
1993                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1994                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1995                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1996                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1997                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1998                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1999                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2000                         clock-names = "pipe",
2001                                       "aux",
2002                                       "cfg",
2003                                       "bus_master",
2004                                       "bus_slave",
2005                                       "slave_q2a",
2006                                       "tbu";
2007
2008                         iommus = <&apps_smmu 0x1c10 0xf>;
2009                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
2010                                     <0x100 &apps_smmu 0x1c11 0x1>,
2011                                     <0x200 &apps_smmu 0x1c12 0x1>,
2012                                     <0x300 &apps_smmu 0x1c13 0x1>,
2013                                     <0x400 &apps_smmu 0x1c14 0x1>,
2014                                     <0x500 &apps_smmu 0x1c15 0x1>,
2015                                     <0x600 &apps_smmu 0x1c16 0x1>,
2016                                     <0x700 &apps_smmu 0x1c17 0x1>,
2017                                     <0x800 &apps_smmu 0x1c18 0x1>,
2018                                     <0x900 &apps_smmu 0x1c19 0x1>,
2019                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
2020                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
2021                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
2022                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
2023                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
2024                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
2025
2026                         resets = <&gcc GCC_PCIE_0_BCR>;
2027                         reset-names = "pci";
2028
2029                         power-domains = <&gcc PCIE_0_GDSC>;
2030
2031                         phys = <&pcie0_lane>;
2032                         phy-names = "pciephy";
2033
2034                         status = "disabled";
2035                 };
2036
2037                 pcie0_phy: phy@1c06000 {
2038                         compatible = "qcom,sdm845-qmp-pcie-phy";
2039                         reg = <0 0x01c06000 0 0x18c>;
2040                         #address-cells = <2>;
2041                         #size-cells = <2>;
2042                         ranges;
2043                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2044                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2045                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
2046                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2047                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2048
2049                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2050                         reset-names = "phy";
2051
2052                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2053                         assigned-clock-rates = <100000000>;
2054
2055                         status = "disabled";
2056
2057                         pcie0_lane: lanes@1c06200 {
2058                                 reg = <0 0x01c06200 0 0x128>,
2059                                       <0 0x01c06400 0 0x1fc>,
2060                                       <0 0x01c06800 0 0x218>,
2061                                       <0 0x01c06600 0 0x70>;
2062                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2063                                 clock-names = "pipe0";
2064
2065                                 #phy-cells = <0>;
2066                                 clock-output-names = "pcie_0_pipe_clk";
2067                         };
2068                 };
2069
2070                 pcie1: pci@1c08000 {
2071                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2072                         reg = <0 0x01c08000 0 0x2000>,
2073                               <0 0x40000000 0 0xf1d>,
2074                               <0 0x40000f20 0 0xa8>,
2075                               <0 0x40100000 0 0x100000>;
2076                         reg-names = "parf", "dbi", "elbi", "config";
2077                         device_type = "pci";
2078                         linux,pci-domain = <1>;
2079                         bus-range = <0x00 0xff>;
2080                         num-lanes = <1>;
2081
2082                         #address-cells = <3>;
2083                         #size-cells = <2>;
2084
2085                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2086                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2087
2088                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2089                         interrupt-names = "msi";
2090                         #interrupt-cells = <1>;
2091                         interrupt-map-mask = <0 0 0 0x7>;
2092                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2093                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2094                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2095                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2096
2097                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2098                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2099                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2100                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2101                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2102                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2103                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2104                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2105                         clock-names = "pipe",
2106                                       "aux",
2107                                       "cfg",
2108                                       "bus_master",
2109                                       "bus_slave",
2110                                       "slave_q2a",
2111                                       "ref",
2112                                       "tbu";
2113
2114                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2115                         assigned-clock-rates = <19200000>;
2116
2117                         iommus = <&apps_smmu 0x1c00 0xf>;
2118                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2119                                     <0x100 &apps_smmu 0x1c01 0x1>,
2120                                     <0x200 &apps_smmu 0x1c02 0x1>,
2121                                     <0x300 &apps_smmu 0x1c03 0x1>,
2122                                     <0x400 &apps_smmu 0x1c04 0x1>,
2123                                     <0x500 &apps_smmu 0x1c05 0x1>,
2124                                     <0x600 &apps_smmu 0x1c06 0x1>,
2125                                     <0x700 &apps_smmu 0x1c07 0x1>,
2126                                     <0x800 &apps_smmu 0x1c08 0x1>,
2127                                     <0x900 &apps_smmu 0x1c09 0x1>,
2128                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
2129                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
2130                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
2131                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
2132                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
2133                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
2134
2135                         resets = <&gcc GCC_PCIE_1_BCR>;
2136                         reset-names = "pci";
2137
2138                         power-domains = <&gcc PCIE_1_GDSC>;
2139
2140                         phys = <&pcie1_lane>;
2141                         phy-names = "pciephy";
2142
2143                         status = "disabled";
2144                 };
2145
2146                 pcie1_phy: phy@1c0a000 {
2147                         compatible = "qcom,sdm845-qhp-pcie-phy";
2148                         reg = <0 0x01c0a000 0 0x800>;
2149                         #address-cells = <2>;
2150                         #size-cells = <2>;
2151                         ranges;
2152                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2153                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2154                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2155                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2156                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2157
2158                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2159                         reset-names = "phy";
2160
2161                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2162                         assigned-clock-rates = <100000000>;
2163
2164                         status = "disabled";
2165
2166                         pcie1_lane: lanes@1c06200 {
2167                                 reg = <0 0x01c0a800 0 0x800>,
2168                                       <0 0x01c0a800 0 0x800>,
2169                                       <0 0x01c0b800 0 0x400>;
2170                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2171                                 clock-names = "pipe0";
2172
2173                                 #phy-cells = <0>;
2174                                 clock-output-names = "pcie_1_pipe_clk";
2175                         };
2176                 };
2177
2178                 mem_noc: interconnect@1380000 {
2179                         compatible = "qcom,sdm845-mem-noc";
2180                         reg = <0 0x01380000 0 0x27200>;
2181                         #interconnect-cells = <2>;
2182                         qcom,bcm-voters = <&apps_bcm_voter>;
2183                 };
2184
2185                 dc_noc: interconnect@14e0000 {
2186                         compatible = "qcom,sdm845-dc-noc";
2187                         reg = <0 0x014e0000 0 0x400>;
2188                         #interconnect-cells = <2>;
2189                         qcom,bcm-voters = <&apps_bcm_voter>;
2190                 };
2191
2192                 config_noc: interconnect@1500000 {
2193                         compatible = "qcom,sdm845-config-noc";
2194                         reg = <0 0x01500000 0 0x5080>;
2195                         #interconnect-cells = <2>;
2196                         qcom,bcm-voters = <&apps_bcm_voter>;
2197                 };
2198
2199                 system_noc: interconnect@1620000 {
2200                         compatible = "qcom,sdm845-system-noc";
2201                         reg = <0 0x01620000 0 0x18080>;
2202                         #interconnect-cells = <2>;
2203                         qcom,bcm-voters = <&apps_bcm_voter>;
2204                 };
2205
2206                 aggre1_noc: interconnect@16e0000 {
2207                         compatible = "qcom,sdm845-aggre1-noc";
2208                         reg = <0 0x016e0000 0 0x15080>;
2209                         #interconnect-cells = <2>;
2210                         qcom,bcm-voters = <&apps_bcm_voter>;
2211                 };
2212
2213                 aggre2_noc: interconnect@1700000 {
2214                         compatible = "qcom,sdm845-aggre2-noc";
2215                         reg = <0 0x01700000 0 0x1f300>;
2216                         #interconnect-cells = <2>;
2217                         qcom,bcm-voters = <&apps_bcm_voter>;
2218                 };
2219
2220                 mmss_noc: interconnect@1740000 {
2221                         compatible = "qcom,sdm845-mmss-noc";
2222                         reg = <0 0x01740000 0 0x1c100>;
2223                         #interconnect-cells = <2>;
2224                         qcom,bcm-voters = <&apps_bcm_voter>;
2225                 };
2226
2227                 ufs_mem_hc: ufshc@1d84000 {
2228                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2229                                      "jedec,ufs-2.0";
2230                         reg = <0 0x01d84000 0 0x2500>,
2231                               <0 0x01d90000 0 0x8000>;
2232                         reg-names = "std", "ice";
2233                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2234                         phys = <&ufs_mem_phy_lanes>;
2235                         phy-names = "ufsphy";
2236                         lanes-per-direction = <2>;
2237                         power-domains = <&gcc UFS_PHY_GDSC>;
2238                         #reset-cells = <1>;
2239                         resets = <&gcc GCC_UFS_PHY_BCR>;
2240                         reset-names = "rst";
2241
2242                         iommus = <&apps_smmu 0x100 0xf>;
2243
2244                         clock-names =
2245                                 "core_clk",
2246                                 "bus_aggr_clk",
2247                                 "iface_clk",
2248                                 "core_clk_unipro",
2249                                 "ref_clk",
2250                                 "tx_lane0_sync_clk",
2251                                 "rx_lane0_sync_clk",
2252                                 "rx_lane1_sync_clk",
2253                                 "ice_core_clk";
2254                         clocks =
2255                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2256                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2257                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2258                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2259                                 <&rpmhcc RPMH_CXO_CLK>,
2260                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2261                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2262                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2263                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2264                         freq-table-hz =
2265                                 <50000000 200000000>,
2266                                 <0 0>,
2267                                 <0 0>,
2268                                 <37500000 150000000>,
2269                                 <0 0>,
2270                                 <0 0>,
2271                                 <0 0>,
2272                                 <0 0>,
2273                                 <0 300000000>;
2274
2275                         status = "disabled";
2276                 };
2277
2278                 ufs_mem_phy: phy@1d87000 {
2279                         compatible = "qcom,sdm845-qmp-ufs-phy";
2280                         reg = <0 0x01d87000 0 0x18c>;
2281                         #address-cells = <2>;
2282                         #size-cells = <2>;
2283                         ranges;
2284                         clock-names = "ref",
2285                                       "ref_aux";
2286                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2287                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2288
2289                         resets = <&ufs_mem_hc 0>;
2290                         reset-names = "ufsphy";
2291                         status = "disabled";
2292
2293                         ufs_mem_phy_lanes: lanes@1d87400 {
2294                                 reg = <0 0x01d87400 0 0x108>,
2295                                       <0 0x01d87600 0 0x1e0>,
2296                                       <0 0x01d87c00 0 0x1dc>,
2297                                       <0 0x01d87800 0 0x108>,
2298                                       <0 0x01d87a00 0 0x1e0>;
2299                                 #phy-cells = <0>;
2300                         };
2301                 };
2302
2303                 cryptobam: dma@1dc4000 {
2304                         compatible = "qcom,bam-v1.7.0";
2305                         reg = <0 0x01dc4000 0 0x24000>;
2306                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2307                         clocks = <&rpmhcc 15>;
2308                         clock-names = "bam_clk";
2309                         #dma-cells = <1>;
2310                         qcom,ee = <0>;
2311                         qcom,controlled-remotely = <1>;
2312                         iommus = <&apps_smmu 0x704 0x1>,
2313                                  <&apps_smmu 0x706 0x1>,
2314                                  <&apps_smmu 0x714 0x1>,
2315                                  <&apps_smmu 0x716 0x1>;
2316                 };
2317
2318                 crypto: crypto@1dfa000 {
2319                         compatible = "qcom,crypto-v5.4";
2320                         reg = <0 0x01dfa000 0 0x6000>;
2321                         clocks = <&gcc GCC_CE1_AHB_CLK>,
2322                                  <&gcc GCC_CE1_AHB_CLK>,
2323                                  <&rpmhcc 15>;
2324                         clock-names = "iface", "bus", "core";
2325                         dmas = <&cryptobam 6>, <&cryptobam 7>;
2326                         dma-names = "rx", "tx";
2327                         iommus = <&apps_smmu 0x704 0x1>,
2328                                  <&apps_smmu 0x706 0x1>,
2329                                  <&apps_smmu 0x714 0x1>,
2330                                  <&apps_smmu 0x716 0x1>;
2331                 };
2332
2333                 ipa: ipa@1e40000 {
2334                         compatible = "qcom,sdm845-ipa";
2335
2336                         iommus = <&apps_smmu 0x720 0x0>,
2337                                  <&apps_smmu 0x722 0x0>;
2338                         reg = <0 0x1e40000 0 0x7000>,
2339                               <0 0x1e47000 0 0x2000>,
2340                               <0 0x1e04000 0 0x2c000>;
2341                         reg-names = "ipa-reg",
2342                                     "ipa-shared",
2343                                     "gsi";
2344
2345                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2346                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2347                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2348                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2349                         interrupt-names = "ipa",
2350                                           "gsi",
2351                                           "ipa-clock-query",
2352                                           "ipa-setup-ready";
2353
2354                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2355                         clock-names = "core";
2356
2357                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2358                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2359                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2360                         interconnect-names = "memory",
2361                                              "imem",
2362                                              "config";
2363
2364                         qcom,smem-states = <&ipa_smp2p_out 0>,
2365                                            <&ipa_smp2p_out 1>;
2366                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2367                                                 "ipa-clock-enabled";
2368
2369                         modem-remoteproc = <&mss_pil>;
2370
2371                         status = "disabled";
2372                 };
2373
2374                 tcsr_mutex_regs: syscon@1f40000 {
2375                         compatible = "syscon";
2376                         reg = <0 0x01f40000 0 0x40000>;
2377                 };
2378
2379                 tlmm: pinctrl@3400000 {
2380                         compatible = "qcom,sdm845-pinctrl";
2381                         reg = <0 0x03400000 0 0xc00000>;
2382                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2383                         gpio-controller;
2384                         #gpio-cells = <2>;
2385                         interrupt-controller;
2386                         #interrupt-cells = <2>;
2387                         gpio-ranges = <&tlmm 0 0 150>;
2388                         wakeup-parent = <&pdc_intc>;
2389
2390                         cci0_default: cci0-default {
2391                                 /* SDA, SCL */
2392                                 pins = "gpio17", "gpio18";
2393                                 function = "cci_i2c";
2394
2395                                 bias-pull-up;
2396                                 drive-strength = <2>; /* 2 mA */
2397                         };
2398
2399                         cci0_sleep: cci0-sleep {
2400                                 /* SDA, SCL */
2401                                 pins = "gpio17", "gpio18";
2402                                 function = "cci_i2c";
2403
2404                                 drive-strength = <2>; /* 2 mA */
2405                                 bias-pull-down;
2406                         };
2407
2408                         cci1_default: cci1-default {
2409                                 /* SDA, SCL */
2410                                 pins = "gpio19", "gpio20";
2411                                 function = "cci_i2c";
2412
2413                                 bias-pull-up;
2414                                 drive-strength = <2>; /* 2 mA */
2415                         };
2416
2417                         cci1_sleep: cci1-sleep {
2418                                 /* SDA, SCL */
2419                                 pins = "gpio19", "gpio20";
2420                                 function = "cci_i2c";
2421
2422                                 drive-strength = <2>; /* 2 mA */
2423                                 bias-pull-down;
2424                         };
2425
2426                         qspi_clk: qspi-clk {
2427                                 pinmux {
2428                                         pins = "gpio95";
2429                                         function = "qspi_clk";
2430                                 };
2431                         };
2432
2433                         qspi_cs0: qspi-cs0 {
2434                                 pinmux {
2435                                         pins = "gpio90";
2436                                         function = "qspi_cs";
2437                                 };
2438                         };
2439
2440                         qspi_cs1: qspi-cs1 {
2441                                 pinmux {
2442                                         pins = "gpio89";
2443                                         function = "qspi_cs";
2444                                 };
2445                         };
2446
2447                         qspi_data01: qspi-data01 {
2448                                 pinmux-data {
2449                                         pins = "gpio91", "gpio92";
2450                                         function = "qspi_data";
2451                                 };
2452                         };
2453
2454                         qspi_data12: qspi-data12 {
2455                                 pinmux-data {
2456                                         pins = "gpio93", "gpio94";
2457                                         function = "qspi_data";
2458                                 };
2459                         };
2460
2461                         qup_i2c0_default: qup-i2c0-default {
2462                                 pinmux {
2463                                         pins = "gpio0", "gpio1";
2464                                         function = "qup0";
2465                                 };
2466                         };
2467
2468                         qup_i2c1_default: qup-i2c1-default {
2469                                 pinmux {
2470                                         pins = "gpio17", "gpio18";
2471                                         function = "qup1";
2472                                 };
2473                         };
2474
2475                         qup_i2c2_default: qup-i2c2-default {
2476                                 pinmux {
2477                                         pins = "gpio27", "gpio28";
2478                                         function = "qup2";
2479                                 };
2480                         };
2481
2482                         qup_i2c3_default: qup-i2c3-default {
2483                                 pinmux {
2484                                         pins = "gpio41", "gpio42";
2485                                         function = "qup3";
2486                                 };
2487                         };
2488
2489                         qup_i2c4_default: qup-i2c4-default {
2490                                 pinmux {
2491                                         pins = "gpio89", "gpio90";
2492                                         function = "qup4";
2493                                 };
2494                         };
2495
2496                         qup_i2c5_default: qup-i2c5-default {
2497                                 pinmux {
2498                                         pins = "gpio85", "gpio86";
2499                                         function = "qup5";
2500                                 };
2501                         };
2502
2503                         qup_i2c6_default: qup-i2c6-default {
2504                                 pinmux {
2505                                         pins = "gpio45", "gpio46";
2506                                         function = "qup6";
2507                                 };
2508                         };
2509
2510                         qup_i2c7_default: qup-i2c7-default {
2511                                 pinmux {
2512                                         pins = "gpio93", "gpio94";
2513                                         function = "qup7";
2514                                 };
2515                         };
2516
2517                         qup_i2c8_default: qup-i2c8-default {
2518                                 pinmux {
2519                                         pins = "gpio65", "gpio66";
2520                                         function = "qup8";
2521                                 };
2522                         };
2523
2524                         qup_i2c9_default: qup-i2c9-default {
2525                                 pinmux {
2526                                         pins = "gpio6", "gpio7";
2527                                         function = "qup9";
2528                                 };
2529                         };
2530
2531                         qup_i2c10_default: qup-i2c10-default {
2532                                 pinmux {
2533                                         pins = "gpio55", "gpio56";
2534                                         function = "qup10";
2535                                 };
2536                         };
2537
2538                         qup_i2c11_default: qup-i2c11-default {
2539                                 pinmux {
2540                                         pins = "gpio31", "gpio32";
2541                                         function = "qup11";
2542                                 };
2543                         };
2544
2545                         qup_i2c12_default: qup-i2c12-default {
2546                                 pinmux {
2547                                         pins = "gpio49", "gpio50";
2548                                         function = "qup12";
2549                                 };
2550                         };
2551
2552                         qup_i2c13_default: qup-i2c13-default {
2553                                 pinmux {
2554                                         pins = "gpio105", "gpio106";
2555                                         function = "qup13";
2556                                 };
2557                         };
2558
2559                         qup_i2c14_default: qup-i2c14-default {
2560                                 pinmux {
2561                                         pins = "gpio33", "gpio34";
2562                                         function = "qup14";
2563                                 };
2564                         };
2565
2566                         qup_i2c15_default: qup-i2c15-default {
2567                                 pinmux {
2568                                         pins = "gpio81", "gpio82";
2569                                         function = "qup15";
2570                                 };
2571                         };
2572
2573                         qup_spi0_default: qup-spi0-default {
2574                                 pinmux {
2575                                         pins = "gpio0", "gpio1",
2576                                                "gpio2", "gpio3";
2577                                         function = "qup0";
2578                                 };
2579                         };
2580
2581                         qup_spi1_default: qup-spi1-default {
2582                                 pinmux {
2583                                         pins = "gpio17", "gpio18",
2584                                                "gpio19", "gpio20";
2585                                         function = "qup1";
2586                                 };
2587                         };
2588
2589                         qup_spi2_default: qup-spi2-default {
2590                                 pinmux {
2591                                         pins = "gpio27", "gpio28",
2592                                                "gpio29", "gpio30";
2593                                         function = "qup2";
2594                                 };
2595                         };
2596
2597                         qup_spi3_default: qup-spi3-default {
2598                                 pinmux {
2599                                         pins = "gpio41", "gpio42",
2600                                                "gpio43", "gpio44";
2601                                         function = "qup3";
2602                                 };
2603                         };
2604
2605                         qup_spi4_default: qup-spi4-default {
2606                                 pinmux {
2607                                         pins = "gpio89", "gpio90",
2608                                                "gpio91", "gpio92";
2609                                         function = "qup4";
2610                                 };
2611                         };
2612
2613                         qup_spi5_default: qup-spi5-default {
2614                                 pinmux {
2615                                         pins = "gpio85", "gpio86",
2616                                                "gpio87", "gpio88";
2617                                         function = "qup5";
2618                                 };
2619                         };
2620
2621                         qup_spi6_default: qup-spi6-default {
2622                                 pinmux {
2623                                         pins = "gpio45", "gpio46",
2624                                                "gpio47", "gpio48";
2625                                         function = "qup6";
2626                                 };
2627                         };
2628
2629                         qup_spi7_default: qup-spi7-default {
2630                                 pinmux {
2631                                         pins = "gpio93", "gpio94",
2632                                                "gpio95", "gpio96";
2633                                         function = "qup7";
2634                                 };
2635                         };
2636
2637                         qup_spi8_default: qup-spi8-default {
2638                                 pinmux {
2639                                         pins = "gpio65", "gpio66",
2640                                                "gpio67", "gpio68";
2641                                         function = "qup8";
2642                                 };
2643                         };
2644
2645                         qup_spi9_default: qup-spi9-default {
2646                                 pinmux {
2647                                         pins = "gpio6", "gpio7",
2648                                                "gpio4", "gpio5";
2649                                         function = "qup9";
2650                                 };
2651                         };
2652
2653                         qup_spi10_default: qup-spi10-default {
2654                                 pinmux {
2655                                         pins = "gpio55", "gpio56",
2656                                                "gpio53", "gpio54";
2657                                         function = "qup10";
2658                                 };
2659                         };
2660
2661                         qup_spi11_default: qup-spi11-default {
2662                                 pinmux {
2663                                         pins = "gpio31", "gpio32",
2664                                                "gpio33", "gpio34";
2665                                         function = "qup11";
2666                                 };
2667                         };
2668
2669                         qup_spi12_default: qup-spi12-default {
2670                                 pinmux {
2671                                         pins = "gpio49", "gpio50",
2672                                                "gpio51", "gpio52";
2673                                         function = "qup12";
2674                                 };
2675                         };
2676
2677                         qup_spi13_default: qup-spi13-default {
2678                                 pinmux {
2679                                         pins = "gpio105", "gpio106",
2680                                                "gpio107", "gpio108";
2681                                         function = "qup13";
2682                                 };
2683                         };
2684
2685                         qup_spi14_default: qup-spi14-default {
2686                                 pinmux {
2687                                         pins = "gpio33", "gpio34",
2688                                                "gpio31", "gpio32";
2689                                         function = "qup14";
2690                                 };
2691                         };
2692
2693                         qup_spi15_default: qup-spi15-default {
2694                                 pinmux {
2695                                         pins = "gpio81", "gpio82",
2696                                                "gpio83", "gpio84";
2697                                         function = "qup15";
2698                                 };
2699                         };
2700
2701                         qup_uart0_default: qup-uart0-default {
2702                                 pinmux {
2703                                         pins = "gpio2", "gpio3";
2704                                         function = "qup0";
2705                                 };
2706                         };
2707
2708                         qup_uart1_default: qup-uart1-default {
2709                                 pinmux {
2710                                         pins = "gpio19", "gpio20";
2711                                         function = "qup1";
2712                                 };
2713                         };
2714
2715                         qup_uart2_default: qup-uart2-default {
2716                                 pinmux {
2717                                         pins = "gpio29", "gpio30";
2718                                         function = "qup2";
2719                                 };
2720                         };
2721
2722                         qup_uart3_default: qup-uart3-default {
2723                                 pinmux {
2724                                         pins = "gpio43", "gpio44";
2725                                         function = "qup3";
2726                                 };
2727                         };
2728
2729                         qup_uart4_default: qup-uart4-default {
2730                                 pinmux {
2731                                         pins = "gpio91", "gpio92";
2732                                         function = "qup4";
2733                                 };
2734                         };
2735
2736                         qup_uart5_default: qup-uart5-default {
2737                                 pinmux {
2738                                         pins = "gpio87", "gpio88";
2739                                         function = "qup5";
2740                                 };
2741                         };
2742
2743                         qup_uart6_default: qup-uart6-default {
2744                                 pinmux {
2745                                         pins = "gpio47", "gpio48";
2746                                         function = "qup6";
2747                                 };
2748                         };
2749
2750                         qup_uart7_default: qup-uart7-default {
2751                                 pinmux {
2752                                         pins = "gpio95", "gpio96";
2753                                         function = "qup7";
2754                                 };
2755                         };
2756
2757                         qup_uart8_default: qup-uart8-default {
2758                                 pinmux {
2759                                         pins = "gpio67", "gpio68";
2760                                         function = "qup8";
2761                                 };
2762                         };
2763
2764                         qup_uart9_default: qup-uart9-default {
2765                                 pinmux {
2766                                         pins = "gpio4", "gpio5";
2767                                         function = "qup9";
2768                                 };
2769                         };
2770
2771                         qup_uart10_default: qup-uart10-default {
2772                                 pinmux {
2773                                         pins = "gpio53", "gpio54";
2774                                         function = "qup10";
2775                                 };
2776                         };
2777
2778                         qup_uart11_default: qup-uart11-default {
2779                                 pinmux {
2780                                         pins = "gpio33", "gpio34";
2781                                         function = "qup11";
2782                                 };
2783                         };
2784
2785                         qup_uart12_default: qup-uart12-default {
2786                                 pinmux {
2787                                         pins = "gpio51", "gpio52";
2788                                         function = "qup12";
2789                                 };
2790                         };
2791
2792                         qup_uart13_default: qup-uart13-default {
2793                                 pinmux {
2794                                         pins = "gpio107", "gpio108";
2795                                         function = "qup13";
2796                                 };
2797                         };
2798
2799                         qup_uart14_default: qup-uart14-default {
2800                                 pinmux {
2801                                         pins = "gpio31", "gpio32";
2802                                         function = "qup14";
2803                                 };
2804                         };
2805
2806                         qup_uart15_default: qup-uart15-default {
2807                                 pinmux {
2808                                         pins = "gpio83", "gpio84";
2809                                         function = "qup15";
2810                                 };
2811                         };
2812
2813                         quat_mi2s_sleep: quat_mi2s_sleep {
2814                                 mux {
2815                                         pins = "gpio58", "gpio59";
2816                                         function = "gpio";
2817                                 };
2818
2819                                 config {
2820                                         pins = "gpio58", "gpio59";
2821                                         drive-strength = <2>;
2822                                         bias-pull-down;
2823                                         input-enable;
2824                                 };
2825                         };
2826
2827                         quat_mi2s_active: quat_mi2s_active {
2828                                 mux {
2829                                         pins = "gpio58", "gpio59";
2830                                         function = "qua_mi2s";
2831                                 };
2832
2833                                 config {
2834                                         pins = "gpio58", "gpio59";
2835                                         drive-strength = <8>;
2836                                         bias-disable;
2837                                         output-high;
2838                                 };
2839                         };
2840
2841                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2842                                 mux {
2843                                         pins = "gpio60";
2844                                         function = "gpio";
2845                                 };
2846
2847                                 config {
2848                                         pins = "gpio60";
2849                                         drive-strength = <2>;
2850                                         bias-pull-down;
2851                                         input-enable;
2852                                 };
2853                         };
2854
2855                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2856                                 mux {
2857                                         pins = "gpio60";
2858                                         function = "qua_mi2s";
2859                                 };
2860
2861                                 config {
2862                                         pins = "gpio60";
2863                                         drive-strength = <8>;
2864                                         bias-disable;
2865                                 };
2866                         };
2867
2868                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2869                                 mux {
2870                                         pins = "gpio61";
2871                                         function = "gpio";
2872                                 };
2873
2874                                 config {
2875                                         pins = "gpio61";
2876                                         drive-strength = <2>;
2877                                         bias-pull-down;
2878                                         input-enable;
2879                                 };
2880                         };
2881
2882                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2883                                 mux {
2884                                         pins = "gpio61";
2885                                         function = "qua_mi2s";
2886                                 };
2887
2888                                 config {
2889                                         pins = "gpio61";
2890                                         drive-strength = <8>;
2891                                         bias-disable;
2892                                 };
2893                         };
2894
2895                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2896                                 mux {
2897                                         pins = "gpio62";
2898                                         function = "gpio";
2899                                 };
2900
2901                                 config {
2902                                         pins = "gpio62";
2903                                         drive-strength = <2>;
2904                                         bias-pull-down;
2905                                         input-enable;
2906                                 };
2907                         };
2908
2909                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2910                                 mux {
2911                                         pins = "gpio62";
2912                                         function = "qua_mi2s";
2913                                 };
2914
2915                                 config {
2916                                         pins = "gpio62";
2917                                         drive-strength = <8>;
2918                                         bias-disable;
2919                                 };
2920                         };
2921
2922                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2923                                 mux {
2924                                         pins = "gpio63";
2925                                         function = "gpio";
2926                                 };
2927
2928                                 config {
2929                                         pins = "gpio63";
2930                                         drive-strength = <2>;
2931                                         bias-pull-down;
2932                                         input-enable;
2933                                 };
2934                         };
2935
2936                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2937                                 mux {
2938                                         pins = "gpio63";
2939                                         function = "qua_mi2s";
2940                                 };
2941
2942                                 config {
2943                                         pins = "gpio63";
2944                                         drive-strength = <8>;
2945                                         bias-disable;
2946                                 };
2947                         };
2948                 };
2949
2950                 mss_pil: remoteproc@4080000 {
2951                         compatible = "qcom,sdm845-mss-pil";
2952                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2953                         reg-names = "qdsp6", "rmb";
2954
2955                         interrupts-extended =
2956                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2957                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2958                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2959                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2960                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2961                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2962                         interrupt-names = "wdog", "fatal", "ready",
2963                                           "handover", "stop-ack",
2964                                           "shutdown-ack";
2965
2966                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2967                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2968                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2969                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2970                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2971                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2972                                  <&gcc GCC_PRNG_AHB_CLK>,
2973                                  <&rpmhcc RPMH_CXO_CLK>;
2974                         clock-names = "iface", "bus", "mem", "gpll0_mss",
2975                                       "snoc_axi", "mnoc_axi", "prng", "xo";
2976
2977                         qcom,smem-states = <&modem_smp2p_out 0>;
2978                         qcom,smem-state-names = "stop";
2979
2980                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2981                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2982                         reset-names = "mss_restart", "pdc_reset";
2983
2984                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2985
2986                         power-domains = <&aoss_qmp 2>,
2987                                         <&rpmhpd SDM845_CX>,
2988                                         <&rpmhpd SDM845_MX>,
2989                                         <&rpmhpd SDM845_MSS>;
2990                         power-domain-names = "load_state", "cx", "mx", "mss";
2991
2992                         mba {
2993                                 memory-region = <&mba_region>;
2994                         };
2995
2996                         mpss {
2997                                 memory-region = <&mpss_region>;
2998                         };
2999
3000                         glink-edge {
3001                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3002                                 label = "modem";
3003                                 qcom,remote-pid = <1>;
3004                                 mboxes = <&apss_shared 12>;
3005                         };
3006                 };
3007
3008                 gpucc: clock-controller@5090000 {
3009                         compatible = "qcom,sdm845-gpucc";
3010                         reg = <0 0x05090000 0 0x9000>;
3011                         #clock-cells = <1>;
3012                         #reset-cells = <1>;
3013                         #power-domain-cells = <1>;
3014                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3015                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3016                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3017                         clock-names = "bi_tcxo",
3018                                       "gcc_gpu_gpll0_clk_src",
3019                                       "gcc_gpu_gpll0_div_clk_src";
3020                 };
3021
3022                 stm@6002000 {
3023                         compatible = "arm,coresight-stm", "arm,primecell";
3024                         reg = <0 0x06002000 0 0x1000>,
3025                               <0 0x16280000 0 0x180000>;
3026                         reg-names = "stm-base", "stm-stimulus-base";
3027
3028                         clocks = <&aoss_qmp>;
3029                         clock-names = "apb_pclk";
3030
3031                         out-ports {
3032                                 port {
3033                                         stm_out: endpoint {
3034                                                 remote-endpoint =
3035                                                   <&funnel0_in7>;
3036                                         };
3037                                 };
3038                         };
3039                 };
3040
3041                 funnel@6041000 {
3042                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3043                         reg = <0 0x06041000 0 0x1000>;
3044
3045                         clocks = <&aoss_qmp>;
3046                         clock-names = "apb_pclk";
3047
3048                         out-ports {
3049                                 port {
3050                                         funnel0_out: endpoint {
3051                                                 remote-endpoint =
3052                                                   <&merge_funnel_in0>;
3053                                         };
3054                                 };
3055                         };
3056
3057                         in-ports {
3058                                 #address-cells = <1>;
3059                                 #size-cells = <0>;
3060
3061                                 port@7 {
3062                                         reg = <7>;
3063                                         funnel0_in7: endpoint {
3064                                                 remote-endpoint = <&stm_out>;
3065                                         };
3066                                 };
3067                         };
3068                 };
3069
3070                 funnel@6043000 {
3071                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3072                         reg = <0 0x06043000 0 0x1000>;
3073
3074                         clocks = <&aoss_qmp>;
3075                         clock-names = "apb_pclk";
3076
3077                         out-ports {
3078                                 port {
3079                                         funnel2_out: endpoint {
3080                                                 remote-endpoint =
3081                                                   <&merge_funnel_in2>;
3082                                         };
3083                                 };
3084                         };
3085
3086                         in-ports {
3087                                 #address-cells = <1>;
3088                                 #size-cells = <0>;
3089
3090                                 port@5 {
3091                                         reg = <5>;
3092                                         funnel2_in5: endpoint {
3093                                                 remote-endpoint =
3094                                                   <&apss_merge_funnel_out>;
3095                                         };
3096                                 };
3097                         };
3098                 };
3099
3100                 funnel@6045000 {
3101                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3102                         reg = <0 0x06045000 0 0x1000>;
3103
3104                         clocks = <&aoss_qmp>;
3105                         clock-names = "apb_pclk";
3106
3107                         out-ports {
3108                                 port {
3109                                         merge_funnel_out: endpoint {
3110                                                 remote-endpoint = <&etf_in>;
3111                                         };
3112                                 };
3113                         };
3114
3115                         in-ports {
3116                                 #address-cells = <1>;
3117                                 #size-cells = <0>;
3118
3119                                 port@0 {
3120                                         reg = <0>;
3121                                         merge_funnel_in0: endpoint {
3122                                                 remote-endpoint =
3123                                                   <&funnel0_out>;
3124                                         };
3125                                 };
3126
3127                                 port@2 {
3128                                         reg = <2>;
3129                                         merge_funnel_in2: endpoint {
3130                                                 remote-endpoint =
3131                                                   <&funnel2_out>;
3132                                         };
3133                                 };
3134                         };
3135                 };
3136
3137                 replicator@6046000 {
3138                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3139                         reg = <0 0x06046000 0 0x1000>;
3140
3141                         clocks = <&aoss_qmp>;
3142                         clock-names = "apb_pclk";
3143
3144                         out-ports {
3145                                 port {
3146                                         replicator_out: endpoint {
3147                                                 remote-endpoint = <&etr_in>;
3148                                         };
3149                                 };
3150                         };
3151
3152                         in-ports {
3153                                 port {
3154                                         replicator_in: endpoint {
3155                                                 remote-endpoint = <&etf_out>;
3156                                         };
3157                                 };
3158                         };
3159                 };
3160
3161                 etf@6047000 {
3162                         compatible = "arm,coresight-tmc", "arm,primecell";
3163                         reg = <0 0x06047000 0 0x1000>;
3164
3165                         clocks = <&aoss_qmp>;
3166                         clock-names = "apb_pclk";
3167
3168                         out-ports {
3169                                 port {
3170                                         etf_out: endpoint {
3171                                                 remote-endpoint =
3172                                                   <&replicator_in>;
3173                                         };
3174                                 };
3175                         };
3176
3177                         in-ports {
3178                                 #address-cells = <1>;
3179                                 #size-cells = <0>;
3180
3181                                 port@1 {
3182                                         reg = <1>;
3183                                         etf_in: endpoint {
3184                                                 remote-endpoint =
3185                                                   <&merge_funnel_out>;
3186                                         };
3187                                 };
3188                         };
3189                 };
3190
3191                 etr@6048000 {
3192                         compatible = "arm,coresight-tmc", "arm,primecell";
3193                         reg = <0 0x06048000 0 0x1000>;
3194
3195                         clocks = <&aoss_qmp>;
3196                         clock-names = "apb_pclk";
3197                         arm,scatter-gather;
3198
3199                         in-ports {
3200                                 port {
3201                                         etr_in: endpoint {
3202                                                 remote-endpoint =
3203                                                   <&replicator_out>;
3204                                         };
3205                                 };
3206                         };
3207                 };
3208
3209                 etm@7040000 {
3210                         compatible = "arm,coresight-etm4x", "arm,primecell";
3211                         reg = <0 0x07040000 0 0x1000>;
3212
3213                         cpu = <&CPU0>;
3214
3215                         clocks = <&aoss_qmp>;
3216                         clock-names = "apb_pclk";
3217                         arm,coresight-loses-context-with-cpu;
3218
3219                         out-ports {
3220                                 port {
3221                                         etm0_out: endpoint {
3222                                                 remote-endpoint =
3223                                                   <&apss_funnel_in0>;
3224                                         };
3225                                 };
3226                         };
3227                 };
3228
3229                 etm@7140000 {
3230                         compatible = "arm,coresight-etm4x", "arm,primecell";
3231                         reg = <0 0x07140000 0 0x1000>;
3232
3233                         cpu = <&CPU1>;
3234
3235                         clocks = <&aoss_qmp>;
3236                         clock-names = "apb_pclk";
3237                         arm,coresight-loses-context-with-cpu;
3238
3239                         out-ports {
3240                                 port {
3241                                         etm1_out: endpoint {
3242                                                 remote-endpoint =
3243                                                   <&apss_funnel_in1>;
3244                                         };
3245                                 };
3246                         };
3247                 };
3248
3249                 etm@7240000 {
3250                         compatible = "arm,coresight-etm4x", "arm,primecell";
3251                         reg = <0 0x07240000 0 0x1000>;
3252
3253                         cpu = <&CPU2>;
3254
3255                         clocks = <&aoss_qmp>;
3256                         clock-names = "apb_pclk";
3257                         arm,coresight-loses-context-with-cpu;
3258
3259                         out-ports {
3260                                 port {
3261                                         etm2_out: endpoint {
3262                                                 remote-endpoint =
3263                                                   <&apss_funnel_in2>;
3264                                         };
3265                                 };
3266                         };
3267                 };
3268
3269                 etm@7340000 {
3270                         compatible = "arm,coresight-etm4x", "arm,primecell";
3271                         reg = <0 0x07340000 0 0x1000>;
3272
3273                         cpu = <&CPU3>;
3274
3275                         clocks = <&aoss_qmp>;
3276                         clock-names = "apb_pclk";
3277                         arm,coresight-loses-context-with-cpu;
3278
3279                         out-ports {
3280                                 port {
3281                                         etm3_out: endpoint {
3282                                                 remote-endpoint =
3283                                                   <&apss_funnel_in3>;
3284                                         };
3285                                 };
3286                         };
3287                 };
3288
3289                 etm@7440000 {
3290                         compatible = "arm,coresight-etm4x", "arm,primecell";
3291                         reg = <0 0x07440000 0 0x1000>;
3292
3293                         cpu = <&CPU4>;
3294
3295                         clocks = <&aoss_qmp>;
3296                         clock-names = "apb_pclk";
3297                         arm,coresight-loses-context-with-cpu;
3298
3299                         out-ports {
3300                                 port {
3301                                         etm4_out: endpoint {
3302                                                 remote-endpoint =
3303                                                   <&apss_funnel_in4>;
3304                                         };
3305                                 };
3306                         };
3307                 };
3308
3309                 etm@7540000 {
3310                         compatible = "arm,coresight-etm4x", "arm,primecell";
3311                         reg = <0 0x07540000 0 0x1000>;
3312
3313                         cpu = <&CPU5>;
3314
3315                         clocks = <&aoss_qmp>;
3316                         clock-names = "apb_pclk";
3317                         arm,coresight-loses-context-with-cpu;
3318
3319                         out-ports {
3320                                 port {
3321                                         etm5_out: endpoint {
3322                                                 remote-endpoint =
3323                                                   <&apss_funnel_in5>;
3324                                         };
3325                                 };
3326                         };
3327                 };
3328
3329                 etm@7640000 {
3330                         compatible = "arm,coresight-etm4x", "arm,primecell";
3331                         reg = <0 0x07640000 0 0x1000>;
3332
3333                         cpu = <&CPU6>;
3334
3335                         clocks = <&aoss_qmp>;
3336                         clock-names = "apb_pclk";
3337                         arm,coresight-loses-context-with-cpu;
3338
3339                         out-ports {
3340                                 port {
3341                                         etm6_out: endpoint {
3342                                                 remote-endpoint =
3343                                                   <&apss_funnel_in6>;
3344                                         };
3345                                 };
3346                         };
3347                 };
3348
3349                 etm@7740000 {
3350                         compatible = "arm,coresight-etm4x", "arm,primecell";
3351                         reg = <0 0x07740000 0 0x1000>;
3352
3353                         cpu = <&CPU7>;
3354
3355                         clocks = <&aoss_qmp>;
3356                         clock-names = "apb_pclk";
3357                         arm,coresight-loses-context-with-cpu;
3358
3359                         out-ports {
3360                                 port {
3361                                         etm7_out: endpoint {
3362                                                 remote-endpoint =
3363                                                   <&apss_funnel_in7>;
3364                                         };
3365                                 };
3366                         };
3367                 };
3368
3369                 funnel@7800000 { /* APSS Funnel */
3370                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3371                         reg = <0 0x07800000 0 0x1000>;
3372
3373                         clocks = <&aoss_qmp>;
3374                         clock-names = "apb_pclk";
3375
3376                         out-ports {
3377                                 port {
3378                                         apss_funnel_out: endpoint {
3379                                                 remote-endpoint =
3380                                                   <&apss_merge_funnel_in>;
3381                                         };
3382                                 };
3383                         };
3384
3385                         in-ports {
3386                                 #address-cells = <1>;
3387                                 #size-cells = <0>;
3388
3389                                 port@0 {
3390                                         reg = <0>;
3391                                         apss_funnel_in0: endpoint {
3392                                                 remote-endpoint =
3393                                                   <&etm0_out>;
3394                                         };
3395                                 };
3396
3397                                 port@1 {
3398                                         reg = <1>;
3399                                         apss_funnel_in1: endpoint {
3400                                                 remote-endpoint =
3401                                                   <&etm1_out>;
3402                                         };
3403                                 };
3404
3405                                 port@2 {
3406                                         reg = <2>;
3407                                         apss_funnel_in2: endpoint {
3408                                                 remote-endpoint =
3409                                                   <&etm2_out>;
3410                                         };
3411                                 };
3412
3413                                 port@3 {
3414                                         reg = <3>;
3415                                         apss_funnel_in3: endpoint {
3416                                                 remote-endpoint =
3417                                                   <&etm3_out>;
3418                                         };
3419                                 };
3420
3421                                 port@4 {
3422                                         reg = <4>;
3423                                         apss_funnel_in4: endpoint {
3424                                                 remote-endpoint =
3425                                                   <&etm4_out>;
3426                                         };
3427                                 };
3428
3429                                 port@5 {
3430                                         reg = <5>;
3431                                         apss_funnel_in5: endpoint {
3432                                                 remote-endpoint =
3433                                                   <&etm5_out>;
3434                                         };
3435                                 };
3436
3437                                 port@6 {
3438                                         reg = <6>;
3439                                         apss_funnel_in6: endpoint {
3440                                                 remote-endpoint =
3441                                                   <&etm6_out>;
3442                                         };
3443                                 };
3444
3445                                 port@7 {
3446                                         reg = <7>;
3447                                         apss_funnel_in7: endpoint {
3448                                                 remote-endpoint =
3449                                                   <&etm7_out>;
3450                                         };
3451                                 };
3452                         };
3453                 };
3454
3455                 funnel@7810000 {
3456                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3457                         reg = <0 0x07810000 0 0x1000>;
3458
3459                         clocks = <&aoss_qmp>;
3460                         clock-names = "apb_pclk";
3461
3462                         out-ports {
3463                                 port {
3464                                         apss_merge_funnel_out: endpoint {
3465                                                 remote-endpoint =
3466                                                   <&funnel2_in5>;
3467                                         };
3468                                 };
3469                         };
3470
3471                         in-ports {
3472                                 port {
3473                                         apss_merge_funnel_in: endpoint {
3474                                                 remote-endpoint =
3475                                                   <&apss_funnel_out>;
3476                                         };
3477                                 };
3478                         };
3479                 };
3480
3481                 sdhc_2: sdhci@8804000 {
3482                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3483                         reg = <0 0x08804000 0 0x1000>;
3484
3485                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3486                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3487                         interrupt-names = "hc_irq", "pwr_irq";
3488
3489                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3490                                  <&gcc GCC_SDCC2_APPS_CLK>;
3491                         clock-names = "iface", "core";
3492                         iommus = <&apps_smmu 0xa0 0xf>;
3493                         power-domains = <&rpmhpd SDM845_CX>;
3494                         operating-points-v2 = <&sdhc2_opp_table>;
3495
3496                         status = "disabled";
3497
3498                         sdhc2_opp_table: sdhc2-opp-table {
3499                                 compatible = "operating-points-v2";
3500
3501                                 opp-9600000 {
3502                                         opp-hz = /bits/ 64 <9600000>;
3503                                         required-opps = <&rpmhpd_opp_min_svs>;
3504                                 };
3505
3506                                 opp-19200000 {
3507                                         opp-hz = /bits/ 64 <19200000>;
3508                                         required-opps = <&rpmhpd_opp_low_svs>;
3509                                 };
3510
3511                                 opp-100000000 {
3512                                         opp-hz = /bits/ 64 <100000000>;
3513                                         required-opps = <&rpmhpd_opp_svs>;
3514                                 };
3515
3516                                 opp-201500000 {
3517                                         opp-hz = /bits/ 64 <201500000>;
3518                                         required-opps = <&rpmhpd_opp_svs_l1>;
3519                                 };
3520                         };
3521                 };
3522
3523                 qspi_opp_table: qspi-opp-table {
3524                         compatible = "operating-points-v2";
3525
3526                         opp-19200000 {
3527                                 opp-hz = /bits/ 64 <19200000>;
3528                                 required-opps = <&rpmhpd_opp_min_svs>;
3529                         };
3530
3531                         opp-100000000 {
3532                                 opp-hz = /bits/ 64 <100000000>;
3533                                 required-opps = <&rpmhpd_opp_low_svs>;
3534                         };
3535
3536                         opp-150000000 {
3537                                 opp-hz = /bits/ 64 <150000000>;
3538                                 required-opps = <&rpmhpd_opp_svs>;
3539                         };
3540
3541                         opp-300000000 {
3542                                 opp-hz = /bits/ 64 <300000000>;
3543                                 required-opps = <&rpmhpd_opp_nom>;
3544                         };
3545                 };
3546
3547                 qspi: spi@88df000 {
3548                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3549                         reg = <0 0x088df000 0 0x600>;
3550                         #address-cells = <1>;
3551                         #size-cells = <0>;
3552                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3553                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3554                                  <&gcc GCC_QSPI_CORE_CLK>;
3555                         clock-names = "iface", "core";
3556                         power-domains = <&rpmhpd SDM845_CX>;
3557                         operating-points-v2 = <&qspi_opp_table>;
3558                         status = "disabled";
3559                 };
3560
3561                 slim: slim@171c0000 {
3562                         compatible = "qcom,slim-ngd-v2.1.0";
3563                         reg = <0 0x171c0000 0 0x2c000>;
3564                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3565
3566                         qcom,apps-ch-pipes = <0x780000>;
3567                         qcom,ea-pc = <0x270>;
3568                         status = "okay";
3569                         dmas =  <&slimbam 3>, <&slimbam 4>,
3570                                 <&slimbam 5>, <&slimbam 6>;
3571                         dma-names = "rx", "tx", "tx2", "rx2";
3572
3573                         iommus = <&apps_smmu 0x1806 0x0>;
3574                         #address-cells = <1>;
3575                         #size-cells = <0>;
3576
3577                         ngd@1 {
3578                                 reg = <1>;
3579                                 #address-cells = <2>;
3580                                 #size-cells = <0>;
3581
3582                                 wcd9340_ifd: ifd@0{
3583                                         compatible = "slim217,250";
3584                                         reg  = <0 0>;
3585                                 };
3586
3587                                 wcd9340: codec@1{
3588                                         compatible = "slim217,250";
3589                                         reg  = <1 0>;
3590                                         slim-ifc-dev  = <&wcd9340_ifd>;
3591
3592                                         #sound-dai-cells = <1>;
3593
3594                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3595                                         interrupt-controller;
3596                                         #interrupt-cells = <1>;
3597
3598                                         #clock-cells = <0>;
3599                                         clock-frequency = <9600000>;
3600                                         clock-output-names = "mclk";
3601                                         qcom,micbias1-millivolt = <1800>;
3602                                         qcom,micbias2-millivolt = <1800>;
3603                                         qcom,micbias3-millivolt = <1800>;
3604                                         qcom,micbias4-millivolt = <1800>;
3605
3606                                         #address-cells = <1>;
3607                                         #size-cells = <1>;
3608
3609                                         wcdgpio: gpio-controller@42 {
3610                                                 compatible = "qcom,wcd9340-gpio";
3611                                                 gpio-controller;
3612                                                 #gpio-cells = <2>;
3613                                                 reg = <0x42 0x2>;
3614                                         };
3615
3616                                         swm: swm@c85 {
3617                                                 compatible = "qcom,soundwire-v1.3.0";
3618                                                 reg = <0xc85 0x40>;
3619                                                 interrupts-extended = <&wcd9340 20>;
3620
3621                                                 qcom,dout-ports = <6>;
3622                                                 qcom,din-ports  = <2>;
3623                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3624                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3625                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3626
3627                                                 #sound-dai-cells = <1>;
3628                                                 clocks = <&wcd9340>;
3629                                                 clock-names = "iface";
3630                                                 #address-cells = <2>;
3631                                                 #size-cells = <0>;
3632
3633
3634                                         };
3635                                 };
3636                         };
3637                 };
3638
3639                 sound: sound {
3640                 };
3641
3642                 usb_1_hsphy: phy@88e2000 {
3643                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3644                         reg = <0 0x088e2000 0 0x400>;
3645                         status = "disabled";
3646                         #phy-cells = <0>;
3647
3648                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3649                                  <&rpmhcc RPMH_CXO_CLK>;
3650                         clock-names = "cfg_ahb", "ref";
3651
3652                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3653
3654                         nvmem-cells = <&qusb2p_hstx_trim>;
3655                 };
3656
3657                 usb_2_hsphy: phy@88e3000 {
3658                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3659                         reg = <0 0x088e3000 0 0x400>;
3660                         status = "disabled";
3661                         #phy-cells = <0>;
3662
3663                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3664                                  <&rpmhcc RPMH_CXO_CLK>;
3665                         clock-names = "cfg_ahb", "ref";
3666
3667                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3668
3669                         nvmem-cells = <&qusb2s_hstx_trim>;
3670                 };
3671
3672                 usb_1_qmpphy: phy@88e9000 {
3673                         compatible = "qcom,sdm845-qmp-usb3-phy";
3674                         reg = <0 0x088e9000 0 0x18c>,
3675                               <0 0x088e8000 0 0x10>;
3676                         reg-names = "reg-base", "dp_com";
3677                         status = "disabled";
3678                         #clock-cells = <1>;
3679                         #address-cells = <2>;
3680                         #size-cells = <2>;
3681                         ranges;
3682
3683                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3684                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3685                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3686                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3687                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3688
3689                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3690                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3691                         reset-names = "phy", "common";
3692
3693                         usb_1_ssphy: lanes@88e9200 {
3694                                 reg = <0 0x088e9200 0 0x128>,
3695                                       <0 0x088e9400 0 0x200>,
3696                                       <0 0x088e9c00 0 0x218>,
3697                                       <0 0x088e9600 0 0x128>,
3698                                       <0 0x088e9800 0 0x200>,
3699                                       <0 0x088e9a00 0 0x100>;
3700                                 #phy-cells = <0>;
3701                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3702                                 clock-names = "pipe0";
3703                                 clock-output-names = "usb3_phy_pipe_clk_src";
3704                         };
3705                 };
3706
3707                 usb_2_qmpphy: phy@88eb000 {
3708                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3709                         reg = <0 0x088eb000 0 0x18c>;
3710                         status = "disabled";
3711                         #clock-cells = <1>;
3712                         #address-cells = <2>;
3713                         #size-cells = <2>;
3714                         ranges;
3715
3716                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3717                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3718                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3719                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3720                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3721
3722                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3723                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3724                         reset-names = "phy", "common";
3725
3726                         usb_2_ssphy: lane@88eb200 {
3727                                 reg = <0 0x088eb200 0 0x128>,
3728                                       <0 0x088eb400 0 0x1fc>,
3729                                       <0 0x088eb800 0 0x218>,
3730                                       <0 0x088eb600 0 0x70>;
3731                                 #phy-cells = <0>;
3732                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3733                                 clock-names = "pipe0";
3734                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3735                         };
3736                 };
3737
3738                 usb_1: usb@a6f8800 {
3739                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3740                         reg = <0 0x0a6f8800 0 0x400>;
3741                         status = "disabled";
3742                         #address-cells = <2>;
3743                         #size-cells = <2>;
3744                         ranges;
3745                         dma-ranges;
3746
3747                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3748                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3749                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3750                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3751                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3752                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3753                                       "sleep";
3754
3755                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3756                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3757                         assigned-clock-rates = <19200000>, <150000000>;
3758
3759                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3760                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3761                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3762                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3763                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3764                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3765
3766                         power-domains = <&gcc USB30_PRIM_GDSC>;
3767
3768                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3769
3770                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3771                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3772                         interconnect-names = "usb-ddr", "apps-usb";
3773
3774                         usb_1_dwc3: dwc3@a600000 {
3775                                 compatible = "snps,dwc3";
3776                                 reg = <0 0x0a600000 0 0xcd00>;
3777                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3778                                 iommus = <&apps_smmu 0x740 0>;
3779                                 snps,dis_u2_susphy_quirk;
3780                                 snps,dis_enblslpm_quirk;
3781                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3782                                 phy-names = "usb2-phy", "usb3-phy";
3783                         };
3784                 };
3785
3786                 usb_2: usb@a8f8800 {
3787                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3788                         reg = <0 0x0a8f8800 0 0x400>;
3789                         status = "disabled";
3790                         #address-cells = <2>;
3791                         #size-cells = <2>;
3792                         ranges;
3793                         dma-ranges;
3794
3795                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3796                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3797                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3798                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3799                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3800                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3801                                       "sleep";
3802
3803                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3804                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3805                         assigned-clock-rates = <19200000>, <150000000>;
3806
3807                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3808                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3809                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3810                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3811                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3812                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3813
3814                         power-domains = <&gcc USB30_SEC_GDSC>;
3815
3816                         resets = <&gcc GCC_USB30_SEC_BCR>;
3817
3818                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3819                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3820                         interconnect-names = "usb-ddr", "apps-usb";
3821
3822                         usb_2_dwc3: dwc3@a800000 {
3823                                 compatible = "snps,dwc3";
3824                                 reg = <0 0x0a800000 0 0xcd00>;
3825                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3826                                 iommus = <&apps_smmu 0x760 0>;
3827                                 snps,dis_u2_susphy_quirk;
3828                                 snps,dis_enblslpm_quirk;
3829                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3830                                 phy-names = "usb2-phy", "usb3-phy";
3831                         };
3832                 };
3833
3834                 venus: video-codec@aa00000 {
3835                         compatible = "qcom,sdm845-venus-v2";
3836                         reg = <0 0x0aa00000 0 0xff000>;
3837                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3838                         power-domains = <&videocc VENUS_GDSC>,
3839                                         <&videocc VCODEC0_GDSC>,
3840                                         <&videocc VCODEC1_GDSC>,
3841                                         <&rpmhpd SDM845_CX>;
3842                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3843                         operating-points-v2 = <&venus_opp_table>;
3844                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3845                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3846                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3847                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3848                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3849                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3850                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3851                         clock-names = "core", "iface", "bus",
3852                                       "vcodec0_core", "vcodec0_bus",
3853                                       "vcodec1_core", "vcodec1_bus";
3854                         iommus = <&apps_smmu 0x10a0 0x8>,
3855                                  <&apps_smmu 0x10b0 0x0>;
3856                         memory-region = <&venus_mem>;
3857                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3858                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3859                         interconnect-names = "video-mem", "cpu-cfg";
3860
3861                         video-core0 {
3862                                 compatible = "venus-decoder";
3863                         };
3864
3865                         video-core1 {
3866                                 compatible = "venus-encoder";
3867                         };
3868
3869                         venus_opp_table: venus-opp-table {
3870                                 compatible = "operating-points-v2";
3871
3872                                 opp-100000000 {
3873                                         opp-hz = /bits/ 64 <100000000>;
3874                                         required-opps = <&rpmhpd_opp_min_svs>;
3875                                 };
3876
3877                                 opp-200000000 {
3878                                         opp-hz = /bits/ 64 <200000000>;
3879                                         required-opps = <&rpmhpd_opp_low_svs>;
3880                                 };
3881
3882                                 opp-320000000 {
3883                                         opp-hz = /bits/ 64 <320000000>;
3884                                         required-opps = <&rpmhpd_opp_svs>;
3885                                 };
3886
3887                                 opp-380000000 {
3888                                         opp-hz = /bits/ 64 <380000000>;
3889                                         required-opps = <&rpmhpd_opp_svs_l1>;
3890                                 };
3891
3892                                 opp-444000000 {
3893                                         opp-hz = /bits/ 64 <444000000>;
3894                                         required-opps = <&rpmhpd_opp_nom>;
3895                                 };
3896
3897                                 opp-533000097 {
3898                                         opp-hz = /bits/ 64 <533000097>;
3899                                         required-opps = <&rpmhpd_opp_turbo>;
3900                                 };
3901                         };
3902                 };
3903
3904                 videocc: clock-controller@ab00000 {
3905                         compatible = "qcom,sdm845-videocc";
3906                         reg = <0 0x0ab00000 0 0x10000>;
3907                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3908                         clock-names = "bi_tcxo";
3909                         #clock-cells = <1>;
3910                         #power-domain-cells = <1>;
3911                         #reset-cells = <1>;
3912                 };
3913
3914                 cci: cci@ac4a000 {
3915                         compatible = "qcom,sdm845-cci";
3916                         #address-cells = <1>;
3917                         #size-cells = <0>;
3918
3919                         reg = <0 0x0ac4a000 0 0x4000>;
3920                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3921                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
3922
3923                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3924                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
3925                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3926                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
3927                                 <&clock_camcc CAM_CC_CCI_CLK>,
3928                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
3929                         clock-names = "camnoc_axi",
3930                                 "soc_ahb",
3931                                 "slow_ahb_src",
3932                                 "cpas_ahb",
3933                                 "cci",
3934                                 "cci_src";
3935
3936                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3937                                 <&clock_camcc CAM_CC_CCI_CLK>;
3938                         assigned-clock-rates = <80000000>, <37500000>;
3939
3940                         pinctrl-names = "default", "sleep";
3941                         pinctrl-0 = <&cci0_default &cci1_default>;
3942                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3943
3944                         status = "disabled";
3945
3946                         cci_i2c0: i2c-bus@0 {
3947                                 reg = <0>;
3948                                 clock-frequency = <1000000>;
3949                                 #address-cells = <1>;
3950                                 #size-cells = <0>;
3951                         };
3952
3953                         cci_i2c1: i2c-bus@1 {
3954                                 reg = <1>;
3955                                 clock-frequency = <1000000>;
3956                                 #address-cells = <1>;
3957                                 #size-cells = <0>;
3958                         };
3959                 };
3960
3961                 clock_camcc: clock-controller@ad00000 {
3962                         compatible = "qcom,sdm845-camcc";
3963                         reg = <0 0x0ad00000 0 0x10000>;
3964                         #clock-cells = <1>;
3965                         #reset-cells = <1>;
3966                         #power-domain-cells = <1>;
3967                 };
3968
3969                 dsi_opp_table: dsi-opp-table {
3970                         compatible = "operating-points-v2";
3971
3972                         opp-19200000 {
3973                                 opp-hz = /bits/ 64 <19200000>;
3974                                 required-opps = <&rpmhpd_opp_min_svs>;
3975                         };
3976
3977                         opp-180000000 {
3978                                 opp-hz = /bits/ 64 <180000000>;
3979                                 required-opps = <&rpmhpd_opp_low_svs>;
3980                         };
3981
3982                         opp-275000000 {
3983                                 opp-hz = /bits/ 64 <275000000>;
3984                                 required-opps = <&rpmhpd_opp_svs>;
3985                         };
3986
3987                         opp-328580000 {
3988                                 opp-hz = /bits/ 64 <328580000>;
3989                                 required-opps = <&rpmhpd_opp_svs_l1>;
3990                         };
3991
3992                         opp-358000000 {
3993                                 opp-hz = /bits/ 64 <358000000>;
3994                                 required-opps = <&rpmhpd_opp_nom>;
3995                         };
3996                 };
3997
3998                 mdss: mdss@ae00000 {
3999                         compatible = "qcom,sdm845-mdss";
4000                         reg = <0 0x0ae00000 0 0x1000>;
4001                         reg-names = "mdss";
4002
4003                         power-domains = <&dispcc MDSS_GDSC>;
4004
4005                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4006                                  <&gcc GCC_DISP_AXI_CLK>,
4007                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4008                         clock-names = "iface", "bus", "core";
4009
4010                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4011                         assigned-clock-rates = <300000000>;
4012
4013                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4014                         interrupt-controller;
4015                         #interrupt-cells = <1>;
4016
4017                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4018                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4019                         interconnect-names = "mdp0-mem", "mdp1-mem";
4020
4021                         iommus = <&apps_smmu 0x880 0x8>,
4022                                  <&apps_smmu 0xc80 0x8>;
4023
4024                         status = "disabled";
4025
4026                         #address-cells = <2>;
4027                         #size-cells = <2>;
4028                         ranges;
4029
4030                         mdss_mdp: mdp@ae01000 {
4031                                 compatible = "qcom,sdm845-dpu";
4032                                 reg = <0 0x0ae01000 0 0x8f000>,
4033                                       <0 0x0aeb0000 0 0x2008>;
4034                                 reg-names = "mdp", "vbif";
4035
4036                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4037                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
4038                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4039                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4040                                 clock-names = "iface", "bus", "core", "vsync";
4041
4042                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4043                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4044                                 assigned-clock-rates = <300000000>,
4045                                                        <19200000>;
4046                                 operating-points-v2 = <&mdp_opp_table>;
4047                                 power-domains = <&rpmhpd SDM845_CX>;
4048
4049                                 interrupt-parent = <&mdss>;
4050                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4051
4052                                 status = "disabled";
4053
4054                                 ports {
4055                                         #address-cells = <1>;
4056                                         #size-cells = <0>;
4057
4058                                         port@0 {
4059                                                 reg = <0>;
4060                                                 dpu_intf1_out: endpoint {
4061                                                         remote-endpoint = <&dsi0_in>;
4062                                                 };
4063                                         };
4064
4065                                         port@1 {
4066                                                 reg = <1>;
4067                                                 dpu_intf2_out: endpoint {
4068                                                         remote-endpoint = <&dsi1_in>;
4069                                                 };
4070                                         };
4071                                 };
4072
4073                                 mdp_opp_table: mdp-opp-table {
4074                                         compatible = "operating-points-v2";
4075
4076                                         opp-19200000 {
4077                                                 opp-hz = /bits/ 64 <19200000>;
4078                                                 required-opps = <&rpmhpd_opp_min_svs>;
4079                                         };
4080
4081                                         opp-171428571 {
4082                                                 opp-hz = /bits/ 64 <171428571>;
4083                                                 required-opps = <&rpmhpd_opp_low_svs>;
4084                                         };
4085
4086                                         opp-344000000 {
4087                                                 opp-hz = /bits/ 64 <344000000>;
4088                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4089                                         };
4090
4091                                         opp-430000000 {
4092                                                 opp-hz = /bits/ 64 <430000000>;
4093                                                 required-opps = <&rpmhpd_opp_nom>;
4094                                         };
4095                                 };
4096                         };
4097
4098                         dsi0: dsi@ae94000 {
4099                                 compatible = "qcom,mdss-dsi-ctrl";
4100                                 reg = <0 0x0ae94000 0 0x400>;
4101                                 reg-names = "dsi_ctrl";
4102
4103                                 interrupt-parent = <&mdss>;
4104                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4105
4106                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4107                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4108                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4109                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4110                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4111                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4112                                 clock-names = "byte",
4113                                               "byte_intf",
4114                                               "pixel",
4115                                               "core",
4116                                               "iface",
4117                                               "bus";
4118                                 operating-points-v2 = <&dsi_opp_table>;
4119                                 power-domains = <&rpmhpd SDM845_CX>;
4120
4121                                 phys = <&dsi0_phy>;
4122                                 phy-names = "dsi";
4123
4124                                 status = "disabled";
4125
4126                                 ports {
4127                                         #address-cells = <1>;
4128                                         #size-cells = <0>;
4129
4130                                         port@0 {
4131                                                 reg = <0>;
4132                                                 dsi0_in: endpoint {
4133                                                         remote-endpoint = <&dpu_intf1_out>;
4134                                                 };
4135                                         };
4136
4137                                         port@1 {
4138                                                 reg = <1>;
4139                                                 dsi0_out: endpoint {
4140                                                 };
4141                                         };
4142                                 };
4143                         };
4144
4145                         dsi0_phy: dsi-phy@ae94400 {
4146                                 compatible = "qcom,dsi-phy-10nm";
4147                                 reg = <0 0x0ae94400 0 0x200>,
4148                                       <0 0x0ae94600 0 0x280>,
4149                                       <0 0x0ae94a00 0 0x1e0>;
4150                                 reg-names = "dsi_phy",
4151                                             "dsi_phy_lane",
4152                                             "dsi_pll";
4153
4154                                 #clock-cells = <1>;
4155                                 #phy-cells = <0>;
4156
4157                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4158                                          <&rpmhcc RPMH_CXO_CLK>;
4159                                 clock-names = "iface", "ref";
4160
4161                                 status = "disabled";
4162                         };
4163
4164                         dsi1: dsi@ae96000 {
4165                                 compatible = "qcom,mdss-dsi-ctrl";
4166                                 reg = <0 0x0ae96000 0 0x400>;
4167                                 reg-names = "dsi_ctrl";
4168
4169                                 interrupt-parent = <&mdss>;
4170                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4171
4172                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4173                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4174                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4175                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4176                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4177                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4178                                 clock-names = "byte",
4179                                               "byte_intf",
4180                                               "pixel",
4181                                               "core",
4182                                               "iface",
4183                                               "bus";
4184                                 operating-points-v2 = <&dsi_opp_table>;
4185                                 power-domains = <&rpmhpd SDM845_CX>;
4186
4187                                 phys = <&dsi1_phy>;
4188                                 phy-names = "dsi";
4189
4190                                 status = "disabled";
4191
4192                                 ports {
4193                                         #address-cells = <1>;
4194                                         #size-cells = <0>;
4195
4196                                         port@0 {
4197                                                 reg = <0>;
4198                                                 dsi1_in: endpoint {
4199                                                         remote-endpoint = <&dpu_intf2_out>;
4200                                                 };
4201                                         };
4202
4203                                         port@1 {
4204                                                 reg = <1>;
4205                                                 dsi1_out: endpoint {
4206                                                 };
4207                                         };
4208                                 };
4209                         };
4210
4211                         dsi1_phy: dsi-phy@ae96400 {
4212                                 compatible = "qcom,dsi-phy-10nm";
4213                                 reg = <0 0x0ae96400 0 0x200>,
4214                                       <0 0x0ae96600 0 0x280>,
4215                                       <0 0x0ae96a00 0 0x10e>;
4216                                 reg-names = "dsi_phy",
4217                                             "dsi_phy_lane",
4218                                             "dsi_pll";
4219
4220                                 #clock-cells = <1>;
4221                                 #phy-cells = <0>;
4222
4223                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4224                                          <&rpmhcc RPMH_CXO_CLK>;
4225                                 clock-names = "iface", "ref";
4226
4227                                 status = "disabled";
4228                         };
4229                 };
4230
4231                 gpu: gpu@5000000 {
4232                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4233                         #stream-id-cells = <16>;
4234
4235                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4236                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4237
4238                         /*
4239                          * Look ma, no clocks! The GPU clocks and power are
4240                          * controlled entirely by the GMU
4241                          */
4242
4243                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4244
4245                         iommus = <&adreno_smmu 0>;
4246
4247                         operating-points-v2 = <&gpu_opp_table>;
4248
4249                         qcom,gmu = <&gmu>;
4250
4251                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4252                         interconnect-names = "gfx-mem";
4253
4254                         gpu_opp_table: opp-table {
4255                                 compatible = "operating-points-v2";
4256
4257                                 opp-710000000 {
4258                                         opp-hz = /bits/ 64 <710000000>;
4259                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4260                                         opp-peak-kBps = <7216000>;
4261                                 };
4262
4263                                 opp-675000000 {
4264                                         opp-hz = /bits/ 64 <675000000>;
4265                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4266                                         opp-peak-kBps = <7216000>;
4267                                 };
4268
4269                                 opp-596000000 {
4270                                         opp-hz = /bits/ 64 <596000000>;
4271                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4272                                         opp-peak-kBps = <6220000>;
4273                                 };
4274
4275                                 opp-520000000 {
4276                                         opp-hz = /bits/ 64 <520000000>;
4277                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4278                                         opp-peak-kBps = <6220000>;
4279                                 };
4280
4281                                 opp-414000000 {
4282                                         opp-hz = /bits/ 64 <414000000>;
4283                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4284                                         opp-peak-kBps = <4068000>;
4285                                 };
4286
4287                                 opp-342000000 {
4288                                         opp-hz = /bits/ 64 <342000000>;
4289                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4290                                         opp-peak-kBps = <2724000>;
4291                                 };
4292
4293                                 opp-257000000 {
4294                                         opp-hz = /bits/ 64 <257000000>;
4295                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4296                                         opp-peak-kBps = <1648000>;
4297                                 };
4298                         };
4299                 };
4300
4301                 adreno_smmu: iommu@5040000 {
4302                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4303                         reg = <0 0x5040000 0 0x10000>;
4304                         #iommu-cells = <1>;
4305                         #global-interrupts = <2>;
4306                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4307                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4308                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4309                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4310                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4311                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4312                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4313                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4314                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4315                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4316                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4317                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4318                         clock-names = "bus", "iface";
4319
4320                         power-domains = <&gpucc GPU_CX_GDSC>;
4321                 };
4322
4323                 gmu: gmu@506a000 {
4324                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4325
4326                         reg = <0 0x506a000 0 0x30000>,
4327                               <0 0xb280000 0 0x10000>,
4328                               <0 0xb480000 0 0x10000>;
4329                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4330
4331                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4332                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4333                         interrupt-names = "hfi", "gmu";
4334
4335                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4336                                  <&gpucc GPU_CC_CXO_CLK>,
4337                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4338                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4339                         clock-names = "gmu", "cxo", "axi", "memnoc";
4340
4341                         power-domains = <&gpucc GPU_CX_GDSC>,
4342                                         <&gpucc GPU_GX_GDSC>;
4343                         power-domain-names = "cx", "gx";
4344
4345                         iommus = <&adreno_smmu 5>;
4346
4347                         operating-points-v2 = <&gmu_opp_table>;
4348
4349                         gmu_opp_table: opp-table {
4350                                 compatible = "operating-points-v2";
4351
4352                                 opp-400000000 {
4353                                         opp-hz = /bits/ 64 <400000000>;
4354                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4355                                 };
4356
4357                                 opp-200000000 {
4358                                         opp-hz = /bits/ 64 <200000000>;
4359                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4360                                 };
4361                         };
4362                 };
4363
4364                 dispcc: clock-controller@af00000 {
4365                         compatible = "qcom,sdm845-dispcc";
4366                         reg = <0 0x0af00000 0 0x10000>;
4367                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4368                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4369                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4370                                  <&dsi0_phy 0>,
4371                                  <&dsi0_phy 1>,
4372                                  <&dsi1_phy 0>,
4373                                  <&dsi1_phy 1>,
4374                                  <0>,
4375                                  <0>;
4376                         clock-names = "bi_tcxo",
4377                                       "gcc_disp_gpll0_clk_src",
4378                                       "gcc_disp_gpll0_div_clk_src",
4379                                       "dsi0_phy_pll_out_byteclk",
4380                                       "dsi0_phy_pll_out_dsiclk",
4381                                       "dsi1_phy_pll_out_byteclk",
4382                                       "dsi1_phy_pll_out_dsiclk",
4383                                       "dp_link_clk_divsel_ten",
4384                                       "dp_vco_divided_clk_src_mux";
4385                         #clock-cells = <1>;
4386                         #reset-cells = <1>;
4387                         #power-domain-cells = <1>;
4388                 };
4389
4390                 pdc_intc: interrupt-controller@b220000 {
4391                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4392                         reg = <0 0x0b220000 0 0x30000>;
4393                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4394                         #interrupt-cells = <2>;
4395                         interrupt-parent = <&intc>;
4396                         interrupt-controller;
4397                 };
4398
4399                 pdc_reset: reset-controller@b2e0000 {
4400                         compatible = "qcom,sdm845-pdc-global";
4401                         reg = <0 0x0b2e0000 0 0x20000>;
4402                         #reset-cells = <1>;
4403                 };
4404
4405                 tsens0: thermal-sensor@c263000 {
4406                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4407                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4408                               <0 0x0c222000 0 0x1ff>; /* SROT */
4409                         #qcom,sensors = <13>;
4410                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4411                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4412                         interrupt-names = "uplow", "critical";
4413                         #thermal-sensor-cells = <1>;
4414                 };
4415
4416                 tsens1: thermal-sensor@c265000 {
4417                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4418                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4419                               <0 0x0c223000 0 0x1ff>; /* SROT */
4420                         #qcom,sensors = <8>;
4421                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4422                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4423                         interrupt-names = "uplow", "critical";
4424                         #thermal-sensor-cells = <1>;
4425                 };
4426
4427                 aoss_reset: reset-controller@c2a0000 {
4428                         compatible = "qcom,sdm845-aoss-cc";
4429                         reg = <0 0x0c2a0000 0 0x31000>;
4430                         #reset-cells = <1>;
4431                 };
4432
4433                 aoss_qmp: qmp@c300000 {
4434                         compatible = "qcom,sdm845-aoss-qmp";
4435                         reg = <0 0x0c300000 0 0x100000>;
4436                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4437                         mboxes = <&apss_shared 0>;
4438
4439                         #clock-cells = <0>;
4440                         #power-domain-cells = <1>;
4441
4442                         cx_cdev: cx {
4443                                 #cooling-cells = <2>;
4444                         };
4445
4446                         ebi_cdev: ebi {
4447                                 #cooling-cells = <2>;
4448                         };
4449                 };
4450
4451                 spmi_bus: spmi@c440000 {
4452                         compatible = "qcom,spmi-pmic-arb";
4453                         reg = <0 0x0c440000 0 0x1100>,
4454                               <0 0x0c600000 0 0x2000000>,
4455                               <0 0x0e600000 0 0x100000>,
4456                               <0 0x0e700000 0 0xa0000>,
4457                               <0 0x0c40a000 0 0x26000>;
4458                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4459                         interrupt-names = "periph_irq";
4460                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4461                         qcom,ee = <0>;
4462                         qcom,channel = <0>;
4463                         #address-cells = <2>;
4464                         #size-cells = <0>;
4465                         interrupt-controller;
4466                         #interrupt-cells = <4>;
4467                         cell-index = <0>;
4468                 };
4469
4470                 imem@146bf000 {
4471                         compatible = "simple-mfd";
4472                         reg = <0 0x146bf000 0 0x1000>;
4473
4474                         #address-cells = <1>;
4475                         #size-cells = <1>;
4476
4477                         ranges = <0 0 0x146bf000 0x1000>;
4478
4479                         pil-reloc@94c {
4480                                 compatible = "qcom,pil-reloc-info";
4481                                 reg = <0x94c 0xc8>;
4482                         };
4483                 };
4484
4485                 apps_smmu: iommu@15000000 {
4486                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4487                         reg = <0 0x15000000 0 0x80000>;
4488                         #iommu-cells = <2>;
4489                         #global-interrupts = <1>;
4490                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4491                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4492                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4493                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4494                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4495                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4496                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4497                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4498                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4499                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4500                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4501                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4502                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4503                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4504                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4505                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4506                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4507                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4508                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4509                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4510                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4511                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4512                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4513                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4514                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4515                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4516                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4517                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4518                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4519                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4520                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4521                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4522                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4523                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4524                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4525                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4526                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4527                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4528                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4529                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4530                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4531                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4532                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4533                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4534                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4535                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4536                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4537                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4538                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4539                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4540                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4541                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4542                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4543                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4544                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4545                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4546                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4547                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4548                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4549                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4550                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4551                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4552                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4553                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4554                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4555                 };
4556
4557                 lpasscc: clock-controller@17014000 {
4558                         compatible = "qcom,sdm845-lpasscc";
4559                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4560                         reg-names = "cc", "qdsp6ss";
4561                         #clock-cells = <1>;
4562                         status = "disabled";
4563                 };
4564
4565                 gladiator_noc: interconnect@17900000 {
4566                         compatible = "qcom,sdm845-gladiator-noc";
4567                         reg = <0 0x17900000 0 0xd080>;
4568                         #interconnect-cells = <2>;
4569                         qcom,bcm-voters = <&apps_bcm_voter>;
4570                 };
4571
4572                 watchdog@17980000 {
4573                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4574                         reg = <0 0x17980000 0 0x1000>;
4575                         clocks = <&sleep_clk>;
4576                 };
4577
4578                 apss_shared: mailbox@17990000 {
4579                         compatible = "qcom,sdm845-apss-shared";
4580                         reg = <0 0x17990000 0 0x1000>;
4581                         #mbox-cells = <1>;
4582                 };
4583
4584                 apps_rsc: rsc@179c0000 {
4585                         label = "apps_rsc";
4586                         compatible = "qcom,rpmh-rsc";
4587                         reg = <0 0x179c0000 0 0x10000>,
4588                               <0 0x179d0000 0 0x10000>,
4589                               <0 0x179e0000 0 0x10000>;
4590                         reg-names = "drv-0", "drv-1", "drv-2";
4591                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4592                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4593                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4594                         qcom,tcs-offset = <0xd00>;
4595                         qcom,drv-id = <2>;
4596                         qcom,tcs-config = <ACTIVE_TCS  2>,
4597                                           <SLEEP_TCS   3>,
4598                                           <WAKE_TCS    3>,
4599                                           <CONTROL_TCS 1>;
4600
4601                         apps_bcm_voter: bcm-voter {
4602                                 compatible = "qcom,bcm-voter";
4603                         };
4604
4605                         rpmhcc: clock-controller {
4606                                 compatible = "qcom,sdm845-rpmh-clk";
4607                                 #clock-cells = <1>;
4608                                 clock-names = "xo";
4609                                 clocks = <&xo_board>;
4610                         };
4611
4612                         rpmhpd: power-controller {
4613                                 compatible = "qcom,sdm845-rpmhpd";
4614                                 #power-domain-cells = <1>;
4615                                 operating-points-v2 = <&rpmhpd_opp_table>;
4616
4617                                 rpmhpd_opp_table: opp-table {
4618                                         compatible = "operating-points-v2";
4619
4620                                         rpmhpd_opp_ret: opp1 {
4621                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4622                                         };
4623
4624                                         rpmhpd_opp_min_svs: opp2 {
4625                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4626                                         };
4627
4628                                         rpmhpd_opp_low_svs: opp3 {
4629                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4630                                         };
4631
4632                                         rpmhpd_opp_svs: opp4 {
4633                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4634                                         };
4635
4636                                         rpmhpd_opp_svs_l1: opp5 {
4637                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4638                                         };
4639
4640                                         rpmhpd_opp_nom: opp6 {
4641                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4642                                         };
4643
4644                                         rpmhpd_opp_nom_l1: opp7 {
4645                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4646                                         };
4647
4648                                         rpmhpd_opp_nom_l2: opp8 {
4649                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4650                                         };
4651
4652                                         rpmhpd_opp_turbo: opp9 {
4653                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4654                                         };
4655
4656                                         rpmhpd_opp_turbo_l1: opp10 {
4657                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4658                                         };
4659                                 };
4660                         };
4661                 };
4662
4663                 intc: interrupt-controller@17a00000 {
4664                         compatible = "arm,gic-v3";
4665                         #address-cells = <2>;
4666                         #size-cells = <2>;
4667                         ranges;
4668                         #interrupt-cells = <3>;
4669                         interrupt-controller;
4670                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
4671                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
4672                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4673
4674                         msi-controller@17a40000 {
4675                                 compatible = "arm,gic-v3-its";
4676                                 msi-controller;
4677                                 #msi-cells = <1>;
4678                                 reg = <0 0x17a40000 0 0x20000>;
4679                                 status = "disabled";
4680                         };
4681                 };
4682
4683                 slimbam: dma-controller@17184000 {
4684                         compatible = "qcom,bam-v1.7.0";
4685                         qcom,controlled-remotely;
4686                         reg = <0 0x17184000 0 0x2a000>;
4687                         num-channels  = <31>;
4688                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4689                         #dma-cells = <1>;
4690                         qcom,ee = <1>;
4691                         qcom,num-ees = <2>;
4692                         iommus = <&apps_smmu 0x1806 0x0>;
4693                 };
4694
4695                 timer@17c90000 {
4696                         #address-cells = <2>;
4697                         #size-cells = <2>;
4698                         ranges;
4699                         compatible = "arm,armv7-timer-mem";
4700                         reg = <0 0x17c90000 0 0x1000>;
4701
4702                         frame@17ca0000 {
4703                                 frame-number = <0>;
4704                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4705                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4706                                 reg = <0 0x17ca0000 0 0x1000>,
4707                                       <0 0x17cb0000 0 0x1000>;
4708                         };
4709
4710                         frame@17cc0000 {
4711                                 frame-number = <1>;
4712                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4713                                 reg = <0 0x17cc0000 0 0x1000>;
4714                                 status = "disabled";
4715                         };
4716
4717                         frame@17cd0000 {
4718                                 frame-number = <2>;
4719                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4720                                 reg = <0 0x17cd0000 0 0x1000>;
4721                                 status = "disabled";
4722                         };
4723
4724                         frame@17ce0000 {
4725                                 frame-number = <3>;
4726                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4727                                 reg = <0 0x17ce0000 0 0x1000>;
4728                                 status = "disabled";
4729                         };
4730
4731                         frame@17cf0000 {
4732                                 frame-number = <4>;
4733                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4734                                 reg = <0 0x17cf0000 0 0x1000>;
4735                                 status = "disabled";
4736                         };
4737
4738                         frame@17d00000 {
4739                                 frame-number = <5>;
4740                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4741                                 reg = <0 0x17d00000 0 0x1000>;
4742                                 status = "disabled";
4743                         };
4744
4745                         frame@17d10000 {
4746                                 frame-number = <6>;
4747                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4748                                 reg = <0 0x17d10000 0 0x1000>;
4749                                 status = "disabled";
4750                         };
4751                 };
4752
4753                 osm_l3: interconnect@17d41000 {
4754                         compatible = "qcom,sdm845-osm-l3";
4755                         reg = <0 0x17d41000 0 0x1400>;
4756
4757                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4758                         clock-names = "xo", "alternate";
4759
4760                         #interconnect-cells = <1>;
4761                 };
4762
4763                 cpufreq_hw: cpufreq@17d43000 {
4764                         compatible = "qcom,cpufreq-hw";
4765                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4766                         reg-names = "freq-domain0", "freq-domain1";
4767
4768                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4769                         clock-names = "xo", "alternate";
4770
4771                         #freq-domain-cells = <1>;
4772                 };
4773
4774                 wifi: wifi@18800000 {
4775                         compatible = "qcom,wcn3990-wifi";
4776                         status = "disabled";
4777                         reg = <0 0x18800000 0 0x800000>;
4778                         reg-names = "membase";
4779                         memory-region = <&wlan_msa_mem>;
4780                         clock-names = "cxo_ref_clk_pin";
4781                         clocks = <&rpmhcc RPMH_RF_CLK2>;
4782                         interrupts =
4783                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4784                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4785                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4786                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4787                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4788                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4789                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4790                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4791                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4792                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4793                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4794                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4795                         iommus = <&apps_smmu 0x0040 0x1>;
4796                 };
4797         };
4798
4799         thermal-zones {
4800                 cpu0-thermal {
4801                         polling-delay-passive = <250>;
4802                         polling-delay = <1000>;
4803
4804                         thermal-sensors = <&tsens0 1>;
4805
4806                         trips {
4807                                 cpu0_alert0: trip-point0 {
4808                                         temperature = <90000>;
4809                                         hysteresis = <2000>;
4810                                         type = "passive";
4811                                 };
4812
4813                                 cpu0_alert1: trip-point1 {
4814                                         temperature = <95000>;
4815                                         hysteresis = <2000>;
4816                                         type = "passive";
4817                                 };
4818
4819                                 cpu0_crit: cpu_crit {
4820                                         temperature = <110000>;
4821                                         hysteresis = <1000>;
4822                                         type = "critical";
4823                                 };
4824                         };
4825
4826                         cooling-maps {
4827                                 map0 {
4828                                         trip = <&cpu0_alert0>;
4829                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4830                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4831                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4832                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4833                                 };
4834                                 map1 {
4835                                         trip = <&cpu0_alert1>;
4836                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4837                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4838                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4839                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4840                                 };
4841                         };
4842                 };
4843
4844                 cpu1-thermal {
4845                         polling-delay-passive = <250>;
4846                         polling-delay = <1000>;
4847
4848                         thermal-sensors = <&tsens0 2>;
4849
4850                         trips {
4851                                 cpu1_alert0: trip-point0 {
4852                                         temperature = <90000>;
4853                                         hysteresis = <2000>;
4854                                         type = "passive";
4855                                 };
4856
4857                                 cpu1_alert1: trip-point1 {
4858                                         temperature = <95000>;
4859                                         hysteresis = <2000>;
4860                                         type = "passive";
4861                                 };
4862
4863                                 cpu1_crit: cpu_crit {
4864                                         temperature = <110000>;
4865                                         hysteresis = <1000>;
4866                                         type = "critical";
4867                                 };
4868                         };
4869
4870                         cooling-maps {
4871                                 map0 {
4872                                         trip = <&cpu1_alert0>;
4873                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4874                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4875                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4876                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4877                                 };
4878                                 map1 {
4879                                         trip = <&cpu1_alert1>;
4880                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4881                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4882                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4883                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4884                                 };
4885                         };
4886                 };
4887
4888                 cpu2-thermal {
4889                         polling-delay-passive = <250>;
4890                         polling-delay = <1000>;
4891
4892                         thermal-sensors = <&tsens0 3>;
4893
4894                         trips {
4895                                 cpu2_alert0: trip-point0 {
4896                                         temperature = <90000>;
4897                                         hysteresis = <2000>;
4898                                         type = "passive";
4899                                 };
4900
4901                                 cpu2_alert1: trip-point1 {
4902                                         temperature = <95000>;
4903                                         hysteresis = <2000>;
4904                                         type = "passive";
4905                                 };
4906
4907                                 cpu2_crit: cpu_crit {
4908                                         temperature = <110000>;
4909                                         hysteresis = <1000>;
4910                                         type = "critical";
4911                                 };
4912                         };
4913
4914                         cooling-maps {
4915                                 map0 {
4916                                         trip = <&cpu2_alert0>;
4917                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4918                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4919                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4920                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4921                                 };
4922                                 map1 {
4923                                         trip = <&cpu2_alert1>;
4924                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4925                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4926                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4927                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4928                                 };
4929                         };
4930                 };
4931
4932                 cpu3-thermal {
4933                         polling-delay-passive = <250>;
4934                         polling-delay = <1000>;
4935
4936                         thermal-sensors = <&tsens0 4>;
4937
4938                         trips {
4939                                 cpu3_alert0: trip-point0 {
4940                                         temperature = <90000>;
4941                                         hysteresis = <2000>;
4942                                         type = "passive";
4943                                 };
4944
4945                                 cpu3_alert1: trip-point1 {
4946                                         temperature = <95000>;
4947                                         hysteresis = <2000>;
4948                                         type = "passive";
4949                                 };
4950
4951                                 cpu3_crit: cpu_crit {
4952                                         temperature = <110000>;
4953                                         hysteresis = <1000>;
4954                                         type = "critical";
4955                                 };
4956                         };
4957
4958                         cooling-maps {
4959                                 map0 {
4960                                         trip = <&cpu3_alert0>;
4961                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4962                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4963                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4964                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4965                                 };
4966                                 map1 {
4967                                         trip = <&cpu3_alert1>;
4968                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4969                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4970                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4971                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4972                                 };
4973                         };
4974                 };
4975
4976                 cpu4-thermal {
4977                         polling-delay-passive = <250>;
4978                         polling-delay = <1000>;
4979
4980                         thermal-sensors = <&tsens0 7>;
4981
4982                         trips {
4983                                 cpu4_alert0: trip-point0 {
4984                                         temperature = <90000>;
4985                                         hysteresis = <2000>;
4986                                         type = "passive";
4987                                 };
4988
4989                                 cpu4_alert1: trip-point1 {
4990                                         temperature = <95000>;
4991                                         hysteresis = <2000>;
4992                                         type = "passive";
4993                                 };
4994
4995                                 cpu4_crit: cpu_crit {
4996                                         temperature = <110000>;
4997                                         hysteresis = <1000>;
4998                                         type = "critical";
4999                                 };
5000                         };
5001
5002                         cooling-maps {
5003                                 map0 {
5004                                         trip = <&cpu4_alert0>;
5005                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5006                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5007                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5008                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5009                                 };
5010                                 map1 {
5011                                         trip = <&cpu4_alert1>;
5012                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5013                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5014                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5015                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5016                                 };
5017                         };
5018                 };
5019
5020                 cpu5-thermal {
5021                         polling-delay-passive = <250>;
5022                         polling-delay = <1000>;
5023
5024                         thermal-sensors = <&tsens0 8>;
5025
5026                         trips {
5027                                 cpu5_alert0: trip-point0 {
5028                                         temperature = <90000>;
5029                                         hysteresis = <2000>;
5030                                         type = "passive";
5031                                 };
5032
5033                                 cpu5_alert1: trip-point1 {
5034                                         temperature = <95000>;
5035                                         hysteresis = <2000>;
5036                                         type = "passive";
5037                                 };
5038
5039                                 cpu5_crit: cpu_crit {
5040                                         temperature = <110000>;
5041                                         hysteresis = <1000>;
5042                                         type = "critical";
5043                                 };
5044                         };
5045
5046                         cooling-maps {
5047                                 map0 {
5048                                         trip = <&cpu5_alert0>;
5049                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5050                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5051                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5052                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5053                                 };
5054                                 map1 {
5055                                         trip = <&cpu5_alert1>;
5056                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5057                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5058                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5059                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5060                                 };
5061                         };
5062                 };
5063
5064                 cpu6-thermal {
5065                         polling-delay-passive = <250>;
5066                         polling-delay = <1000>;
5067
5068                         thermal-sensors = <&tsens0 9>;
5069
5070                         trips {
5071                                 cpu6_alert0: trip-point0 {
5072                                         temperature = <90000>;
5073                                         hysteresis = <2000>;
5074                                         type = "passive";
5075                                 };
5076
5077                                 cpu6_alert1: trip-point1 {
5078                                         temperature = <95000>;
5079                                         hysteresis = <2000>;
5080                                         type = "passive";
5081                                 };
5082
5083                                 cpu6_crit: cpu_crit {
5084                                         temperature = <110000>;
5085                                         hysteresis = <1000>;
5086                                         type = "critical";
5087                                 };
5088                         };
5089
5090                         cooling-maps {
5091                                 map0 {
5092                                         trip = <&cpu6_alert0>;
5093                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5094                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5095                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5096                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5097                                 };
5098                                 map1 {
5099                                         trip = <&cpu6_alert1>;
5100                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5101                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5102                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5103                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5104                                 };
5105                         };
5106                 };
5107
5108                 cpu7-thermal {
5109                         polling-delay-passive = <250>;
5110                         polling-delay = <1000>;
5111
5112                         thermal-sensors = <&tsens0 10>;
5113
5114                         trips {
5115                                 cpu7_alert0: trip-point0 {
5116                                         temperature = <90000>;
5117                                         hysteresis = <2000>;
5118                                         type = "passive";
5119                                 };
5120
5121                                 cpu7_alert1: trip-point1 {
5122                                         temperature = <95000>;
5123                                         hysteresis = <2000>;
5124                                         type = "passive";
5125                                 };
5126
5127                                 cpu7_crit: cpu_crit {
5128                                         temperature = <110000>;
5129                                         hysteresis = <1000>;
5130                                         type = "critical";
5131                                 };
5132                         };
5133
5134                         cooling-maps {
5135                                 map0 {
5136                                         trip = <&cpu7_alert0>;
5137                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5138                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5139                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5140                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5141                                 };
5142                                 map1 {
5143                                         trip = <&cpu7_alert1>;
5144                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5145                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5146                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5147                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5148                                 };
5149                         };
5150                 };
5151
5152                 aoss0-thermal {
5153                         polling-delay-passive = <250>;
5154                         polling-delay = <1000>;
5155
5156                         thermal-sensors = <&tsens0 0>;
5157
5158                         trips {
5159                                 aoss0_alert0: trip-point0 {
5160                                         temperature = <90000>;
5161                                         hysteresis = <2000>;
5162                                         type = "hot";
5163                                 };
5164                         };
5165                 };
5166
5167                 cluster0-thermal {
5168                         polling-delay-passive = <250>;
5169                         polling-delay = <1000>;
5170
5171                         thermal-sensors = <&tsens0 5>;
5172
5173                         trips {
5174                                 cluster0_alert0: trip-point0 {
5175                                         temperature = <90000>;
5176                                         hysteresis = <2000>;
5177                                         type = "hot";
5178                                 };
5179                                 cluster0_crit: cluster0_crit {
5180                                         temperature = <110000>;
5181                                         hysteresis = <2000>;
5182                                         type = "critical";
5183                                 };
5184                         };
5185                 };
5186
5187                 cluster1-thermal {
5188                         polling-delay-passive = <250>;
5189                         polling-delay = <1000>;
5190
5191                         thermal-sensors = <&tsens0 6>;
5192
5193                         trips {
5194                                 cluster1_alert0: trip-point0 {
5195                                         temperature = <90000>;
5196                                         hysteresis = <2000>;
5197                                         type = "hot";
5198                                 };
5199                                 cluster1_crit: cluster1_crit {
5200                                         temperature = <110000>;
5201                                         hysteresis = <2000>;
5202                                         type = "critical";
5203                                 };
5204                         };
5205                 };
5206
5207                 gpu-thermal-top {
5208                         polling-delay-passive = <250>;
5209                         polling-delay = <1000>;
5210
5211                         thermal-sensors = <&tsens0 11>;
5212
5213                         trips {
5214                                 gpu1_alert0: trip-point0 {
5215                                         temperature = <90000>;
5216                                         hysteresis = <2000>;
5217                                         type = "hot";
5218                                 };
5219                         };
5220                 };
5221
5222                 gpu-thermal-bottom {
5223                         polling-delay-passive = <250>;
5224                         polling-delay = <1000>;
5225
5226                         thermal-sensors = <&tsens0 12>;
5227
5228                         trips {
5229                                 gpu2_alert0: trip-point0 {
5230                                         temperature = <90000>;
5231                                         hysteresis = <2000>;
5232                                         type = "hot";
5233                                 };
5234                         };
5235                 };
5236
5237                 aoss1-thermal {
5238                         polling-delay-passive = <250>;
5239                         polling-delay = <1000>;
5240
5241                         thermal-sensors = <&tsens1 0>;
5242
5243                         trips {
5244                                 aoss1_alert0: trip-point0 {
5245                                         temperature = <90000>;
5246                                         hysteresis = <2000>;
5247                                         type = "hot";
5248                                 };
5249                         };
5250                 };
5251
5252                 q6-modem-thermal {
5253                         polling-delay-passive = <250>;
5254                         polling-delay = <1000>;
5255
5256                         thermal-sensors = <&tsens1 1>;
5257
5258                         trips {
5259                                 q6_modem_alert0: trip-point0 {
5260                                         temperature = <90000>;
5261                                         hysteresis = <2000>;
5262                                         type = "hot";
5263                                 };
5264                         };
5265                 };
5266
5267                 mem-thermal {
5268                         polling-delay-passive = <250>;
5269                         polling-delay = <1000>;
5270
5271                         thermal-sensors = <&tsens1 2>;
5272
5273                         trips {
5274                                 mem_alert0: trip-point0 {
5275                                         temperature = <90000>;
5276                                         hysteresis = <2000>;
5277                                         type = "hot";
5278                                 };
5279                         };
5280                 };
5281
5282                 wlan-thermal {
5283                         polling-delay-passive = <250>;
5284                         polling-delay = <1000>;
5285
5286                         thermal-sensors = <&tsens1 3>;
5287
5288                         trips {
5289                                 wlan_alert0: trip-point0 {
5290                                         temperature = <90000>;
5291                                         hysteresis = <2000>;
5292                                         type = "hot";
5293                                 };
5294                         };
5295                 };
5296
5297                 q6-hvx-thermal {
5298                         polling-delay-passive = <250>;
5299                         polling-delay = <1000>;
5300
5301                         thermal-sensors = <&tsens1 4>;
5302
5303                         trips {
5304                                 q6_hvx_alert0: trip-point0 {
5305                                         temperature = <90000>;
5306                                         hysteresis = <2000>;
5307                                         type = "hot";
5308                                 };
5309                         };
5310                 };
5311
5312                 camera-thermal {
5313                         polling-delay-passive = <250>;
5314                         polling-delay = <1000>;
5315
5316                         thermal-sensors = <&tsens1 5>;
5317
5318                         trips {
5319                                 camera_alert0: trip-point0 {
5320                                         temperature = <90000>;
5321                                         hysteresis = <2000>;
5322                                         type = "hot";
5323                                 };
5324                         };
5325                 };
5326
5327                 video-thermal {
5328                         polling-delay-passive = <250>;
5329                         polling-delay = <1000>;
5330
5331                         thermal-sensors = <&tsens1 6>;
5332
5333                         trips {
5334                                 video_alert0: trip-point0 {
5335                                         temperature = <90000>;
5336                                         hysteresis = <2000>;
5337                                         type = "hot";
5338                                 };
5339                         };
5340                 };
5341
5342                 modem-thermal {
5343                         polling-delay-passive = <250>;
5344                         polling-delay = <1000>;
5345
5346                         thermal-sensors = <&tsens1 7>;
5347
5348                         trips {
5349                                 modem_alert0: trip-point0 {
5350                                         temperature = <90000>;
5351                                         hysteresis = <2000>;
5352                                         type = "hot";
5353                                 };
5354                         };
5355                 };
5356         };
5357 };